1 /* $OpenBSD: if_msk.c,v 1.129 2017/06/02 01:47:36 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include "bpfilter.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/timeout.h> 99 #include <sys/device.h> 100 #include <sys/queue.h> 101 102 #include <net/if.h> 103 104 #include <netinet/in.h> 105 #include <netinet/if_ether.h> 106 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/pci/if_skreg.h> 121 #include <dev/pci/if_mskvar.h> 122 123 int mskc_probe(struct device *, void *, void *); 124 void mskc_attach(struct device *, struct device *self, void *aux); 125 int mskc_detach(struct device *, int); 126 int mskc_activate(struct device *, int); 127 void mskc_reset(struct sk_softc *); 128 int msk_probe(struct device *, void *, void *); 129 void msk_attach(struct device *, struct device *self, void *aux); 130 int msk_detach(struct device *, int); 131 int msk_activate(struct device *, int); 132 void msk_reset(struct sk_if_softc *); 133 int mskcprint(void *, const char *); 134 int msk_intr(void *); 135 void msk_intr_yukon(struct sk_if_softc *); 136 static __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 137 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 138 void msk_txeof(struct sk_if_softc *); 139 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 140 void msk_start(struct ifnet *); 141 int msk_ioctl(struct ifnet *, u_long, caddr_t); 142 void msk_init(void *); 143 void msk_init_yukon(struct sk_if_softc *); 144 void msk_stop(struct sk_if_softc *, int); 145 void msk_watchdog(struct ifnet *); 146 int msk_ifmedia_upd(struct ifnet *); 147 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148 int msk_newbuf(struct sk_if_softc *); 149 int msk_init_rx_ring(struct sk_if_softc *); 150 int msk_init_tx_ring(struct sk_if_softc *); 151 void msk_fill_rx_ring(struct sk_if_softc *); 152 153 int msk_miibus_readreg(struct device *, int, int); 154 void msk_miibus_writereg(struct device *, int, int, int); 155 void msk_miibus_statchg(struct device *); 156 157 void msk_iff(struct sk_if_softc *); 158 void msk_tick(void *); 159 160 #ifdef MSK_DEBUG 161 #define DPRINTF(x) if (mskdebug) printf x 162 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 163 int mskdebug = 0; 164 165 void msk_dump_txdesc(struct msk_tx_desc *, int); 166 void msk_dump_mbuf(struct mbuf *); 167 void msk_dump_bytes(const char *, int); 168 #else 169 #define DPRINTF(x) 170 #define DPRINTFN(n,x) 171 #endif 172 173 /* supported device vendors */ 174 const struct pci_matchid mskc_devices[] = { 175 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 176 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 177 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 178 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021CU }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021X }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 200 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061CU }, 201 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061X }, 202 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062CU }, 203 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062X }, 204 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 205 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 206 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 207 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 208 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 209 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 210 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 211 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 212 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 213 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 214 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Exx }, 215 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Sxx } 216 }; 217 218 static inline u_int32_t 219 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 220 { 221 return CSR_READ_4(sc, reg); 222 } 223 224 static inline u_int16_t 225 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 226 { 227 return CSR_READ_2(sc, reg); 228 } 229 230 static inline u_int8_t 231 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 232 { 233 return CSR_READ_1(sc, reg); 234 } 235 236 static inline void 237 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 238 { 239 CSR_WRITE_4(sc, reg, x); 240 } 241 242 static inline void 243 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 244 { 245 CSR_WRITE_2(sc, reg, x); 246 } 247 248 static inline void 249 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 250 { 251 CSR_WRITE_1(sc, reg, x); 252 } 253 254 int 255 msk_miibus_readreg(struct device *dev, int phy, int reg) 256 { 257 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 258 u_int16_t val; 259 int i; 260 261 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 262 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 263 264 for (i = 0; i < SK_TIMEOUT; i++) { 265 DELAY(1); 266 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 267 if (val & YU_SMICR_READ_VALID) 268 break; 269 } 270 271 if (i == SK_TIMEOUT) { 272 printf("%s: phy failed to come ready\n", 273 sc_if->sk_dev.dv_xname); 274 return (0); 275 } 276 277 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 278 SK_TIMEOUT)); 279 280 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 281 282 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 283 phy, reg, val)); 284 285 return (val); 286 } 287 288 void 289 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 290 { 291 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 292 int i; 293 294 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 295 phy, reg, val)); 296 297 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 298 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 299 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 300 301 for (i = 0; i < SK_TIMEOUT; i++) { 302 DELAY(1); 303 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 304 break; 305 } 306 307 if (i == SK_TIMEOUT) 308 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 309 } 310 311 void 312 msk_miibus_statchg(struct device *dev) 313 { 314 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 315 struct mii_data *mii = &sc_if->sk_mii; 316 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 317 int gpcr; 318 319 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 320 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 321 322 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 323 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 324 /* Set speed. */ 325 gpcr |= YU_GPCR_SPEED_DIS; 326 switch (IFM_SUBTYPE(mii->mii_media_active)) { 327 case IFM_1000_SX: 328 case IFM_1000_LX: 329 case IFM_1000_CX: 330 case IFM_1000_T: 331 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 332 break; 333 case IFM_100_TX: 334 gpcr |= YU_GPCR_SPEED; 335 break; 336 } 337 338 /* Set duplex. */ 339 gpcr |= YU_GPCR_DPLX_DIS; 340 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 341 gpcr |= YU_GPCR_DUPLEX; 342 343 /* Disable flow control. */ 344 gpcr |= YU_GPCR_FCTL_DIS; 345 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 346 } 347 348 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 349 350 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 351 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 352 } 353 354 void 355 msk_iff(struct sk_if_softc *sc_if) 356 { 357 struct ifnet *ifp = &sc_if->arpcom.ac_if; 358 struct arpcom *ac = &sc_if->arpcom; 359 struct ether_multi *enm; 360 struct ether_multistep step; 361 u_int32_t hashes[2]; 362 u_int16_t rcr; 363 int h; 364 365 rcr = SK_YU_READ_2(sc_if, YUKON_RCR); 366 rcr &= ~(YU_RCR_MUFLEN | YU_RCR_UFLEN); 367 ifp->if_flags &= ~IFF_ALLMULTI; 368 369 /* 370 * Always accept frames destined to our station address. 371 */ 372 rcr |= YU_RCR_UFLEN; 373 374 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 375 ifp->if_flags |= IFF_ALLMULTI; 376 if (ifp->if_flags & IFF_PROMISC) 377 rcr &= ~YU_RCR_UFLEN; 378 else 379 rcr |= YU_RCR_MUFLEN; 380 hashes[0] = hashes[1] = 0xFFFFFFFF; 381 } else { 382 rcr |= YU_RCR_MUFLEN; 383 /* Program new filter. */ 384 bzero(hashes, sizeof(hashes)); 385 386 ETHER_FIRST_MULTI(step, ac, enm); 387 while (enm != NULL) { 388 h = ether_crc32_be(enm->enm_addrlo, 389 ETHER_ADDR_LEN) & ((1 << SK_HASH_BITS) - 1); 390 391 if (h < 32) 392 hashes[0] |= (1 << h); 393 else 394 hashes[1] |= (1 << (h - 32)); 395 396 ETHER_NEXT_MULTI(step, enm); 397 } 398 } 399 400 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 401 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 402 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 403 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 404 SK_YU_WRITE_2(sc_if, YUKON_RCR, rcr); 405 } 406 407 int 408 msk_init_rx_ring(struct sk_if_softc *sc_if) 409 { 410 struct msk_chain_data *cd = &sc_if->sk_cdata; 411 struct msk_ring_data *rd = sc_if->sk_rdata; 412 int i, nexti; 413 414 bzero(rd->sk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 415 416 for (i = 0; i < MSK_RX_RING_CNT; i++) { 417 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 418 if (i == (MSK_RX_RING_CNT - 1)) 419 nexti = 0; 420 else 421 nexti = i + 1; 422 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 423 } 424 425 sc_if->sk_cdata.sk_rx_prod = 0; 426 sc_if->sk_cdata.sk_rx_cons = 0; 427 428 /* two ring entries per packet, so the effective ring size is halved */ 429 if_rxr_init(&sc_if->sk_cdata.sk_rx_ring, 2, MSK_RX_RING_CNT/2); 430 431 msk_fill_rx_ring(sc_if); 432 return (0); 433 } 434 435 int 436 msk_init_tx_ring(struct sk_if_softc *sc_if) 437 { 438 struct sk_softc *sc = sc_if->sk_softc; 439 struct msk_chain_data *cd = &sc_if->sk_cdata; 440 struct msk_ring_data *rd = sc_if->sk_rdata; 441 bus_dmamap_t dmamap; 442 struct sk_txmap_entry *entry; 443 int i, nexti; 444 445 bzero(sc_if->sk_rdata->sk_tx_ring, 446 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 447 448 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 449 for (i = 0; i < MSK_TX_RING_CNT; i++) { 450 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 451 if (i == (MSK_TX_RING_CNT - 1)) 452 nexti = 0; 453 else 454 nexti = i + 1; 455 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 456 457 if (bus_dmamap_create(sc->sc_dmatag, sc_if->sk_pktlen, 458 SK_NTXSEG, sc_if->sk_pktlen, 0, BUS_DMA_NOWAIT, &dmamap)) 459 return (ENOBUFS); 460 461 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 462 if (!entry) { 463 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 464 return (ENOBUFS); 465 } 466 entry->dmamap = dmamap; 467 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 468 } 469 470 sc_if->sk_cdata.sk_tx_prod = 0; 471 sc_if->sk_cdata.sk_tx_cons = 0; 472 sc_if->sk_cdata.sk_tx_cnt = 0; 473 474 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 475 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 476 477 return (0); 478 } 479 480 int 481 msk_newbuf(struct sk_if_softc *sc_if) 482 { 483 struct sk_chain *c; 484 struct msk_rx_desc *r; 485 struct mbuf *m; 486 bus_dmamap_t dmamap; 487 int error; 488 int i, head; 489 uint64_t addr; 490 491 m = MCLGETI(NULL, M_DONTWAIT, NULL, sc_if->sk_pktlen); 492 if (m == NULL) 493 return (0); 494 m->m_len = m->m_pkthdr.len = sc_if->sk_pktlen; 495 m_adj(m, ETHER_ALIGN); 496 497 dmamap = sc_if->sk_cdata.sk_rx_map[sc_if->sk_cdata.sk_rx_prod]; 498 499 error = bus_dmamap_load_mbuf(sc_if->sk_softc->sc_dmatag, dmamap, m, 500 BUS_DMA_READ|BUS_DMA_NOWAIT); 501 if (error) { 502 m_freem(m); 503 return (0); 504 } 505 506 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 507 dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 508 509 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 510 head = sc_if->sk_cdata.sk_rx_prod; 511 r = c->sk_le; 512 c->sk_mbuf = m; 513 514 /* high 32 bits of address */ 515 addr = dmamap->dm_segs[0].ds_addr; 516 r->sk_addr = htole32(addr >> 32); 517 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 518 BUS_DMASYNC_PREWRITE); 519 520 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 521 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 522 r = c->sk_le; 523 524 /* low 32 bits of address + length */ 525 r->sk_addr = htole32(addr & 0xffffffff); 526 r->sk_len = htole16(dmamap->dm_segs[0].ds_len); 527 r->sk_ctl = 0; 528 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 529 BUS_DMASYNC_PREWRITE); 530 531 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 532 533 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 534 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 535 536 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 537 538 for (i = 1; i < dmamap->dm_nsegs; i++) { 539 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 540 r = c->sk_le; 541 c->sk_mbuf = NULL; 542 543 /* high 32 bits of address */ 544 addr = dmamap->dm_segs[i].ds_addr; 545 r->sk_addr = htole32(addr >> 32); 546 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 547 BUS_DMASYNC_PREWRITE); 548 549 r->sk_opcode = SK_Y2_RXOPC_ADDR64 | SK_Y2_RXOPC_OWN; 550 551 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 552 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 553 554 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 555 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 556 c->sk_mbuf = NULL; 557 r = c->sk_le; 558 559 /* low 32 bits of address + length */ 560 r->sk_addr = htole32(addr & 0xffffffff); 561 r->sk_len = htole16(dmamap->dm_segs[i].ds_len); 562 r->sk_ctl = 0; 563 564 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 565 BUS_DMASYNC_PREWRITE); 566 567 r->sk_opcode = SK_Y2_RXOPC_BUFFER | SK_Y2_RXOPC_OWN; 568 569 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 570 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 571 572 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 573 } 574 575 c = &sc_if->sk_cdata.sk_rx_chain[head]; 576 r = c->sk_le; 577 r->sk_opcode = SK_Y2_RXOPC_ADDR64 | SK_Y2_RXOPC_OWN; 578 579 MSK_CDRXSYNC(sc_if, head, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 580 581 return (dmamap->dm_nsegs); 582 } 583 584 /* 585 * Set media options. 586 */ 587 int 588 msk_ifmedia_upd(struct ifnet *ifp) 589 { 590 struct sk_if_softc *sc_if = ifp->if_softc; 591 592 mii_mediachg(&sc_if->sk_mii); 593 return (0); 594 } 595 596 /* 597 * Report current media status. 598 */ 599 void 600 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 601 { 602 struct sk_if_softc *sc_if = ifp->if_softc; 603 604 mii_pollstat(&sc_if->sk_mii); 605 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 606 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 607 } 608 609 int 610 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 611 { 612 struct sk_if_softc *sc_if = ifp->if_softc; 613 struct ifreq *ifr = (struct ifreq *) data; 614 struct mii_data *mii; 615 int s, error = 0; 616 617 s = splnet(); 618 619 switch(command) { 620 case SIOCSIFADDR: 621 ifp->if_flags |= IFF_UP; 622 if (!(ifp->if_flags & IFF_RUNNING)) 623 msk_init(sc_if); 624 break; 625 626 case SIOCSIFFLAGS: 627 if (ifp->if_flags & IFF_UP) { 628 if (ifp->if_flags & IFF_RUNNING) 629 error = ENETRESET; 630 else 631 msk_init(sc_if); 632 } else { 633 if (ifp->if_flags & IFF_RUNNING) 634 msk_stop(sc_if, 0); 635 } 636 break; 637 638 case SIOCGIFMEDIA: 639 case SIOCSIFMEDIA: 640 mii = &sc_if->sk_mii; 641 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 642 break; 643 644 case SIOCGIFRXR: 645 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 646 NULL, sc_if->sk_pktlen, &sc_if->sk_cdata.sk_rx_ring); 647 break; 648 649 default: 650 error = ether_ioctl(ifp, &sc_if->arpcom, command, data); 651 } 652 653 if (error == ENETRESET) { 654 if (ifp->if_flags & IFF_RUNNING) 655 msk_iff(sc_if); 656 error = 0; 657 } 658 659 splx(s); 660 return (error); 661 } 662 663 /* 664 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 665 * IDs against our list and return a device name if we find a match. 666 */ 667 int 668 mskc_probe(struct device *parent, void *match, void *aux) 669 { 670 return (pci_matchbyid((struct pci_attach_args *)aux, mskc_devices, 671 nitems(mskc_devices))); 672 } 673 674 /* 675 * Force the GEnesis into reset, then bring it out of reset. 676 */ 677 void 678 mskc_reset(struct sk_softc *sc) 679 { 680 u_int32_t imtimer_ticks, reg1; 681 int reg; 682 683 DPRINTFN(2, ("mskc_reset\n")); 684 685 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 686 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 687 688 DELAY(1000); 689 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 690 DELAY(2); 691 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 692 693 sk_win_write_1(sc, SK_TESTCTL1, 2); 694 695 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 696 sc->sk_type >= SK_YUKON_FE_P) { 697 /* enable all clocks. */ 698 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 699 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 700 reg1 &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 701 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 702 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 703 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 704 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), reg1); 705 706 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5)); 707 reg1 &= SK_Y2_REG5_TIM_VMAIN_AV_MASK; 708 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), reg1); 709 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_CFGREG1), 0); 710 711 /* 712 * Disable status race, workaround for Yukon EC Ultra & 713 * Yukon EX. 714 */ 715 reg1 = sk_win_read_4(sc, SK_GPIO); 716 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 717 sk_win_write_4(sc, SK_GPIO, reg1); 718 sk_win_read_4(sc, SK_GPIO); 719 } 720 721 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 722 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 723 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 724 else 725 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 726 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 727 728 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 729 sk_win_write_1(sc, SK_Y2_CLKGATE, 730 SK_Y2_CLKGATE_LINK1_GATE_DIS | 731 SK_Y2_CLKGATE_LINK2_GATE_DIS | 732 SK_Y2_CLKGATE_LINK1_CORE_DIS | 733 SK_Y2_CLKGATE_LINK2_CORE_DIS | 734 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 735 else 736 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 737 738 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 739 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 740 DELAY(1000); 741 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 742 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 743 744 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 745 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 746 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 747 } 748 749 sk_win_write_1(sc, SK_TESTCTL1, 1); 750 751 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 752 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 753 CSR_READ_2(sc, SK_LINK_CTRL))); 754 755 /* Disable ASF */ 756 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 757 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 758 759 /* Clear I2C IRQ noise */ 760 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 761 762 /* Disable hardware timer */ 763 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 764 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 765 766 /* Disable descriptor polling */ 767 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 768 769 /* Disable time stamps */ 770 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 771 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 772 773 /* Enable RAM interface */ 774 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 775 for (reg = SK_TO0;reg <= SK_TO11; reg++) 776 sk_win_write_1(sc, reg, 36); 777 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 778 for (reg = SK_TO0;reg <= SK_TO11; reg++) 779 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 780 781 /* 782 * Configure interrupt moderation. The moderation timer 783 * defers interrupts specified in the interrupt moderation 784 * timer mask based on the timeout specified in the interrupt 785 * moderation timer init register. Each bit in the timer 786 * register represents one tick, so to specify a timeout in 787 * microseconds, we have to multiply by the correct number of 788 * ticks-per-microsecond. 789 */ 790 switch (sc->sk_type) { 791 case SK_YUKON_EC: 792 case SK_YUKON_EC_U: 793 case SK_YUKON_EX: 794 case SK_YUKON_SUPR: 795 case SK_YUKON_ULTRA2: 796 case SK_YUKON_OPTIMA: 797 case SK_YUKON_PRM: 798 case SK_YUKON_OPTIMA2: 799 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 800 break; 801 case SK_YUKON_FE: 802 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 803 break; 804 case SK_YUKON_FE_P: 805 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 806 break; 807 case SK_YUKON_XL: 808 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 809 break; 810 default: 811 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 812 break; 813 } 814 815 /* Reset status ring. */ 816 bzero(sc->sk_status_ring, 817 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 818 sc->sk_status_idx = 0; 819 820 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 821 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 822 823 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 824 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 825 sc->sk_status_map->dm_segs[0].ds_addr); 826 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 827 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 828 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 10); 829 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 16); 830 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 16); 831 832 #if 0 833 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 834 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 835 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(20)); 836 #else 837 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(4)); 838 #endif 839 840 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 841 842 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 843 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 844 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 845 } 846 847 int 848 msk_probe(struct device *parent, void *match, void *aux) 849 { 850 struct skc_attach_args *sa = aux; 851 852 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 853 return (0); 854 855 switch (sa->skc_type) { 856 case SK_YUKON_XL: 857 case SK_YUKON_EC_U: 858 case SK_YUKON_EX: 859 case SK_YUKON_EC: 860 case SK_YUKON_FE: 861 case SK_YUKON_FE_P: 862 case SK_YUKON_SUPR: 863 case SK_YUKON_ULTRA2: 864 case SK_YUKON_OPTIMA: 865 case SK_YUKON_PRM: 866 case SK_YUKON_OPTIMA2: 867 return (1); 868 } 869 870 return (0); 871 } 872 873 void 874 msk_reset(struct sk_if_softc *sc_if) 875 { 876 /* GMAC and GPHY Reset */ 877 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 878 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 879 DELAY(1000); 880 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 881 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 882 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 883 } 884 885 /* 886 * Each XMAC chip is attached as a separate logical IP interface. 887 * Single port cards will have only one logical interface of course. 888 */ 889 void 890 msk_attach(struct device *parent, struct device *self, void *aux) 891 { 892 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 893 struct sk_softc *sc = (struct sk_softc *)parent; 894 struct skc_attach_args *sa = aux; 895 struct ifnet *ifp; 896 caddr_t kva; 897 int i; 898 u_int32_t chunk; 899 int mii_flags; 900 int error; 901 902 sc_if->sk_port = sa->skc_port; 903 sc_if->sk_softc = sc; 904 sc->sk_if[sa->skc_port] = sc_if; 905 906 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 907 908 /* 909 * Get station address for this interface. Note that 910 * dual port cards actually come with three station 911 * addresses: one for each port, plus an extra. The 912 * extra one is used by the SysKonnect driver software 913 * as a 'virtual' station address for when both ports 914 * are operating in failover mode. Currently we don't 915 * use this extra address. 916 */ 917 for (i = 0; i < ETHER_ADDR_LEN; i++) 918 sc_if->arpcom.ac_enaddr[i] = 919 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 920 921 printf(": address %s\n", 922 ether_sprintf(sc_if->arpcom.ac_enaddr)); 923 924 /* 925 * Set up RAM buffer addresses. The Yukon2 has a small amount 926 * of SRAM on it, somewhere between 4K and 48K. We need to 927 * divide this up between the transmitter and receiver. We 928 * give the receiver 2/3 of the memory (rounded down), and the 929 * transmitter whatever remains. 930 */ 931 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 932 sc_if->sk_rx_ramstart = 0; 933 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 934 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 935 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 936 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 937 938 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 939 " tx_ramstart=%#x tx_ramend=%#x\n", 940 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 941 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 942 943 /* Allocate the descriptor queues. */ 944 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 945 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 946 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 947 printf(": can't alloc rx buffers\n"); 948 goto fail; 949 } 950 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 951 sc_if->sk_ring_nseg, 952 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 953 printf(": can't map dma buffers (%lu bytes)\n", 954 (ulong)sizeof(struct msk_ring_data)); 955 goto fail_1; 956 } 957 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 958 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 959 &sc_if->sk_ring_map)) { 960 printf(": can't create dma map\n"); 961 goto fail_2; 962 } 963 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 964 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 965 printf(": can't load dma map\n"); 966 goto fail_3; 967 } 968 sc_if->sk_rdata = (struct msk_ring_data *)kva; 969 970 if (sc->sk_type != SK_YUKON_FE && 971 sc->sk_type != SK_YUKON_FE_P) 972 sc_if->sk_pktlen = SK_JLEN; 973 else 974 sc_if->sk_pktlen = MCLBYTES; 975 976 for (i = 0; i < MSK_RX_RING_CNT; i++) { 977 if ((error = bus_dmamap_create(sc->sc_dmatag, 978 sc_if->sk_pktlen, SK_NRXSEG, sc_if->sk_pktlen, 979 0, 0, &sc_if->sk_cdata.sk_rx_map[i])) != 0) { 980 printf("\n%s: unable to create rx DMA map %d, " 981 "error = %d\n", sc->sk_dev.dv_xname, i, error); 982 goto fail_4; 983 } 984 } 985 986 ifp = &sc_if->arpcom.ac_if; 987 ifp->if_softc = sc_if; 988 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 989 ifp->if_ioctl = msk_ioctl; 990 ifp->if_start = msk_start; 991 ifp->if_watchdog = msk_watchdog; 992 if (sc->sk_type != SK_YUKON_FE && 993 sc->sk_type != SK_YUKON_FE_P) 994 ifp->if_hardmtu = SK_JUMBO_MTU; 995 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 996 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 997 998 ifp->if_capabilities = IFCAP_VLAN_MTU; 999 1000 msk_reset(sc_if); 1001 1002 /* 1003 * Do miibus setup. 1004 */ 1005 msk_init_yukon(sc_if); 1006 1007 DPRINTFN(2, ("msk_attach: 1\n")); 1008 1009 sc_if->sk_mii.mii_ifp = ifp; 1010 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1011 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1012 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1013 1014 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1015 msk_ifmedia_upd, msk_ifmedia_sts); 1016 mii_flags = MIIF_DOPAUSE; 1017 if (sc->sk_fibertype) 1018 mii_flags |= MIIF_HAVEFIBER; 1019 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 1020 MII_OFFSET_ANY, mii_flags); 1021 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1022 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1023 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1024 0, NULL); 1025 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1026 } else 1027 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1028 1029 timeout_set(&sc_if->sk_tick_ch, msk_tick, sc_if); 1030 1031 /* 1032 * Call MI attach routines. 1033 */ 1034 if_attach(ifp); 1035 ether_ifattach(ifp); 1036 1037 DPRINTFN(2, ("msk_attach: end\n")); 1038 return; 1039 1040 fail_4: 1041 for (i = 0; i < MSK_RX_RING_CNT; i++) { 1042 if (sc_if->sk_cdata.sk_rx_map[i] != NULL) 1043 bus_dmamap_destroy(sc->sc_dmatag, 1044 sc_if->sk_cdata.sk_rx_map[i]); 1045 } 1046 1047 fail_3: 1048 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1049 fail_2: 1050 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1051 fail_1: 1052 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1053 fail: 1054 sc->sk_if[sa->skc_port] = NULL; 1055 } 1056 1057 int 1058 msk_detach(struct device *self, int flags) 1059 { 1060 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1061 struct sk_softc *sc = sc_if->sk_softc; 1062 struct ifnet *ifp= &sc_if->arpcom.ac_if; 1063 1064 if (sc->sk_if[sc_if->sk_port] == NULL) 1065 return (0); 1066 1067 msk_stop(sc_if, 1); 1068 1069 /* Detach any PHYs we might have. */ 1070 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1071 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1072 1073 /* Delete any remaining media. */ 1074 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1075 1076 ether_ifdetach(ifp); 1077 if_detach(ifp); 1078 1079 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc_if->sk_rdata, 1080 sizeof(struct msk_ring_data)); 1081 bus_dmamem_free(sc->sc_dmatag, 1082 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1083 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1084 sc->sk_if[sc_if->sk_port] = NULL; 1085 1086 return (0); 1087 } 1088 1089 int 1090 msk_activate(struct device *self, int act) 1091 { 1092 struct sk_if_softc *sc_if = (void *)self; 1093 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1094 int rv = 0; 1095 1096 switch (act) { 1097 case DVACT_RESUME: 1098 msk_reset(sc_if); 1099 if (ifp->if_flags & IFF_RUNNING) 1100 msk_init(sc_if); 1101 break; 1102 default: 1103 rv = config_activate_children(self, act); 1104 break; 1105 } 1106 return (rv); 1107 } 1108 1109 int 1110 mskcprint(void *aux, const char *pnp) 1111 { 1112 struct skc_attach_args *sa = aux; 1113 1114 if (pnp) 1115 printf("msk port %c at %s", 1116 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1117 else 1118 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1119 return (UNCONF); 1120 } 1121 1122 /* 1123 * Attach the interface. Allocate softc structures, do ifmedia 1124 * setup and ethernet/BPF attach. 1125 */ 1126 void 1127 mskc_attach(struct device *parent, struct device *self, void *aux) 1128 { 1129 struct sk_softc *sc = (struct sk_softc *)self; 1130 struct pci_attach_args *pa = aux; 1131 struct skc_attach_args skca; 1132 pci_chipset_tag_t pc = pa->pa_pc; 1133 pcireg_t memtype; 1134 pci_intr_handle_t ih; 1135 const char *intrstr = NULL; 1136 u_int8_t hw, pmd; 1137 char *revstr = NULL; 1138 caddr_t kva; 1139 1140 DPRINTFN(2, ("begin mskc_attach\n")); 1141 1142 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 1143 1144 /* 1145 * Map control/status registers. 1146 */ 1147 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1148 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1149 &sc->sk_bhandle, NULL, &sc->sk_bsize, 0)) { 1150 printf(": can't map mem space\n"); 1151 return; 1152 } 1153 1154 sc->sc_dmatag = pa->pa_dmat; 1155 1156 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1157 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1158 1159 /* bail out here if chip is not recognized */ 1160 if (!(SK_IS_YUKON2(sc))) { 1161 printf(": unknown chip type: %d\n", sc->sk_type); 1162 goto fail_1; 1163 } 1164 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1165 1166 /* Allocate interrupt */ 1167 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 1168 printf(": couldn't map interrupt\n"); 1169 goto fail_1; 1170 } 1171 1172 intrstr = pci_intr_string(pc, ih); 1173 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc, 1174 self->dv_xname); 1175 if (sc->sk_intrhand == NULL) { 1176 printf(": couldn't establish interrupt"); 1177 if (intrstr != NULL) 1178 printf(" at %s", intrstr); 1179 printf("\n"); 1180 goto fail_1; 1181 } 1182 sc->sk_pc = pc; 1183 1184 if (bus_dmamem_alloc(sc->sc_dmatag, 1185 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1186 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1187 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, 1188 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 1189 printf(": can't alloc status buffers\n"); 1190 goto fail_2; 1191 } 1192 1193 if (bus_dmamem_map(sc->sc_dmatag, 1194 &sc->sk_status_seg, sc->sk_status_nseg, 1195 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1196 &kva, BUS_DMA_NOWAIT)) { 1197 printf(": can't map dma buffers (%lu bytes)\n", 1198 (ulong)(MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc))); 1199 goto fail_3; 1200 } 1201 if (bus_dmamap_create(sc->sc_dmatag, 1202 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1203 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1204 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1205 printf(": can't create dma map\n"); 1206 goto fail_4; 1207 } 1208 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1209 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1210 NULL, BUS_DMA_NOWAIT)) { 1211 printf(": can't load dma map\n"); 1212 goto fail_5; 1213 } 1214 sc->sk_status_ring = (struct msk_status_desc *)kva; 1215 1216 /* Reset the adapter. */ 1217 mskc_reset(sc); 1218 1219 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1220 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1221 1222 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1223 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1224 sc->sk_fibertype = 1; 1225 1226 switch (sc->sk_type) { 1227 case SK_YUKON_XL: 1228 sc->sk_name = "Yukon-2 XL"; 1229 break; 1230 case SK_YUKON_EC_U: 1231 sc->sk_name = "Yukon-2 EC Ultra"; 1232 break; 1233 case SK_YUKON_EX: 1234 sc->sk_name = "Yukon-2 Extreme"; 1235 break; 1236 case SK_YUKON_EC: 1237 sc->sk_name = "Yukon-2 EC"; 1238 break; 1239 case SK_YUKON_FE: 1240 sc->sk_name = "Yukon-2 FE"; 1241 break; 1242 case SK_YUKON_FE_P: 1243 sc->sk_name = "Yukon-2 FE+"; 1244 break; 1245 case SK_YUKON_SUPR: 1246 sc->sk_name = "Yukon-2 Supreme"; 1247 break; 1248 case SK_YUKON_ULTRA2: 1249 sc->sk_name = "Yukon-2 Ultra 2"; 1250 break; 1251 case SK_YUKON_OPTIMA: 1252 sc->sk_name = "Yukon-2 Optima"; 1253 break; 1254 case SK_YUKON_PRM: 1255 sc->sk_name = "Yukon-2 Optima Prime"; 1256 break; 1257 case SK_YUKON_OPTIMA2: 1258 sc->sk_name = "Yukon-2 Optima 2"; 1259 break; 1260 default: 1261 sc->sk_name = "Yukon (Unknown)"; 1262 } 1263 1264 if (sc->sk_type == SK_YUKON_XL) { 1265 switch (sc->sk_rev) { 1266 case SK_YUKON_XL_REV_A0: 1267 revstr = "A0"; 1268 break; 1269 case SK_YUKON_XL_REV_A1: 1270 revstr = "A1"; 1271 break; 1272 case SK_YUKON_XL_REV_A2: 1273 revstr = "A2"; 1274 break; 1275 case SK_YUKON_XL_REV_A3: 1276 revstr = "A3"; 1277 break; 1278 default: 1279 ; 1280 } 1281 } 1282 1283 if (sc->sk_type == SK_YUKON_EC) { 1284 switch (sc->sk_rev) { 1285 case SK_YUKON_EC_REV_A1: 1286 revstr = "A1"; 1287 break; 1288 case SK_YUKON_EC_REV_A2: 1289 revstr = "A2"; 1290 break; 1291 case SK_YUKON_EC_REV_A3: 1292 revstr = "A3"; 1293 break; 1294 default: 1295 ; 1296 } 1297 } 1298 1299 if (sc->sk_type == SK_YUKON_EC_U) { 1300 switch (sc->sk_rev) { 1301 case SK_YUKON_EC_U_REV_A0: 1302 revstr = "A0"; 1303 break; 1304 case SK_YUKON_EC_U_REV_A1: 1305 revstr = "A1"; 1306 break; 1307 case SK_YUKON_EC_U_REV_B0: 1308 revstr = "B0"; 1309 break; 1310 case SK_YUKON_EC_U_REV_B1: 1311 revstr = "B1"; 1312 break; 1313 default: 1314 ; 1315 } 1316 } 1317 1318 if (sc->sk_type == SK_YUKON_FE) { 1319 switch (sc->sk_rev) { 1320 case SK_YUKON_FE_REV_A1: 1321 revstr = "A1"; 1322 break; 1323 case SK_YUKON_FE_REV_A2: 1324 revstr = "A2"; 1325 break; 1326 default: 1327 ; 1328 } 1329 } 1330 1331 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1332 revstr = "A0"; 1333 1334 if (sc->sk_type == SK_YUKON_EX) { 1335 switch (sc->sk_rev) { 1336 case SK_YUKON_EX_REV_A0: 1337 revstr = "A0"; 1338 break; 1339 case SK_YUKON_EX_REV_B0: 1340 revstr = "B0"; 1341 break; 1342 default: 1343 ; 1344 } 1345 } 1346 1347 if (sc->sk_type == SK_YUKON_SUPR) { 1348 switch (sc->sk_rev) { 1349 case SK_YUKON_SUPR_REV_A0: 1350 revstr = "A0"; 1351 break; 1352 case SK_YUKON_SUPR_REV_B0: 1353 revstr = "B0"; 1354 break; 1355 case SK_YUKON_SUPR_REV_B1: 1356 revstr = "B1"; 1357 break; 1358 default: 1359 ; 1360 } 1361 } 1362 1363 if (sc->sk_type == SK_YUKON_PRM) { 1364 switch (sc->sk_rev) { 1365 case SK_YUKON_PRM_REV_Z1: 1366 revstr = "Z1"; 1367 break; 1368 case SK_YUKON_PRM_REV_A0: 1369 revstr = "A0"; 1370 break; 1371 default: 1372 ; 1373 } 1374 } 1375 1376 /* Announce the product name. */ 1377 printf(", %s", sc->sk_name); 1378 if (revstr != NULL) 1379 printf(" rev. %s", revstr); 1380 printf(" (0x%x): %s\n", sc->sk_rev, intrstr); 1381 1382 sc->sk_macs = 1; 1383 1384 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1385 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1386 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1387 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1388 sc->sk_macs++; 1389 } 1390 1391 skca.skc_port = SK_PORT_A; 1392 skca.skc_type = sc->sk_type; 1393 skca.skc_rev = sc->sk_rev; 1394 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1395 1396 if (sc->sk_macs > 1) { 1397 skca.skc_port = SK_PORT_B; 1398 skca.skc_type = sc->sk_type; 1399 skca.skc_rev = sc->sk_rev; 1400 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1401 } 1402 1403 /* Turn on the 'driver is loaded' LED. */ 1404 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1405 1406 return; 1407 1408 fail_4: 1409 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1410 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1411 fail_3: 1412 bus_dmamem_free(sc->sc_dmatag, 1413 &sc->sk_status_seg, sc->sk_status_nseg); 1414 sc->sk_status_nseg = 0; 1415 fail_5: 1416 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1417 fail_2: 1418 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1419 sc->sk_intrhand = NULL; 1420 fail_1: 1421 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1422 sc->sk_bsize = 0; 1423 } 1424 1425 int 1426 mskc_detach(struct device *self, int flags) 1427 { 1428 struct sk_softc *sc = (struct sk_softc *)self; 1429 int rv; 1430 1431 if (sc->sk_intrhand) 1432 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1433 1434 rv = config_detach_children(self, flags); 1435 if (rv != 0) 1436 return (rv); 1437 1438 if (sc->sk_status_nseg > 0) { 1439 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1440 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1441 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1442 bus_dmamem_free(sc->sc_dmatag, 1443 &sc->sk_status_seg, sc->sk_status_nseg); 1444 } 1445 1446 if (sc->sk_bsize > 0) 1447 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1448 1449 return(0); 1450 } 1451 1452 int 1453 mskc_activate(struct device *self, int act) 1454 { 1455 struct sk_softc *sc = (void *)self; 1456 int rv = 0; 1457 1458 switch (act) { 1459 case DVACT_RESUME: 1460 mskc_reset(sc); 1461 rv = config_activate_children(self, act); 1462 break; 1463 default: 1464 rv = config_activate_children(self, act); 1465 break; 1466 } 1467 return (rv); 1468 } 1469 1470 int 1471 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1472 { 1473 struct sk_softc *sc = sc_if->sk_softc; 1474 struct msk_tx_desc *f = NULL; 1475 u_int32_t frag, cur; 1476 int i, entries = 0; 1477 struct sk_txmap_entry *entry; 1478 bus_dmamap_t txmap; 1479 uint64_t addr; 1480 uint32_t hiaddr; 1481 uint8_t opcode; 1482 1483 DPRINTFN(2, ("msk_encap\n")); 1484 1485 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1486 if (entry == NULL) { 1487 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1488 return (ENOBUFS); 1489 } 1490 txmap = entry->dmamap; 1491 1492 cur = frag = *txidx; 1493 1494 switch (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1495 BUS_DMA_STREAMING | BUS_DMA_NOWAIT)) { 1496 case 0: 1497 break; 1498 case EFBIG: /* mbuf chain is too fragmented */ 1499 if (m_defrag(m_head, M_DONTWAIT) == 0 && 1500 bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1501 BUS_DMA_STREAMING | BUS_DMA_NOWAIT) == 0) 1502 break; 1503 /* FALLTHROUGH */ 1504 default: 1505 return (1); 1506 } 1507 1508 /* Sync the DMA map. */ 1509 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1510 BUS_DMASYNC_PREWRITE); 1511 1512 opcode = 0; 1513 for (i = 0; i < txmap->dm_nsegs; i++) { 1514 /* high 32 bits of address */ 1515 addr = txmap->dm_segs[i].ds_addr; 1516 hiaddr = addr >> 32; 1517 if (sc_if->sk_tx_hiaddr != hiaddr) { 1518 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1519 f->sk_addr = htole32(hiaddr); 1520 f->sk_opcode = opcode | SK_Y2_TXOPC_ADDR64; 1521 1522 sc_if->sk_tx_hiaddr = hiaddr; 1523 1524 SK_INC(frag, MSK_TX_RING_CNT); 1525 opcode = SK_Y2_TXOPC_OWN; 1526 entries++; 1527 } 1528 1529 /* low 32 bits of address + length */ 1530 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1531 f->sk_addr = htole32(addr); 1532 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1533 f->sk_ctl = 0; 1534 f->sk_opcode = opcode | 1535 (i == 0 ? SK_Y2_TXOPC_PACKET : SK_Y2_TXOPC_BUFFER); 1536 cur = frag; 1537 1538 SK_INC(frag, MSK_TX_RING_CNT); 1539 opcode = SK_Y2_TXOPC_OWN; 1540 entries++; 1541 } 1542 1543 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1544 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1545 1546 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1547 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1548 1549 /* Sync descriptors before handing to chip */ 1550 MSK_CDTXSYNC(sc_if, *txidx, entries, 1551 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1552 1553 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1554 1555 /* Sync first descriptor to hand it off */ 1556 MSK_CDTXSYNC(sc_if, *txidx, 1, 1557 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1558 1559 sc_if->sk_cdata.sk_tx_cnt += entries; 1560 1561 #ifdef MSK_DEBUG 1562 if (mskdebug >= 2) { 1563 struct msk_tx_desc *le; 1564 u_int32_t idx; 1565 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1566 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1567 msk_dump_txdesc(le, idx); 1568 } 1569 } 1570 #endif 1571 1572 *txidx = frag; 1573 1574 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1575 1576 return (0); 1577 } 1578 1579 void 1580 msk_start(struct ifnet *ifp) 1581 { 1582 struct sk_if_softc *sc_if = ifp->if_softc; 1583 struct mbuf *m_head = NULL; 1584 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1585 int post = 0; 1586 1587 for (;;) { 1588 if (sc_if->sk_cdata.sk_tx_cnt + (SK_NTXSEG * 2) + 1 > 1589 MSK_TX_RING_CNT) { 1590 ifq_set_oactive(&ifp->if_snd); 1591 break; 1592 } 1593 1594 m_head = ifq_dequeue(&ifp->if_snd); 1595 if (m_head == NULL) 1596 break; 1597 1598 /* 1599 * Pack the data into the transmit ring. If we 1600 * don't have room, set the OACTIVE flag and wait 1601 * for the NIC to drain the ring. 1602 */ 1603 if (msk_encap(sc_if, m_head, &idx)) { 1604 m_freem(m_head); 1605 continue; 1606 } 1607 1608 /* now we are committed to transmit the packet */ 1609 1610 /* 1611 * If there's a BPF listener, bounce a copy of this frame 1612 * to him. 1613 */ 1614 #if NBPFILTER > 0 1615 if (ifp->if_bpf) 1616 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1617 #endif 1618 post = 1; 1619 } 1620 if (post == 0) 1621 return; 1622 1623 /* Transmit */ 1624 sc_if->sk_cdata.sk_tx_prod = idx; 1625 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1626 1627 /* Set a timeout in case the chip goes out to lunch. */ 1628 ifp->if_timer = MSK_TX_TIMEOUT; 1629 } 1630 1631 void 1632 msk_watchdog(struct ifnet *ifp) 1633 { 1634 struct sk_if_softc *sc_if = ifp->if_softc; 1635 1636 /* 1637 * Reclaim first as there is a possibility of losing Tx completion 1638 * interrupts. 1639 */ 1640 msk_txeof(sc_if); 1641 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1642 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1643 1644 ifp->if_oerrors++; 1645 1646 /* XXX Resets both ports; we shouldn't do that. */ 1647 mskc_reset(sc_if->sk_softc); 1648 msk_reset(sc_if); 1649 msk_init(sc_if); 1650 } 1651 } 1652 1653 static __inline int 1654 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1655 { 1656 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1657 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1658 YU_RXSTAT_JABBER)) != 0 || 1659 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1660 YU_RXSTAT_BYTES(stat) != len) 1661 return (0); 1662 1663 return (1); 1664 } 1665 1666 void 1667 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1668 { 1669 struct sk_softc *sc = sc_if->sk_softc; 1670 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1671 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1672 struct mbuf *m; 1673 struct sk_chain *cur_rx; 1674 int i, cur, total_len = len; 1675 bus_dmamap_t dmamap; 1676 1677 DPRINTFN(2, ("msk_rxeof\n")); 1678 1679 cur = sc_if->sk_cdata.sk_rx_cons; 1680 1681 /* Sync the descriptor */ 1682 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1683 1684 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1685 if (cur_rx->sk_mbuf == NULL) 1686 return; 1687 1688 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1689 for (i = 0; i < dmamap->dm_nsegs; i++) { 1690 /* each segment consumes two slots on the ring */ 1691 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1692 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1693 } 1694 if_rxr_put(&sc_if->sk_cdata.sk_rx_ring, dmamap->dm_nsegs); 1695 1696 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1697 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1698 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap); 1699 1700 m = cur_rx->sk_mbuf; 1701 cur_rx->sk_mbuf = NULL; 1702 1703 if (total_len < SK_MIN_FRAMELEN || 1704 total_len > SK_JUMBO_FRAMELEN || 1705 msk_rxvalid(sc, rxstat, total_len) == 0) { 1706 ifp->if_ierrors++; 1707 m_freem(m); 1708 return; 1709 } 1710 1711 m->m_pkthdr.len = m->m_len = total_len; 1712 1713 ml_enqueue(&ml, m); 1714 if_input(ifp, &ml); 1715 } 1716 1717 void 1718 msk_txeof(struct sk_if_softc *sc_if) 1719 { 1720 struct sk_softc *sc = sc_if->sk_softc; 1721 struct msk_tx_desc *cur_tx; 1722 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1723 u_int32_t idx, reg, sk_ctl; 1724 struct sk_txmap_entry *entry; 1725 1726 DPRINTFN(2, ("msk_txeof\n")); 1727 1728 if (sc_if->sk_port == SK_PORT_A) 1729 reg = SK_STAT_BMU_TXA1_RIDX; 1730 else 1731 reg = SK_STAT_BMU_TXA2_RIDX; 1732 1733 /* 1734 * Go through our tx ring and free mbufs for those 1735 * frames that have been sent. 1736 */ 1737 idx = sc_if->sk_cdata.sk_tx_cons; 1738 while (idx != sk_win_read_2(sc, reg)) { 1739 MSK_CDTXSYNC(sc_if, idx, 1, 1740 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1741 1742 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1743 sk_ctl = cur_tx->sk_ctl; 1744 #ifdef MSK_DEBUG 1745 if (mskdebug >= 2) 1746 msk_dump_txdesc(cur_tx, idx); 1747 #endif 1748 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1749 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1750 1751 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1752 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1753 1754 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1755 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1756 1757 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1758 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1759 link); 1760 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1761 } 1762 sc_if->sk_cdata.sk_tx_cnt--; 1763 SK_INC(idx, MSK_TX_RING_CNT); 1764 } 1765 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? MSK_TX_TIMEOUT : 0; 1766 1767 sc_if->sk_cdata.sk_tx_cons = idx; 1768 1769 if (ifq_is_oactive(&ifp->if_snd)) 1770 ifq_restart(&ifp->if_snd); 1771 } 1772 1773 void 1774 msk_fill_rx_ring(struct sk_if_softc *sc_if) 1775 { 1776 u_int slots, used; 1777 1778 slots = if_rxr_get(&sc_if->sk_cdata.sk_rx_ring, MSK_RX_RING_CNT/2); 1779 while (slots > 0) { 1780 used = msk_newbuf(sc_if); 1781 if (used == 0) 1782 break; 1783 1784 slots -= used; 1785 } 1786 if_rxr_put(&sc_if->sk_cdata.sk_rx_ring, slots); 1787 } 1788 1789 void 1790 msk_tick(void *xsc_if) 1791 { 1792 struct sk_if_softc *sc_if = xsc_if; 1793 struct mii_data *mii = &sc_if->sk_mii; 1794 int s; 1795 1796 s = splnet(); 1797 mii_tick(mii); 1798 splx(s); 1799 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1800 } 1801 1802 void 1803 msk_intr_yukon(struct sk_if_softc *sc_if) 1804 { 1805 u_int8_t status; 1806 1807 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1808 /* RX overrun */ 1809 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1810 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1811 SK_RFCTL_RX_FIFO_OVER); 1812 } 1813 /* TX underrun */ 1814 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1815 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1816 SK_TFCTL_TX_FIFO_UNDER); 1817 } 1818 1819 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1820 } 1821 1822 int 1823 msk_intr(void *xsc) 1824 { 1825 struct sk_softc *sc = xsc; 1826 struct sk_if_softc *sc_if; 1827 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1828 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1829 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1830 int claimed = 0, rx[2] = {0, 0}; 1831 u_int32_t status; 1832 struct msk_status_desc *cur_st; 1833 1834 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1835 if (status == 0xffffffff) 1836 return (0); 1837 if (status == 0) { 1838 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1839 return (0); 1840 } 1841 1842 status = CSR_READ_4(sc, SK_ISR); 1843 1844 if (sc_if0 != NULL) 1845 ifp0 = &sc_if0->arpcom.ac_if; 1846 if (sc_if1 != NULL) 1847 ifp1 = &sc_if1->arpcom.ac_if; 1848 1849 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1850 (ifp0->if_flags & IFF_RUNNING)) { 1851 msk_intr_yukon(sc_if0); 1852 } 1853 1854 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1855 (ifp1->if_flags & IFF_RUNNING)) { 1856 msk_intr_yukon(sc_if1); 1857 } 1858 1859 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1860 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1861 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1862 1863 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1864 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1865 switch (cur_st->sk_opcode) { 1866 case SK_Y2_STOPC_RXSTAT: 1867 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 1868 rx[cur_st->sk_link & 0x01] = 1; 1869 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 1870 letoh32(cur_st->sk_status)); 1871 break; 1872 case SK_Y2_STOPC_TXSTAT: 1873 if (sc_if0) 1874 msk_txeof(sc_if0); 1875 if (sc_if1) 1876 msk_txeof(sc_if1); 1877 break; 1878 default: 1879 printf("opcode=0x%x\n", cur_st->sk_opcode); 1880 break; 1881 } 1882 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1883 1884 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1885 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1886 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1887 } 1888 1889 if (status & SK_Y2_IMR_BMU) { 1890 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1891 claimed = 1; 1892 } 1893 1894 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1895 1896 if (rx[0]) { 1897 msk_fill_rx_ring(sc_if0); 1898 SK_IF_WRITE_2(sc_if0, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1899 sc_if0->sk_cdata.sk_rx_prod); 1900 } 1901 if (rx[1]) { 1902 msk_fill_rx_ring(sc_if1); 1903 SK_IF_WRITE_2(sc_if1, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1904 sc_if1->sk_cdata.sk_rx_prod); 1905 } 1906 1907 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1908 msk_start(ifp0); 1909 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1910 msk_start(ifp1); 1911 1912 return (claimed); 1913 } 1914 1915 void 1916 msk_init_yukon(struct sk_if_softc *sc_if) 1917 { 1918 u_int32_t v; 1919 u_int16_t reg; 1920 struct sk_softc *sc; 1921 int i; 1922 1923 sc = sc_if->sk_softc; 1924 1925 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1926 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1927 1928 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1929 1930 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1931 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1932 1933 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1934 1935 /* unused read of the interrupt source register */ 1936 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1937 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1938 1939 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1940 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1941 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1942 1943 /* MIB Counter Clear Mode set */ 1944 reg |= YU_PAR_MIB_CLR; 1945 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1946 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1947 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1948 1949 /* MIB Counter Clear Mode clear */ 1950 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1951 reg &= ~YU_PAR_MIB_CLR; 1952 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1953 1954 /* receive control reg */ 1955 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1956 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1957 1958 /* transmit parameter register */ 1959 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1960 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1961 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 1962 1963 /* serial mode register */ 1964 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1965 reg = YU_SMR_DATA_BLIND(0x1c) | 1966 YU_SMR_MFL_VLAN | 1967 YU_SMR_IPG_DATA(0x1e); 1968 1969 if (sc->sk_type != SK_YUKON_FE && 1970 sc->sk_type != SK_YUKON_FE_P) 1971 reg |= YU_SMR_MFL_JUMBO; 1972 1973 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 1974 1975 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1976 /* Setup Yukon's address */ 1977 for (i = 0; i < 3; i++) { 1978 /* Write Source Address 1 (unicast filter) */ 1979 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 1980 sc_if->arpcom.ac_enaddr[i * 2] | 1981 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 1982 } 1983 1984 for (i = 0; i < 3; i++) { 1985 reg = sk_win_read_2(sc_if->sk_softc, 1986 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 1987 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 1988 } 1989 1990 /* Program promiscuous mode and multicast filters */ 1991 DPRINTFN(6, ("msk_init_yukon: 11\n")); 1992 msk_iff(sc_if); 1993 1994 /* enable interrupt mask for counter overflows */ 1995 DPRINTFN(6, ("msk_init_yukon: 12\n")); 1996 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 1997 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 1998 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 1999 2000 /* Configure RX MAC FIFO Flush Mask */ 2001 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2002 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2003 YU_RXSTAT_JABBER; 2004 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2005 2006 /* Configure RX MAC FIFO */ 2007 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2008 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2009 SK_RFCTL_FIFO_FLUSH_ON); 2010 2011 /* Increase flush threshould to 64 bytes */ 2012 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2013 SK_RFCTL_FIFO_THRESHOLD + 1); 2014 2015 /* Configure TX MAC FIFO */ 2016 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2017 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2018 2019 #if 1 2020 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2021 #endif 2022 DPRINTFN(6, ("msk_init_yukon: end\n")); 2023 } 2024 2025 /* 2026 * Note that to properly initialize any part of the GEnesis chip, 2027 * you first have to take it out of reset mode. 2028 */ 2029 void 2030 msk_init(void *xsc_if) 2031 { 2032 struct sk_if_softc *sc_if = xsc_if; 2033 struct sk_softc *sc = sc_if->sk_softc; 2034 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2035 struct mii_data *mii = &sc_if->sk_mii; 2036 int s; 2037 2038 DPRINTFN(2, ("msk_init\n")); 2039 2040 s = splnet(); 2041 2042 /* Cancel pending I/O and free all RX/TX buffers. */ 2043 msk_stop(sc_if, 0); 2044 2045 /* Configure I2C registers */ 2046 2047 /* Configure XMAC(s) */ 2048 msk_init_yukon(sc_if); 2049 mii_mediachg(mii); 2050 2051 sc_if->sk_tx_hiaddr = 0; 2052 2053 /* Configure transmit arbiter(s) */ 2054 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2055 #if 0 2056 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2057 #endif 2058 2059 /* Configure RAMbuffers */ 2060 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2061 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2062 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2063 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2064 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2065 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2066 2067 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2068 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2069 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2070 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2071 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2072 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2073 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2074 2075 /* Configure BMUs */ 2076 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2077 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2078 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2079 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_WATERMARK, 0x00000600); 2080 2081 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2082 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2083 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2084 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_WATERMARK, 0x00000600); 2085 2086 /* Make sure the sync transmit queue is disabled. */ 2087 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2088 2089 /* Init descriptors */ 2090 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2091 printf("%s: initialization failed: no " 2092 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2093 msk_stop(sc_if, 0); 2094 splx(s); 2095 return; 2096 } 2097 2098 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2099 printf("%s: initialization failed: no " 2100 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2101 msk_stop(sc_if, 0); 2102 splx(s); 2103 return; 2104 } 2105 2106 /* Initialize prefetch engine. */ 2107 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2108 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2109 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2110 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2111 MSK_RX_RING_ADDR(sc_if, 0)); 2112 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2113 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2114 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2115 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2116 2117 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2118 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2119 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2120 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2121 MSK_TX_RING_ADDR(sc_if, 0)); 2122 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2123 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2124 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2125 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2126 2127 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2128 sc_if->sk_cdata.sk_rx_prod); 2129 2130 /* Configure interrupt handling */ 2131 if (sc_if->sk_port == SK_PORT_A) 2132 sc->sk_intrmask |= SK_Y2_INTRS1; 2133 else 2134 sc->sk_intrmask |= SK_Y2_INTRS2; 2135 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2136 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2137 2138 ifp->if_flags |= IFF_RUNNING; 2139 ifq_clr_oactive(&ifp->if_snd); 2140 2141 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2142 2143 splx(s); 2144 } 2145 2146 void 2147 msk_stop(struct sk_if_softc *sc_if, int softonly) 2148 { 2149 struct sk_softc *sc = sc_if->sk_softc; 2150 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2151 struct sk_txmap_entry *dma; 2152 int i; 2153 2154 DPRINTFN(2, ("msk_stop\n")); 2155 2156 timeout_del(&sc_if->sk_tick_ch); 2157 2158 ifp->if_flags &= ~IFF_RUNNING; 2159 ifq_clr_oactive(&ifp->if_snd); 2160 2161 /* Stop transfer of Tx descriptors */ 2162 2163 /* Stop transfer of Rx descriptors */ 2164 2165 if (!softonly) { 2166 /* Turn off various components of this interface. */ 2167 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2168 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2169 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2170 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2171 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2172 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2173 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2174 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2175 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2176 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2177 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2178 2179 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2180 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2181 2182 /* Disable interrupts */ 2183 if (sc_if->sk_port == SK_PORT_A) 2184 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2185 else 2186 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2187 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2188 } 2189 2190 /* Free RX and TX mbufs still in the queues. */ 2191 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2192 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2193 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2194 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2195 } 2196 } 2197 2198 sc_if->sk_cdata.sk_rx_prod = 0; 2199 sc_if->sk_cdata.sk_rx_cons = 0; 2200 2201 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2202 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2203 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2204 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2205 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2206 sc_if->sk_cdata.sk_tx_map[i], link); 2207 sc_if->sk_cdata.sk_tx_map[i] = 0; 2208 } 2209 } 2210 2211 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2212 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2213 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2214 free(dma, M_DEVBUF, sizeof *dma); 2215 } 2216 } 2217 2218 struct cfattach mskc_ca = { 2219 sizeof(struct sk_softc), mskc_probe, mskc_attach, mskc_detach, 2220 mskc_activate 2221 }; 2222 2223 struct cfdriver mskc_cd = { 2224 NULL, "mskc", DV_DULL 2225 }; 2226 2227 struct cfattach msk_ca = { 2228 sizeof(struct sk_if_softc), msk_probe, msk_attach, msk_detach, 2229 msk_activate 2230 }; 2231 2232 struct cfdriver msk_cd = { 2233 NULL, "msk", DV_IFNET 2234 }; 2235 2236 #ifdef MSK_DEBUG 2237 void 2238 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2239 { 2240 #define DESC_PRINT(X) \ 2241 if (X) \ 2242 printf("txdesc[%d]." #X "=%#x\n", \ 2243 idx, X); 2244 2245 DESC_PRINT(letoh32(le->sk_addr)); 2246 DESC_PRINT(letoh16(le->sk_len)); 2247 DESC_PRINT(le->sk_ctl); 2248 DESC_PRINT(le->sk_opcode); 2249 #undef DESC_PRINT 2250 } 2251 2252 void 2253 msk_dump_bytes(const char *data, int len) 2254 { 2255 int c, i, j; 2256 2257 for (i = 0; i < len; i += 16) { 2258 printf("%08x ", i); 2259 c = len - i; 2260 if (c > 16) c = 16; 2261 2262 for (j = 0; j < c; j++) { 2263 printf("%02x ", data[i + j] & 0xff); 2264 if ((j & 0xf) == 7 && j > 0) 2265 printf(" "); 2266 } 2267 2268 for (; j < 16; j++) 2269 printf(" "); 2270 printf(" "); 2271 2272 for (j = 0; j < c; j++) { 2273 int ch = data[i + j] & 0xff; 2274 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2275 } 2276 2277 printf("\n"); 2278 2279 if (c < 16) 2280 break; 2281 } 2282 } 2283 2284 void 2285 msk_dump_mbuf(struct mbuf *m) 2286 { 2287 int count = m->m_pkthdr.len; 2288 2289 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2290 2291 while (count > 0 && m) { 2292 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2293 m, m->m_data, m->m_len); 2294 msk_dump_bytes(mtod(m, char *), m->m_len); 2295 2296 count -= m->m_len; 2297 m = m->m_next; 2298 } 2299 } 2300 #endif 2301