1 /* $OpenBSD: if_pcn.c,v 1.41 2016/04/13 10:34:32 mpi Exp $ */ 2 /* $NetBSD: if_pcn.c,v 1.26 2005/05/07 09:15:44 is Exp $ */ 3 4 /* 5 * Copyright (c) 2001 Wasabi Systems, Inc. 6 * All rights reserved. 7 * 8 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * Wasabi Systems, Inc. 22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the AMD PCnet-PCI series of Ethernet 41 * chips: 42 * 43 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 44 * Local Bus 45 * 46 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 47 * for PCI Local Bus 48 * 49 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 50 * Ethernet Controller for PCI Local Bus 51 * 52 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 53 * with OnNow Support 54 * 55 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 56 * Ethernet Controller with Integrated PHY 57 * 58 * This also supports the virtual PCnet-PCI Ethernet interface found 59 * in VMware. 60 * 61 * TODO: 62 * 63 * * Split this into bus-specific and bus-independent portions. 64 * The core could also be used for the ILACC (Am79900) 32-bit 65 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 66 */ 67 68 #include "bpfilter.h" 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/timeout.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/ioctl.h> 78 #include <sys/errno.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/endian.h> 82 83 #include <net/if.h> 84 #include <net/if_dl.h> 85 86 #include <netinet/in.h> 87 #include <netinet/if_ether.h> 88 89 #include <net/if_media.h> 90 91 #if NBPFILTER > 0 92 #include <net/bpf.h> 93 #endif 94 95 #include <machine/bus.h> 96 #include <machine/intr.h> 97 98 #include <dev/mii/miivar.h> 99 100 #include <dev/ic/am79900reg.h> 101 #include <dev/ic/lancereg.h> 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcidevs.h> 106 107 /* 108 * Register definitions for the AMD PCnet-PCI series of Ethernet 109 * chips. 110 * 111 * These are only the registers that we access directly from PCI 112 * space. Everything else (accessed via the RAP + RDP/BDP) is 113 * defined in <dev/ic/lancereg.h>. 114 */ 115 116 /* 117 * PCI configuration space. 118 */ 119 120 #define PCN_PCI_CBIO (PCI_MAPREG_START + 0x00) 121 #define PCN_PCI_CBMEM (PCI_MAPREG_START + 0x04) 122 123 /* 124 * I/O map in Word I/O mode. 125 */ 126 127 #define PCN16_APROM 0x00 128 #define PCN16_RDP 0x10 129 #define PCN16_RAP 0x12 130 #define PCN16_RESET 0x14 131 #define PCN16_BDP 0x16 132 133 /* 134 * I/O map in DWord I/O mode. 135 */ 136 137 #define PCN32_APROM 0x00 138 #define PCN32_RDP 0x10 139 #define PCN32_RAP 0x14 140 #define PCN32_RESET 0x18 141 #define PCN32_BDP 0x1c 142 143 /* 144 * Transmit descriptor list size. This is arbitrary, but allocate 145 * enough descriptors for 128 pending transmissions, and 4 segments 146 * per packet. This MUST work out to a power of 2. 147 * 148 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 149 * 150 * So we play a little trick here. We give each packet up to 16 151 * DMA segments, but only allocate the max of 512 descriptors. The 152 * transmit logic can deal with this, we just are hoping to sneak by. 153 */ 154 #define PCN_NTXSEGS 16 155 156 #define PCN_TXQUEUELEN 128 157 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 158 #define PCN_NTXDESC 512 159 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 160 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 161 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 162 163 /* Tx interrupt every N + 1 packets. */ 164 #define PCN_TXINTR_MASK 7 165 166 /* 167 * Receive descriptor list size. We have one Rx buffer per incoming 168 * packet, so this logic is a little simpler. 169 */ 170 #define PCN_NRXDESC 128 171 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 172 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 173 174 /* 175 * Control structures are DMA'd to the PCnet chip. We allocate them in 176 * a single clump that maps to a single DMA segment to make several things 177 * easier. 178 */ 179 struct pcn_control_data { 180 /* The transmit descriptors. */ 181 struct letmd pcd_txdescs[PCN_NTXDESC]; 182 183 /* The receive descriptors. */ 184 struct lermd pcd_rxdescs[PCN_NRXDESC]; 185 186 /* The init block. */ 187 struct leinit pcd_initblock; 188 }; 189 190 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 191 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 192 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 193 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 194 195 /* 196 * Software state for transmit jobs. 197 */ 198 struct pcn_txsoft { 199 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 200 bus_dmamap_t txs_dmamap; /* our DMA map */ 201 int txs_firstdesc; /* first descriptor in packet */ 202 int txs_lastdesc; /* last descriptor in packet */ 203 }; 204 205 /* 206 * Software state for receive jobs. 207 */ 208 struct pcn_rxsoft { 209 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 210 bus_dmamap_t rxs_dmamap; /* our DMA map */ 211 }; 212 213 /* 214 * Description of Rx FIFO watermarks for various revisions. 215 */ 216 static const char * const pcn_79c970_rcvfw[] = { 217 "16 bytes", 218 "64 bytes", 219 "128 bytes", 220 NULL, 221 }; 222 223 static const char * const pcn_79c971_rcvfw[] = { 224 "16 bytes", 225 "64 bytes", 226 "112 bytes", 227 NULL, 228 }; 229 230 /* 231 * Description of Tx start points for various revisions. 232 */ 233 static const char * const pcn_79c970_xmtsp[] = { 234 "8 bytes", 235 "64 bytes", 236 "128 bytes", 237 "248 bytes", 238 }; 239 240 static const char * const pcn_79c971_xmtsp[] = { 241 "20 bytes", 242 "64 bytes", 243 "128 bytes", 244 "248 bytes", 245 }; 246 247 static const char * const pcn_79c971_xmtsp_sram[] = { 248 "44 bytes", 249 "64 bytes", 250 "128 bytes", 251 "store-and-forward", 252 }; 253 254 /* 255 * Description of Tx FIFO watermarks for various revisions. 256 */ 257 static const char * const pcn_79c970_xmtfw[] = { 258 "16 bytes", 259 "64 bytes", 260 "128 bytes", 261 NULL, 262 }; 263 264 static const char * const pcn_79c971_xmtfw[] = { 265 "16 bytes", 266 "64 bytes", 267 "108 bytes", 268 NULL, 269 }; 270 271 /* 272 * Software state per device. 273 */ 274 struct pcn_softc { 275 struct device sc_dev; /* generic device information */ 276 bus_space_tag_t sc_st; /* bus space tag */ 277 bus_space_handle_t sc_sh; /* bus space handle */ 278 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 279 struct arpcom sc_arpcom; /* Ethernet common data */ 280 281 /* Points to our media routines, etc. */ 282 const struct pcn_variant *sc_variant; 283 284 void *sc_ih; /* interrupt cookie */ 285 286 struct mii_data sc_mii; /* MII/media information */ 287 288 struct timeout sc_tick_timeout; /* tick timeout */ 289 290 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 291 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 292 293 /* Software state for transmit and receive descriptors. */ 294 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 295 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 296 297 /* Control data structures */ 298 struct pcn_control_data *sc_control_data; 299 #define sc_txdescs sc_control_data->pcd_txdescs 300 #define sc_rxdescs sc_control_data->pcd_rxdescs 301 #define sc_initblock sc_control_data->pcd_initblock 302 303 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 304 int sc_rcvfw; 305 306 const char * const *sc_xmtsp_desc; /* Tx start point info */ 307 int sc_xmtsp; 308 309 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 310 int sc_xmtfw; 311 312 int sc_flags; /* misc. flags; see below */ 313 int sc_swstyle; /* the software style in use */ 314 315 int sc_txfree; /* number of free Tx descriptors */ 316 int sc_txnext; /* next ready Tx descriptor */ 317 318 int sc_txsfree; /* number of free Tx jobs */ 319 int sc_txsnext; /* next free Tx job */ 320 int sc_txsdirty; /* dirty Tx jobs */ 321 322 int sc_rxptr; /* next ready Rx descriptor/job */ 323 324 uint32_t sc_csr5; /* prototype CSR5 register */ 325 uint32_t sc_mode; /* prototype MODE register */ 326 }; 327 328 /* sc_flags */ 329 #define PCN_F_HAS_MII 0x0001 /* has MII */ 330 331 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 332 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 333 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 334 335 #define PCN_CDTXSYNC(sc, x, n, ops) \ 336 do { \ 337 int __x, __n; \ 338 \ 339 __x = (x); \ 340 __n = (n); \ 341 \ 342 /* If it will wrap around, sync to the end of the ring. */ \ 343 if ((__x + __n) > PCN_NTXDESC) { \ 344 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 345 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 346 (PCN_NTXDESC - __x), (ops)); \ 347 __n -= (PCN_NTXDESC - __x); \ 348 __x = 0; \ 349 } \ 350 \ 351 /* Now sync whatever is left. */ \ 352 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 353 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 354 } while (/*CONSTCOND*/0) 355 356 #define PCN_CDRXSYNC(sc, x, ops) \ 357 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 358 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 359 360 #define PCN_CDINITSYNC(sc, ops) \ 361 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 362 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 363 364 #define PCN_INIT_RXDESC(sc, x) \ 365 do { \ 366 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 367 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 368 struct mbuf *__m = __rxs->rxs_mbuf; \ 369 \ 370 /* \ 371 * Note: We scoot the packet forward 2 bytes in the buffer \ 372 * so that the payload after the Ethernet header is aligned \ 373 * to a 4-byte boundary. \ 374 */ \ 375 __m->m_data = __m->m_ext.ext_buf + 2; \ 376 \ 377 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 378 __rmd->rmd2 = \ 379 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 380 __rmd->rmd0 = 0; \ 381 } else { \ 382 __rmd->rmd2 = 0; \ 383 __rmd->rmd0 = \ 384 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 385 } \ 386 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 387 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 388 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 389 } while(/*CONSTCOND*/0) 390 391 void pcn_start(struct ifnet *); 392 void pcn_watchdog(struct ifnet *); 393 int pcn_ioctl(struct ifnet *, u_long, caddr_t); 394 int pcn_init(struct ifnet *); 395 void pcn_stop(struct ifnet *, int); 396 397 void pcn_reset(struct pcn_softc *); 398 void pcn_rxdrain(struct pcn_softc *); 399 int pcn_add_rxbuf(struct pcn_softc *, int); 400 void pcn_tick(void *); 401 402 void pcn_spnd(struct pcn_softc *); 403 404 void pcn_set_filter(struct pcn_softc *); 405 406 int pcn_intr(void *); 407 void pcn_txintr(struct pcn_softc *); 408 int pcn_rxintr(struct pcn_softc *); 409 410 int pcn_mii_readreg(struct device *, int, int); 411 void pcn_mii_writereg(struct device *, int, int, int); 412 void pcn_mii_statchg(struct device *); 413 414 void pcn_79c970_mediainit(struct pcn_softc *); 415 int pcn_79c970_mediachange(struct ifnet *); 416 void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 417 418 void pcn_79c971_mediainit(struct pcn_softc *); 419 int pcn_79c971_mediachange(struct ifnet *); 420 void pcn_79c971_mediastatus(struct ifnet *, struct ifmediareq *); 421 422 /* 423 * Description of a PCnet-PCI variant. Used to select media access 424 * method, mostly, and to print a nice description of the chip. 425 */ 426 static const struct pcn_variant { 427 const char *pcv_desc; 428 void (*pcv_mediainit)(struct pcn_softc *); 429 uint16_t pcv_chipid; 430 } pcn_variants[] = { 431 { "Am79c970", 432 pcn_79c970_mediainit, 433 PARTID_Am79c970 }, 434 435 { "Am79c970A", 436 pcn_79c970_mediainit, 437 PARTID_Am79c970A }, 438 439 { "Am79c971", 440 pcn_79c971_mediainit, 441 PARTID_Am79c971 }, 442 443 { "Am79c972", 444 pcn_79c971_mediainit, 445 PARTID_Am79c972 }, 446 447 { "Am79c973", 448 pcn_79c971_mediainit, 449 PARTID_Am79c973 }, 450 451 { "Am79c975", 452 pcn_79c971_mediainit, 453 PARTID_Am79c975 }, 454 455 { "Am79c976", 456 pcn_79c971_mediainit, 457 PARTID_Am79c976 }, 458 459 { "Am79c978", 460 pcn_79c971_mediainit, 461 PARTID_Am79c978 }, 462 463 { "Unknown", 464 pcn_79c971_mediainit, 465 0 }, 466 }; 467 468 int pcn_copy_small = 0; 469 470 int pcn_match(struct device *, void *, void *); 471 void pcn_attach(struct device *, struct device *, void *); 472 473 struct cfattach pcn_ca = { 474 sizeof(struct pcn_softc), pcn_match, pcn_attach, 475 }; 476 477 const struct pci_matchid pcn_devices[] = { 478 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_PCI }, 479 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCHOME_PCI } 480 }; 481 482 struct cfdriver pcn_cd = { 483 NULL, "pcn", DV_IFNET 484 }; 485 486 /* 487 * Routines to read and write the PCnet-PCI CSR/BCR space. 488 */ 489 490 static __inline uint32_t 491 pcn_csr_read(struct pcn_softc *sc, int reg) 492 { 493 494 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 495 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 496 } 497 498 static __inline void 499 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 500 { 501 502 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 503 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 504 } 505 506 static __inline uint32_t 507 pcn_bcr_read(struct pcn_softc *sc, int reg) 508 { 509 510 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 511 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 512 } 513 514 static __inline void 515 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 516 { 517 518 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 519 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 520 } 521 522 static const struct pcn_variant * 523 pcn_lookup_variant(uint16_t chipid) 524 { 525 const struct pcn_variant *pcv; 526 527 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 528 if (chipid == pcv->pcv_chipid) 529 return (pcv); 530 } 531 532 /* 533 * This covers unknown chips, which we simply treat like 534 * a generic PCnet-FAST. 535 */ 536 return (pcv); 537 } 538 539 int 540 pcn_match(struct device *parent, void *match, void *aux) 541 { 542 struct pci_attach_args *pa = aux; 543 544 /* 545 * IBM makes a PCI variant of this card which shows up as a 546 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 547 * this card is truly a pcn card, so we have a special case match for 548 * it. 549 */ 550 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 551 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 552 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 553 return(1); 554 555 return (pci_matchbyid((struct pci_attach_args *)aux, pcn_devices, 556 nitems(pcn_devices))); 557 } 558 559 void 560 pcn_attach(struct device *parent, struct device *self, void *aux) 561 { 562 struct pcn_softc *sc = (struct pcn_softc *) self; 563 struct pci_attach_args *pa = aux; 564 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 565 pci_chipset_tag_t pc = pa->pa_pc; 566 pci_intr_handle_t ih; 567 const char *intrstr = NULL; 568 bus_space_tag_t iot, memt; 569 bus_space_handle_t ioh, memh; 570 bus_dma_segment_t seg; 571 int ioh_valid, memh_valid; 572 int i, rseg, error; 573 uint32_t chipid, reg; 574 uint8_t enaddr[ETHER_ADDR_LEN]; 575 576 timeout_set(&sc->sc_tick_timeout, pcn_tick, sc); 577 578 /* 579 * Map the device. 580 */ 581 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 582 &iot, &ioh, NULL, NULL, 0) == 0); 583 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 584 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 585 &memt, &memh, NULL, NULL, 0) == 0); 586 587 if (memh_valid) { 588 sc->sc_st = memt; 589 sc->sc_sh = memh; 590 } else if (ioh_valid) { 591 sc->sc_st = iot; 592 sc->sc_sh = ioh; 593 } else { 594 printf(": unable to map device registers\n"); 595 return; 596 } 597 598 sc->sc_dmat = pa->pa_dmat; 599 600 /* Get it out of power save mode, if needed. */ 601 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 602 603 /* 604 * Reset the chip to a known state. This also puts the 605 * chip into 32-bit mode. 606 */ 607 pcn_reset(sc); 608 609 #if !defined(PCN_NO_PROM) 610 611 /* 612 * Read the Ethernet address from the EEPROM. 613 */ 614 for (i = 0; i < ETHER_ADDR_LEN; i++) 615 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 616 PCN32_APROM + i); 617 #else 618 /* 619 * The PROM is not used; instead we assume that the MAC address 620 * has been programmed into the device's physical address 621 * registers by the boot firmware 622 */ 623 624 for (i=0; i < 3; i++) { 625 uint32_t val; 626 val = pcn_csr_read(sc, LE_CSR12 + i); 627 enaddr[2*i] = val & 0x0ff; 628 enaddr[2*i+1] = (val >> 8) & 0x0ff; 629 } 630 #endif 631 632 /* 633 * Now that the device is mapped, attempt to figure out what 634 * kind of chip we have. Note that IDL has all 32 bits of 635 * the chip ID when we're in 32-bit mode. 636 */ 637 chipid = pcn_csr_read(sc, LE_CSR88); 638 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 639 640 /* 641 * Map and establish our interrupt. 642 */ 643 if (pci_intr_map(pa, &ih)) { 644 printf(": unable to map interrupt\n"); 645 return; 646 } 647 intrstr = pci_intr_string(pc, ih); 648 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc, 649 self->dv_xname); 650 if (sc->sc_ih == NULL) { 651 printf(": unable to establish interrupt"); 652 if (intrstr != NULL) 653 printf(" at %s", intrstr); 654 printf("\n"); 655 return; 656 } 657 658 /* 659 * Allocate the control data structures, and create and load the 660 * DMA map for it. 661 */ 662 if ((error = bus_dmamem_alloc(sc->sc_dmat, 663 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 664 0)) != 0) { 665 printf(": unable to allocate control data, error = %d\n", 666 error); 667 return; 668 } 669 670 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 671 sizeof(struct pcn_control_data), (caddr_t *)&sc->sc_control_data, 672 BUS_DMA_COHERENT)) != 0) { 673 printf(": unable to map control data, error = %d\n", 674 error); 675 goto fail_1; 676 } 677 678 if ((error = bus_dmamap_create(sc->sc_dmat, 679 sizeof(struct pcn_control_data), 1, 680 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 681 printf(": unable to create control data DMA map, " 682 "error = %d\n", error); 683 goto fail_2; 684 } 685 686 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 687 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 688 0)) != 0) { 689 printf(": unable to load control data DMA map, error = %d\n", 690 error); 691 goto fail_3; 692 } 693 694 /* Create the transmit buffer DMA maps. */ 695 for (i = 0; i < PCN_TXQUEUELEN; i++) { 696 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 697 PCN_NTXSEGS, MCLBYTES, 0, 0, 698 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 699 printf(": unable to create tx DMA map %d, " 700 "error = %d\n", i, error); 701 goto fail_4; 702 } 703 } 704 705 /* Create the receive buffer DMA maps. */ 706 for (i = 0; i < PCN_NRXDESC; i++) { 707 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 708 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 709 printf(": unable to create rx DMA map %d, " 710 "error = %d\n", i, error); 711 goto fail_5; 712 } 713 sc->sc_rxsoft[i].rxs_mbuf = NULL; 714 } 715 716 printf(", %s, rev %d: %s, address %s\n", sc->sc_variant->pcv_desc, 717 CHIPID_VER(chipid), intrstr, ether_sprintf(enaddr)); 718 719 /* Initialize our media structures. */ 720 (*sc->sc_variant->pcv_mediainit)(sc); 721 722 /* 723 * Initialize FIFO watermark info. 724 */ 725 switch (sc->sc_variant->pcv_chipid) { 726 case PARTID_Am79c970: 727 case PARTID_Am79c970A: 728 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 729 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 730 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 731 break; 732 733 default: 734 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 735 /* 736 * Read BCR25 to determine how much SRAM is 737 * on the board. If > 0, then we the chip 738 * uses different Start Point thresholds. 739 * 740 * Note BCR25 and BCR26 are loaded from the 741 * EEPROM on RST, and unaffected by S_RESET, 742 * so we don't really have to worry about 743 * them except for this. 744 */ 745 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 746 if (reg != 0) 747 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 748 else 749 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 750 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 751 break; 752 } 753 754 /* 755 * Set up defaults -- see the tables above for what these 756 * values mean. 757 * 758 * XXX How should we tune RCVFW and XMTFW? 759 */ 760 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 761 sc->sc_xmtsp = 1; 762 sc->sc_xmtfw = 0; 763 764 ifp = &sc->sc_arpcom.ac_if; 765 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 766 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 767 ifp->if_softc = sc; 768 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 769 ifp->if_ioctl = pcn_ioctl; 770 ifp->if_start = pcn_start; 771 ifp->if_watchdog = pcn_watchdog; 772 IFQ_SET_MAXLEN(&ifp->if_snd, PCN_NTXDESC -1); 773 774 /* Attach the interface. */ 775 if_attach(ifp); 776 ether_ifattach(ifp); 777 return; 778 779 /* 780 * Free any resources we've allocated during the failed attach 781 * attempt. Do this in reverse order and fall through. 782 */ 783 fail_5: 784 for (i = 0; i < PCN_NRXDESC; i++) { 785 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 786 bus_dmamap_destroy(sc->sc_dmat, 787 sc->sc_rxsoft[i].rxs_dmamap); 788 } 789 fail_4: 790 for (i = 0; i < PCN_TXQUEUELEN; i++) { 791 if (sc->sc_txsoft[i].txs_dmamap != NULL) 792 bus_dmamap_destroy(sc->sc_dmat, 793 sc->sc_txsoft[i].txs_dmamap); 794 } 795 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 796 fail_3: 797 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 798 fail_2: 799 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 800 sizeof(struct pcn_control_data)); 801 fail_1: 802 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 803 } 804 805 /* 806 * pcn_start: [ifnet interface function] 807 * 808 * Start packet transmission on the interface. 809 */ 810 void 811 pcn_start(struct ifnet *ifp) 812 { 813 struct pcn_softc *sc = ifp->if_softc; 814 struct mbuf *m0, *m; 815 struct pcn_txsoft *txs; 816 bus_dmamap_t dmamap; 817 int error, nexttx, lasttx = -1, ofree, seg; 818 819 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 820 return; 821 822 /* 823 * Remember the previous number of free descriptors and 824 * the first descriptor we'll use. 825 */ 826 ofree = sc->sc_txfree; 827 828 /* 829 * Loop through the send queue, setting up transmit descriptors 830 * until we drain the queue, or use up all available transmit 831 * descriptors. 832 */ 833 for (;;) { 834 /* Grab a packet off the queue. */ 835 m0 = ifq_deq_begin(&ifp->if_snd); 836 if (m0 == NULL) 837 break; 838 m = NULL; 839 840 /* Get a work queue entry. */ 841 if (sc->sc_txsfree == 0) { 842 ifq_deq_rollback(&ifp->if_snd, m0); 843 break; 844 } 845 846 txs = &sc->sc_txsoft[sc->sc_txsnext]; 847 dmamap = txs->txs_dmamap; 848 849 /* 850 * Load the DMA map. If this fails, the packet either 851 * didn't fit in the alloted number of segments, or we 852 * were short on resources. In this case, we'll copy 853 * and try again. 854 */ 855 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 856 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 857 MGETHDR(m, M_DONTWAIT, MT_DATA); 858 if (m == NULL) { 859 ifq_deq_rollback(&ifp->if_snd, m0); 860 break; 861 } 862 if (m0->m_pkthdr.len > MHLEN) { 863 MCLGET(m, M_DONTWAIT); 864 if ((m->m_flags & M_EXT) == 0) { 865 ifq_deq_rollback(&ifp->if_snd, m0); 866 m_freem(m); 867 break; 868 } 869 } 870 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 871 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 872 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 873 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 874 if (error) { 875 ifq_deq_rollback(&ifp->if_snd, m0); 876 break; 877 } 878 } 879 880 /* 881 * Ensure we have enough descriptors free to describe 882 * the packet. Note, we always reserve one descriptor 883 * at the end of the ring as a termination point, to 884 * prevent wrap-around. 885 */ 886 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 887 /* 888 * Not enough free descriptors to transmit this 889 * packet. We haven't committed anything yet, 890 * so just unload the DMA map, put the packet 891 * back on the queue, and punt. Notify the upper 892 * layer that there are not more slots left. 893 * 894 * XXX We could allocate an mbuf and copy, but 895 * XXX is it worth it? 896 */ 897 ifq_set_oactive(&ifp->if_snd); 898 bus_dmamap_unload(sc->sc_dmat, dmamap); 899 if (m != NULL) 900 m_freem(m); 901 ifq_deq_rollback(&ifp->if_snd, m0); 902 break; 903 } 904 905 ifq_deq_commit(&ifp->if_snd, m0); 906 if (m != NULL) { 907 m_freem(m0); 908 m0 = m; 909 } 910 911 /* 912 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 913 */ 914 915 /* Sync the DMA map. */ 916 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 917 BUS_DMASYNC_PREWRITE); 918 919 /* 920 * Initialize the transmit descriptors. 921 */ 922 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 923 for (nexttx = sc->sc_txnext, seg = 0; 924 seg < dmamap->dm_nsegs; 925 seg++, nexttx = PCN_NEXTTX(nexttx)) { 926 /* 927 * If this is the first descriptor we're 928 * enqueueing, don't set the OWN bit just 929 * yet. That could cause a race condition. 930 * We'll do it below. 931 */ 932 sc->sc_txdescs[nexttx].tmd0 = 0; 933 sc->sc_txdescs[nexttx].tmd2 = 934 htole32(dmamap->dm_segs[seg].ds_addr); 935 sc->sc_txdescs[nexttx].tmd1 = 936 htole32(LE_T1_ONES | 937 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 938 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 939 LE_T1_BCNT_MASK)); 940 lasttx = nexttx; 941 } 942 } else { 943 for (nexttx = sc->sc_txnext, seg = 0; 944 seg < dmamap->dm_nsegs; 945 seg++, nexttx = PCN_NEXTTX(nexttx)) { 946 /* 947 * If this is the first descriptor we're 948 * enqueueing, don't set the OWN bit just 949 * yet. That could cause a race condition. 950 * We'll do it below. 951 */ 952 sc->sc_txdescs[nexttx].tmd0 = 953 htole32(dmamap->dm_segs[seg].ds_addr); 954 sc->sc_txdescs[nexttx].tmd2 = 0; 955 sc->sc_txdescs[nexttx].tmd1 = 956 htole32(LE_T1_ONES | 957 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 958 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 959 LE_T1_BCNT_MASK)); 960 lasttx = nexttx; 961 } 962 } 963 964 KASSERT(lasttx != -1); 965 /* Interrupt on the packet, if appropriate. */ 966 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 967 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 968 969 /* Set `start of packet' and `end of packet' appropriately. */ 970 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 971 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 972 htole32(LE_T1_OWN|LE_T1_STP); 973 974 /* Sync the descriptors we're using. */ 975 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 976 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 977 978 /* Kick the transmitter. */ 979 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 980 981 /* 982 * Store a pointer to the packet so we can free it later, 983 * and remember what txdirty will be once the packet is 984 * done. 985 */ 986 txs->txs_mbuf = m0; 987 txs->txs_firstdesc = sc->sc_txnext; 988 txs->txs_lastdesc = lasttx; 989 990 /* Advance the tx pointer. */ 991 sc->sc_txfree -= dmamap->dm_nsegs; 992 sc->sc_txnext = nexttx; 993 994 sc->sc_txsfree--; 995 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 996 997 #if NBPFILTER > 0 998 /* Pass the packet to any BPF listeners. */ 999 if (ifp->if_bpf) 1000 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 1001 #endif /* NBPFILTER > 0 */ 1002 } 1003 1004 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1005 /* No more slots left; notify upper layer. */ 1006 ifq_set_oactive(&ifp->if_snd); 1007 } 1008 1009 if (sc->sc_txfree != ofree) { 1010 /* Set a watchdog timer in case the chip flakes out. */ 1011 ifp->if_timer = 5; 1012 } 1013 } 1014 1015 /* 1016 * pcn_watchdog: [ifnet interface function] 1017 * 1018 * Watchdog timer handler. 1019 */ 1020 void 1021 pcn_watchdog(struct ifnet *ifp) 1022 { 1023 struct pcn_softc *sc = ifp->if_softc; 1024 1025 /* 1026 * Since we're not interrupting every packet, sweep 1027 * up before we report an error. 1028 */ 1029 pcn_txintr(sc); 1030 1031 if (sc->sc_txfree != PCN_NTXDESC) { 1032 printf("%s: device timeout (txfree %d txsfree %d)\n", 1033 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree); 1034 ifp->if_oerrors++; 1035 1036 /* Reset the interface. */ 1037 (void) pcn_init(ifp); 1038 } 1039 1040 /* Try to get more packets going. */ 1041 pcn_start(ifp); 1042 } 1043 1044 /* 1045 * pcn_ioctl: [ifnet interface function] 1046 * 1047 * Handle control requests from the operator. 1048 */ 1049 int 1050 pcn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1051 { 1052 struct pcn_softc *sc = ifp->if_softc; 1053 struct ifreq *ifr = (struct ifreq *) data; 1054 int s, error = 0; 1055 1056 s = splnet(); 1057 1058 switch (cmd) { 1059 case SIOCSIFADDR: 1060 ifp->if_flags |= IFF_UP; 1061 if (!(ifp->if_flags & IFF_RUNNING)) 1062 pcn_init(ifp); 1063 break; 1064 1065 case SIOCSIFFLAGS: 1066 if (ifp->if_flags & IFF_UP) { 1067 if (ifp->if_flags & IFF_RUNNING) 1068 error = ENETRESET; 1069 else 1070 pcn_init(ifp); 1071 } else { 1072 if (ifp->if_flags & IFF_RUNNING) 1073 pcn_stop(ifp, 1); 1074 } 1075 break; 1076 1077 case SIOCSIFMEDIA: 1078 case SIOCGIFMEDIA: 1079 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1080 break; 1081 1082 default: 1083 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1084 } 1085 1086 if (error == ENETRESET) { 1087 if (ifp->if_flags & IFF_RUNNING) 1088 error = pcn_init(ifp); 1089 else 1090 error = 0; 1091 } 1092 1093 splx(s); 1094 return (error); 1095 } 1096 1097 /* 1098 * pcn_intr: 1099 * 1100 * Interrupt service routine. 1101 */ 1102 int 1103 pcn_intr(void *arg) 1104 { 1105 struct pcn_softc *sc = arg; 1106 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1107 uint32_t csr0; 1108 int wantinit, handled = 0; 1109 1110 for (wantinit = 0; wantinit == 0;) { 1111 csr0 = pcn_csr_read(sc, LE_CSR0); 1112 if ((csr0 & LE_C0_INTR) == 0) 1113 break; 1114 1115 /* ACK the bits and re-enable interrupts. */ 1116 pcn_csr_write(sc, LE_CSR0, csr0 & 1117 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1118 LE_C0_TINT|LE_C0_IDON)); 1119 1120 handled = 1; 1121 1122 if (csr0 & LE_C0_RINT) 1123 wantinit = pcn_rxintr(sc); 1124 1125 if (csr0 & LE_C0_TINT) 1126 pcn_txintr(sc); 1127 1128 if (csr0 & LE_C0_ERR) { 1129 if (csr0 & LE_C0_BABL) 1130 ifp->if_oerrors++; 1131 if (csr0 & LE_C0_MISS) 1132 ifp->if_ierrors++; 1133 if (csr0 & LE_C0_MERR) { 1134 printf("%s: memory error\n", 1135 sc->sc_dev.dv_xname); 1136 wantinit = 1; 1137 break; 1138 } 1139 } 1140 1141 if ((csr0 & LE_C0_RXON) == 0) { 1142 printf("%s: receiver disabled\n", 1143 sc->sc_dev.dv_xname); 1144 ifp->if_ierrors++; 1145 wantinit = 1; 1146 } 1147 1148 if ((csr0 & LE_C0_TXON) == 0) { 1149 printf("%s: transmitter disabled\n", 1150 sc->sc_dev.dv_xname); 1151 ifp->if_oerrors++; 1152 wantinit = 1; 1153 } 1154 } 1155 1156 if (handled) { 1157 if (wantinit) 1158 pcn_init(ifp); 1159 1160 /* Try to get more packets going. */ 1161 pcn_start(ifp); 1162 } 1163 1164 return (handled); 1165 } 1166 1167 /* 1168 * pcn_spnd: 1169 * 1170 * Suspend the chip. 1171 */ 1172 void 1173 pcn_spnd(struct pcn_softc *sc) 1174 { 1175 int i; 1176 1177 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1178 1179 for (i = 0; i < 10000; i++) { 1180 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1181 return; 1182 delay(5); 1183 } 1184 1185 printf("%s: WARNING: chip failed to enter suspended state\n", 1186 sc->sc_dev.dv_xname); 1187 } 1188 1189 /* 1190 * pcn_txintr: 1191 * 1192 * Helper; handle transmit interrupts. 1193 */ 1194 void 1195 pcn_txintr(struct pcn_softc *sc) 1196 { 1197 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1198 struct pcn_txsoft *txs; 1199 uint32_t tmd1, tmd2, tmd; 1200 int i, j; 1201 1202 ifq_clr_oactive(&ifp->if_snd); 1203 1204 /* 1205 * Go through our Tx list and free mbufs for those 1206 * frames which have been transmitted. 1207 */ 1208 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1209 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1210 txs = &sc->sc_txsoft[i]; 1211 1212 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1213 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1214 1215 tmd1 = letoh32(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1216 if (tmd1 & LE_T1_OWN) 1217 break; 1218 1219 /* 1220 * Slightly annoying -- we have to loop through the 1221 * descriptors we've used looking for ERR, since it 1222 * can appear on any descriptor in the chain. 1223 */ 1224 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1225 tmd = letoh32(sc->sc_txdescs[j].tmd1); 1226 if (tmd & LE_T1_ERR) { 1227 ifp->if_oerrors++; 1228 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1229 tmd2 = letoh32(sc->sc_txdescs[j].tmd0); 1230 else 1231 tmd2 = letoh32(sc->sc_txdescs[j].tmd2); 1232 if (tmd2 & LE_T2_UFLO) { 1233 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1234 sc->sc_xmtsp++; 1235 printf("%s: transmit " 1236 "underrun; new threshold: " 1237 "%s\n", 1238 sc->sc_dev.dv_xname, 1239 sc->sc_xmtsp_desc[ 1240 sc->sc_xmtsp]); 1241 pcn_spnd(sc); 1242 pcn_csr_write(sc, LE_CSR80, 1243 LE_C80_RCVFW(sc->sc_rcvfw) | 1244 LE_C80_XMTSP(sc->sc_xmtsp) | 1245 LE_C80_XMTFW(sc->sc_xmtfw)); 1246 pcn_csr_write(sc, LE_CSR5, 1247 sc->sc_csr5); 1248 } else { 1249 printf("%s: transmit " 1250 "underrun\n", 1251 sc->sc_dev.dv_xname); 1252 } 1253 } else if (tmd2 & LE_T2_BUFF) { 1254 printf("%s: transmit buffer error\n", 1255 sc->sc_dev.dv_xname); 1256 } 1257 if (tmd2 & LE_T2_LCOL) 1258 ifp->if_collisions++; 1259 if (tmd2 & LE_T2_RTRY) 1260 ifp->if_collisions += 16; 1261 goto next_packet; 1262 } 1263 if (j == txs->txs_lastdesc) 1264 break; 1265 } 1266 if (tmd1 & LE_T1_ONE) 1267 ifp->if_collisions++; 1268 else if (tmd & LE_T1_MORE) { 1269 /* Real number is unknown. */ 1270 ifp->if_collisions += 2; 1271 } 1272 ifp->if_opackets++; 1273 next_packet: 1274 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1275 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1276 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1277 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1278 m_freem(txs->txs_mbuf); 1279 txs->txs_mbuf = NULL; 1280 } 1281 1282 /* Update the dirty transmit buffer pointer. */ 1283 sc->sc_txsdirty = i; 1284 1285 /* 1286 * If there are no more pending transmissions, cancel the watchdog 1287 * timer. 1288 */ 1289 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1290 ifp->if_timer = 0; 1291 } 1292 1293 /* 1294 * pcn_rxintr: 1295 * 1296 * Helper; handle receive interrupts. 1297 */ 1298 int 1299 pcn_rxintr(struct pcn_softc *sc) 1300 { 1301 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1302 struct pcn_rxsoft *rxs; 1303 struct mbuf *m; 1304 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1305 uint32_t rmd1; 1306 int i, len; 1307 int rv = 0; 1308 1309 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1310 rxs = &sc->sc_rxsoft[i]; 1311 1312 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1313 1314 rmd1 = letoh32(sc->sc_rxdescs[i].rmd1); 1315 1316 if (rmd1 & LE_R1_OWN) 1317 break; 1318 1319 /* 1320 * Check for errors and make sure the packet fit into 1321 * a single buffer. We have structured this block of 1322 * code the way it is in order to compress it into 1323 * one test in the common case (no error). 1324 */ 1325 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1326 (LE_R1_STP|LE_R1_ENP))) { 1327 /* Make sure the packet is in a single buffer. */ 1328 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1329 (LE_R1_STP|LE_R1_ENP)) { 1330 printf("%s: packet spilled into next buffer\n", 1331 sc->sc_dev.dv_xname); 1332 rv = 1; /* pcn_intr() will re-init */ 1333 goto done; 1334 } 1335 1336 /* 1337 * If the packet had an error, simple recycle the 1338 * buffer. 1339 */ 1340 if (rmd1 & LE_R1_ERR) { 1341 ifp->if_ierrors++; 1342 /* 1343 * If we got an overflow error, chances 1344 * are there will be a CRC error. In 1345 * this case, just print the overflow 1346 * error, and skip the others. 1347 */ 1348 if (rmd1 & LE_R1_OFLO) 1349 printf("%s: overflow error\n", 1350 sc->sc_dev.dv_xname); 1351 else { 1352 #define PRINTIT(x, str) \ 1353 if (rmd1 & (x)) \ 1354 printf("%s: %s\n", \ 1355 sc->sc_dev.dv_xname, str); 1356 PRINTIT(LE_R1_FRAM, "framing error"); 1357 PRINTIT(LE_R1_CRC, "CRC error"); 1358 PRINTIT(LE_R1_BUFF, "buffer error"); 1359 } 1360 #undef PRINTIT 1361 PCN_INIT_RXDESC(sc, i); 1362 continue; 1363 } 1364 } 1365 1366 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1367 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1368 1369 /* 1370 * No errors; receive the packet. 1371 */ 1372 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1373 len = letoh32(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1374 else 1375 len = letoh32(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1376 1377 /* 1378 * The LANCE family includes the CRC with every packet; 1379 * trim it off here. 1380 */ 1381 len -= ETHER_CRC_LEN; 1382 1383 /* 1384 * If the packet is small enough to fit in a 1385 * single header mbuf, allocate one and copy 1386 * the data into it. This greatly reduces 1387 * memory consumption when we receive lots 1388 * of small packets. 1389 * 1390 * Otherwise, we add a new buffer to the receive 1391 * chain. If this fails, we drop the packet and 1392 * recycle the old buffer. 1393 */ 1394 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1395 MGETHDR(m, M_DONTWAIT, MT_DATA); 1396 if (m == NULL) 1397 goto dropit; 1398 m->m_data += 2; 1399 memcpy(mtod(m, caddr_t), 1400 mtod(rxs->rxs_mbuf, caddr_t), len); 1401 PCN_INIT_RXDESC(sc, i); 1402 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1403 rxs->rxs_dmamap->dm_mapsize, 1404 BUS_DMASYNC_PREREAD); 1405 } else { 1406 m = rxs->rxs_mbuf; 1407 if (pcn_add_rxbuf(sc, i) != 0) { 1408 dropit: 1409 ifp->if_ierrors++; 1410 PCN_INIT_RXDESC(sc, i); 1411 bus_dmamap_sync(sc->sc_dmat, 1412 rxs->rxs_dmamap, 0, 1413 rxs->rxs_dmamap->dm_mapsize, 1414 BUS_DMASYNC_PREREAD); 1415 continue; 1416 } 1417 } 1418 1419 m->m_pkthdr.len = m->m_len = len; 1420 1421 ml_enqueue(&ml, m); 1422 } 1423 1424 /* Update the receive pointer. */ 1425 sc->sc_rxptr = i; 1426 done: 1427 if_input(ifp, &ml); 1428 return (rv); 1429 } 1430 1431 /* 1432 * pcn_tick: 1433 * 1434 * One second timer, used to tick the MII. 1435 */ 1436 void 1437 pcn_tick(void *arg) 1438 { 1439 struct pcn_softc *sc = arg; 1440 int s; 1441 1442 s = splnet(); 1443 mii_tick(&sc->sc_mii); 1444 splx(s); 1445 1446 timeout_add_sec(&sc->sc_tick_timeout, 1); 1447 } 1448 1449 /* 1450 * pcn_reset: 1451 * 1452 * Perform a soft reset on the PCnet-PCI. 1453 */ 1454 void 1455 pcn_reset(struct pcn_softc *sc) 1456 { 1457 1458 /* 1459 * The PCnet-PCI chip is reset by reading from the 1460 * RESET register. Note that while the NE2100 LANCE 1461 * boards require a write after the read, the PCnet-PCI 1462 * chips do not require this. 1463 * 1464 * Since we don't know if we're in 16-bit or 32-bit 1465 * mode right now, issue both (it's safe) in the 1466 * hopes that one will succeed. 1467 */ 1468 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1469 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1470 1471 /* Wait 1ms for it to finish. */ 1472 delay(1000); 1473 1474 /* 1475 * Select 32-bit I/O mode by issuing a 32-bit write to the 1476 * RDP. Since the RAP is 0 after a reset, writing a 0 1477 * to RDP is safe (since it simply clears CSR0). 1478 */ 1479 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1480 } 1481 1482 /* 1483 * pcn_init: [ifnet interface function] 1484 * 1485 * Initialize the interface. Must be called at splnet(). 1486 */ 1487 int 1488 pcn_init(struct ifnet *ifp) 1489 { 1490 struct pcn_softc *sc = ifp->if_softc; 1491 struct pcn_rxsoft *rxs; 1492 uint8_t *enaddr = LLADDR(ifp->if_sadl); 1493 int i, error = 0; 1494 uint32_t reg; 1495 1496 /* Cancel any pending I/O. */ 1497 pcn_stop(ifp, 0); 1498 1499 /* Reset the chip to a known state. */ 1500 pcn_reset(sc); 1501 1502 /* 1503 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1504 * else. 1505 * 1506 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1507 * because the structure layout is compatible with ILACC, 1508 * but the burst mode is only available in SSTYLE 3, and 1509 * burst mode should provide some performance enhancement. 1510 */ 1511 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1512 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1513 else 1514 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1515 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1516 1517 /* Initialize the transmit descriptor ring. */ 1518 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1519 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1520 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1521 sc->sc_txfree = PCN_NTXDESC; 1522 sc->sc_txnext = 0; 1523 1524 /* Initialize the transmit job descriptors. */ 1525 for (i = 0; i < PCN_TXQUEUELEN; i++) 1526 sc->sc_txsoft[i].txs_mbuf = NULL; 1527 sc->sc_txsfree = PCN_TXQUEUELEN; 1528 sc->sc_txsnext = 0; 1529 sc->sc_txsdirty = 0; 1530 1531 /* 1532 * Initialize the receive descriptor and receive job 1533 * descriptor rings. 1534 */ 1535 for (i = 0; i < PCN_NRXDESC; i++) { 1536 rxs = &sc->sc_rxsoft[i]; 1537 if (rxs->rxs_mbuf == NULL) { 1538 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1539 printf("%s: unable to allocate or map rx " 1540 "buffer %d, error = %d\n", 1541 sc->sc_dev.dv_xname, i, error); 1542 /* 1543 * XXX Should attempt to run with fewer receive 1544 * XXX buffers instead of just failing. 1545 */ 1546 pcn_rxdrain(sc); 1547 goto out; 1548 } 1549 } else 1550 PCN_INIT_RXDESC(sc, i); 1551 } 1552 sc->sc_rxptr = 0; 1553 1554 /* Initialize MODE for the initialization block. */ 1555 sc->sc_mode = 0; 1556 1557 /* 1558 * If we have MII, simply select MII in the MODE register, 1559 * and clear ASEL. Otherwise, let ASEL stand (for now), 1560 * and leave PORTSEL alone (it is ignored with ASEL is set). 1561 */ 1562 if (sc->sc_flags & PCN_F_HAS_MII) { 1563 pcn_bcr_write(sc, LE_BCR2, 1564 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1565 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1566 1567 /* 1568 * Disable MII auto-negotiation. We handle that in 1569 * our own MII layer. 1570 */ 1571 pcn_bcr_write(sc, LE_BCR32, 1572 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1573 } 1574 1575 /* Set the multicast filter in the init block. */ 1576 pcn_set_filter(sc); 1577 1578 /* 1579 * Set the Tx and Rx descriptor ring addresses in the init 1580 * block, the TLEN and RLEN other fields of the init block 1581 * MODE register. 1582 */ 1583 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1584 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1585 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1586 ((ffs(PCN_NTXDESC) - 1) << 28) | 1587 ((ffs(PCN_NRXDESC) - 1) << 20)); 1588 1589 /* Set the station address in the init block. */ 1590 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1591 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1592 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1593 (enaddr[5] << 8)); 1594 1595 /* Initialize CSR3. */ 1596 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1597 1598 /* Initialize CSR4. */ 1599 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1600 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1601 1602 /* Initialize CSR5. */ 1603 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1604 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1605 1606 /* 1607 * If we have an Am79c971 or greater, initialize CSR7. 1608 * 1609 * XXX Might be nice to use the MII auto-poll interrupt someday. 1610 */ 1611 switch (sc->sc_variant->pcv_chipid) { 1612 case PARTID_Am79c970: 1613 case PARTID_Am79c970A: 1614 /* Not available on these chips. */ 1615 break; 1616 1617 default: 1618 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1619 break; 1620 } 1621 1622 /* 1623 * On the Am79c970A and greater, initialize BCR18 to 1624 * enable burst mode. 1625 * 1626 * Also enable the "no underflow" option on the Am79c971 and 1627 * higher, which prevents the chip from generating transmit 1628 * underflows, yet sill provides decent performance. Note if 1629 * chip is not connected to external SRAM, then we still have 1630 * to handle underflow errors (the NOUFLO bit is ignored in 1631 * that case). 1632 */ 1633 reg = pcn_bcr_read(sc, LE_BCR18); 1634 switch (sc->sc_variant->pcv_chipid) { 1635 case PARTID_Am79c970: 1636 break; 1637 1638 case PARTID_Am79c970A: 1639 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1640 break; 1641 1642 default: 1643 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1644 break; 1645 } 1646 pcn_bcr_write(sc, LE_BCR18, reg); 1647 1648 /* 1649 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1650 */ 1651 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1652 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1653 1654 /* 1655 * Send the init block to the chip, and wait for it 1656 * to be processed. 1657 */ 1658 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1659 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1660 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1661 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1662 delay(100); 1663 for (i = 0; i < 10000; i++) { 1664 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1665 break; 1666 delay(10); 1667 } 1668 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1669 if (i == 10000) { 1670 printf("%s: timeout processing init block\n", 1671 sc->sc_dev.dv_xname); 1672 error = EIO; 1673 goto out; 1674 } 1675 1676 /* Set the media. */ 1677 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 1678 1679 /* Enable interrupts and external activity (and ACK IDON). */ 1680 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1681 1682 if (sc->sc_flags & PCN_F_HAS_MII) { 1683 /* Start the one second MII clock. */ 1684 timeout_add_sec(&sc->sc_tick_timeout, 1); 1685 } 1686 1687 /* ...all done! */ 1688 ifp->if_flags |= IFF_RUNNING; 1689 ifq_clr_oactive(&ifp->if_snd); 1690 1691 out: 1692 if (error) 1693 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1694 return (error); 1695 } 1696 1697 /* 1698 * pcn_rxdrain: 1699 * 1700 * Drain the receive queue. 1701 */ 1702 void 1703 pcn_rxdrain(struct pcn_softc *sc) 1704 { 1705 struct pcn_rxsoft *rxs; 1706 int i; 1707 1708 for (i = 0; i < PCN_NRXDESC; i++) { 1709 rxs = &sc->sc_rxsoft[i]; 1710 if (rxs->rxs_mbuf != NULL) { 1711 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1712 m_freem(rxs->rxs_mbuf); 1713 rxs->rxs_mbuf = NULL; 1714 } 1715 } 1716 } 1717 1718 /* 1719 * pcn_stop: [ifnet interface function] 1720 * 1721 * Stop transmission on the interface. 1722 */ 1723 void 1724 pcn_stop(struct ifnet *ifp, int disable) 1725 { 1726 struct pcn_softc *sc = ifp->if_softc; 1727 struct pcn_txsoft *txs; 1728 int i; 1729 1730 if (sc->sc_flags & PCN_F_HAS_MII) { 1731 /* Stop the one second clock. */ 1732 timeout_del(&sc->sc_tick_timeout); 1733 1734 /* Down the MII. */ 1735 mii_down(&sc->sc_mii); 1736 } 1737 1738 /* Mark the interface as down and cancel the watchdog timer. */ 1739 ifp->if_flags &= ~IFF_RUNNING; 1740 ifq_clr_oactive(&ifp->if_snd); 1741 ifp->if_timer = 0; 1742 1743 /* Stop the chip. */ 1744 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1745 1746 /* Release any queued transmit buffers. */ 1747 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1748 txs = &sc->sc_txsoft[i]; 1749 if (txs->txs_mbuf != NULL) { 1750 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1751 m_freem(txs->txs_mbuf); 1752 txs->txs_mbuf = NULL; 1753 } 1754 } 1755 1756 if (disable) 1757 pcn_rxdrain(sc); 1758 } 1759 1760 /* 1761 * pcn_add_rxbuf: 1762 * 1763 * Add a receive buffer to the indicated descriptor. 1764 */ 1765 int 1766 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1767 { 1768 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1769 struct mbuf *m; 1770 int error; 1771 1772 MGETHDR(m, M_DONTWAIT, MT_DATA); 1773 if (m == NULL) 1774 return (ENOBUFS); 1775 1776 MCLGET(m, M_DONTWAIT); 1777 if ((m->m_flags & M_EXT) == 0) { 1778 m_freem(m); 1779 return (ENOBUFS); 1780 } 1781 1782 if (rxs->rxs_mbuf != NULL) 1783 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1784 1785 rxs->rxs_mbuf = m; 1786 1787 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1788 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1789 BUS_DMA_READ|BUS_DMA_NOWAIT); 1790 if (error) { 1791 printf("%s: can't load rx DMA map %d, error = %d\n", 1792 sc->sc_dev.dv_xname, idx, error); 1793 panic("pcn_add_rxbuf"); 1794 } 1795 1796 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1797 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1798 1799 PCN_INIT_RXDESC(sc, idx); 1800 1801 return (0); 1802 } 1803 1804 /* 1805 * pcn_set_filter: 1806 * 1807 * Set up the receive filter. 1808 */ 1809 void 1810 pcn_set_filter(struct pcn_softc *sc) 1811 { 1812 struct arpcom *ac = &sc->sc_arpcom; 1813 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1814 struct ether_multi *enm; 1815 struct ether_multistep step; 1816 uint32_t crc; 1817 1818 ifp->if_flags &= ~IFF_ALLMULTI; 1819 1820 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1821 ifp->if_flags |= IFF_ALLMULTI; 1822 if (ifp->if_flags & IFF_PROMISC) 1823 sc->sc_mode |= LE_C15_PROM; 1824 sc->sc_initblock.init_ladrf[0] = 1825 sc->sc_initblock.init_ladrf[1] = 1826 sc->sc_initblock.init_ladrf[2] = 1827 sc->sc_initblock.init_ladrf[3] = 0xffff; 1828 } else { 1829 sc->sc_initblock.init_ladrf[0] = 1830 sc->sc_initblock.init_ladrf[1] = 1831 sc->sc_initblock.init_ladrf[2] = 1832 sc->sc_initblock.init_ladrf[3] = 0; 1833 1834 /* 1835 * Set up the multicast address filter by passing all multicast 1836 * addresses through a CRC generator, and then using the high 1837 * order 6 bits as an index into the 64-bit logical address 1838 * filter. The high order bits select the word, while the rest 1839 * of the bits select the bit within the word. 1840 */ 1841 ETHER_FIRST_MULTI(step, ac, enm); 1842 while (enm != NULL) { 1843 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1844 1845 /* Just want the 6 most significant bits. */ 1846 crc >>= 26; 1847 1848 /* Set the corresponding bit in the filter. */ 1849 sc->sc_initblock.init_ladrf[crc >> 4] |= 1850 htole16(1 << (crc & 0xf)); 1851 1852 ETHER_NEXT_MULTI(step, enm); 1853 } 1854 } 1855 } 1856 1857 /* 1858 * pcn_79c970_mediainit: 1859 * 1860 * Initialize media for the Am79c970. 1861 */ 1862 void 1863 pcn_79c970_mediainit(struct pcn_softc *sc) 1864 { 1865 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 1866 pcn_79c970_mediastatus); 1867 1868 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_5, 1869 PORTSEL_AUI, NULL); 1870 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1871 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_5|IFM_FDX, 1872 PORTSEL_AUI, NULL); 1873 1874 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_T, 1875 PORTSEL_10T, NULL); 1876 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1877 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_T|IFM_FDX, 1878 PORTSEL_10T, NULL); 1879 1880 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 1881 0, NULL); 1882 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1883 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO|IFM_FDX, 1884 0, NULL); 1885 1886 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1887 } 1888 1889 /* 1890 * pcn_79c970_mediastatus: [ifmedia interface function] 1891 * 1892 * Get the current interface media status (Am79c970 version). 1893 */ 1894 void 1895 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1896 { 1897 struct pcn_softc *sc = ifp->if_softc; 1898 1899 /* 1900 * The currently selected media is always the active media. 1901 * Note: We have no way to determine what media the AUTO 1902 * process picked. 1903 */ 1904 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 1905 } 1906 1907 /* 1908 * pcn_79c970_mediachange: [ifmedia interface function] 1909 * 1910 * Set hardware to newly-selected media (Am79c970 version). 1911 */ 1912 int 1913 pcn_79c970_mediachange(struct ifnet *ifp) 1914 { 1915 struct pcn_softc *sc = ifp->if_softc; 1916 uint32_t reg; 1917 1918 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 1919 /* 1920 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 1921 */ 1922 reg = pcn_bcr_read(sc, LE_BCR2); 1923 reg |= LE_B2_ASEL; 1924 pcn_bcr_write(sc, LE_BCR2, reg); 1925 } else { 1926 /* 1927 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 1928 */ 1929 reg = pcn_bcr_read(sc, LE_BCR2); 1930 reg &= ~LE_B2_ASEL; 1931 pcn_bcr_write(sc, LE_BCR2, reg); 1932 1933 reg = pcn_csr_read(sc, LE_CSR15); 1934 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 1935 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 1936 pcn_csr_write(sc, LE_CSR15, reg); 1937 } 1938 1939 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 1940 reg = LE_B9_FDEN; 1941 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 1942 reg |= LE_B9_AUIFD; 1943 pcn_bcr_write(sc, LE_BCR9, reg); 1944 } else 1945 pcn_bcr_write(sc, LE_BCR9, 0); 1946 1947 return (0); 1948 } 1949 1950 /* 1951 * pcn_79c971_mediainit: 1952 * 1953 * Initialize media for the Am79c971. 1954 */ 1955 void 1956 pcn_79c971_mediainit(struct pcn_softc *sc) 1957 { 1958 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1959 1960 /* We have MII. */ 1961 sc->sc_flags |= PCN_F_HAS_MII; 1962 1963 /* 1964 * The built-in 10BASE-T interface is mapped to the MII 1965 * on the PCNet-FAST. Unfortunately, there's no EEPROM 1966 * word that tells us which PHY to use. 1967 * This driver used to ignore all but the first PHY to 1968 * answer, but this code was removed to support multiple 1969 * external PHYs. As the default instance will be the first 1970 * one to answer, no harm is done by letting the possibly 1971 * non-connected internal PHY show up. 1972 */ 1973 1974 /* Initialize our media structures and probe the MII. */ 1975 sc->sc_mii.mii_ifp = ifp; 1976 sc->sc_mii.mii_readreg = pcn_mii_readreg; 1977 sc->sc_mii.mii_writereg = pcn_mii_writereg; 1978 sc->sc_mii.mii_statchg = pcn_mii_statchg; 1979 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c971_mediachange, 1980 pcn_79c971_mediastatus); 1981 1982 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1983 MII_OFFSET_ANY, 0); 1984 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1985 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1986 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1987 } else 1988 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1989 } 1990 1991 /* 1992 * pcn_79c971_mediastatus: [ifmedia interface function] 1993 * 1994 * Get the current interface media status (Am79c971 version). 1995 */ 1996 void 1997 pcn_79c971_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1998 { 1999 struct pcn_softc *sc = ifp->if_softc; 2000 2001 mii_pollstat(&sc->sc_mii); 2002 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2003 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2004 } 2005 2006 /* 2007 * pcn_79c971_mediachange: [ifmedia interface function] 2008 * 2009 * Set hardware to newly-selected media (Am79c971 version). 2010 */ 2011 int 2012 pcn_79c971_mediachange(struct ifnet *ifp) 2013 { 2014 struct pcn_softc *sc = ifp->if_softc; 2015 2016 if (ifp->if_flags & IFF_UP) 2017 mii_mediachg(&sc->sc_mii); 2018 return (0); 2019 } 2020 2021 /* 2022 * pcn_mii_readreg: [mii interface function] 2023 * 2024 * Read a PHY register on the MII. 2025 */ 2026 int 2027 pcn_mii_readreg(struct device *self, int phy, int reg) 2028 { 2029 struct pcn_softc *sc = (void *) self; 2030 uint32_t rv; 2031 2032 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2033 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2034 if (rv == 0xffff) 2035 return (0); 2036 2037 return (rv); 2038 } 2039 2040 /* 2041 * pcn_mii_writereg: [mii interface function] 2042 * 2043 * Write a PHY register on the MII. 2044 */ 2045 void 2046 pcn_mii_writereg(struct device *self, int phy, int reg, int val) 2047 { 2048 struct pcn_softc *sc = (void *) self; 2049 2050 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2051 pcn_bcr_write(sc, LE_BCR34, val); 2052 } 2053 2054 /* 2055 * pcn_mii_statchg: [mii interface function] 2056 * 2057 * Callback from MII layer when media changes. 2058 */ 2059 void 2060 pcn_mii_statchg(struct device *self) 2061 { 2062 struct pcn_softc *sc = (void *) self; 2063 2064 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2065 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2066 else 2067 pcn_bcr_write(sc, LE_BCR9, 0); 2068 } 2069