1 /* $OpenBSD: if_skreg.h,v 1.8 2003/05/14 01:54:15 nate Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_skreg.h,v 1.9 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * SysKonnect PCI vendor ID 39 */ 40 #define SK_VENDORID 0x1148 41 42 /* 43 * SK-NET gigabit ethernet device ID 44 */ 45 #define SK_DEVICEID_GE 0x4300 46 47 /* 48 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 49 * but internally it has a 16K register space. This 16K space is 50 * divided into 128-byte blocks. The first 128 bytes of the I/O 51 * window represent the first block, which is permanently mapped 52 * at the start of the window. The other 127 blocks can be mapped 53 * to the second 128 bytes of the I/O window by setting the desired 54 * block value in the RAP register in block 0. Not all of the 127 55 * blocks are actually used. Most registers are 32 bits wide, but 56 * there are a few 16-bit and 8-bit ones as well. 57 */ 58 59 60 /* Start of remappable register window. */ 61 #define SK_WIN_BASE 0x0080 62 63 /* Size of a window */ 64 #define SK_WIN_LEN 0x80 65 66 #define SK_WIN_MASK 0x3F80 67 #define SK_REG_MASK 0x7F 68 69 /* Compute the window of a given register (for the RAP register) */ 70 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 71 72 /* Compute the relative offset of a register within the window */ 73 #define SK_REG(reg) ((reg) & SK_REG_MASK) 74 75 #define SK_PORT_A 0 76 #define SK_PORT_B 1 77 78 /* 79 * Compute offset of port-specific register. Since there are two 80 * ports, there are two of some GEnesis modules (e.g. two sets of 81 * DMA queues, two sets of FIFO control registers, etc...). Normally, 82 * the block for port 0 is at offset 0x0 and the block for port 1 is 83 * at offset 0x80 (i.e. the next page over). However for the transmit 84 * BMUs and RAMbuffers, there are two blocks for each port: one for 85 * the sync transmit queue and one for the async queue (which we don't 86 * use). However instead of ordering them like this: 87 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 88 * SysKonnect has instead ordered them like this: 89 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 90 * This means that when referencing the TX BMU and RAMbuffer registers, 91 * we have to double the block offset (0x80 * 2) in order to reach the 92 * second queue. This prevents us from using the same formula 93 * (sk_port * 0x80) to compute the offsets for all of the port-specific 94 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 95 * The simplest thing is to provide an extra argument to these macros: 96 * the 'skip' parameter. The 'skip' value is the number of extra pages 97 * for skip when computing the port0/port1 offsets. For most registers, 98 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 99 */ 100 #define SK_IF_READ_4(sc_if, skip, reg) \ 101 sk_win_read_4(sc_if->sk_softc, reg + \ 102 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 103 #define SK_IF_READ_2(sc_if, skip, reg) \ 104 sk_win_read_2(sc_if->sk_softc, reg + \ 105 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 106 #define SK_IF_READ_1(sc_if, skip, reg) \ 107 sk_win_read_1(sc_if->sk_softc, reg + \ 108 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 109 110 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 111 sk_win_write_4(sc_if->sk_softc, \ 112 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 113 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 114 sk_win_write_2(sc_if->sk_softc, \ 115 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 116 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 117 sk_win_write_1(sc_if->sk_softc, \ 118 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 119 120 /* Block 0 registers, permanently mapped at iobase. */ 121 #define SK_RAP 0x0000 122 #define SK_CSR 0x0004 123 #define SK_LED 0x0006 124 #define SK_ISR 0x0008 /* interrupt source */ 125 #define SK_IMR 0x000C /* interrupt mask */ 126 #define SK_IESR 0x0010 /* interrupt hardware error source */ 127 #define SK_IEMR 0x0014 /* interrupt hardware error mask */ 128 #define SK_ISSR 0x0018 /* special interrupt source */ 129 #define SK_XM_IMR0 0x0020 130 #define SK_XM_ISR0 0x0028 131 #define SK_XM_PHYADDR0 0x0030 132 #define SK_XM_PHYDATA0 0x0034 133 #define SK_XM_IMR1 0x0040 134 #define SK_XM_ISR1 0x0048 135 #define SK_XM_PHYADDR1 0x0050 136 #define SK_XM_PHYDATA1 0x0054 137 #define SK_BMU_RX_CSR0 0x0060 138 #define SK_BMU_RX_CSR1 0x0064 139 #define SK_BMU_TXS_CSR0 0x0068 140 #define SK_BMU_TXA_CSR0 0x006C 141 #define SK_BMU_TXS_CSR1 0x0070 142 #define SK_BMU_TXA_CSR1 0x0074 143 144 /* SK_CSR register */ 145 #define SK_CSR_SW_RESET 0x0001 146 #define SK_CSR_SW_UNRESET 0x0002 147 #define SK_CSR_MASTER_RESET 0x0004 148 #define SK_CSR_MASTER_UNRESET 0x0008 149 #define SK_CSR_MASTER_STOP 0x0010 150 #define SK_CSR_MASTER_DONE 0x0020 151 #define SK_CSR_SW_IRQ_CLEAR 0x0040 152 #define SK_CSR_SW_IRQ_SET 0x0080 153 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 154 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 MHz, = 33 */ 155 156 /* SK_LED register */ 157 #define SK_LED_GREEN_OFF 0x01 158 #define SK_LED_GREEN_ON 0x02 159 160 /* SK_ISR register */ 161 #define SK_ISR_TX2_AS_CHECK 0x00000001 162 #define SK_ISR_TX2_AS_EOF 0x00000002 163 #define SK_ISR_TX2_AS_EOB 0x00000004 164 #define SK_ISR_TX2_S_CHECK 0x00000008 165 #define SK_ISR_TX2_S_EOF 0x00000010 166 #define SK_ISR_TX2_S_EOB 0x00000020 167 #define SK_ISR_TX1_AS_CHECK 0x00000040 168 #define SK_ISR_TX1_AS_EOF 0x00000080 169 #define SK_ISR_TX1_AS_EOB 0x00000100 170 #define SK_ISR_TX1_S_CHECK 0x00000200 171 #define SK_ISR_TX1_S_EOF 0x00000400 172 #define SK_ISR_TX1_S_EOB 0x00000800 173 #define SK_ISR_RX2_CHECK 0x00001000 174 #define SK_ISR_RX2_EOF 0x00002000 175 #define SK_ISR_RX2_EOB 0x00004000 176 #define SK_ISR_RX1_CHECK 0x00008000 177 #define SK_ISR_RX1_EOF 0x00010000 178 #define SK_ISR_RX1_EOB 0x00020000 179 #define SK_ISR_LINK2_OFLOW 0x00040000 180 #define SK_ISR_MAC2 0x00080000 181 #define SK_ISR_LINK1_OFLOW 0x00100000 182 #define SK_ISR_MAC1 0x00200000 183 #define SK_ISR_TIMER 0x00400000 184 #define SK_ISR_EXTERNAL_REG 0x00800000 185 #define SK_ISR_SW 0x01000000 186 #define SK_ISR_I2C_RDY 0x02000000 187 #define SK_ISR_TX2_TIMEO 0x04000000 188 #define SK_ISR_TX1_TIMEO 0x08000000 189 #define SK_ISR_RX2_TIMEO 0x10000000 190 #define SK_ISR_RX1_TIMEO 0x20000000 191 #define SK_ISR_RSVD 0x40000000 192 #define SK_ISR_HWERR 0x80000000 193 194 /* SK_IMR register */ 195 #define SK_IMR_TX2_AS_CHECK 0x00000001 196 #define SK_IMR_TX2_AS_EOF 0x00000002 197 #define SK_IMR_TX2_AS_EOB 0x00000004 198 #define SK_IMR_TX2_S_CHECK 0x00000008 199 #define SK_IMR_TX2_S_EOF 0x00000010 200 #define SK_IMR_TX2_S_EOB 0x00000020 201 #define SK_IMR_TX1_AS_CHECK 0x00000040 202 #define SK_IMR_TX1_AS_EOF 0x00000080 203 #define SK_IMR_TX1_AS_EOB 0x00000100 204 #define SK_IMR_TX1_S_CHECK 0x00000200 205 #define SK_IMR_TX1_S_EOF 0x00000400 206 #define SK_IMR_TX1_S_EOB 0x00000800 207 #define SK_IMR_RX2_CHECK 0x00001000 208 #define SK_IMR_RX2_EOF 0x00002000 209 #define SK_IMR_RX2_EOB 0x00004000 210 #define SK_IMR_RX1_CHECK 0x00008000 211 #define SK_IMR_RX1_EOF 0x00010000 212 #define SK_IMR_RX1_EOB 0x00020000 213 #define SK_IMR_LINK2_OFLOW 0x00040000 214 #define SK_IMR_MAC2 0x00080000 215 #define SK_IMR_LINK1_OFLOW 0x00100000 216 #define SK_IMR_MAC1 0x00200000 217 #define SK_IMR_TIMER 0x00400000 218 #define SK_IMR_EXTERNAL_REG 0x00800000 219 #define SK_IMR_SW 0x01000000 220 #define SK_IMR_I2C_RDY 0x02000000 221 #define SK_IMR_TX2_TIMEO 0x04000000 222 #define SK_IMR_TX1_TIMEO 0x08000000 223 #define SK_IMR_RX2_TIMEO 0x10000000 224 #define SK_IMR_RX1_TIMEO 0x20000000 225 #define SK_IMR_RSVD 0x40000000 226 #define SK_IMR_HWERR 0x80000000 227 228 #define SK_INTRS1 \ 229 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 230 231 #define SK_INTRS2 \ 232 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 233 234 /* SK_IESR register */ 235 #define SK_IESR_PAR_RX2 0x00000001 236 #define SK_IESR_PAR_RX1 0x00000002 237 #define SK_IESR_PAR_MAC2 0x00000004 238 #define SK_IESR_PAR_MAC1 0x00000008 239 #define SK_IESR_PAR_WR_RAM 0x00000010 240 #define SK_IESR_PAR_RD_RAM 0x00000020 241 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040 242 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080 243 #define SK_IESR_NO_STS_MAC2 0x00000100 244 #define SK_IESR_NO_STS_MAC1 0x00000200 245 #define SK_IESR_IRQ_STS 0x00000400 246 #define SK_IESR_MASTERERR 0x00000800 247 248 /* SK_IEMR register */ 249 #define SK_IEMR_PAR_RX2 0x00000001 250 #define SK_IEMR_PAR_RX1 0x00000002 251 #define SK_IEMR_PAR_MAC2 0x00000004 252 #define SK_IEMR_PAR_MAC1 0x00000008 253 #define SK_IEMR_PAR_WR_RAM 0x00000010 254 #define SK_IEMR_PAR_RD_RAM 0x00000020 255 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 256 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 257 #define SK_IEMR_NO_STS_MAC2 0x00000100 258 #define SK_IEMR_NO_STS_MAC1 0x00000200 259 #define SK_IEMR_IRQ_STS 0x00000400 260 #define SK_IEMR_MASTERERR 0x00000800 261 262 /* Block 2 */ 263 #define SK_MAC0_0 0x0100 264 #define SK_MAC0_1 0x0104 265 #define SK_MAC1_0 0x0108 266 #define SK_MAC1_1 0x010C 267 #define SK_MAC2_0 0x0110 268 #define SK_MAC2_1 0x0114 269 #define SK_CONNTYPE 0x0118 270 #define SK_PMDTYPE 0x0119 271 #define SK_CONFIG 0x011A 272 #define SK_CHIPVER 0x011B 273 #define SK_EPROM0 0x011C 274 #define SK_EPROM1 0x011D 275 #define SK_EPROM2 0x011E 276 #define SK_EPROM3 0x011F 277 #define SK_EP_ADDR 0x0120 278 #define SK_EP_DATA 0x0124 279 #define SK_EP_LOADCTL 0x0128 280 #define SK_EP_LOADTST 0x0129 281 #define SK_TIMERINIT 0x0130 282 #define SK_TIMER 0x0134 283 #define SK_TIMERCTL 0x0138 284 #define SK_TIMERTST 0x0139 285 #define SK_IMTIMERINIT 0x0140 286 #define SK_IMTIMER 0x0144 287 #define SK_IMTIMERCTL 0x0148 288 #define SK_IMTIMERTST 0x0149 289 #define SK_IMMR 0x014C 290 #define SK_IHWEMR 0x0150 291 #define SK_TESTCTL1 0x0158 292 #define SK_TESTCTL2 0x0159 293 #define SK_GPIO 0x015C 294 #define SK_I2CHWCTL 0x0160 295 #define SK_I2CHWDATA 0x0164 296 #define SK_I2CHWIRQ 0x0168 297 #define SK_I2CSW 0x016C 298 #define SK_BLNKINIT 0x0170 299 #define SK_BLNKCOUNT 0x0174 300 #define SK_BLNKCTL 0x0178 301 #define SK_BLNKSTS 0x0179 302 #define SK_BLNKTST 0x017A 303 304 #define SK_IMCTL_STOP 0x02 305 #define SK_IMCTL_START 0x04 306 307 #define SK_IMTIMER_TICKS 54 308 #define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 309 310 /* 311 * The SK_EPROM0 register contains a byte that describes the 312 * amount of SRAM mounted on the NIC. The value also tells if 313 * the chips are 64K or 128K. This affects the RAMbuffer address 314 * offset that we need to use. 315 */ 316 #define SK_RAMSIZE_512K_64 0x1 317 #define SK_RAMSIZE_1024K_128 0x2 318 #define SK_RAMSIZE_1024K_64 0x3 319 #define SK_RAMSIZE_2048K_128 0x4 320 321 #define SK_RBOFF_0 0x0 322 #define SK_RBOFF_80000 0x80000 323 324 /* 325 * SK_EEPROM1 contains the PHY type, which may be XMAC for 326 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 327 * PHY. 328 */ 329 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 330 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 331 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 332 #define SK_PHYTYPE_NAT 3 /* National DP83891 */ 333 334 /* 335 * PHY addresses. 336 */ 337 #define SK_PHYADDR_XMAC 0x0 338 #define SK_PHYADDR_BCOM 0x1 339 #define SK_PHYADDR_LONE 0x3 340 #define SK_PHYADDR_NAT 0x0 341 342 #define SK_CONFIG_SINGLEMAC 0x01 343 #define SK_CONFIG_DIS_DSL_CLK 0x02 344 345 #define SK_PMD_1000BASELX 0x4C 346 #define SK_PMD_1000BASESX 0x53 347 #define SK_PMD_1000BASECX 0x43 348 #define SK_PMD_1000BASETX 0x54 349 350 /* GPIO bits */ 351 #define SK_GPIO_DAT0 0x00000001 352 #define SK_GPIO_DAT1 0x00000002 353 #define SK_GPIO_DAT2 0x00000004 354 #define SK_GPIO_DAT3 0x00000008 355 #define SK_GPIO_DAT4 0x00000010 356 #define SK_GPIO_DAT5 0x00000020 357 #define SK_GPIO_DAT6 0x00000040 358 #define SK_GPIO_DAT7 0x00000080 359 #define SK_GPIO_DAT8 0x00000100 360 #define SK_GPIO_DAT9 0x00000200 361 #define SK_GPIO_DIR0 0x00010000 362 #define SK_GPIO_DIR1 0x00020000 363 #define SK_GPIO_DIR2 0x00040000 364 #define SK_GPIO_DIR3 0x00080000 365 #define SK_GPIO_DIR4 0x00100000 366 #define SK_GPIO_DIR5 0x00200000 367 #define SK_GPIO_DIR6 0x00400000 368 #define SK_GPIO_DIR7 0x00800000 369 #define SK_GPIO_DIR8 0x01000000 370 #define SK_GPIO_DIR9 0x02000000 371 372 /* Block 3 Ram interface and MAC arbiter registers */ 373 #define SK_RAMADDR 0x0180 374 #define SK_RAMDATA0 0x0184 375 #define SK_RAMDATA1 0x0188 376 #define SK_TO0 0x0190 377 #define SK_TO1 0x0191 378 #define SK_TO2 0x0192 379 #define SK_TO3 0x0193 380 #define SK_TO4 0x0194 381 #define SK_TO5 0x0195 382 #define SK_TO6 0x0196 383 #define SK_TO7 0x0197 384 #define SK_TO8 0x0198 385 #define SK_TO9 0x0199 386 #define SK_TO10 0x019A 387 #define SK_TO11 0x019B 388 #define SK_RITIMEO_TMR 0x019C 389 #define SK_RAMCTL 0x01A0 390 #define SK_RITIMER_TST 0x01A2 391 392 #define SK_RAMCTL_RESET 0x0001 393 #define SK_RAMCTL_UNRESET 0x0002 394 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 395 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 396 397 /* Mac arbiter registers */ 398 #define SK_MINIT_RX1 0x01B0 399 #define SK_MINIT_RX2 0x01B1 400 #define SK_MINIT_TX1 0x01B2 401 #define SK_MINIT_TX2 0x01B3 402 #define SK_MTIMEO_RX1 0x01B4 403 #define SK_MTIMEO_RX2 0x01B5 404 #define SK_MTIMEO_TX1 0x01B6 405 #define SK_MTIEMO_TX2 0x01B7 406 #define SK_MACARB_CTL 0x01B8 407 #define SK_MTIMER_TST 0x01BA 408 #define SK_RCINIT_RX1 0x01C0 409 #define SK_RCINIT_RX2 0x01C1 410 #define SK_RCINIT_TX1 0x01C2 411 #define SK_RCINIT_TX2 0x01C3 412 #define SK_RCTIMEO_RX1 0x01C4 413 #define SK_RCTIMEO_RX2 0x01C5 414 #define SK_RCTIMEO_TX1 0x01C6 415 #define SK_RCTIMEO_TX2 0x01C7 416 #define SK_RECOVERY_CTL 0x01C8 417 #define SK_RCTIMER_TST 0x01CA 418 419 /* Packet arbiter registers */ 420 #define SK_RXPA1_TINIT 0x01D0 421 #define SK_RXPA2_TINIT 0x01D4 422 #define SK_TXPA1_TINIT 0x01D8 423 #define SK_TXPA2_TINIT 0x01DC 424 #define SK_RXPA1_TIMEO 0x01E0 425 #define SK_RXPA2_TIMEO 0x01E4 426 #define SK_TXPA1_TIMEO 0x01E8 427 #define SK_TXPA2_TIMEO 0x01EC 428 #define SK_PKTARB_CTL 0x01F0 429 #define SK_PKTATB_TST 0x01F2 430 431 #define SK_PKTARB_TIMEOUT 0x2000 432 433 #define SK_PKTARBCTL_RESET 0x0001 434 #define SK_PKTARBCTL_UNRESET 0x0002 435 #define SK_PKTARBCTL_RXTO1_OFF 0x0004 436 #define SK_PKTARBCTL_RXTO1_ON 0x0008 437 #define SK_PKTARBCTL_RXTO2_OFF 0x0010 438 #define SK_PKTARBCTL_RXTO2_ON 0x0020 439 #define SK_PKTARBCTL_TXTO1_OFF 0x0040 440 #define SK_PKTARBCTL_TXTO1_ON 0x0080 441 #define SK_PKTARBCTL_TXTO2_OFF 0x0100 442 #define SK_PKTARBCTL_TXTO2_ON 0x0200 443 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 444 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 445 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 446 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 447 448 #define SK_MINIT_XMAC_B2 54 449 #define SK_MINIT_XMAC_C1 63 450 451 #define SK_MACARBCTL_RESET 0x0001 452 #define SK_MACARBCTL_UNRESET 0x0002 453 #define SK_MACARBCTL_FASTOE_OFF 0x0004 454 #define SK_MACARBCRL_FASTOE_ON 0x0008 455 456 #define SK_RCINIT_XMAC_B2 54 457 #define SK_RCINIT_XMAC_C1 0 458 459 #define SK_RECOVERYCTL_RX1_OFF 0x0001 460 #define SK_RECOVERYCTL_RX1_ON 0x0002 461 #define SK_RECOVERYCTL_RX2_OFF 0x0004 462 #define SK_RECOVERYCTL_RX2_ON 0x0008 463 #define SK_RECOVERYCTL_TX1_OFF 0x0010 464 #define SK_RECOVERYCTL_TX1_ON 0x0020 465 #define SK_RECOVERYCTL_TX2_OFF 0x0040 466 #define SK_RECOVERYCTL_TX2_ON 0x0080 467 468 #define SK_RECOVERY_XMAC_B2 \ 469 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 470 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 471 472 #define SK_RECOVERY_XMAC_C1 \ 473 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 474 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 475 476 /* Block 4 -- TX Arbiter MAC 1 */ 477 #define SK_TXAR1_TIMERINIT 0x0200 478 #define SK_TXAR1_TIMERVAL 0x0204 479 #define SK_TXAR1_LIMITINIT 0x0208 480 #define SK_TXAR1_LIMITCNT 0x020C 481 #define SK_TXAR1_COUNTERCTL 0x0210 482 #define SK_TXAR1_COUNTERTST 0x0212 483 #define SK_TXAR1_COUNTERSTS 0x0212 484 485 /* Block 5 -- TX Arbiter MAC 2 */ 486 #define SK_TXAR2_TIMERINIT 0x0280 487 #define SK_TXAR2_TIMERVAL 0x0284 488 #define SK_TXAR2_LIMITINIT 0x0288 489 #define SK_TXAR2_LIMITCNT 0x028C 490 #define SK_TXAR2_COUNTERCTL 0x0290 491 #define SK_TXAR2_COUNTERTST 0x0291 492 #define SK_TXAR2_COUNTERSTS 0x0292 493 494 #define SK_TXARCTL_OFF 0x01 495 #define SK_TXARCTL_ON 0x02 496 #define SK_TXARCTL_RATECTL_OFF 0x04 497 #define SK_TXARCTL_RATECTL_ON 0x08 498 #define SK_TXARCTL_ALLOC_OFF 0x10 499 #define SK_TXARCTL_ALLOC_ON 0x20 500 #define SK_TXARCTL_FSYNC_OFF 0x40 501 #define SK_TXARCTL_FSYNC_ON 0x80 502 503 /* Block 6 -- External registers */ 504 #define SK_EXTREG_BASE 0x300 505 #define SK_EXTREG_END 0x37C 506 507 /* Block 7 -- PCI config registers */ 508 #define SK_PCI_BASE 0x0380 509 #define SK_PCI_END 0x03FC 510 511 /* Compute offset of mirrored PCI register */ 512 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 513 514 /* Block 8 -- RX queue 1 */ 515 #define SK_RXQ1_BUFCNT 0x0400 516 #define SK_RXQ1_BUFCTL 0x0402 517 #define SK_RXQ1_NEXTDESC 0x0404 518 #define SK_RXQ1_RXBUF_LO 0x0408 519 #define SK_RXQ1_RXBUF_HI 0x040C 520 #define SK_RXQ1_RXSTAT 0x0410 521 #define SK_RXQ1_TIMESTAMP 0x0414 522 #define SK_RXQ1_CSUM1 0x0418 523 #define SK_RXQ1_CSUM2 0x041A 524 #define SK_RXQ1_CSUM1_START 0x041C 525 #define SK_RXQ1_CSUM2_START 0x041E 526 #define SK_RXQ1_CURADDR_LO 0x0420 527 #define SK_RXQ1_CURADDR_HI 0x0424 528 #define SK_RXQ1_CURCNT_LO 0x0428 529 #define SK_RXQ1_CURCNT_HI 0x042C 530 #define SK_RXQ1_CURBYTES 0x0430 531 #define SK_RXQ1_BMU_CSR 0x0434 532 #define SK_RXQ1_WATERMARK 0x0438 533 #define SK_RXQ1_FLAG 0x043A 534 #define SK_RXQ1_TEST1 0x043C 535 #define SK_RXQ1_TEST2 0x0440 536 #define SK_RXQ1_TEST3 0x0444 537 538 /* Block 9 -- RX queue 2 */ 539 #define SK_RXQ2_BUFCNT 0x0480 540 #define SK_RXQ2_BUFCTL 0x0482 541 #define SK_RXQ2_NEXTDESC 0x0484 542 #define SK_RXQ2_RXBUF_LO 0x0488 543 #define SK_RXQ2_RXBUF_HI 0x048C 544 #define SK_RXQ2_RXSTAT 0x0490 545 #define SK_RXQ2_TIMESTAMP 0x0494 546 #define SK_RXQ2_CSUM1 0x0498 547 #define SK_RXQ2_CSUM2 0x049A 548 #define SK_RXQ2_CSUM1_START 0x049C 549 #define SK_RXQ2_CSUM2_START 0x049E 550 #define SK_RXQ2_CURADDR_LO 0x04A0 551 #define SK_RXQ2_CURADDR_HI 0x04A4 552 #define SK_RXQ2_CURCNT_LO 0x04A8 553 #define SK_RXQ2_CURCNT_HI 0x04AC 554 #define SK_RXQ2_CURBYTES 0x04B0 555 #define SK_RXQ2_BMU_CSR 0x04B4 556 #define SK_RXQ2_WATERMARK 0x04B8 557 #define SK_RXQ2_FLAG 0x04BA 558 #define SK_RXQ2_TEST1 0x04BC 559 #define SK_RXQ2_TEST2 0x04C0 560 #define SK_RXQ2_TEST3 0x04C4 561 562 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001 563 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002 564 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004 565 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008 566 #define SK_RXBMU_RX_START 0x00000010 567 #define SK_RXBMU_RX_STOP 0x00000020 568 #define SK_RXBMU_POLL_OFF 0x00000040 569 #define SK_RXBMU_POLL_ON 0x00000080 570 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 571 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 572 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400 573 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 574 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000 575 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 576 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 577 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 578 #define SK_RXBMU_PFI_SM_RESET 0x00010000 579 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000 580 #define SK_RXBMU_FIFO_RESET 0x00040000 581 #define SK_RXBMU_FIFO_UNRESET 0x00080000 582 #define SK_RXBMU_DESC_RESET 0x00100000 583 #define SK_RXBMU_DESC_UNRESET 0x00200000 584 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 585 586 #define SK_RXBMU_ONLINE \ 587 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 588 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 589 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 590 SK_RXBMU_DESC_UNRESET) 591 592 #define SK_RXBMU_OFFLINE \ 593 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 594 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 595 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 596 SK_RXBMU_DESC_RESET) 597 598 /* Block 12 -- TX sync queue 1 */ 599 #define SK_TXQS1_BUFCNT 0x0600 600 #define SK_TXQS1_BUFCTL 0x0602 601 #define SK_TXQS1_NEXTDESC 0x0604 602 #define SK_TXQS1_RXBUF_LO 0x0608 603 #define SK_TXQS1_RXBUF_HI 0x060C 604 #define SK_TXQS1_RXSTAT 0x0610 605 #define SK_TXQS1_CSUM_STARTVAL 0x0614 606 #define SK_TXQS1_CSUM_STARTPOS 0x0618 607 #define SK_TXQS1_CSUM_WRITEPOS 0x061A 608 #define SK_TXQS1_CURADDR_LO 0x0620 609 #define SK_TXQS1_CURADDR_HI 0x0624 610 #define SK_TXQS1_CURCNT_LO 0x0628 611 #define SK_TXQS1_CURCNT_HI 0x062C 612 #define SK_TXQS1_CURBYTES 0x0630 613 #define SK_TXQS1_BMU_CSR 0x0634 614 #define SK_TXQS1_WATERMARK 0x0638 615 #define SK_TXQS1_FLAG 0x063A 616 #define SK_TXQS1_TEST1 0x063C 617 #define SK_TXQS1_TEST2 0x0640 618 #define SK_TXQS1_TEST3 0x0644 619 620 /* Block 13 -- TX async queue 1 */ 621 #define SK_TXQA1_BUFCNT 0x0680 622 #define SK_TXQA1_BUFCTL 0x0682 623 #define SK_TXQA1_NEXTDESC 0x0684 624 #define SK_TXQA1_RXBUF_LO 0x0688 625 #define SK_TXQA1_RXBUF_HI 0x068C 626 #define SK_TXQA1_RXSTAT 0x0690 627 #define SK_TXQA1_CSUM_STARTVAL 0x0694 628 #define SK_TXQA1_CSUM_STARTPOS 0x0698 629 #define SK_TXQA1_CSUM_WRITEPOS 0x069A 630 #define SK_TXQA1_CURADDR_LO 0x06A0 631 #define SK_TXQA1_CURADDR_HI 0x06A4 632 #define SK_TXQA1_CURCNT_LO 0x06A8 633 #define SK_TXQA1_CURCNT_HI 0x06AC 634 #define SK_TXQA1_CURBYTES 0x06B0 635 #define SK_TXQA1_BMU_CSR 0x06B4 636 #define SK_TXQA1_WATERMARK 0x06B8 637 #define SK_TXQA1_FLAG 0x06BA 638 #define SK_TXQA1_TEST1 0x06BC 639 #define SK_TXQA1_TEST2 0x06C0 640 #define SK_TXQA1_TEST3 0x06C4 641 642 /* Block 14 -- TX sync queue 2 */ 643 #define SK_TXQS2_BUFCNT 0x0700 644 #define SK_TXQS2_BUFCTL 0x0702 645 #define SK_TXQS2_NEXTDESC 0x0704 646 #define SK_TXQS2_RXBUF_LO 0x0708 647 #define SK_TXQS2_RXBUF_HI 0x070C 648 #define SK_TXQS2_RXSTAT 0x0710 649 #define SK_TXQS2_CSUM_STARTVAL 0x0714 650 #define SK_TXQS2_CSUM_STARTPOS 0x0718 651 #define SK_TXQS2_CSUM_WRITEPOS 0x071A 652 #define SK_TXQS2_CURADDR_LO 0x0720 653 #define SK_TXQS2_CURADDR_HI 0x0724 654 #define SK_TXQS2_CURCNT_LO 0x0728 655 #define SK_TXQS2_CURCNT_HI 0x072C 656 #define SK_TXQS2_CURBYTES 0x0730 657 #define SK_TXQS2_BMU_CSR 0x0734 658 #define SK_TXQS2_WATERMARK 0x0738 659 #define SK_TXQS2_FLAG 0x073A 660 #define SK_TXQS2_TEST1 0x073C 661 #define SK_TXQS2_TEST2 0x0740 662 #define SK_TXQS2_TEST3 0x0744 663 664 /* Block 15 -- TX async queue 2 */ 665 #define SK_TXQA2_BUFCNT 0x0780 666 #define SK_TXQA2_BUFCTL 0x0782 667 #define SK_TXQA2_NEXTDESC 0x0784 668 #define SK_TXQA2_RXBUF_LO 0x0788 669 #define SK_TXQA2_RXBUF_HI 0x078C 670 #define SK_TXQA2_RXSTAT 0x0790 671 #define SK_TXQA2_CSUM_STARTVAL 0x0794 672 #define SK_TXQA2_CSUM_STARTPOS 0x0798 673 #define SK_TXQA2_CSUM_WRITEPOS 0x079A 674 #define SK_TXQA2_CURADDR_LO 0x07A0 675 #define SK_TXQA2_CURADDR_HI 0x07A4 676 #define SK_TXQA2_CURCNT_LO 0x07A8 677 #define SK_TXQA2_CURCNT_HI 0x07AC 678 #define SK_TXQA2_CURBYTES 0x07B0 679 #define SK_TXQA2_BMU_CSR 0x07B4 680 #define SK_TXQA2_WATERMARK 0x07B8 681 #define SK_TXQA2_FLAG 0x07BA 682 #define SK_TXQA2_TEST1 0x07BC 683 #define SK_TXQA2_TEST2 0x07C0 684 #define SK_TXQA2_TEST3 0x07C4 685 686 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001 687 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002 688 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004 689 #define SK_TXBMU_TX_START 0x00000010 690 #define SK_TXBMU_TX_STOP 0x00000020 691 #define SK_TXBMU_POLL_OFF 0x00000040 692 #define SK_TXBMU_POLL_ON 0x00000080 693 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 694 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 695 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400 696 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 697 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000 698 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 699 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 700 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 701 #define SK_TXBMU_PFI_SM_RESET 0x00010000 702 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000 703 #define SK_TXBMU_FIFO_RESET 0x00040000 704 #define SK_TXBMU_FIFO_UNRESET 0x00080000 705 #define SK_TXBMU_DESC_RESET 0x00100000 706 #define SK_TXBMU_DESC_UNRESET 0x00200000 707 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 708 709 #define SK_TXBMU_ONLINE \ 710 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 711 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 712 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 713 SK_TXBMU_DESC_UNRESET) 714 715 #define SK_TXBMU_OFFLINE \ 716 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 717 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 718 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 719 SK_TXBMU_DESC_RESET) 720 721 /* Block 16 -- Receive RAMbuffer 1 */ 722 #define SK_RXRB1_START 0x0800 723 #define SK_RXRB1_END 0x0804 724 #define SK_RXRB1_WR_PTR 0x0808 725 #define SK_RXRB1_RD_PTR 0x080C 726 #define SK_RXRB1_UTHR_PAUSE 0x0810 727 #define SK_RXRB1_LTHR_PAUSE 0x0814 728 #define SK_RXRB1_UTHR_HIPRIO 0x0818 729 #define SK_RXRB1_UTHR_LOPRIO 0x081C 730 #define SK_RXRB1_PKTCNT 0x0820 731 #define SK_RXRB1_LVL 0x0824 732 #define SK_RXRB1_CTLTST 0x0828 733 734 /* Block 17 -- Receive RAMbuffer 2 */ 735 #define SK_RXRB2_START 0x0880 736 #define SK_RXRB2_END 0x0884 737 #define SK_RXRB2_WR_PTR 0x0888 738 #define SK_RXRB2_RD_PTR 0x088C 739 #define SK_RXRB2_UTHR_PAUSE 0x0890 740 #define SK_RXRB2_LTHR_PAUSE 0x0894 741 #define SK_RXRB2_UTHR_HIPRIO 0x0898 742 #define SK_RXRB2_UTHR_LOPRIO 0x089C 743 #define SK_RXRB2_PKTCNT 0x08A0 744 #define SK_RXRB2_LVL 0x08A4 745 #define SK_RXRB2_CTLTST 0x08A8 746 747 /* Block 20 -- Sync. Transmit RAMbuffer 1 */ 748 #define SK_TXRBS1_START 0x0A00 749 #define SK_TXRBS1_END 0x0A04 750 #define SK_TXRBS1_WR_PTR 0x0A08 751 #define SK_TXRBS1_RD_PTR 0x0A0C 752 #define SK_TXRBS1_PKTCNT 0x0A20 753 #define SK_TXRBS1_LVL 0x0A24 754 #define SK_TXRBS1_CTLTST 0x0A28 755 756 /* Block 21 -- Async. Transmit RAMbuffer 1 */ 757 #define SK_TXRBA1_START 0x0A80 758 #define SK_TXRBA1_END 0x0A84 759 #define SK_TXRBA1_WR_PTR 0x0A88 760 #define SK_TXRBA1_RD_PTR 0x0A8C 761 #define SK_TXRBA1_PKTCNT 0x0AA0 762 #define SK_TXRBA1_LVL 0x0AA4 763 #define SK_TXRBA1_CTLTST 0x0AA8 764 765 /* Block 22 -- Sync. Transmit RAMbuffer 2 */ 766 #define SK_TXRBS2_START 0x0B00 767 #define SK_TXRBS2_END 0x0B04 768 #define SK_TXRBS2_WR_PTR 0x0B08 769 #define SK_TXRBS2_RD_PTR 0x0B0C 770 #define SK_TXRBS2_PKTCNT 0x0B20 771 #define SK_TXRBS2_LVL 0x0B24 772 #define SK_TXRBS2_CTLTST 0x0B28 773 774 /* Block 23 -- Async. Transmit RAMbuffer 2 */ 775 #define SK_TXRBA2_START 0x0B80 776 #define SK_TXRBA2_END 0x0B84 777 #define SK_TXRBA2_WR_PTR 0x0B88 778 #define SK_TXRBA2_RD_PTR 0x0B8C 779 #define SK_TXRBA2_PKTCNT 0x0BA0 780 #define SK_TXRBA2_LVL 0x0BA4 781 #define SK_TXRBA2_CTLTST 0x0BA8 782 783 #define SK_RBCTL_RESET 0x00000001 784 #define SK_RBCTL_UNRESET 0x00000002 785 #define SK_RBCTL_OFF 0x00000004 786 #define SK_RBCTL_ON 0x00000008 787 #define SK_RBCTL_STORENFWD_OFF 0x00000010 788 #define SK_RBCTL_STORENFWD_ON 0x00000020 789 790 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 791 #define SK_RXF1_END 0x0C00 792 #define SK_RXF1_WPTR 0x0C04 793 #define SK_RXF1_RPTR 0x0C0C 794 #define SK_RXF1_PKTCNT 0x0C10 795 #define SK_RXF1_LVL 0x0C14 796 #define SK_RXF1_MACCTL 0x0C18 797 #define SK_RXF1_CTL 0x0C1C 798 #define SK_RXLED1_CNTINIT 0x0C20 799 #define SK_RXLED1_COUNTER 0x0C24 800 #define SK_RXLED1_CTL 0x0C28 801 #define SK_RXLED1_TST 0x0C29 802 #define SK_LINK_SYNC1_CINIT 0x0C30 803 #define SK_LINK_SYNC1_COUNTER 0x0C34 804 #define SK_LINK_SYNC1_CTL 0x0C38 805 #define SK_LINK_SYNC1_TST 0x0C39 806 #define SK_LINKLED1_CTL 0x0C3C 807 808 #define SK_FIFO_END 0x3F 809 810 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 811 #define SK_RXF2_END 0x0C80 812 #define SK_RXF2_WPTR 0x0C84 813 #define SK_RXF2_RPTR 0x0C8C 814 #define SK_RXF2_PKTCNT 0x0C90 815 #define SK_RXF2_LVL 0x0C94 816 #define SK_RXF2_MACCTL 0x0C98 817 #define SK_RXF2_CTL 0x0C9C 818 #define SK_RXLED2_CNTINIT 0x0CA0 819 #define SK_RXLED2_COUNTER 0x0CA4 820 #define SK_RXLED2_CTL 0x0CA8 821 #define SK_RXLED2_TST 0x0CA9 822 #define SK_LINK_SYNC2_CINIT 0x0CB0 823 #define SK_LINK_SYNC2_COUNTER 0x0CB4 824 #define SK_LINK_SYNC2_CTL 0x0CB8 825 #define SK_LINK_SYNC2_TST 0x0CB9 826 #define SK_LINKLED2_CTL 0x0CBC 827 828 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 829 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 830 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004 831 #define SK_RXMACCTL_RSTAMP_ON 0x00000008 832 #define SK_RXMACCTL_FLUSH_OFF 0x00000010 833 #define SK_RXMACCTL_FLUSH_ON 0x00000020 834 #define SK_RXMACCTL_PAUSE_OFF 0x00000040 835 #define SK_RXMACCTL_PAUSE_ON 0x00000080 836 #define SK_RXMACCTL_AFULL_OFF 0x00000100 837 #define SK_RXMACCTL_AFULL_ON 0x00000200 838 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 839 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 840 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 841 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 842 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000 843 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 844 845 #define SK_RXLEDCTL_ENABLE 0x0001 846 #define SK_RXLEDCTL_COUNTER_STOP 0x0002 847 #define SK_RXLEDCTL_COUNTER_START 0x0004 848 849 #define SK_LINKLED_OFF 0x0001 850 #define SK_LINKLED_ON 0x0002 851 #define SK_LINKLED_LINKSYNC_OFF 0x0004 852 #define SK_LINKLED_LINKSYNC_ON 0x0008 853 #define SK_LINKLED_BLINK_OFF 0x0010 854 #define SK_LINKLED_BLINK_ON 0x0020 855 856 /* Block 26 -- TX MAC FIFO 1 regisrers */ 857 #define SK_TXF1_END 0x0D00 858 #define SK_TXF1_WPTR 0x0D04 859 #define SK_TXF1_RPTR 0x0D0C 860 #define SK_TXF1_PKTCNT 0x0D10 861 #define SK_TXF1_LVL 0x0D14 862 #define SK_TXF1_MACCTL 0x0D18 863 #define SK_TXF1_CTL 0x0D1C 864 #define SK_TXLED1_CNTINIT 0x0D20 865 #define SK_TXLED1_COUNTER 0x0D24 866 #define SK_TXLED1_CTL 0x0D28 867 #define SK_TXLED1_TST 0x0D29 868 869 /* Block 27 -- TX MAC FIFO 2 regisrers */ 870 #define SK_TXF2_END 0x0D80 871 #define SK_TXF2_WPTR 0x0D84 872 #define SK_TXF2_RPTR 0x0D8C 873 #define SK_TXF2_PKTCNT 0x0D90 874 #define SK_TXF2_LVL 0x0D94 875 #define SK_TXF2_MACCTL 0x0D98 876 #define SK_TXF2_CTL 0x0D9C 877 #define SK_TXLED2_CNTINIT 0x0DA0 878 #define SK_TXLED2_COUNTER 0x0DA4 879 #define SK_TXLED2_CTL 0x0DA8 880 #define SK_TXLED2_TST 0x0DA9 881 882 #define SK_TXMACCTL_XMAC_RESET 0x00000001 883 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002 884 #define SK_TXMACCTL_LOOP_OFF 0x00000004 885 #define SK_TXMACCTL_LOOP_ON 0x00000008 886 #define SK_TXMACCTL_FLUSH_OFF 0x00000010 887 #define SK_TXMACCTL_FLUSH_ON 0x00000020 888 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 889 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 890 #define SK_TXMACCTL_AFULL_OFF 0x00000100 891 #define SK_TXMACCTL_AFULL_ON 0x00000200 892 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 893 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 894 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 895 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 896 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 897 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 898 899 #define SK_TXLEDCTL_ENABLE 0x0001 900 #define SK_TXLEDCTL_COUNTER_STOP 0x0002 901 #define SK_TXLEDCTL_COUNTER_START 0x0004 902 903 #define SK_FIFO_RESET 0x00000001 904 #define SK_FIFO_UNRESET 0x00000002 905 #define SK_FIFO_OFF 0x00000004 906 #define SK_FIFO_ON 0x00000008 907 908 /* Block 0x40 to 0x4F -- XMAC 1 registers */ 909 #define SK_XMAC1_BASE 0x2000 910 #define SK_XMAC1_END 0x23FF 911 912 /* Block 0x60 to 0x6F -- XMAC 2 registers */ 913 #define SK_XMAC2_BASE 0x3000 914 #define SK_XMAC2_END 0x33FF 915 916 /* Compute relative offset of an XMAC register in the XMAC window(s). */ 917 #define SK_XMAC_REG(reg, mac) (((reg) * 2) + SK_XMAC1_BASE + \ 918 (mac * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 919 920 #define SK_XM_READ_4(sc, reg) \ 921 (sk_win_read_2(sc->sk_softc, \ 922 SK_XMAC_REG(reg, sc->sk_port)) & 0xFFFF) | \ 923 ((sk_win_read_2(sc->sk_softc, \ 924 SK_XMAC_REG(reg + 2, sc->sk_port)) << 16) & 0xFFFF0000) 925 926 #define SK_XM_WRITE_4(sc, reg, val) \ 927 sk_win_write_2(sc->sk_softc, \ 928 SK_XMAC_REG(reg, sc->sk_port), ((val) & 0xFFFF)); \ 929 sk_win_write_2(sc->sk_softc, \ 930 SK_XMAC_REG(reg + 2, sc->sk_port), ((val) >> 16) & 0xFFFF); 931 932 #define SK_XM_READ_2(sc, reg) \ 933 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(reg, sc->sk_port)) 934 935 #define SK_XM_WRITE_2(sc, reg, val) \ 936 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(reg, sc->sk_port), val) 937 938 #define SK_XM_SETBIT_4(sc, reg, x) \ 939 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 940 941 #define SK_XM_CLRBIT_4(sc, reg, x) \ 942 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 943 944 #define SK_XM_SETBIT_2(sc, reg, x) \ 945 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 946 947 #define SK_XM_CLRBIT_2(sc, reg, x) \ 948 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 949 950 951 /* 952 * The default FIFO threshold on the XMAC II is 4 bytes. On 953 * dual port NICs, this often leads to transmit underruns, so we 954 * bump the threshold a little. 955 */ 956 #define SK_XM_TX_FIFOTHRESH 512 957 958 #define SK_PCI_VENDOR_ID 0x0000 959 #define SK_PCI_DEVICE_ID 0x0002 960 #define SK_PCI_COMMAND 0x0004 961 #define SK_PCI_STATUS 0x0006 962 #define SK_PCI_REVID 0x0008 963 #define SK_PCI_CLASSCODE 0x0009 964 #define SK_PCI_CACHELEN 0x000C 965 #define SK_PCI_LATENCY_TIMER 0x000D 966 #define SK_PCI_HEADER_TYPE 0x000E 967 #define SK_PCI_LOMEM 0x0010 968 #define SK_PCI_LOIO 0x0014 969 #define SK_PCI_SUBVEN_ID 0x002C 970 #define SK_PCI_SYBSYS_ID 0x002E 971 #define SK_PCI_BIOSROM 0x0030 972 #define SK_PCI_INTLINE 0x003C 973 #define SK_PCI_INTPIN 0x003D 974 #define SK_PCI_MINGNT 0x003E 975 #define SK_PCI_MINLAT 0x003F 976 977 /* device specific PCI registers */ 978 #define SK_PCI_OURREG1 0x0040 979 #define SK_PCI_OURREG2 0x0044 980 #define SK_PCI_CAPID 0x0048 /* 8 bits */ 981 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 982 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 983 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 984 #define SK_PCI_PME_EVENT 0x004F 985 #define SK_PCI_VPD_CAPID 0x0050 986 #define SK_PCI_VPD_NEXTPTR 0x0051 987 #define SK_PCI_VPD_ADDR 0x0052 988 #define SK_PCI_VPD_DATA 0x0054 989 990 #define SK_PSTATE_MASK 0x0003 991 #define SK_PSTATE_D0 0x0000 992 #define SK_PSTATE_D1 0x0001 993 #define SK_PSTATE_D2 0x0002 994 #define SK_PSTATE_D3 0x0003 995 #define SK_PME_EN 0x0010 996 #define SK_PME_STATUS 0x8000 997 998 /* 999 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1000 * read is complete. Set to 1 to initiate a write, will become 0 1001 * when write is finished. 1002 */ 1003 #define SK_VPD_FLAG 0x8000 1004 1005 /* VPD structures */ 1006 struct vpd_res { 1007 u_int8_t vr_id; 1008 u_int8_t vr_len; 1009 u_int8_t vr_pad; 1010 }; 1011 1012 struct vpd_key { 1013 char vk_key[2]; 1014 u_int8_t vk_len; 1015 }; 1016 1017 #define VPD_RES_ID 0x82 /* ID string */ 1018 #define VPD_RES_READ 0x90 /* start of read only area */ 1019 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 1020 #define VPD_RES_END 0x78 /* end tag */ 1021 1022 #define CSR_WRITE_4(sc, reg, val) \ 1023 bus_space_write_4(sc->sk_btag, sc->sk_bhandle, reg, val) 1024 #define CSR_WRITE_2(sc, reg, val) \ 1025 bus_space_write_2(sc->sk_btag, sc->sk_bhandle, reg, val) 1026 #define CSR_WRITE_1(sc, reg, val) \ 1027 bus_space_write_1(sc->sk_btag, sc->sk_bhandle, reg, val) 1028 1029 #define CSR_READ_4(sc, reg) \ 1030 bus_space_read_4(sc->sk_btag, sc->sk_bhandle, reg) 1031 #define CSR_READ_2(sc, reg) \ 1032 bus_space_read_2(sc->sk_btag, sc->sk_bhandle, reg) 1033 #define CSR_READ_1(sc, reg) \ 1034 bus_space_read_1(sc->sk_btag, sc->sk_bhandle, reg) 1035 1036 struct sk_type { 1037 u_int16_t sk_vid; 1038 u_int16_t sk_did; 1039 char *sk_name; 1040 }; 1041 1042 /* RX queue descriptor data structure */ 1043 struct sk_rx_desc { 1044 u_int32_t sk_ctl; 1045 u_int32_t sk_next; 1046 u_int32_t sk_data_lo; 1047 u_int32_t sk_data_hi; 1048 u_int32_t sk_xmac_rxstat; 1049 u_int32_t sk_timestamp; 1050 u_int16_t sk_csum2; 1051 u_int16_t sk_csum1; 1052 u_int16_t sk_csum2_start; 1053 u_int16_t sk_csum1_start; 1054 }; 1055 1056 #define SK_OPCODE_DEFAULT 0x00550000 1057 #define SK_OPCODE_CSUM 0x00560000 1058 1059 #define SK_RXCTL_LEN 0x0000FFFF 1060 #define SK_RXCTL_OPCODE 0x00FF0000 1061 #define SK_RXCTL_TSTAMP_VALID 0x01000000 1062 #define SK_RXCTL_STATUS_VALID 0x02000000 1063 #define SK_RXCTL_DEV0 0x04000000 1064 #define SK_RXCTL_EOF_INTR 0x08000000 1065 #define SK_RXCTL_EOB_INTR 0x10000000 1066 #define SK_RXCTL_LASTFRAG 0x20000000 1067 #define SK_RXCTL_FIRSTFRAG 0x40000000 1068 #define SK_RXCTL_OWN 0x80000000 1069 1070 #define SK_RXSTAT \ 1071 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1072 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1073 1074 struct sk_tx_desc { 1075 u_int32_t sk_ctl; 1076 u_int32_t sk_next; 1077 u_int32_t sk_data_lo; 1078 u_int32_t sk_data_hi; 1079 u_int32_t sk_xmac_txstat; 1080 u_int16_t sk_rsvd0; 1081 u_int16_t sk_csum_startval; 1082 u_int16_t sk_csum_startpos; 1083 u_int16_t sk_csum_writepos; 1084 u_int32_t sk_rsvd1; 1085 }; 1086 1087 #define SK_TXCTL_LEN 0x0000FFFF 1088 #define SK_TXCTL_OPCODE 0x00FF0000 1089 #define SK_TXCTL_SW 0x01000000 1090 #define SK_TXCTL_NOCRC 0x02000000 1091 #define SK_TXCTL_STORENFWD 0x04000000 1092 #define SK_TXCTL_EOF_INTR 0x08000000 1093 #define SK_TXCTL_EOB_INTR 0x10000000 1094 #define SK_TXCTL_LASTFRAG 0x20000000 1095 #define SK_TXCTL_FIRSTFRAG 0x40000000 1096 #define SK_TXCTL_OWN 0x80000000 1097 1098 #define SK_TXSTAT \ 1099 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1100 1101 #define SK_RXBYTES(x) (x) & 0x0000FFFF; 1102 #define SK_TXBYTES SK_RXBYTES 1103 1104 #define SK_TX_RING_CNT 512 1105 #define SK_RX_RING_CNT 256 1106 1107 /* 1108 * Jumbo buffer stuff. Note that we must allocate more jumbo 1109 * buffers than there are descriptors in the receive ring. This 1110 * is because we don't know how long it will take for a packet 1111 * to be released after we hand it off to the upper protocol 1112 * layers. To be safe, we allocate 1.5 times the number of 1113 * receive descriptors. 1114 */ 1115 #define SK_JUMBO_FRAMELEN 9018 1116 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1117 #define SK_JSLOTS 384 1118 1119 #define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1120 #define SK_JLEN SK_JRAWLEN 1121 #define SK_MCLBYTES SK_JLEN 1122 #define SK_JPAGESZ PAGE_SIZE 1123 #define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1124 #define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1125 1126 struct sk_jslot { 1127 caddr_t sk_buf; 1128 int sk_inuse; 1129 }; 1130 1131 struct sk_jpool_entry { 1132 int slot; 1133 LIST_ENTRY(sk_jpool_entry) jpool_entries; 1134 }; 1135 1136 struct sk_chain { 1137 void *sk_desc; 1138 struct mbuf *sk_mbuf; 1139 struct sk_chain *sk_next; 1140 }; 1141 1142 /* 1143 * Number of DMA segments in a TxCB. Note that this is carefully 1144 * chosen to make the total struct size an even power of two. It's 1145 * critical that no TxCB be split across a page boundry since 1146 * no attempt is made to allocate physically contiguous memory. 1147 * 1148 */ 1149 #define SK_NTXSEG 30 1150 1151 struct sk_txmap_entry { 1152 bus_dmamap_t dmamap; 1153 SLIST_ENTRY(sk_txmap_entry) link; 1154 }; 1155 1156 struct sk_chain_data { 1157 struct sk_chain sk_tx_chain[SK_TX_RING_CNT]; 1158 struct sk_chain sk_rx_chain[SK_RX_RING_CNT]; 1159 struct sk_txmap_entry *sk_tx_map[SK_TX_RING_CNT]; 1160 bus_dmamap_t sk_rx_map[SK_RX_RING_CNT]; 1161 int sk_tx_prod; 1162 int sk_tx_cons; 1163 int sk_tx_cnt; 1164 int sk_rx_prod; 1165 int sk_rx_cons; 1166 int sk_rx_cnt; 1167 /* Stick the jumbo mem management stuff here too. */ 1168 struct sk_jslot sk_jslots[SK_JSLOTS]; 1169 void *sk_jumbo_buf; 1170 1171 }; 1172 1173 struct sk_ring_data { 1174 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT]; 1175 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT]; 1176 }; 1177 1178 #define SK_TX_RING_ADDR(sc, i) \ 1179 ((sc)->sk_ring_map->dm_segs[0].ds_addr + \ 1180 offsetof(struct sk_ring_data, sk_tx_ring[(i)])) 1181 1182 #define SK_RX_RING_ADDR(sc, i) \ 1183 ((sc)->sk_ring_map->dm_segs[0].ds_addr + \ 1184 offsetof(struct sk_ring_data, sk_rx_ring[(i)])) 1185 1186 struct sk_bcom_hack { 1187 int reg; 1188 int val; 1189 }; 1190 1191 #define SK_INC(x, y) (x) = (x + 1) % y 1192 1193 /* Forward decl. */ 1194 struct sk_if_softc; 1195 1196 /* Softc for the GEnesis controller. */ 1197 struct sk_softc { 1198 struct device sk_dev; /* generic device */ 1199 bus_space_handle_t sk_bhandle; /* bus space handle */ 1200 bus_space_tag_t sk_btag; /* bus space tag */ 1201 void *sk_intrhand; /* irq handler handle */ 1202 struct resource *sk_irq; /* IRQ resource handle */ 1203 struct resource *sk_res; /* I/O or shared mem handle */ 1204 u_int8_t sk_type; 1205 char *sk_vpd_prodname; 1206 char *sk_vpd_readonly; 1207 u_int32_t sk_rboff; /* RAMbuffer offset */ 1208 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1209 u_int32_t sk_pmd; /* physical media type */ 1210 u_int32_t sk_intrmask; 1211 bus_dma_tag_t sc_dmatag; 1212 struct sk_if_softc *sk_if[2]; 1213 }; 1214 1215 /* Softc for each logical interface */ 1216 struct sk_if_softc { 1217 struct device sk_dev; /* generic device */ 1218 struct arpcom arpcom; /* interface info */ 1219 struct mii_data sk_mii; 1220 u_int8_t sk_port; /* port # on controller */ 1221 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1222 u_int32_t sk_rx_ramstart; 1223 u_int32_t sk_rx_ramend; 1224 u_int32_t sk_tx_ramstart; 1225 u_int32_t sk_tx_ramend; 1226 int sk_phytype; 1227 int sk_phyaddr; 1228 int sk_cnt; 1229 int sk_link; 1230 struct timeout sk_tick_ch; 1231 struct sk_chain_data sk_cdata; 1232 struct sk_ring_data *sk_rdata; 1233 bus_dmamap_t sk_ring_map; 1234 struct sk_softc *sk_softc; /* parent controller */ 1235 int sk_tx_bmu; /* TX BMU register */ 1236 int sk_if_flags; 1237 LIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1238 LIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1239 SLIST_HEAD(__sk_txmaphead, sk_txmap_entry) sk_txmap_listhead; 1240 }; 1241 1242 struct skc_attach_args { 1243 u_int16_t skc_port; 1244 }; 1245 1246 #define SK_MAXUNIT 256 1247 #define SK_TIMEOUT 1000 1248 #define ETHER_ALIGN 2 1249