1 /* $OpenBSD: if_wb.c,v 1.16 2002/02/15 20:45:31 nordin Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26 1999/09/25 17:29:02 wpaul Exp $ 35 */ 36 37 /* 38 * Winbond fast ethernet PCI NIC driver 39 * 40 * Supports various cheap network adapters based on the Winbond W89C840F 41 * fast ethernet controller chip. This includes adapters manufactured by 42 * Winbond itself and some made by Linksys. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The Winbond W89C840F chip is a bus master; in some ways it resembles 51 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 52 * one major difference which is that while the registers do many of 53 * the same things as a tulip adapter, the offsets are different: where 54 * tulip registers are typically spaced 8 bytes apart, the Winbond 55 * registers are spaced 4 bytes apart. The receiver filter is also 56 * programmed differently. 57 * 58 * Like the tulip, the Winbond chip uses small descriptors containing 59 * a status word, a control word and 32-bit areas that can either be used 60 * to point to two external data blocks, or to point to a single block 61 * and another descriptor in a linked list. Descriptors can be grouped 62 * together in blocks to form fixed length rings or can be chained 63 * together in linked lists. A single packet may be spread out over 64 * several descriptors if necessary. 65 * 66 * For the receive ring, this driver uses a linked list of descriptors, 67 * each pointing to a single mbuf cluster buffer, which us large enough 68 * to hold an entire packet. The link list is looped back to created a 69 * closed ring. 70 * 71 * For transmission, the driver creates a linked list of 'super descriptors' 72 * which each contain several individual descriptors linked toghether. 73 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 74 * abuse as fragment pointers. This allows us to use a buffer managment 75 * scheme very similar to that used in the ThunderLAN and Etherlink XL 76 * drivers. 77 * 78 * Autonegotiation is performed using the external PHY via the MII bus. 79 * The sample boards I have all use a Davicom PHY. 80 * 81 * Note: the author of the Linux driver for the Winbond chip alludes 82 * to some sort of flaw in the chip's design that seems to mandate some 83 * drastic workaround which signigicantly impairs transmit performance. 84 * I have no idea what he's on about: transmit performance with all 85 * three of my test boards seems fine. 86 */ 87 88 #include "bpfilter.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 #include <sys/timeout.h> 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_types.h> 104 105 #ifdef INET 106 #include <netinet/in.h> 107 #include <netinet/in_systm.h> 108 #include <netinet/in_var.h> 109 #include <netinet/ip.h> 110 #include <netinet/if_ether.h> 111 #endif 112 113 #include <net/if_media.h> 114 115 #if NBPFILTER > 0 116 #include <net/bpf.h> 117 #endif 118 119 #include <uvm/uvm_extern.h> /* for vtophys */ 120 121 #include <dev/mii/mii.h> 122 #include <dev/mii/miivar.h> 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #define WB_USEIOSPACE 128 129 /* #define WB_BACKGROUND_AUTONEG */ 130 131 #include <dev/pci/if_wbreg.h> 132 133 int wb_probe __P((struct device *, void *, void *)); 134 void wb_attach __P((struct device *, struct device *, void *)); 135 136 void wb_bfree __P((caddr_t, u_int, void *)); 137 int wb_newbuf __P((struct wb_softc *, struct wb_chain_onefrag *, 138 struct mbuf *)); 139 int wb_encap __P((struct wb_softc *, struct wb_chain *, 140 struct mbuf *)); 141 142 void wb_rxeof __P((struct wb_softc *)); 143 void wb_rxeoc __P((struct wb_softc *)); 144 void wb_txeof __P((struct wb_softc *)); 145 void wb_txeoc __P((struct wb_softc *)); 146 int wb_intr __P((void *)); 147 void wb_tick __P((void *)); 148 void wb_start __P((struct ifnet *)); 149 int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 150 void wb_init __P((void *)); 151 void wb_stop __P((struct wb_softc *)); 152 void wb_watchdog __P((struct ifnet *)); 153 void wb_shutdown __P((void *)); 154 int wb_ifmedia_upd __P((struct ifnet *)); 155 void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 156 157 void wb_eeprom_putbyte __P((struct wb_softc *, int)); 158 void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 159 void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, int, int)); 160 void wb_mii_sync __P((struct wb_softc *)); 161 void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 162 int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 163 int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 164 165 void wb_setcfg __P((struct wb_softc *, u_int32_t)); 166 u_int8_t wb_calchash __P((caddr_t)); 167 void wb_setmulti __P((struct wb_softc *)); 168 void wb_reset __P((struct wb_softc *)); 169 void wb_fixmedia __P((struct wb_softc *)); 170 int wb_list_rx_init __P((struct wb_softc *)); 171 int wb_list_tx_init __P((struct wb_softc *)); 172 173 int wb_miibus_readreg __P((struct device *, int, int)); 174 void wb_miibus_writereg __P((struct device *, int, int, int)); 175 void wb_miibus_statchg __P((struct device *)); 176 177 #define WB_SETBIT(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, \ 179 CSR_READ_4(sc, reg) | x) 180 181 #define WB_CLRBIT(sc, reg, x) \ 182 CSR_WRITE_4(sc, reg, \ 183 CSR_READ_4(sc, reg) & ~x) 184 185 #define SIO_SET(x) \ 186 CSR_WRITE_4(sc, WB_SIO, \ 187 CSR_READ_4(sc, WB_SIO) | x) 188 189 #define SIO_CLR(x) \ 190 CSR_WRITE_4(sc, WB_SIO, \ 191 CSR_READ_4(sc, WB_SIO) & ~x) 192 193 /* 194 * Send a read command and address to the EEPROM, check for ACK. 195 */ 196 void wb_eeprom_putbyte(sc, addr) 197 struct wb_softc *sc; 198 int addr; 199 { 200 register int d, i; 201 202 d = addr | WB_EECMD_READ; 203 204 /* 205 * Feed in each bit and stobe the clock. 206 */ 207 for (i = 0x400; i; i >>= 1) { 208 if (d & i) { 209 SIO_SET(WB_SIO_EE_DATAIN); 210 } else { 211 SIO_CLR(WB_SIO_EE_DATAIN); 212 } 213 DELAY(100); 214 SIO_SET(WB_SIO_EE_CLK); 215 DELAY(150); 216 SIO_CLR(WB_SIO_EE_CLK); 217 DELAY(100); 218 } 219 220 return; 221 } 222 223 /* 224 * Read a word of data stored in the EEPROM at address 'addr.' 225 */ 226 void wb_eeprom_getword(sc, addr, dest) 227 struct wb_softc *sc; 228 int addr; 229 u_int16_t *dest; 230 { 231 register int i; 232 u_int16_t word = 0; 233 234 /* Enter EEPROM access mode. */ 235 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 236 237 /* 238 * Send address of word we want to read. 239 */ 240 wb_eeprom_putbyte(sc, addr); 241 242 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 243 244 /* 245 * Start reading bits from EEPROM. 246 */ 247 for (i = 0x8000; i; i >>= 1) { 248 SIO_SET(WB_SIO_EE_CLK); 249 DELAY(100); 250 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 251 word |= i; 252 SIO_CLR(WB_SIO_EE_CLK); 253 DELAY(100); 254 } 255 256 /* Turn off EEPROM access mode. */ 257 CSR_WRITE_4(sc, WB_SIO, 0); 258 259 *dest = word; 260 261 return; 262 } 263 264 /* 265 * Read a sequence of words from the EEPROM. 266 */ 267 void wb_read_eeprom(sc, dest, off, cnt, swap) 268 struct wb_softc *sc; 269 caddr_t dest; 270 int off; 271 int cnt; 272 int swap; 273 { 274 int i; 275 u_int16_t word = 0, *ptr; 276 277 for (i = 0; i < cnt; i++) { 278 wb_eeprom_getword(sc, off + i, &word); 279 ptr = (u_int16_t *)(dest + (i * 2)); 280 if (swap) 281 *ptr = ntohs(word); 282 else 283 *ptr = word; 284 } 285 286 return; 287 } 288 289 /* 290 * Sync the PHYs by setting data bit and strobing the clock 32 times. 291 */ 292 void wb_mii_sync(sc) 293 struct wb_softc *sc; 294 { 295 register int i; 296 297 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 298 299 for (i = 0; i < 32; i++) { 300 SIO_SET(WB_SIO_MII_CLK); 301 DELAY(1); 302 SIO_CLR(WB_SIO_MII_CLK); 303 DELAY(1); 304 } 305 306 return; 307 } 308 309 /* 310 * Clock a series of bits through the MII. 311 */ 312 void wb_mii_send(sc, bits, cnt) 313 struct wb_softc *sc; 314 u_int32_t bits; 315 int cnt; 316 { 317 int i; 318 319 SIO_CLR(WB_SIO_MII_CLK); 320 321 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 322 if (bits & i) { 323 SIO_SET(WB_SIO_MII_DATAIN); 324 } else { 325 SIO_CLR(WB_SIO_MII_DATAIN); 326 } 327 DELAY(1); 328 SIO_CLR(WB_SIO_MII_CLK); 329 DELAY(1); 330 SIO_SET(WB_SIO_MII_CLK); 331 } 332 } 333 334 /* 335 * Read an PHY register through the MII. 336 */ 337 int wb_mii_readreg(sc, frame) 338 struct wb_softc *sc; 339 struct wb_mii_frame *frame; 340 341 { 342 int i, ack, s; 343 344 s = splimp(); 345 346 /* 347 * Set up frame for RX. 348 */ 349 frame->mii_stdelim = WB_MII_STARTDELIM; 350 frame->mii_opcode = WB_MII_READOP; 351 frame->mii_turnaround = 0; 352 frame->mii_data = 0; 353 354 CSR_WRITE_4(sc, WB_SIO, 0); 355 356 /* 357 * Turn on data xmit. 358 */ 359 SIO_SET(WB_SIO_MII_DIR); 360 361 wb_mii_sync(sc); 362 363 /* 364 * Send command/address info. 365 */ 366 wb_mii_send(sc, frame->mii_stdelim, 2); 367 wb_mii_send(sc, frame->mii_opcode, 2); 368 wb_mii_send(sc, frame->mii_phyaddr, 5); 369 wb_mii_send(sc, frame->mii_regaddr, 5); 370 371 /* Idle bit */ 372 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 373 DELAY(1); 374 SIO_SET(WB_SIO_MII_CLK); 375 DELAY(1); 376 377 /* Turn off xmit. */ 378 SIO_CLR(WB_SIO_MII_DIR); 379 /* Check for ack */ 380 SIO_CLR(WB_SIO_MII_CLK); 381 DELAY(1); 382 SIO_SET(WB_SIO_MII_CLK); 383 DELAY(1); 384 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 385 SIO_CLR(WB_SIO_MII_CLK); 386 DELAY(1); 387 SIO_SET(WB_SIO_MII_CLK); 388 DELAY(1); 389 390 /* 391 * Now try reading data bits. If the ack failed, we still 392 * need to clock through 16 cycles to keep the PHY(s) in sync. 393 */ 394 if (ack) { 395 for(i = 0; i < 16; i++) { 396 SIO_CLR(WB_SIO_MII_CLK); 397 DELAY(1); 398 SIO_SET(WB_SIO_MII_CLK); 399 DELAY(1); 400 } 401 goto fail; 402 } 403 404 for (i = 0x8000; i; i >>= 1) { 405 SIO_CLR(WB_SIO_MII_CLK); 406 DELAY(1); 407 if (!ack) { 408 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 409 frame->mii_data |= i; 410 DELAY(1); 411 } 412 SIO_SET(WB_SIO_MII_CLK); 413 DELAY(1); 414 } 415 416 fail: 417 418 SIO_CLR(WB_SIO_MII_CLK); 419 DELAY(1); 420 SIO_SET(WB_SIO_MII_CLK); 421 DELAY(1); 422 423 splx(s); 424 425 if (ack) 426 return(1); 427 return(0); 428 } 429 430 /* 431 * Write to a PHY register through the MII. 432 */ 433 int wb_mii_writereg(sc, frame) 434 struct wb_softc *sc; 435 struct wb_mii_frame *frame; 436 437 { 438 int s; 439 440 s = splimp(); 441 /* 442 * Set up frame for TX. 443 */ 444 445 frame->mii_stdelim = WB_MII_STARTDELIM; 446 frame->mii_opcode = WB_MII_WRITEOP; 447 frame->mii_turnaround = WB_MII_TURNAROUND; 448 449 /* 450 * Turn on data output. 451 */ 452 SIO_SET(WB_SIO_MII_DIR); 453 454 wb_mii_sync(sc); 455 456 wb_mii_send(sc, frame->mii_stdelim, 2); 457 wb_mii_send(sc, frame->mii_opcode, 2); 458 wb_mii_send(sc, frame->mii_phyaddr, 5); 459 wb_mii_send(sc, frame->mii_regaddr, 5); 460 wb_mii_send(sc, frame->mii_turnaround, 2); 461 wb_mii_send(sc, frame->mii_data, 16); 462 463 /* Idle bit. */ 464 SIO_SET(WB_SIO_MII_CLK); 465 DELAY(1); 466 SIO_CLR(WB_SIO_MII_CLK); 467 DELAY(1); 468 469 /* 470 * Turn off xmit. 471 */ 472 SIO_CLR(WB_SIO_MII_DIR); 473 474 splx(s); 475 476 return(0); 477 } 478 479 int 480 wb_miibus_readreg(dev, phy, reg) 481 struct device *dev; 482 int phy, reg; 483 { 484 struct wb_softc *sc = (struct wb_softc *)dev; 485 struct wb_mii_frame frame; 486 487 bzero((char *)&frame, sizeof(frame)); 488 489 frame.mii_phyaddr = phy; 490 frame.mii_regaddr = reg; 491 wb_mii_readreg(sc, &frame); 492 493 return(frame.mii_data); 494 } 495 496 void 497 wb_miibus_writereg(dev, phy, reg, data) 498 struct device *dev; 499 int phy, reg, data; 500 { 501 struct wb_softc *sc = (struct wb_softc *)dev; 502 struct wb_mii_frame frame; 503 504 bzero((char *)&frame, sizeof(frame)); 505 506 frame.mii_phyaddr = phy; 507 frame.mii_regaddr = reg; 508 frame.mii_data = data; 509 510 wb_mii_writereg(sc, &frame); 511 512 return; 513 } 514 515 void 516 wb_miibus_statchg(dev) 517 struct device *dev; 518 { 519 struct wb_softc *sc = (struct wb_softc *)dev; 520 521 wb_setcfg(sc, sc->sc_mii.mii_media_active); 522 } 523 524 u_int8_t wb_calchash(addr) 525 caddr_t addr; 526 { 527 u_int32_t crc, carry; 528 int i, j; 529 u_int8_t c; 530 531 /* Compute CRC for the address value. */ 532 crc = 0xFFFFFFFF; /* initial value */ 533 534 for (i = 0; i < 6; i++) { 535 c = *(addr + i); 536 for (j = 0; j < 8; j++) { 537 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 538 crc <<= 1; 539 c >>= 1; 540 if (carry) 541 crc = (crc ^ 0x04c11db6) | carry; 542 } 543 } 544 545 /* 546 * return the filter bit position 547 * Note: I arrived at the following nonsense 548 * through experimentation. It's not the usual way to 549 * generate the bit position but it's the only thing 550 * I could come up with that works. 551 */ 552 return(~(crc >> 26) & 0x0000003F); 553 } 554 555 /* 556 * Program the 64-bit multicast hash filter. 557 */ 558 void wb_setmulti(sc) 559 struct wb_softc *sc; 560 { 561 struct ifnet *ifp; 562 int h = 0; 563 u_int32_t hashes[2] = { 0, 0 }; 564 struct arpcom *ac = &sc->arpcom; 565 struct ether_multi *enm; 566 struct ether_multistep step; 567 u_int32_t rxfilt; 568 int mcnt = 0; 569 570 ifp = &sc->arpcom.ac_if; 571 572 rxfilt = CSR_READ_4(sc, WB_NETCFG); 573 574 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 575 rxfilt |= WB_NETCFG_RX_MULTI; 576 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 577 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 578 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 579 return; 580 } 581 582 /* first, zot all the existing hash bits */ 583 CSR_WRITE_4(sc, WB_MAR0, 0); 584 CSR_WRITE_4(sc, WB_MAR1, 0); 585 586 /* now program new ones */ 587 ETHER_FIRST_MULTI(step, ac, enm); 588 while (enm != NULL) { 589 h = wb_calchash(enm->enm_addrlo); 590 if (h < 32) 591 hashes[0] |= (1 << h); 592 else 593 hashes[1] |= (1 << (h - 32)); 594 mcnt++; 595 ETHER_NEXT_MULTI(step, enm); 596 } 597 598 if (mcnt) 599 rxfilt |= WB_NETCFG_RX_MULTI; 600 else 601 rxfilt &= ~WB_NETCFG_RX_MULTI; 602 603 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 604 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 605 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 606 607 return; 608 } 609 610 /* 611 * The Winbond manual states that in order to fiddle with the 612 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 613 * first have to put the transmit and/or receive logic in the idle state. 614 */ 615 void 616 wb_setcfg(sc, media) 617 struct wb_softc *sc; 618 u_int32_t media; 619 { 620 int i, restart = 0; 621 622 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 623 restart = 1; 624 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 625 626 for (i = 0; i < WB_TIMEOUT; i++) { 627 DELAY(10); 628 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 629 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 630 break; 631 } 632 633 if (i == WB_TIMEOUT) 634 printf("%s: failed to force tx and " 635 "rx to idle state\n", sc->sc_dev.dv_xname); 636 } 637 638 if (IFM_SUBTYPE(media) == IFM_10_T) 639 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 640 else 641 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 642 643 if ((media & IFM_GMASK) == IFM_FDX) 644 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 645 else 646 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 647 648 if (restart) 649 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 650 651 return; 652 } 653 654 void 655 wb_reset(sc) 656 struct wb_softc *sc; 657 { 658 register int i; 659 struct mii_data *mii = &sc->sc_mii; 660 661 CSR_WRITE_4(sc, WB_NETCFG, 0); 662 CSR_WRITE_4(sc, WB_BUSCTL, 0); 663 CSR_WRITE_4(sc, WB_TXADDR, 0); 664 CSR_WRITE_4(sc, WB_RXADDR, 0); 665 666 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 667 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 668 669 for (i = 0; i < WB_TIMEOUT; i++) { 670 DELAY(10); 671 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 672 break; 673 } 674 if (i == WB_TIMEOUT) 675 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 676 677 /* Wait a little while for the chip to get its brains in order. */ 678 DELAY(1000); 679 680 if (mii->mii_instance) { 681 struct mii_softc *miisc; 682 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 683 miisc = LIST_NEXT(miisc, mii_list)) 684 mii_phy_reset(miisc); 685 } 686 } 687 688 void 689 wb_fixmedia(sc) 690 struct wb_softc *sc; 691 { 692 struct mii_data *mii = &sc->sc_mii; 693 u_int32_t media; 694 695 if (LIST_FIRST(&mii->mii_phys) == NULL) 696 return; 697 698 mii_pollstat(mii); 699 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 700 media = mii->mii_media_active & ~IFM_10_T; 701 media |= IFM_100_TX; 702 } if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 703 media = mii->mii_media_active & ~IFM_100_TX; 704 media |= IFM_10_T; 705 } else 706 return; 707 708 ifmedia_set(&mii->mii_media, media); 709 } 710 711 /* 712 * Probe for a Winbond chip. Check the PCI vendor and device 713 * IDs against our list and return a device name if we find a match. 714 */ 715 int 716 wb_probe(parent, match, aux) 717 struct device *parent; 718 void *match, *aux; 719 { 720 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 721 722 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_WINBOND) { 723 switch (PCI_PRODUCT(pa->pa_id)) { 724 case PCI_PRODUCT_WINBOND_W89C840F: 725 return (1); 726 } 727 } 728 729 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_COMPEX) { 730 switch (PCI_PRODUCT(pa->pa_id)) { 731 case PCI_PRODUCT_COMPEX_RL100ATX: 732 return (1); 733 } 734 } 735 736 return (0); 737 } 738 739 /* 740 * Attach the interface. Allocate softc structures, do ifmedia 741 * setup and ethernet/BPF attach. 742 */ 743 void 744 wb_attach(parent, self, aux) 745 struct device *parent, *self; 746 void *aux; 747 { 748 struct wb_softc *sc = (struct wb_softc *)self; 749 struct pci_attach_args *pa = aux; 750 pci_chipset_tag_t pc = pa->pa_pc; 751 pci_intr_handle_t ih; 752 const char *intrstr = NULL; 753 struct ifnet *ifp = &sc->arpcom.ac_if; 754 bus_addr_t iobase; 755 bus_size_t iosize; 756 int s, rseg; 757 u_int32_t command; 758 bus_dma_segment_t seg; 759 bus_dmamap_t dmamap; 760 caddr_t kva; 761 762 s = splimp(); 763 764 /* 765 * Handle power management nonsense. 766 */ 767 768 command = pci_conf_read(pc, pa->pa_tag, WB_PCI_CAPID) & 0x000000FF; 769 if (command == 0x01) { 770 771 command = pci_conf_read(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL); 772 if (command & WB_PSTATE_MASK) { 773 u_int32_t io, mem, irq; 774 775 /* Save important PCI config data. */ 776 io = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOIO); 777 mem = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOMEM); 778 irq = pci_conf_read(pc, pa->pa_tag, WB_PCI_INTLINE); 779 780 /* Reset the power state. */ 781 printf("%s: chip is in D%d power mode " 782 "-- setting to D0\n", sc->sc_dev.dv_xname, 783 command & WB_PSTATE_MASK); 784 command &= 0xFFFFFFFC; 785 pci_conf_write(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL, 786 command); 787 788 /* Restore PCI config data. */ 789 pci_conf_write(pc, pa->pa_tag, WB_PCI_LOIO, io); 790 pci_conf_write(pc, pa->pa_tag, WB_PCI_LOMEM, mem); 791 pci_conf_write(pc, pa->pa_tag, WB_PCI_INTLINE, irq); 792 } 793 } 794 795 /* 796 * Map control/status registers. 797 */ 798 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 799 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 800 PCI_COMMAND_MASTER_ENABLE; 801 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 802 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 803 804 #ifdef WB_USEIOSPACE 805 if (!(command & PCI_COMMAND_IO_ENABLE)) { 806 printf(": failed to enable I/O ports!\n"); 807 goto fail; 808 } 809 if (pci_io_find(pc, pa->pa_tag, WB_PCI_LOIO, &iobase, &iosize)) { 810 printf(": can't find i/o space\n"); 811 goto fail; 812 } 813 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->wb_bhandle)) { 814 printf(": can't map i/o space\n"); 815 goto fail; 816 } 817 sc->wb_btag = pa->pa_iot; 818 #else 819 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 820 printf(": failed to enable memory mapping!\n"); 821 goto fail; 822 } 823 if (pci_mem_find(pc, pa->pa_tag, WB_PCI_LOMEM, &iobase, &iosize, NULL)){ 824 printf(": can't find mem space\n"); 825 goto fail; 826 } 827 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->wb_bhandle)) { 828 printf(": can't map mem space\n"); 829 goto fail; 830 } 831 sc->wb_btag = pa->pa_memt; 832 #endif 833 834 /* Allocate interrupt */ 835 if (pci_intr_map(pa, &ih)) { 836 printf(": couldn't map interrupt\n"); 837 goto fail; 838 } 839 intrstr = pci_intr_string(pc, ih); 840 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wb_intr, sc, 841 self->dv_xname); 842 if (sc->sc_ih == NULL) { 843 printf(": couldn't establish interrupt"); 844 if (intrstr != NULL) 845 printf(" at %s", intrstr); 846 printf("\n"); 847 goto fail; 848 } 849 printf(": %s", intrstr); 850 851 sc->wb_cachesize = pci_conf_read(pc, pa->pa_tag, WB_PCI_CACHELEN)&0xff; 852 853 /* Reset the adapter. */ 854 wb_reset(sc); 855 856 /* 857 * Get station address from the EEPROM. 858 */ 859 wb_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0, 3, 0); 860 printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 861 862 if (bus_dmamem_alloc(pa->pa_dmat, sizeof(struct wb_list_data), 863 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 864 printf("%s: can't alloc list data\n", sc->sc_dev.dv_xname); 865 goto fail; 866 } 867 if (bus_dmamem_map(pa->pa_dmat, &seg, rseg, 868 sizeof(struct wb_list_data), &kva, BUS_DMA_NOWAIT)) { 869 printf("%s: can't map list data, size %d\n", 870 sc->sc_dev.dv_xname, sizeof(struct wb_list_data)); 871 bus_dmamem_free(pa->pa_dmat, &seg, rseg); 872 goto fail; 873 } 874 if (bus_dmamap_create(pa->pa_dmat, sizeof(struct wb_list_data), 1, 875 sizeof(struct wb_list_data), 0, BUS_DMA_NOWAIT, &dmamap)) { 876 printf("%s: can't create dma map\n", sc->sc_dev.dv_xname); 877 bus_dmamem_unmap(pa->pa_dmat, kva, 878 sizeof(struct wb_list_data)); 879 bus_dmamem_free(pa->pa_dmat, &seg, rseg); 880 goto fail; 881 } 882 if (bus_dmamap_load(pa->pa_dmat, dmamap, kva, 883 sizeof(struct wb_list_data), NULL, BUS_DMA_NOWAIT)) { 884 printf("%s: can't load dma map\n", sc->sc_dev.dv_xname); 885 bus_dmamap_destroy(pa->pa_dmat, dmamap); 886 bus_dmamem_unmap(pa->pa_dmat, kva, 887 sizeof(struct wb_list_data)); 888 bus_dmamem_free(pa->pa_dmat, &seg, rseg); 889 goto fail; 890 } 891 sc->wb_ldata = (struct wb_list_data *)kva; 892 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 893 894 ifp->if_softc = sc; 895 ifp->if_mtu = ETHERMTU; 896 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 897 ifp->if_ioctl = wb_ioctl; 898 ifp->if_output = ether_output; 899 ifp->if_start = wb_start; 900 ifp->if_watchdog = wb_watchdog; 901 ifp->if_baudrate = 10000000; 902 IFQ_SET_MAXLEN(&ifp->if_snd, WB_TX_LIST_CNT - 1); 903 IFQ_SET_READY(&ifp->if_snd); 904 905 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 906 907 /* 908 * Do ifmedia setup. 909 */ 910 wb_stop(sc); 911 912 ifmedia_init(&sc->sc_mii.mii_media, 0, wb_ifmedia_upd, wb_ifmedia_sts); 913 sc->sc_mii.mii_ifp = ifp; 914 sc->sc_mii.mii_readreg = wb_miibus_readreg; 915 sc->sc_mii.mii_writereg = wb_miibus_writereg; 916 sc->sc_mii.mii_statchg = wb_miibus_statchg; 917 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 918 0); 919 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 920 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE,0,NULL); 921 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 922 } else 923 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 924 925 /* 926 * Call MI attach routines. 927 */ 928 if_attach(ifp); 929 ether_ifattach(ifp); 930 931 shutdownhook_establish(wb_shutdown, sc); 932 933 fail: 934 splx(s); 935 return; 936 } 937 938 /* 939 * Initialize the transmit descriptors. 940 */ 941 int wb_list_tx_init(sc) 942 struct wb_softc *sc; 943 { 944 struct wb_chain_data *cd; 945 struct wb_list_data *ld; 946 int i; 947 948 cd = &sc->wb_cdata; 949 ld = sc->wb_ldata; 950 951 for (i = 0; i < WB_TX_LIST_CNT; i++) { 952 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 953 if (i == (WB_TX_LIST_CNT - 1)) { 954 cd->wb_tx_chain[i].wb_nextdesc = 955 &cd->wb_tx_chain[0]; 956 } else { 957 cd->wb_tx_chain[i].wb_nextdesc = 958 &cd->wb_tx_chain[i + 1]; 959 } 960 } 961 962 cd->wb_tx_free = &cd->wb_tx_chain[0]; 963 cd->wb_tx_tail = cd->wb_tx_head = NULL; 964 965 return(0); 966 } 967 968 969 /* 970 * Initialize the RX descriptors and allocate mbufs for them. Note that 971 * we arrange the descriptors in a closed ring, so that the last descriptor 972 * points back to the first. 973 */ 974 int wb_list_rx_init(sc) 975 struct wb_softc *sc; 976 { 977 struct wb_chain_data *cd; 978 struct wb_list_data *ld; 979 int i; 980 981 cd = &sc->wb_cdata; 982 ld = sc->wb_ldata; 983 984 for (i = 0; i < WB_RX_LIST_CNT; i++) { 985 cd->wb_rx_chain[i].wb_ptr = 986 (struct wb_desc *)&ld->wb_rx_list[i]; 987 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 988 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 989 return(ENOBUFS); 990 if (i == (WB_RX_LIST_CNT - 1)) { 991 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 992 ld->wb_rx_list[i].wb_next = 993 vtophys(&ld->wb_rx_list[0]); 994 } else { 995 cd->wb_rx_chain[i].wb_nextdesc = 996 &cd->wb_rx_chain[i + 1]; 997 ld->wb_rx_list[i].wb_next = 998 vtophys(&ld->wb_rx_list[i + 1]); 999 } 1000 } 1001 1002 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1003 1004 return(0); 1005 } 1006 1007 void 1008 wb_bfree(buf, size, arg) 1009 caddr_t buf; 1010 u_int size; 1011 void *arg; 1012 { 1013 } 1014 1015 /* 1016 * Initialize an RX descriptor and attach an MBUF cluster. 1017 */ 1018 int 1019 wb_newbuf(sc, c, m) 1020 struct wb_softc *sc; 1021 struct wb_chain_onefrag *c; 1022 struct mbuf *m; 1023 { 1024 struct mbuf *m_new = NULL; 1025 1026 if (m == NULL) { 1027 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1028 if (m_new == NULL) 1029 return(ENOBUFS); 1030 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 1031 m_new->m_flags |= M_EXT; 1032 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1033 m_new->m_len = WB_BUFBYTES; 1034 m_new->m_ext.ext_free = wb_bfree; 1035 m_new->m_ext.ext_arg = NULL; 1036 MCLINITREFERENCE(m_new); 1037 } else { 1038 m_new = m; 1039 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1040 m_new->m_data = m_new->m_ext.ext_buf; 1041 } 1042 1043 m_adj(m_new, sizeof(u_int64_t)); 1044 1045 c->wb_mbuf = m_new; 1046 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1047 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1048 c->wb_ptr->wb_status = WB_RXSTAT; 1049 1050 return(0); 1051 } 1052 1053 /* 1054 * A frame has been uploaded: pass the resulting mbuf chain up to 1055 * the higher level protocols. 1056 */ 1057 void wb_rxeof(sc) 1058 struct wb_softc *sc; 1059 { 1060 struct mbuf *m = NULL; 1061 struct ifnet *ifp; 1062 struct wb_chain_onefrag *cur_rx; 1063 int total_len = 0; 1064 u_int32_t rxstat; 1065 1066 ifp = &sc->arpcom.ac_if; 1067 1068 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1069 WB_RXSTAT_OWN)) { 1070 struct mbuf *m0 = NULL; 1071 1072 cur_rx = sc->wb_cdata.wb_rx_head; 1073 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1074 1075 m = cur_rx->wb_mbuf; 1076 1077 if ((rxstat & WB_RXSTAT_MIIERR) || 1078 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1079 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1080 !(rxstat & WB_RXSTAT_LASTFRAG) || 1081 !(rxstat & WB_RXSTAT_RXCMP)) { 1082 ifp->if_ierrors++; 1083 wb_newbuf(sc, cur_rx, m); 1084 printf("%s: receiver babbling: possible chip " 1085 "bug, forcing reset\n", sc->sc_dev.dv_xname); 1086 wb_fixmedia(sc); 1087 wb_reset(sc); 1088 wb_init(sc); 1089 return; 1090 } 1091 1092 if (rxstat & WB_RXSTAT_RXERR) { 1093 ifp->if_ierrors++; 1094 wb_newbuf(sc, cur_rx, m); 1095 break; 1096 } 1097 1098 /* No errors; receive the packet. */ 1099 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1100 1101 /* 1102 * XXX The Winbond chip includes the CRC with every 1103 * received frame, and there's no way to turn this 1104 * behavior off (at least, I can't find anything in 1105 * the manual that explains how to do it) so we have 1106 * to trim off the CRC manually. 1107 */ 1108 total_len -= ETHER_CRC_LEN; 1109 1110 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1111 total_len + ETHER_ALIGN, 0, ifp, NULL); 1112 wb_newbuf(sc, cur_rx, m); 1113 if (m0 == NULL) { 1114 ifp->if_ierrors++; 1115 break; 1116 } 1117 m_adj(m0, ETHER_ALIGN); 1118 m = m0; 1119 1120 ifp->if_ipackets++; 1121 1122 #if NBPFILTER > 0 1123 /* 1124 * Handle BPF listeners. Let the BPF user see the packet. 1125 */ 1126 if (ifp->if_bpf) 1127 bpf_mtap(ifp->if_bpf, m); 1128 #endif 1129 /* pass it on. */ 1130 ether_input_mbuf(ifp, m); 1131 } 1132 1133 return; 1134 } 1135 1136 void wb_rxeoc(sc) 1137 struct wb_softc *sc; 1138 { 1139 wb_rxeof(sc); 1140 1141 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1142 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1143 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1144 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1145 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1146 1147 return; 1148 } 1149 1150 /* 1151 * A frame was downloaded to the chip. It's safe for us to clean up 1152 * the list buffers. 1153 */ 1154 void wb_txeof(sc) 1155 struct wb_softc *sc; 1156 { 1157 struct wb_chain *cur_tx; 1158 struct ifnet *ifp; 1159 1160 ifp = &sc->arpcom.ac_if; 1161 1162 /* Clear the timeout timer. */ 1163 ifp->if_timer = 0; 1164 1165 if (sc->wb_cdata.wb_tx_head == NULL) 1166 return; 1167 1168 /* 1169 * Go through our tx list and free mbufs for those 1170 * frames that have been transmitted. 1171 */ 1172 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1173 u_int32_t txstat; 1174 1175 cur_tx = sc->wb_cdata.wb_tx_head; 1176 txstat = WB_TXSTATUS(cur_tx); 1177 1178 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1179 break; 1180 1181 if (txstat & WB_TXSTAT_TXERR) { 1182 ifp->if_oerrors++; 1183 if (txstat & WB_TXSTAT_ABORT) 1184 ifp->if_collisions++; 1185 if (txstat & WB_TXSTAT_LATECOLL) 1186 ifp->if_collisions++; 1187 } 1188 1189 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1190 1191 ifp->if_opackets++; 1192 m_freem(cur_tx->wb_mbuf); 1193 cur_tx->wb_mbuf = NULL; 1194 1195 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1196 sc->wb_cdata.wb_tx_head = NULL; 1197 sc->wb_cdata.wb_tx_tail = NULL; 1198 break; 1199 } 1200 1201 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1202 } 1203 1204 return; 1205 } 1206 1207 /* 1208 * TX 'end of channel' interrupt handler. 1209 */ 1210 void wb_txeoc(sc) 1211 struct wb_softc *sc; 1212 { 1213 struct ifnet *ifp; 1214 1215 ifp = &sc->arpcom.ac_if; 1216 1217 ifp->if_timer = 0; 1218 1219 if (sc->wb_cdata.wb_tx_head == NULL) { 1220 ifp->if_flags &= ~IFF_OACTIVE; 1221 sc->wb_cdata.wb_tx_tail = NULL; 1222 } else { 1223 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1224 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1225 ifp->if_timer = 5; 1226 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1227 } 1228 } 1229 1230 return; 1231 } 1232 1233 int wb_intr(arg) 1234 void *arg; 1235 { 1236 struct wb_softc *sc; 1237 struct ifnet *ifp; 1238 u_int32_t status; 1239 int r = 0; 1240 1241 sc = arg; 1242 ifp = &sc->arpcom.ac_if; 1243 1244 if (!(ifp->if_flags & IFF_UP)) 1245 return (r); 1246 1247 /* Disable interrupts. */ 1248 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1249 1250 for (;;) { 1251 1252 status = CSR_READ_4(sc, WB_ISR); 1253 if (status) 1254 CSR_WRITE_4(sc, WB_ISR, status); 1255 1256 if ((status & WB_INTRS) == 0) 1257 break; 1258 1259 r = 1; 1260 1261 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1262 ifp->if_ierrors++; 1263 wb_reset(sc); 1264 if (status & WB_ISR_RX_ERR) 1265 wb_fixmedia(sc); 1266 wb_init(sc); 1267 continue; 1268 } 1269 1270 if (status & WB_ISR_RX_OK) 1271 wb_rxeof(sc); 1272 1273 if (status & WB_ISR_RX_IDLE) 1274 wb_rxeoc(sc); 1275 1276 if (status & WB_ISR_TX_OK) 1277 wb_txeof(sc); 1278 1279 if (status & WB_ISR_TX_NOBUF) 1280 wb_txeoc(sc); 1281 1282 if (status & WB_ISR_TX_IDLE) { 1283 wb_txeof(sc); 1284 if (sc->wb_cdata.wb_tx_head != NULL) { 1285 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1286 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1287 } 1288 } 1289 1290 if (status & WB_ISR_TX_UNDERRUN) { 1291 ifp->if_oerrors++; 1292 wb_txeof(sc); 1293 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1294 /* Jack up TX threshold */ 1295 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1296 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1297 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1298 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1299 } 1300 1301 if (status & WB_ISR_BUS_ERR) { 1302 wb_reset(sc); 1303 wb_init(sc); 1304 } 1305 1306 } 1307 1308 /* Re-enable interrupts. */ 1309 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1310 1311 if (!IFQ_IS_EMPTY(&ifp->if_snd)) { 1312 wb_start(ifp); 1313 } 1314 1315 return (r); 1316 } 1317 1318 void 1319 wb_tick(xsc) 1320 void *xsc; 1321 { 1322 struct wb_softc *sc = xsc; 1323 int s; 1324 1325 s = splimp(); 1326 mii_tick(&sc->sc_mii); 1327 splx(s); 1328 timeout_add(&sc->wb_tick_tmo, hz); 1329 } 1330 1331 /* 1332 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1333 * pointers to the fragment pointers. 1334 */ 1335 int wb_encap(sc, c, m_head) 1336 struct wb_softc *sc; 1337 struct wb_chain *c; 1338 struct mbuf *m_head; 1339 { 1340 int frag = 0; 1341 struct wb_desc *f = NULL; 1342 int total_len; 1343 struct mbuf *m; 1344 1345 /* 1346 * Start packing the mbufs in this chain into 1347 * the fragment pointers. Stop when we run out 1348 * of fragments or hit the end of the mbuf chain. 1349 */ 1350 m = m_head; 1351 total_len = 0; 1352 1353 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1354 if (m->m_len != 0) { 1355 if (frag == WB_MAXFRAGS) 1356 break; 1357 total_len += m->m_len; 1358 f = &c->wb_ptr->wb_frag[frag]; 1359 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1360 if (frag == 0) { 1361 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1362 f->wb_status = 0; 1363 } else 1364 f->wb_status = WB_TXSTAT_OWN; 1365 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1366 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1367 frag++; 1368 } 1369 } 1370 1371 /* 1372 * Handle special case: we used up all 16 fragments, 1373 * but we have more mbufs left in the chain. Copy the 1374 * data into an mbuf cluster. Note that we don't 1375 * bother clearing the values in the other fragment 1376 * pointers/counters; it wouldn't gain us anything, 1377 * and would waste cycles. 1378 */ 1379 if (m != NULL) { 1380 struct mbuf *m_new = NULL; 1381 1382 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1383 if (m_new == NULL) 1384 return(1); 1385 if (m_head->m_pkthdr.len > MHLEN) { 1386 MCLGET(m_new, M_DONTWAIT); 1387 if (!(m_new->m_flags & M_EXT)) { 1388 m_freem(m_new); 1389 return(1); 1390 } 1391 } 1392 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1393 mtod(m_new, caddr_t)); 1394 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1395 m_freem(m_head); 1396 m_head = m_new; 1397 f = &c->wb_ptr->wb_frag[0]; 1398 f->wb_status = 0; 1399 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1400 f->wb_ctl = total_len = m_new->m_len; 1401 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1402 frag = 1; 1403 } 1404 1405 if (total_len < WB_MIN_FRAMELEN) { 1406 f = &c->wb_ptr->wb_frag[frag]; 1407 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1408 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1409 f->wb_ctl |= WB_TXCTL_TLINK; 1410 f->wb_status = WB_TXSTAT_OWN; 1411 frag++; 1412 } 1413 1414 c->wb_mbuf = m_head; 1415 c->wb_lastdesc = frag - 1; 1416 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1417 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1418 1419 return(0); 1420 } 1421 1422 /* 1423 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1424 * to the mbuf data regions directly in the transmit lists. We also save a 1425 * copy of the pointers since the transmit list fragment pointers are 1426 * physical addresses. 1427 */ 1428 1429 void wb_start(ifp) 1430 struct ifnet *ifp; 1431 { 1432 struct wb_softc *sc; 1433 struct mbuf *m_head = NULL; 1434 struct wb_chain *cur_tx = NULL, *start_tx; 1435 1436 sc = ifp->if_softc; 1437 1438 /* 1439 * Check for an available queue slot. If there are none, 1440 * punt. 1441 */ 1442 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1443 ifp->if_flags |= IFF_OACTIVE; 1444 return; 1445 } 1446 1447 start_tx = sc->wb_cdata.wb_tx_free; 1448 1449 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1450 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1451 if (m_head == NULL) 1452 break; 1453 1454 /* Pick a descriptor off the free list. */ 1455 cur_tx = sc->wb_cdata.wb_tx_free; 1456 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1457 1458 /* Pack the data into the descriptor. */ 1459 wb_encap(sc, cur_tx, m_head); 1460 1461 if (cur_tx != start_tx) 1462 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1463 1464 #if NBPFILTER > 0 1465 /* 1466 * If there's a BPF listener, bounce a copy of this frame 1467 * to him. 1468 */ 1469 if (ifp->if_bpf) 1470 bpf_mtap(ifp->if_bpf, cur_tx->wb_mbuf); 1471 #endif 1472 } 1473 1474 /* 1475 * If there are no packets queued, bail. 1476 */ 1477 if (cur_tx == NULL) 1478 return; 1479 1480 /* 1481 * Place the request for the upload interrupt 1482 * in the last descriptor in the chain. This way, if 1483 * we're chaining several packets at once, we'll only 1484 * get an interupt once for the whole chain rather than 1485 * once for each packet. 1486 */ 1487 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1488 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1489 sc->wb_cdata.wb_tx_tail = cur_tx; 1490 1491 if (sc->wb_cdata.wb_tx_head == NULL) { 1492 sc->wb_cdata.wb_tx_head = start_tx; 1493 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1494 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1495 } else { 1496 /* 1497 * We need to distinguish between the case where 1498 * the own bit is clear because the chip cleared it 1499 * and where the own bit is clear because we haven't 1500 * set it yet. The magic value WB_UNSET is just some 1501 * ramdomly chosen number which doesn't have the own 1502 * bit set. When we actually transmit the frame, the 1503 * status word will have _only_ the own bit set, so 1504 * the txeoc handler will be able to tell if it needs 1505 * to initiate another transmission to flush out pending 1506 * frames. 1507 */ 1508 WB_TXOWN(start_tx) = WB_UNSENT; 1509 } 1510 1511 /* 1512 * Set a timeout in case the chip goes out to lunch. 1513 */ 1514 ifp->if_timer = 5; 1515 1516 return; 1517 } 1518 1519 void wb_init(xsc) 1520 void *xsc; 1521 { 1522 struct wb_softc *sc = xsc; 1523 struct ifnet *ifp = &sc->arpcom.ac_if; 1524 int s, i; 1525 1526 s = splimp(); 1527 1528 /* 1529 * Cancel pending I/O and free all RX/TX buffers. 1530 */ 1531 wb_stop(sc); 1532 wb_reset(sc); 1533 1534 sc->wb_txthresh = WB_TXTHRESH_INIT; 1535 1536 /* 1537 * Set cache alignment and burst length. 1538 */ 1539 #ifdef foo 1540 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1541 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1542 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1543 #endif 1544 1545 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1546 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1547 switch(sc->wb_cachesize) { 1548 case 32: 1549 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1550 break; 1551 case 16: 1552 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1553 break; 1554 case 8: 1555 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1556 break; 1557 case 0: 1558 default: 1559 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1560 break; 1561 } 1562 1563 /* This doesn't tend to work too well at 100Mbps. */ 1564 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1565 1566 /* Init our MAC address */ 1567 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1568 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1569 } 1570 1571 /* Init circular RX list. */ 1572 if (wb_list_rx_init(sc) == ENOBUFS) { 1573 printf("%s: initialization failed: no " 1574 "memory for rx buffers\n", sc->sc_dev.dv_xname); 1575 wb_stop(sc); 1576 splx(s); 1577 return; 1578 } 1579 1580 /* Init TX descriptors. */ 1581 wb_list_tx_init(sc); 1582 1583 /* If we want promiscuous mode, set the allframes bit. */ 1584 if (ifp->if_flags & IFF_PROMISC) { 1585 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1586 } else { 1587 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1588 } 1589 1590 /* 1591 * Set capture broadcast bit to capture broadcast frames. 1592 */ 1593 if (ifp->if_flags & IFF_BROADCAST) { 1594 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1595 } else { 1596 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1597 } 1598 1599 /* 1600 * Program the multicast filter, if necessary. 1601 */ 1602 wb_setmulti(sc); 1603 1604 /* 1605 * Load the address of the RX list. 1606 */ 1607 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1608 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1609 1610 /* 1611 * Enable interrupts. 1612 */ 1613 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1614 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1615 1616 /* Enable receiver and transmitter. */ 1617 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1618 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1619 1620 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1621 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1622 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1623 1624 ifp->if_flags |= IFF_RUNNING; 1625 ifp->if_flags &= ~IFF_OACTIVE; 1626 1627 splx(s); 1628 1629 timeout_set(&sc->wb_tick_tmo, wb_tick, sc); 1630 timeout_add(&sc->wb_tick_tmo, hz); 1631 1632 return; 1633 } 1634 1635 /* 1636 * Set media options. 1637 */ 1638 int 1639 wb_ifmedia_upd(ifp) 1640 struct ifnet *ifp; 1641 { 1642 struct wb_softc *sc = ifp->if_softc; 1643 1644 if (ifp->if_flags & IFF_UP) 1645 wb_init(sc); 1646 1647 return(0); 1648 } 1649 1650 /* 1651 * Report current media status. 1652 */ 1653 void 1654 wb_ifmedia_sts(ifp, ifmr) 1655 struct ifnet *ifp; 1656 struct ifmediareq *ifmr; 1657 { 1658 struct wb_softc *sc = ifp->if_softc; 1659 struct mii_data *mii = &sc->sc_mii; 1660 1661 mii_pollstat(mii); 1662 ifmr->ifm_active = mii->mii_media_active; 1663 ifmr->ifm_status = mii->mii_media_status; 1664 } 1665 1666 int wb_ioctl(ifp, command, data) 1667 struct ifnet *ifp; 1668 u_long command; 1669 caddr_t data; 1670 { 1671 struct wb_softc *sc = ifp->if_softc; 1672 struct ifreq *ifr = (struct ifreq *) data; 1673 struct ifaddr *ifa = (struct ifaddr *)data; 1674 int s, error = 0; 1675 1676 s = splimp(); 1677 1678 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1679 splx(s); 1680 return (error); 1681 } 1682 1683 switch(command) { 1684 case SIOCSIFADDR: 1685 ifp->if_flags |= IFF_UP; 1686 switch (ifa->ifa_addr->sa_family) { 1687 #ifdef INET 1688 case AF_INET: 1689 wb_init(sc); 1690 arp_ifinit(&sc->arpcom, ifa); 1691 break; 1692 #endif /* INET */ 1693 default: 1694 wb_init(sc); 1695 } 1696 case SIOCSIFFLAGS: 1697 if (ifp->if_flags & IFF_UP) { 1698 wb_init(sc); 1699 } else { 1700 if (ifp->if_flags & IFF_RUNNING) 1701 wb_stop(sc); 1702 } 1703 error = 0; 1704 break; 1705 case SIOCADDMULTI: 1706 case SIOCDELMULTI: 1707 error = (command == SIOCADDMULTI) ? 1708 ether_addmulti(ifr, &sc->arpcom) : 1709 ether_delmulti(ifr, &sc->arpcom); 1710 1711 if (error == ENETRESET) { 1712 /* 1713 * Multicast list has changed; set the hardware 1714 * filter accordingly. 1715 */ 1716 wb_setmulti(sc); 1717 error = 0; 1718 } 1719 break; 1720 case SIOCGIFMEDIA: 1721 case SIOCSIFMEDIA: 1722 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1723 break; 1724 default: 1725 error = EINVAL; 1726 break; 1727 } 1728 1729 splx(s); 1730 1731 return(error); 1732 } 1733 1734 void wb_watchdog(ifp) 1735 struct ifnet *ifp; 1736 { 1737 struct wb_softc *sc; 1738 1739 sc = ifp->if_softc; 1740 1741 ifp->if_oerrors++; 1742 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1743 1744 #ifdef foo 1745 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1746 printf("%s: no carrier - transceiver cable problem?\n", 1747 sc->sc_dev.dv_xname); 1748 #endif 1749 wb_stop(sc); 1750 wb_reset(sc); 1751 wb_init(sc); 1752 1753 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1754 wb_start(ifp); 1755 1756 return; 1757 } 1758 1759 /* 1760 * Stop the adapter and free any mbufs allocated to the 1761 * RX and TX lists. 1762 */ 1763 void wb_stop(sc) 1764 struct wb_softc *sc; 1765 { 1766 register int i; 1767 struct ifnet *ifp; 1768 1769 ifp = &sc->arpcom.ac_if; 1770 ifp->if_timer = 0; 1771 1772 timeout_del(&sc->wb_tick_tmo); 1773 1774 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1775 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1776 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1777 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1778 1779 /* 1780 * Free data in the RX lists. 1781 */ 1782 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1783 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1784 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1785 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1786 } 1787 } 1788 bzero((char *)&sc->wb_ldata->wb_rx_list, 1789 sizeof(sc->wb_ldata->wb_rx_list)); 1790 1791 /* 1792 * Free the TX list buffers. 1793 */ 1794 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1795 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1796 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1797 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1798 } 1799 } 1800 1801 bzero((char *)&sc->wb_ldata->wb_tx_list, 1802 sizeof(sc->wb_ldata->wb_tx_list)); 1803 1804 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1805 1806 return; 1807 } 1808 1809 /* 1810 * Stop all chip I/O so that the kernel's probe routines don't 1811 * get confused by errant DMAs when rebooting. 1812 */ 1813 void wb_shutdown(arg) 1814 void *arg; 1815 { 1816 struct wb_softc *sc = (struct wb_softc *)arg; 1817 1818 wb_stop(sc); 1819 1820 return; 1821 } 1822 1823 struct cfattach wb_ca = { 1824 sizeof(struct wb_softc), wb_probe, wb_attach 1825 }; 1826 1827 struct cfdriver wb_cd = { 1828 0, "wb", DV_IFNET 1829 }; 1830