1 /* $OpenBSD: if_xge.c,v 1.54 2011/04/05 18:01:21 henning Exp $ */ 2 /* $NetBSD: if_xge.c,v 1.1 2005/09/09 10:30:27 ragge Exp $ */ 3 4 /* 5 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 6 * All rights reserved. 7 * 8 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * SUNET, Swedish University Computer Network. 22 * 4. The name of SUNET may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SUNET 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Driver for the Neterion Xframe Ten Gigabit Ethernet controller. 40 */ 41 42 #include "bpfilter.h" 43 #include "vlan.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/sockio.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/device.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #ifdef INET 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_ether.h> 64 #include <netinet/tcp.h> 65 #include <netinet/udp.h> 66 #endif 67 68 #if NVLAN > 0 69 #include <net/if_types.h> 70 #include <net/if_vlan_var.h> 71 #endif 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 #include <machine/endian.h> 80 81 #include <dev/mii/mii.h> 82 #include <dev/mii/miivar.h> 83 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcidevs.h> 87 88 #include <sys/lock.h> 89 90 #include <dev/pci/if_xgereg.h> 91 92 /* Xframe chipset revisions */ 93 #define XGE_TYPE_XENA 1 /* Xframe */ 94 #define XGE_TYPE_HERC 2 /* Xframe-II */ 95 96 #define XGE_PCISIZE_XENA 26 97 #define XGE_PCISIZE_HERC 64 98 99 /* 100 * Some tunable constants, tune with care! 101 */ 102 #define RX_MODE RX_MODE_1 /* Receive mode (buffer usage, see below) */ 103 #define NRXDESCS 1016 /* # of receive descriptors (requested) */ 104 #define NTXDESCS 2048 /* Number of transmit descriptors */ 105 #define NTXFRAGS 100 /* Max fragments per packet */ 106 107 /* 108 * Receive buffer modes; 1, 3 or 5 buffers. 109 */ 110 #define RX_MODE_1 1 111 #define RX_MODE_3 3 112 #define RX_MODE_5 5 113 114 /* 115 * Use clever macros to avoid a bunch of #ifdef's. 116 */ 117 #define XCONCAT3(x,y,z) x ## y ## z 118 #define CONCAT3(x,y,z) XCONCAT3(x,y,z) 119 #define NDESC_BUFMODE CONCAT3(NDESC_,RX_MODE,BUFMODE) 120 #define rxd_4k CONCAT3(rxd,RX_MODE,_4k) 121 /* XXX */ 122 #if 0 123 #define rxdesc ___CONCAT(rxd,RX_MODE) 124 #endif 125 #define rxdesc rxd1 126 127 #define NEXTTX(x) (((x)+1) % NTXDESCS) 128 #define NRXFRAGS RX_MODE /* hardware imposed frags */ 129 #define NRXPAGES ((NRXDESCS/NDESC_BUFMODE)+1) 130 #define NRXREAL (NRXPAGES*NDESC_BUFMODE) 131 #define RXMAPSZ (NRXPAGES*PAGE_SIZE) 132 133 /* 134 * Magic to fix a bug when the MAC address cannot be read correctly. 135 * This came from the Linux driver. 136 */ 137 static uint64_t fix_mac[] = { 138 0x0060000000000000ULL, 0x0060600000000000ULL, 139 0x0040600000000000ULL, 0x0000600000000000ULL, 140 0x0020600000000000ULL, 0x0060600000000000ULL, 141 0x0020600000000000ULL, 0x0060600000000000ULL, 142 0x0020600000000000ULL, 0x0060600000000000ULL, 143 0x0020600000000000ULL, 0x0060600000000000ULL, 144 0x0020600000000000ULL, 0x0060600000000000ULL, 145 0x0020600000000000ULL, 0x0060600000000000ULL, 146 0x0020600000000000ULL, 0x0060600000000000ULL, 147 0x0020600000000000ULL, 0x0060600000000000ULL, 148 0x0020600000000000ULL, 0x0060600000000000ULL, 149 0x0020600000000000ULL, 0x0060600000000000ULL, 150 0x0020600000000000ULL, 0x0000600000000000ULL, 151 0x0040600000000000ULL, 0x0060600000000000ULL, 152 }; 153 154 /* 155 * Constants to be programmed into Hercules's registers, to configure 156 * the XGXS transciever. 157 */ 158 #define END_SIGN 0x0 159 static uint64_t herc_dtx_cfg[] = { 160 0x8000051536750000ULL, 0x80000515367500E0ULL, 161 0x8000051536750004ULL, 0x80000515367500E4ULL, 162 163 0x80010515003F0000ULL, 0x80010515003F00E0ULL, 164 0x80010515003F0004ULL, 0x80010515003F00E4ULL, 165 166 0x801205150D440000ULL, 0x801205150D4400E0ULL, 167 0x801205150D440004ULL, 0x801205150D4400E4ULL, 168 169 0x80020515F2100000ULL, 0x80020515F21000E0ULL, 170 0x80020515F2100004ULL, 0x80020515F21000E4ULL, 171 172 END_SIGN 173 }; 174 175 struct xge_softc { 176 struct device sc_dev; 177 struct arpcom sc_arpcom; 178 struct ifmedia xena_media; 179 180 void *sc_ih; 181 182 bus_dma_tag_t sc_dmat; 183 bus_space_tag_t sc_st; 184 bus_space_handle_t sc_sh; 185 bus_space_tag_t sc_txt; 186 bus_space_handle_t sc_txh; 187 188 pcireg_t sc_pciregs[16]; 189 190 int xge_type; /* chip type */ 191 int xge_if_flags; 192 193 /* Transmit structures */ 194 struct txd *sc_txd[NTXDESCS]; /* transmit frags array */ 195 bus_addr_t sc_txdp[NTXDESCS]; /* dva of transmit frags */ 196 bus_dmamap_t sc_txm[NTXDESCS]; /* transmit frags map */ 197 struct mbuf *sc_txb[NTXDESCS]; /* transmit mbuf pointer */ 198 int sc_nexttx, sc_lasttx; 199 bus_dmamap_t sc_txmap; /* transmit descriptor map */ 200 201 /* Receive data */ 202 bus_dmamap_t sc_rxmap; /* receive descriptor map */ 203 struct rxd_4k *sc_rxd_4k[NRXPAGES]; /* receive desc pages */ 204 bus_dmamap_t sc_rxm[NRXREAL]; /* receive buffer map */ 205 struct mbuf *sc_rxb[NRXREAL]; /* mbufs on rx descriptors */ 206 int sc_nextrx; /* next descriptor to check */ 207 }; 208 209 #ifdef XGE_DEBUG 210 #define DPRINTF(x) do { if (xgedebug) printf x ; } while (0) 211 #define DPRINTFN(n,x) do { if (xgedebug >= (n)) printf x ; } while (0) 212 int xgedebug = 0; 213 #else 214 #define DPRINTF(x) 215 #define DPRINTFN(n,x) 216 #endif 217 218 int xge_match(struct device *, void *, void *); 219 void xge_attach(struct device *, struct device *, void *); 220 int xge_alloc_txmem(struct xge_softc *); 221 int xge_alloc_rxmem(struct xge_softc *); 222 void xge_start(struct ifnet *); 223 void xge_stop(struct ifnet *, int); 224 int xge_add_rxbuf(struct xge_softc *, int); 225 void xge_setmulti(struct xge_softc *); 226 void xge_setpromisc(struct xge_softc *); 227 int xge_setup_xgxs_xena(struct xge_softc *); 228 int xge_setup_xgxs_herc(struct xge_softc *); 229 int xge_ioctl(struct ifnet *, u_long, caddr_t); 230 int xge_init(struct ifnet *); 231 void xge_ifmedia_status(struct ifnet *, struct ifmediareq *); 232 int xge_xgmii_mediachange(struct ifnet *); 233 void xge_enable(struct xge_softc *); 234 int xge_intr(void *); 235 236 /* 237 * Helpers to address registers. 238 */ 239 #define PIF_WCSR(csr, val) pif_wcsr(sc, csr, val) 240 #define PIF_RCSR(csr) pif_rcsr(sc, csr) 241 #define TXP_WCSR(csr, val) txp_wcsr(sc, csr, val) 242 #define PIF_WKEY(csr, val) pif_wkey(sc, csr, val) 243 244 static inline void 245 pif_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val) 246 { 247 uint32_t lval, hval; 248 249 lval = val&0xffffffff; 250 hval = val>>32; 251 252 bus_space_write_4(sc->sc_st, sc->sc_sh, csr, lval); 253 bus_space_write_4(sc->sc_st, sc->sc_sh, csr+4, hval); 254 } 255 256 static inline uint64_t 257 pif_rcsr(struct xge_softc *sc, bus_size_t csr) 258 { 259 uint64_t val, val2; 260 261 val = bus_space_read_4(sc->sc_st, sc->sc_sh, csr); 262 val2 = bus_space_read_4(sc->sc_st, sc->sc_sh, csr+4); 263 val |= (val2 << 32); 264 return (val); 265 } 266 267 static inline void 268 txp_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val) 269 { 270 uint32_t lval, hval; 271 272 lval = val&0xffffffff; 273 hval = val>>32; 274 275 bus_space_write_4(sc->sc_txt, sc->sc_txh, csr, lval); 276 bus_space_write_4(sc->sc_txt, sc->sc_txh, csr+4, hval); 277 } 278 279 280 static inline void 281 pif_wkey(struct xge_softc *sc, bus_size_t csr, uint64_t val) 282 { 283 uint32_t lval, hval; 284 285 lval = val&0xffffffff; 286 hval = val>>32; 287 288 if (sc->xge_type == XGE_TYPE_XENA) 289 PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE); 290 291 bus_space_write_4(sc->sc_st, sc->sc_sh, csr, lval); 292 293 if (sc->xge_type == XGE_TYPE_XENA) 294 PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE); 295 296 bus_space_write_4(sc->sc_st, sc->sc_sh, csr+4, hval); 297 } 298 299 struct cfattach xge_ca = { 300 sizeof(struct xge_softc), xge_match, xge_attach 301 }; 302 303 struct cfdriver xge_cd = { 304 NULL, "xge", DV_IFNET 305 }; 306 307 #define XNAME sc->sc_dev.dv_xname 308 309 #define XGE_RXSYNC(desc, what) \ 310 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap, \ 311 (desc/NDESC_BUFMODE) * XGE_PAGE + sizeof(struct rxdesc) * \ 312 (desc%NDESC_BUFMODE), sizeof(struct rxdesc), what) 313 #define XGE_RXD(desc) &sc->sc_rxd_4k[desc/NDESC_BUFMODE]-> \ 314 r4_rxd[desc%NDESC_BUFMODE] 315 316 /* 317 * Non-tunable constants. 318 */ 319 #define XGE_MAX_FRAMELEN 9622 320 #define XGE_MAX_MTU (XGE_MAX_FRAMELEN - ETHER_HDR_LEN - \ 321 ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 322 323 const struct pci_matchid xge_devices[] = { 324 { PCI_VENDOR_NETERION, PCI_PRODUCT_NETERION_XFRAME }, 325 { PCI_VENDOR_NETERION, PCI_PRODUCT_NETERION_XFRAME_2 } 326 }; 327 328 int 329 xge_match(struct device *parent, void *match, void *aux) 330 { 331 return (pci_matchbyid((struct pci_attach_args *)aux, xge_devices, 332 nitems(xge_devices))); 333 } 334 335 void 336 xge_attach(struct device *parent, struct device *self, void *aux) 337 { 338 struct pci_attach_args *pa = aux; 339 struct xge_softc *sc; 340 struct ifnet *ifp; 341 pcireg_t memtype; 342 pci_intr_handle_t ih; 343 const char *intrstr = NULL; 344 pci_chipset_tag_t pc = pa->pa_pc; 345 uint8_t enaddr[ETHER_ADDR_LEN]; 346 uint64_t val; 347 int i; 348 349 sc = (struct xge_softc *)self; 350 351 sc->sc_dmat = pa->pa_dmat; 352 353 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETERION_XFRAME) 354 sc->xge_type = XGE_TYPE_XENA; 355 else 356 sc->xge_type = XGE_TYPE_HERC; 357 358 /* Get BAR0 address */ 359 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, XGE_PIF_BAR); 360 if (pci_mapreg_map(pa, XGE_PIF_BAR, memtype, 0, 361 &sc->sc_st, &sc->sc_sh, 0, 0, 0)) { 362 printf(": unable to map PIF BAR registers\n"); 363 return; 364 } 365 366 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, XGE_TXP_BAR); 367 if (pci_mapreg_map(pa, XGE_TXP_BAR, memtype, 0, 368 &sc->sc_txt, &sc->sc_txh, 0, 0, 0)) { 369 printf(": unable to map TXP BAR registers\n"); 370 return; 371 } 372 373 if (sc->xge_type == XGE_TYPE_XENA) { 374 /* Save PCI config space */ 375 for (i = 0; i < XGE_PCISIZE_XENA; i += 4) 376 sc->sc_pciregs[i/4] = pci_conf_read(pa->pa_pc, pa->pa_tag, i); 377 } 378 379 #if BYTE_ORDER == LITTLE_ENDIAN 380 val = (uint64_t)0xFFFFFFFFFFFFFFFFULL; 381 val &= ~(TxF_R_SE|RxF_W_SE); 382 PIF_WCSR(SWAPPER_CTRL, val); 383 PIF_WCSR(SWAPPER_CTRL, val); 384 #endif 385 386 if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) { 387 printf(": failed configuring endian, %llx != %llx!\n", 388 (unsigned long long)val, SWAPPER_MAGIC); 389 return; 390 } 391 392 /* 393 * Fix for all "FFs" MAC address problems observed on 394 * Alpha platforms. Not needed for Herc. 395 */ 396 if (sc->xge_type == XGE_TYPE_XENA) { 397 /* 398 * The MAC addr may be all FF's, which is not good. 399 * Resolve it by writing some magics to GPIO_CONTROL and 400 * force a chip reset to read in the serial eeprom again. 401 */ 402 for (i = 0; i < nitems(fix_mac); i++) { 403 PIF_WCSR(GPIO_CONTROL, fix_mac[i]); 404 PIF_RCSR(GPIO_CONTROL); 405 } 406 407 /* 408 * Reset the chip and restore the PCI registers. 409 */ 410 PIF_WCSR(SW_RESET, 0xa5a5a50000000000ULL); 411 DELAY(500000); 412 for (i = 0; i < XGE_PCISIZE_XENA; i += 4) 413 pci_conf_write(pa->pa_pc, pa->pa_tag, i, sc->sc_pciregs[i/4]); 414 415 /* 416 * Restore the byte order registers. 417 */ 418 #if BYTE_ORDER == LITTLE_ENDIAN 419 val = (uint64_t)0xFFFFFFFFFFFFFFFFULL; 420 val &= ~(TxF_R_SE|RxF_W_SE); 421 PIF_WCSR(SWAPPER_CTRL, val); 422 PIF_WCSR(SWAPPER_CTRL, val); 423 #endif 424 425 if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) { 426 printf(": failed configuring endian2, %llx != %llx!\n", 427 (unsigned long long)val, SWAPPER_MAGIC); 428 return; 429 } 430 } 431 432 /* 433 * XGXS initialization. 434 */ 435 436 /* 437 * For Herc, bring EOI out of reset before XGXS. 438 */ 439 if (sc->xge_type == XGE_TYPE_HERC) { 440 val = PIF_RCSR(SW_RESET); 441 val &= 0xffff00ffffffffffULL; 442 PIF_WCSR(SW_RESET,val); 443 delay(1000*1000); /* wait for 1 sec */ 444 } 445 446 /* 29, Bring adapter out of reset */ 447 val = PIF_RCSR(SW_RESET); 448 val &= 0xffffff00ffffffffULL; 449 PIF_WCSR(SW_RESET, val); 450 DELAY(500000); 451 452 /* Ensure that it's safe to access registers by checking 453 * RIC_RUNNING bit is reset. Check is valid only for XframeII. 454 */ 455 if (sc->xge_type == XGE_TYPE_HERC){ 456 for (i = 0; i < 50; i++) { 457 val = PIF_RCSR(ADAPTER_STATUS); 458 if (!(val & RIC_RUNNING)) 459 break; 460 delay(20*1000); 461 } 462 463 if (i == 50) { 464 printf(": not safe to access registers\n"); 465 return; 466 } 467 } 468 469 /* 30, configure XGXS transceiver */ 470 if (sc->xge_type == XGE_TYPE_XENA) 471 xge_setup_xgxs_xena(sc); 472 else if(sc->xge_type == XGE_TYPE_HERC) 473 xge_setup_xgxs_herc(sc); 474 475 /* 33, program MAC address (not needed here) */ 476 /* Get ethernet address */ 477 PIF_WCSR(RMAC_ADDR_CMD_MEM, 478 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(0)); 479 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 480 ; 481 val = PIF_RCSR(RMAC_ADDR_DATA0_MEM); 482 for (i = 0; i < ETHER_ADDR_LEN; i++) 483 enaddr[i] = (uint8_t)(val >> (56 - (8*i))); 484 485 /* 486 * Get memory for transmit descriptor lists. 487 */ 488 if (xge_alloc_txmem(sc)) { 489 printf(": failed allocating txmem.\n"); 490 return; 491 } 492 493 /* 9 and 10 - set FIFO number/prio */ 494 PIF_WCSR(TX_FIFO_P0, TX_FIFO_LEN0(NTXDESCS)); 495 PIF_WCSR(TX_FIFO_P1, 0ULL); 496 PIF_WCSR(TX_FIFO_P2, 0ULL); 497 PIF_WCSR(TX_FIFO_P3, 0ULL); 498 499 /* 11, XXX set round-robin prio? */ 500 501 /* 12, enable transmit FIFO */ 502 val = PIF_RCSR(TX_FIFO_P0); 503 val |= TX_FIFO_ENABLE; 504 PIF_WCSR(TX_FIFO_P0, val); 505 506 /* 13, disable some error checks */ 507 PIF_WCSR(TX_PA_CFG, 508 TX_PA_CFG_IFR|TX_PA_CFG_ISO|TX_PA_CFG_ILC|TX_PA_CFG_ILE); 509 510 /* Create transmit DMA maps */ 511 for (i = 0; i < NTXDESCS; i++) { 512 if (bus_dmamap_create(sc->sc_dmat, XGE_MAX_FRAMELEN, 513 NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_txm[i])) { 514 printf(": cannot create TX DMA maps\n"); 515 return; 516 } 517 } 518 519 sc->sc_lasttx = NTXDESCS-1; 520 521 /* 522 * RxDMA initialization. 523 * Only use one out of 8 possible receive queues. 524 */ 525 /* allocate rx descriptor memory */ 526 if (xge_alloc_rxmem(sc)) { 527 printf(": failed allocating rxmem\n"); 528 return; 529 } 530 531 /* Create receive buffer DMA maps */ 532 for (i = 0; i < NRXREAL; i++) { 533 if (bus_dmamap_create(sc->sc_dmat, XGE_MAX_FRAMELEN, 534 NRXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_rxm[i])) { 535 printf(": cannot create RX DMA maps\n"); 536 return; 537 } 538 } 539 540 /* allocate mbufs to receive descriptors */ 541 for (i = 0; i < NRXREAL; i++) 542 if (xge_add_rxbuf(sc, i)) 543 panic("out of mbufs too early"); 544 545 /* 14, setup receive ring priority */ 546 PIF_WCSR(RX_QUEUE_PRIORITY, 0ULL); /* only use one ring */ 547 548 /* 15, setup receive ring round-robin calendar */ 549 PIF_WCSR(RX_W_ROUND_ROBIN_0, 0ULL); /* only use one ring */ 550 PIF_WCSR(RX_W_ROUND_ROBIN_1, 0ULL); 551 PIF_WCSR(RX_W_ROUND_ROBIN_2, 0ULL); 552 PIF_WCSR(RX_W_ROUND_ROBIN_3, 0ULL); 553 PIF_WCSR(RX_W_ROUND_ROBIN_4, 0ULL); 554 555 /* 16, write receive ring start address */ 556 PIF_WCSR(PRC_RXD0_0, (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr); 557 /* PRC_RXD0_[1-7] are not used */ 558 559 /* 17, Setup alarm registers */ 560 PIF_WCSR(PRC_ALARM_ACTION, 0ULL); /* Default everything to retry */ 561 562 /* 18, init receive ring controller */ 563 #if RX_MODE == RX_MODE_1 564 val = RING_MODE_1; 565 #elif RX_MODE == RX_MODE_3 566 val = RING_MODE_3; 567 #else /* RX_MODE == RX_MODE_5 */ 568 val = RING_MODE_5; 569 #endif 570 PIF_WCSR(PRC_CTRL_0, RC_IN_SVC|val); 571 /* leave 1-7 disabled */ 572 /* XXXX snoop configuration? */ 573 574 /* 19, set chip memory assigned to the queue */ 575 if (sc->xge_type == XGE_TYPE_XENA) { 576 /* all 64M to queue 0 */ 577 PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 64)); 578 } else { 579 /* all 32M to queue 0 */ 580 PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 32)); 581 } 582 583 /* 20, setup RLDRAM parameters */ 584 /* do not touch it for now */ 585 586 /* 21, setup pause frame thresholds */ 587 /* so not touch the defaults */ 588 /* XXX - must 0xff be written as stated in the manual? */ 589 590 /* 22, configure RED */ 591 /* we do not want to drop packets, so ignore */ 592 593 /* 23, initiate RLDRAM */ 594 val = PIF_RCSR(MC_RLDRAM_MRS); 595 val |= MC_QUEUE_SIZE_ENABLE|MC_RLDRAM_MRS_ENABLE; 596 PIF_WCSR(MC_RLDRAM_MRS, val); 597 DELAY(1000); 598 599 /* 600 * Setup interrupt policies. 601 */ 602 /* 40, Transmit interrupts */ 603 PIF_WCSR(TTI_DATA1_MEM, TX_TIMER_VAL(0x1ff) | TX_TIMER_AC | 604 TX_URNG_A(5) | TX_URNG_B(20) | TX_URNG_C(48)); 605 PIF_WCSR(TTI_DATA2_MEM, 606 TX_UFC_A(25) | TX_UFC_B(64) | TX_UFC_C(128) | TX_UFC_D(512)); 607 PIF_WCSR(TTI_COMMAND_MEM, TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE); 608 while (PIF_RCSR(TTI_COMMAND_MEM) & TTI_CMD_MEM_STROBE) 609 ; 610 611 /* 41, Receive interrupts */ 612 PIF_WCSR(RTI_DATA1_MEM, RX_TIMER_VAL(0x800) | RX_TIMER_AC | 613 RX_URNG_A(5) | RX_URNG_B(20) | RX_URNG_C(50)); 614 PIF_WCSR(RTI_DATA2_MEM, 615 RX_UFC_A(64) | RX_UFC_B(128) | RX_UFC_C(256) | RX_UFC_D(512)); 616 PIF_WCSR(RTI_COMMAND_MEM, RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE); 617 while (PIF_RCSR(RTI_COMMAND_MEM) & RTI_CMD_MEM_STROBE) 618 ; 619 620 /* 621 * Setup media stuff. 622 */ 623 ifmedia_init(&sc->xena_media, IFM_IMASK, xge_xgmii_mediachange, 624 xge_ifmedia_status); 625 ifmedia_add(&sc->xena_media, IFM_ETHER|IFM_10G_SR, 0, NULL); 626 ifmedia_set(&sc->xena_media, IFM_ETHER|IFM_10G_SR); 627 628 ifp = &sc->sc_arpcom.ac_if; 629 strlcpy(ifp->if_xname, XNAME, IFNAMSIZ); 630 memcpy(sc->sc_arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN); 631 ifp->if_baudrate = IF_Gbps(10); 632 ifp->if_softc = sc; 633 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 634 ifp->if_ioctl = xge_ioctl; 635 ifp->if_start = xge_start; 636 #ifdef XGE_JUMBO 637 ifp->if_hardmtu = XGE_MAX_MTU; 638 #endif 639 IFQ_SET_MAXLEN(&ifp->if_snd, NTXDESCS - 1); 640 IFQ_SET_READY(&ifp->if_snd); 641 642 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 643 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 644 645 #if NVLAN > 0 646 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 647 #endif 648 649 /* 650 * Attach the interface. 651 */ 652 if_attach(ifp); 653 ether_ifattach(ifp); 654 655 /* 656 * Setup interrupt vector before initializing. 657 */ 658 if (pci_intr_map(pa, &ih)) { 659 printf(": unable to map interrupt\n"); 660 return; 661 } 662 intrstr = pci_intr_string(pc, ih); 663 if ((sc->sc_ih = 664 pci_intr_establish(pc, ih, IPL_NET, xge_intr, sc, XNAME)) == NULL) { 665 printf(": unable to establish interrupt at %s\n", 666 intrstr ? intrstr : "<unknown>"); 667 return; 668 } 669 printf(": %s, address %s\n", intrstr, ether_sprintf(enaddr)); 670 } 671 672 void 673 xge_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 674 { 675 struct xge_softc *sc = ifp->if_softc; 676 uint64_t reg; 677 678 ifmr->ifm_status = IFM_AVALID; 679 ifmr->ifm_active = IFM_ETHER|IFM_10G_SR; 680 681 reg = PIF_RCSR(ADAPTER_STATUS); 682 if ((reg & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0) 683 ifmr->ifm_status |= IFM_ACTIVE; 684 } 685 686 int 687 xge_xgmii_mediachange(struct ifnet *ifp) 688 { 689 return (0); 690 } 691 692 void 693 xge_enable(struct xge_softc *sc) 694 { 695 uint64_t val; 696 697 /* 2, enable adapter */ 698 val = PIF_RCSR(ADAPTER_CONTROL); 699 val |= ADAPTER_EN; 700 PIF_WCSR(ADAPTER_CONTROL, val); 701 702 /* 3, light the card enable led */ 703 val = PIF_RCSR(ADAPTER_CONTROL); 704 val |= LED_ON; 705 PIF_WCSR(ADAPTER_CONTROL, val); 706 #ifdef XGE_DEBUG 707 printf("%s: link up\n", XNAME); 708 #endif 709 } 710 711 int 712 xge_init(struct ifnet *ifp) 713 { 714 struct xge_softc *sc = ifp->if_softc; 715 uint64_t val; 716 int s; 717 718 s = splnet(); 719 720 /* 721 * Cancel any pending I/O 722 */ 723 xge_stop(ifp, 0); 724 725 /* 31+32, setup MAC config */ 726 PIF_WKEY(MAC_CFG, TMAC_EN|RMAC_EN|TMAC_APPEND_PAD|RMAC_STRIP_FCS| 727 RMAC_BCAST_EN|RMAC_DISCARD_PFRM); 728 729 DELAY(1000); 730 731 /* 54, ensure that the adapter is 'quiescent' */ 732 val = PIF_RCSR(ADAPTER_STATUS); 733 if ((val & QUIESCENT) != QUIESCENT) { 734 #if 0 735 char buf[200]; 736 #endif 737 printf("%s: adapter not quiescent, aborting\n", XNAME); 738 val = (val & QUIESCENT) ^ QUIESCENT; 739 #if 0 740 bitmask_snprintf(val, QUIESCENT_BMSK, buf, sizeof buf); 741 printf("%s: ADAPTER_STATUS missing bits %s\n", XNAME, buf); 742 #endif 743 splx(s); 744 return (1); 745 } 746 747 if (!(ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 748 /* disable VLAN tag stripping */ 749 val = PIF_RCSR(RX_PA_CFG); 750 val &= ~STRIP_VLAN_TAG; 751 PIF_WCSR(RX_PA_CFG, val); 752 } 753 754 /* set MRU */ 755 #ifdef XGE_JUMBO 756 PIF_WCSR(RMAC_MAX_PYLD_LEN, RMAC_PYLD_LEN(XGE_MAX_FRAMELEN)); 757 #else 758 PIF_WCSR(RMAC_MAX_PYLD_LEN, RMAC_PYLD_LEN(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)); 759 #endif 760 761 /* 56, enable the transmit laser */ 762 val = PIF_RCSR(ADAPTER_CONTROL); 763 val |= EOI_TX_ON; 764 PIF_WCSR(ADAPTER_CONTROL, val); 765 766 xge_enable(sc); 767 768 /* 769 * Enable all interrupts 770 */ 771 PIF_WCSR(TX_TRAFFIC_MASK, 0); 772 PIF_WCSR(RX_TRAFFIC_MASK, 0); 773 PIF_WCSR(GENERAL_INT_MASK, 0); 774 PIF_WCSR(TXPIC_INT_MASK, 0); 775 PIF_WCSR(RXPIC_INT_MASK, 0); 776 777 PIF_WCSR(MAC_INT_MASK, MAC_TMAC_INT); /* only from RMAC */ 778 PIF_WCSR(MAC_RMAC_ERR_MASK, ~RMAC_LINK_STATE_CHANGE_INT); 779 780 xge_setpromisc(sc); 781 782 xge_setmulti(sc); 783 784 /* Done... */ 785 ifp->if_flags |= IFF_RUNNING; 786 ifp->if_flags &= ~IFF_OACTIVE; 787 788 splx(s); 789 790 return (0); 791 } 792 793 void 794 xge_stop(struct ifnet *ifp, int disable) 795 { 796 struct xge_softc *sc = ifp->if_softc; 797 uint64_t val; 798 799 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 800 801 val = PIF_RCSR(ADAPTER_CONTROL); 802 val &= ~ADAPTER_EN; 803 PIF_WCSR(ADAPTER_CONTROL, val); 804 805 while ((PIF_RCSR(ADAPTER_STATUS) & QUIESCENT) != QUIESCENT) 806 ; 807 } 808 809 int 810 xge_intr(void *pv) 811 { 812 struct xge_softc *sc = pv; 813 struct txd *txd; 814 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 815 bus_dmamap_t dmp; 816 uint64_t val; 817 int i, lasttx, plen; 818 819 val = PIF_RCSR(GENERAL_INT_STATUS); 820 if (val == 0) 821 return (0); /* no interrupt here */ 822 823 PIF_WCSR(GENERAL_INT_STATUS, val); 824 825 if ((val = PIF_RCSR(MAC_RMAC_ERR_REG)) & RMAC_LINK_STATE_CHANGE_INT) { 826 /* Wait for quiescence */ 827 #ifdef XGE_DEBUG 828 printf("%s: link down\n", XNAME); 829 #endif 830 while ((PIF_RCSR(ADAPTER_STATUS) & QUIESCENT) != QUIESCENT) 831 ; 832 PIF_WCSR(MAC_RMAC_ERR_REG, RMAC_LINK_STATE_CHANGE_INT); 833 834 val = PIF_RCSR(ADAPTER_STATUS); 835 if ((val & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0) 836 xge_enable(sc); /* Only if link restored */ 837 } 838 839 if ((val = PIF_RCSR(TX_TRAFFIC_INT))) 840 PIF_WCSR(TX_TRAFFIC_INT, val); /* clear interrupt bits */ 841 /* 842 * Collect sent packets. 843 */ 844 lasttx = sc->sc_lasttx; 845 while ((i = NEXTTX(sc->sc_lasttx)) != sc->sc_nexttx) { 846 txd = sc->sc_txd[i]; 847 dmp = sc->sc_txm[i]; 848 849 bus_dmamap_sync(sc->sc_dmat, dmp, 0, 850 dmp->dm_mapsize, 851 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 852 853 if (txd->txd_control1 & TXD_CTL1_OWN) { 854 bus_dmamap_sync(sc->sc_dmat, dmp, 0, 855 dmp->dm_mapsize, BUS_DMASYNC_PREREAD); 856 break; 857 } 858 bus_dmamap_unload(sc->sc_dmat, dmp); 859 m_freem(sc->sc_txb[i]); 860 ifp->if_opackets++; 861 sc->sc_lasttx = i; 862 } 863 864 if (sc->sc_lasttx != lasttx) 865 ifp->if_flags &= ~IFF_OACTIVE; 866 867 /* Try to get more packets on the wire */ 868 xge_start(ifp); 869 870 /* clear interrupt bits */ 871 if ((val = PIF_RCSR(RX_TRAFFIC_INT))) 872 PIF_WCSR(RX_TRAFFIC_INT, val); 873 874 for (;;) { 875 struct rxdesc *rxd; 876 struct mbuf *m; 877 878 XGE_RXSYNC(sc->sc_nextrx, 879 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 880 881 rxd = XGE_RXD(sc->sc_nextrx); 882 if (rxd->rxd_control1 & RXD_CTL1_OWN) { 883 XGE_RXSYNC(sc->sc_nextrx, BUS_DMASYNC_PREREAD); 884 break; 885 } 886 887 /* got a packet */ 888 m = sc->sc_rxb[sc->sc_nextrx]; 889 #if RX_MODE == RX_MODE_1 890 plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2); 891 #elif RX_MODE == RX_MODE_3 892 #error Fix rxmodes in xge_intr 893 #elif RX_MODE == RX_MODE_5 894 plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2); 895 plen += m->m_next->m_len = RXD_CTL2_BUF1SIZ(rxd->rxd_control2); 896 plen += m->m_next->m_next->m_len = 897 RXD_CTL2_BUF2SIZ(rxd->rxd_control2); 898 plen += m->m_next->m_next->m_next->m_len = 899 RXD_CTL3_BUF3SIZ(rxd->rxd_control3); 900 plen += m->m_next->m_next->m_next->m_next->m_len = 901 RXD_CTL3_BUF4SIZ(rxd->rxd_control3); 902 #endif 903 m->m_pkthdr.rcvif = ifp; 904 m->m_pkthdr.len = plen; 905 906 val = rxd->rxd_control1; 907 908 if (xge_add_rxbuf(sc, sc->sc_nextrx)) { 909 /* Failed, recycle this mbuf */ 910 #if RX_MODE == RX_MODE_1 911 rxd->rxd_control2 = RXD_MKCTL2(MCLBYTES, 0, 0); 912 rxd->rxd_control1 = RXD_CTL1_OWN; 913 #elif RX_MODE == RX_MODE_3 914 #elif RX_MODE == RX_MODE_5 915 #endif 916 XGE_RXSYNC(sc->sc_nextrx, 917 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 918 ifp->if_ierrors++; 919 break; 920 } 921 922 ifp->if_ipackets++; 923 924 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_IPv4) 925 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 926 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_TCP) 927 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 928 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_UDP) 929 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 930 931 #if NVLAN > 0 932 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_VLAN) { 933 m->m_pkthdr.ether_vtag = 934 RXD_CTL2_VLANTAG(rxd->rxd_control2); 935 m->m_flags |= M_VLANTAG; 936 } 937 #endif 938 939 #if NBPFILTER > 0 940 if (ifp->if_bpf) 941 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 942 #endif /* NBPFILTER > 0 */ 943 944 ether_input_mbuf(ifp, m); 945 946 if (++sc->sc_nextrx == NRXREAL) 947 sc->sc_nextrx = 0; 948 } 949 950 return (1); 951 } 952 953 int 954 xge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 955 { 956 struct xge_softc *sc = ifp->if_softc; 957 struct ifaddr *ifa = (struct ifaddr *) data; 958 struct ifreq *ifr = (struct ifreq *) data; 959 int s, error = 0; 960 961 s = splnet(); 962 963 switch (cmd) { 964 case SIOCSIFADDR: 965 ifp->if_flags |= IFF_UP; 966 if (!(ifp->if_flags & IFF_RUNNING)) 967 xge_init(ifp); 968 #ifdef INET 969 if (ifa->ifa_addr->sa_family == AF_INET) 970 arp_ifinit(&sc->sc_arpcom, ifa); 971 #endif /* INET */ 972 break; 973 974 case SIOCSIFFLAGS: 975 if (ifp->if_flags & IFF_UP) { 976 if (ifp->if_flags & IFF_RUNNING && 977 (ifp->if_flags ^ sc->xge_if_flags) & 978 IFF_PROMISC) { 979 xge_setpromisc(sc); 980 } else { 981 if (!(ifp->if_flags & IFF_RUNNING)) 982 xge_init(ifp); 983 } 984 } else { 985 if (ifp->if_flags & IFF_RUNNING) 986 xge_stop(ifp, 1); 987 } 988 sc->xge_if_flags = ifp->if_flags; 989 break; 990 991 case SIOCGIFMEDIA: 992 case SIOCSIFMEDIA: 993 error = ifmedia_ioctl(ifp, ifr, &sc->xena_media, cmd); 994 break; 995 996 default: 997 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 998 } 999 1000 if (error == ENETRESET) { 1001 if (ifp->if_flags & IFF_RUNNING) 1002 xge_setmulti(sc); 1003 error = 0; 1004 } 1005 1006 splx(s); 1007 return (error); 1008 } 1009 1010 void 1011 xge_setmulti(struct xge_softc *sc) 1012 { 1013 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1014 struct arpcom *ac = &sc->sc_arpcom; 1015 struct ether_multi *enm; 1016 struct ether_multistep step; 1017 int i, numaddr = 1; /* first slot used for card unicast address */ 1018 uint64_t val; 1019 1020 ETHER_FIRST_MULTI(step, ac, enm); 1021 while (enm != NULL) { 1022 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1023 /* Skip ranges */ 1024 goto allmulti; 1025 } 1026 if (numaddr == MAX_MCAST_ADDR) 1027 goto allmulti; 1028 for (val = 0, i = 0; i < ETHER_ADDR_LEN; i++) { 1029 val <<= 8; 1030 val |= enm->enm_addrlo[i]; 1031 } 1032 PIF_WCSR(RMAC_ADDR_DATA0_MEM, val << 16); 1033 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL); 1034 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 1035 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(numaddr)); 1036 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 1037 ; 1038 numaddr++; 1039 ETHER_NEXT_MULTI(step, enm); 1040 } 1041 /* set the remaining entries to the broadcast address */ 1042 for (i = numaddr; i < MAX_MCAST_ADDR; i++) { 1043 PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0xffffffffffff0000ULL); 1044 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL); 1045 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 1046 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(i)); 1047 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 1048 ; 1049 } 1050 ifp->if_flags &= ~IFF_ALLMULTI; 1051 return; 1052 1053 allmulti: 1054 /* Just receive everything with the multicast bit set */ 1055 ifp->if_flags |= IFF_ALLMULTI; 1056 PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0x8000000000000000ULL); 1057 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xF000000000000000ULL); 1058 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 1059 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(1)); 1060 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 1061 ; 1062 } 1063 1064 void 1065 xge_setpromisc(struct xge_softc *sc) 1066 { 1067 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1068 uint64_t val; 1069 1070 val = PIF_RCSR(MAC_CFG); 1071 1072 if (ifp->if_flags & IFF_PROMISC) 1073 val |= RMAC_PROM_EN; 1074 else 1075 val &= ~RMAC_PROM_EN; 1076 1077 PIF_WCSR(MAC_CFG, val); 1078 } 1079 1080 void 1081 xge_start(struct ifnet *ifp) 1082 { 1083 struct xge_softc *sc = ifp->if_softc; 1084 struct txd *txd = NULL; /* XXX - gcc */ 1085 bus_dmamap_t dmp; 1086 struct mbuf *m; 1087 uint64_t par, lcr; 1088 int nexttx = 0, ntxd, error, i; 1089 1090 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1091 return; 1092 1093 par = lcr = 0; 1094 for (;;) { 1095 IFQ_POLL(&ifp->if_snd, m); 1096 if (m == NULL) 1097 break; /* out of packets */ 1098 1099 if (sc->sc_nexttx == sc->sc_lasttx) 1100 break; /* No more space */ 1101 1102 nexttx = sc->sc_nexttx; 1103 dmp = sc->sc_txm[nexttx]; 1104 1105 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmp, m, 1106 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0) { 1107 printf("%s: bus_dmamap_load_mbuf error %d\n", 1108 XNAME, error); 1109 break; 1110 } 1111 IFQ_DEQUEUE(&ifp->if_snd, m); 1112 1113 bus_dmamap_sync(sc->sc_dmat, dmp, 0, dmp->dm_mapsize, 1114 BUS_DMASYNC_PREWRITE); 1115 1116 txd = sc->sc_txd[nexttx]; 1117 sc->sc_txb[nexttx] = m; 1118 for (i = 0; i < dmp->dm_nsegs; i++) { 1119 if (dmp->dm_segs[i].ds_len == 0) 1120 continue; 1121 txd->txd_control1 = dmp->dm_segs[i].ds_len; 1122 txd->txd_control2 = 0; 1123 txd->txd_bufaddr = dmp->dm_segs[i].ds_addr; 1124 txd++; 1125 } 1126 ntxd = txd - sc->sc_txd[nexttx] - 1; 1127 txd = sc->sc_txd[nexttx]; 1128 txd->txd_control1 |= TXD_CTL1_OWN|TXD_CTL1_GCF; 1129 txd->txd_control2 = TXD_CTL2_UTIL; 1130 1131 #if NVLAN > 0 1132 if (m->m_flags & M_VLANTAG) { 1133 txd->txd_control2 |= TXD_CTL2_VLANE; 1134 txd->txd_control2 |= 1135 TXD_CTL2_VLANT(m->m_pkthdr.ether_vtag); 1136 } 1137 #endif 1138 1139 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1140 txd->txd_control2 |= TXD_CTL2_CIPv4; 1141 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1142 txd->txd_control2 |= TXD_CTL2_CTCP; 1143 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1144 txd->txd_control2 |= TXD_CTL2_CUDP; 1145 1146 txd[ntxd].txd_control1 |= TXD_CTL1_GCL; 1147 1148 bus_dmamap_sync(sc->sc_dmat, dmp, 0, dmp->dm_mapsize, 1149 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1150 1151 par = sc->sc_txdp[nexttx]; 1152 lcr = TXDL_NUMTXD(ntxd) | TXDL_LGC_FIRST | TXDL_LGC_LAST; 1153 TXP_WCSR(TXDL_PAR, par); 1154 TXP_WCSR(TXDL_LCR, lcr); 1155 1156 #if NBPFILTER > 0 1157 if (ifp->if_bpf) 1158 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1159 #endif /* NBPFILTER > 0 */ 1160 1161 sc->sc_nexttx = NEXTTX(nexttx); 1162 } 1163 } 1164 1165 /* 1166 * Allocate DMA memory for transmit descriptor fragments. 1167 * Only one map is used for all descriptors. 1168 */ 1169 int 1170 xge_alloc_txmem(struct xge_softc *sc) 1171 { 1172 struct txd *txp; 1173 bus_dma_segment_t seg; 1174 bus_addr_t txdp; 1175 caddr_t kva; 1176 int i, rseg, state; 1177 1178 #define TXMAPSZ (NTXDESCS*NTXFRAGS*sizeof(struct txd)) 1179 state = 0; 1180 if (bus_dmamem_alloc(sc->sc_dmat, TXMAPSZ, PAGE_SIZE, 0, 1181 &seg, 1, &rseg, BUS_DMA_NOWAIT)) 1182 goto err; 1183 state++; 1184 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, TXMAPSZ, &kva, 1185 BUS_DMA_NOWAIT)) 1186 goto err; 1187 1188 state++; 1189 if (bus_dmamap_create(sc->sc_dmat, TXMAPSZ, 1, TXMAPSZ, 0, 1190 BUS_DMA_NOWAIT, &sc->sc_txmap)) 1191 goto err; 1192 state++; 1193 if (bus_dmamap_load(sc->sc_dmat, sc->sc_txmap, 1194 kva, TXMAPSZ, NULL, BUS_DMA_NOWAIT)) 1195 goto err; 1196 1197 /* setup transmit array pointers */ 1198 txp = (struct txd *)kva; 1199 txdp = seg.ds_addr; 1200 for (i = 0; i < NTXDESCS; i++) { 1201 sc->sc_txd[i] = txp; 1202 sc->sc_txdp[i] = txdp; 1203 txp += NTXFRAGS; 1204 txdp += (NTXFRAGS * sizeof(struct txd)); 1205 } 1206 1207 return (0); 1208 1209 err: 1210 if (state > 2) 1211 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap); 1212 if (state > 1) 1213 bus_dmamem_unmap(sc->sc_dmat, kva, TXMAPSZ); 1214 if (state > 0) 1215 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1216 return (ENOBUFS); 1217 } 1218 1219 /* 1220 * Allocate DMA memory for receive descriptor, 1221 * only one map is used for all descriptors. 1222 * link receive descriptor pages together. 1223 */ 1224 int 1225 xge_alloc_rxmem(struct xge_softc *sc) 1226 { 1227 struct rxd_4k *rxpp; 1228 bus_dma_segment_t seg; 1229 caddr_t kva; 1230 int i, rseg, state; 1231 1232 /* sanity check */ 1233 if (sizeof(struct rxd_4k) != XGE_PAGE) { 1234 printf("bad compiler struct alignment, %d != %d\n", 1235 (int)sizeof(struct rxd_4k), XGE_PAGE); 1236 return (EINVAL); 1237 } 1238 1239 state = 0; 1240 if (bus_dmamem_alloc(sc->sc_dmat, RXMAPSZ, PAGE_SIZE, 0, 1241 &seg, 1, &rseg, BUS_DMA_NOWAIT)) 1242 goto err; 1243 state++; 1244 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, RXMAPSZ, &kva, 1245 BUS_DMA_NOWAIT)) 1246 goto err; 1247 1248 state++; 1249 if (bus_dmamap_create(sc->sc_dmat, RXMAPSZ, 1, RXMAPSZ, 0, 1250 BUS_DMA_NOWAIT, &sc->sc_rxmap)) 1251 goto err; 1252 state++; 1253 if (bus_dmamap_load(sc->sc_dmat, sc->sc_rxmap, 1254 kva, RXMAPSZ, NULL, BUS_DMA_NOWAIT)) 1255 goto err; 1256 1257 /* setup receive page link pointers */ 1258 for (rxpp = (struct rxd_4k *)kva, i = 0; i < NRXPAGES; i++, rxpp++) { 1259 sc->sc_rxd_4k[i] = rxpp; 1260 rxpp->r4_next = (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr + 1261 (i*sizeof(struct rxd_4k)) + sizeof(struct rxd_4k); 1262 } 1263 sc->sc_rxd_4k[NRXPAGES-1]->r4_next = 1264 (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr; 1265 1266 return (0); 1267 1268 err: 1269 if (state > 2) 1270 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap); 1271 if (state > 1) 1272 bus_dmamem_unmap(sc->sc_dmat, kva, RXMAPSZ); 1273 if (state > 0) 1274 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1275 return (ENOBUFS); 1276 } 1277 1278 1279 /* 1280 * Add a new mbuf chain to descriptor id. 1281 */ 1282 int 1283 xge_add_rxbuf(struct xge_softc *sc, int id) 1284 { 1285 struct rxdesc *rxd; 1286 struct mbuf *m[5]; 1287 int page, desc, error; 1288 #if RX_MODE == RX_MODE_5 1289 int i; 1290 #endif 1291 1292 page = id/NDESC_BUFMODE; 1293 desc = id%NDESC_BUFMODE; 1294 1295 rxd = &sc->sc_rxd_4k[page]->r4_rxd[desc]; 1296 1297 /* 1298 * Allocate mbufs. 1299 * Currently five mbufs and two clusters are used, 1300 * the hardware will put (ethernet, ip, tcp/udp) headers in 1301 * their own buffer and the clusters are only used for data. 1302 */ 1303 #if RX_MODE == RX_MODE_1 1304 MGETHDR(m[0], M_DONTWAIT, MT_DATA); 1305 if (m[0] == NULL) 1306 return (ENOBUFS); 1307 MCLGET(m[0], M_DONTWAIT); 1308 if ((m[0]->m_flags & M_EXT) == 0) { 1309 m_freem(m[0]); 1310 return (ENOBUFS); 1311 } 1312 m[0]->m_len = m[0]->m_pkthdr.len = m[0]->m_ext.ext_size; 1313 #elif RX_MODE == RX_MODE_3 1314 #error missing rxmode 3. 1315 #elif RX_MODE == RX_MODE_5 1316 MGETHDR(m[0], M_DONTWAIT, MT_DATA); 1317 for (i = 1; i < 5; i++) { 1318 MGET(m[i], M_DONTWAIT, MT_DATA); 1319 } 1320 if (m[3]) 1321 MCLGET(m[3], M_DONTWAIT); 1322 if (m[4]) 1323 MCLGET(m[4], M_DONTWAIT); 1324 if (!m[0] || !m[1] || !m[2] || !m[3] || !m[4] || 1325 ((m[3]->m_flags & M_EXT) == 0) || ((m[4]->m_flags & M_EXT) == 0)) { 1326 /* Out of something */ 1327 for (i = 0; i < 5; i++) 1328 if (m[i] != NULL) 1329 m_free(m[i]); 1330 return (ENOBUFS); 1331 } 1332 /* Link'em together */ 1333 m[0]->m_next = m[1]; 1334 m[1]->m_next = m[2]; 1335 m[2]->m_next = m[3]; 1336 m[3]->m_next = m[4]; 1337 #else 1338 #error bad mode RX_MODE 1339 #endif 1340 1341 if (sc->sc_rxb[id]) 1342 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxm[id]); 1343 sc->sc_rxb[id] = m[0]; 1344 1345 error = bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rxm[id], m[0], 1346 BUS_DMA_READ|BUS_DMA_NOWAIT); 1347 if (error) 1348 return (error); 1349 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxm[id], 0, 1350 sc->sc_rxm[id]->dm_mapsize, BUS_DMASYNC_PREREAD); 1351 1352 #if RX_MODE == RX_MODE_1 1353 rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, 0, 0); 1354 rxd->rxd_buf0 = (uint64_t)sc->sc_rxm[id]->dm_segs[0].ds_addr; 1355 rxd->rxd_control1 = RXD_CTL1_OWN; 1356 #elif RX_MODE == RX_MODE_3 1357 #elif RX_MODE == RX_MODE_5 1358 rxd->rxd_control3 = RXD_MKCTL3(0, m[3]->m_len, m[4]->m_len); 1359 rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, m[1]->m_len, m[2]->m_len); 1360 rxd->rxd_buf0 = (uint64_t)sc->sc_rxm[id]->dm_segs[0].ds_addr; 1361 rxd->rxd_buf1 = (uint64_t)sc->sc_rxm[id]->dm_segs[1].ds_addr; 1362 rxd->rxd_buf2 = (uint64_t)sc->sc_rxm[id]->dm_segs[2].ds_addr; 1363 rxd->rxd_buf3 = (uint64_t)sc->sc_rxm[id]->dm_segs[3].ds_addr; 1364 rxd->rxd_buf4 = (uint64_t)sc->sc_rxm[id]->dm_segs[4].ds_addr; 1365 rxd->rxd_control1 = RXD_CTL1_OWN; 1366 #endif 1367 1368 XGE_RXSYNC(id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1369 return (0); 1370 } 1371 1372 /* 1373 * This magic comes from the FreeBSD driver. 1374 */ 1375 int 1376 xge_setup_xgxs_xena(struct xge_softc *sc) 1377 { 1378 /* The magic numbers are described in the users guide */ 1379 1380 /* Writing to MDIO 0x8000 (Global Config 0) */ 1381 PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50); 1382 PIF_WCSR(DTX_CONTROL, 0x80000515000000E0ULL); DELAY(50); 1383 PIF_WCSR(DTX_CONTROL, 0x80000515D93500E4ULL); DELAY(50); 1384 1385 /* Writing to MDIO 0x8000 (Global Config 1) */ 1386 PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50); 1387 PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50); 1388 PIF_WCSR(DTX_CONTROL, 0x80010515001e00e4ULL); DELAY(50); 1389 1390 /* Reset the Gigablaze */ 1391 PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50); 1392 PIF_WCSR(DTX_CONTROL, 0x80020515000000E0ULL); DELAY(50); 1393 PIF_WCSR(DTX_CONTROL, 0x80020515F21000E4ULL); DELAY(50); 1394 1395 /* read the pole settings */ 1396 PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50); 1397 PIF_WCSR(DTX_CONTROL, 0x80000515000000e0ULL); DELAY(50); 1398 PIF_WCSR(DTX_CONTROL, 0x80000515000000ecULL); DELAY(50); 1399 1400 PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50); 1401 PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50); 1402 PIF_WCSR(DTX_CONTROL, 0x80010515000000ecULL); DELAY(50); 1403 1404 PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50); 1405 PIF_WCSR(DTX_CONTROL, 0x80020515000000e0ULL); DELAY(50); 1406 PIF_WCSR(DTX_CONTROL, 0x80020515000000ecULL); DELAY(50); 1407 1408 /* Workaround for TX Lane XAUI initialization error. 1409 Read Xpak PHY register 24 for XAUI lane status */ 1410 PIF_WCSR(DTX_CONTROL, 0x0018040000000000ULL); DELAY(50); 1411 PIF_WCSR(DTX_CONTROL, 0x00180400000000e0ULL); DELAY(50); 1412 PIF_WCSR(DTX_CONTROL, 0x00180400000000ecULL); DELAY(50); 1413 1414 /* 1415 * Reading the MDIO control with value 0x1804001c0F001c 1416 * means the TxLanes were already in sync 1417 * Reading the MDIO control with value 0x1804000c0x001c 1418 * means some TxLanes are not in sync where x is a 4-bit 1419 * value representing each lanes 1420 */ 1421 #if 0 1422 val = PIF_RCSR(MDIO_CONTROL); 1423 if (val != 0x1804001c0F001cULL) { 1424 printf("%s: MDIO_CONTROL: %llx != %llx\n", 1425 XNAME, val, 0x1804001c0F001cULL); 1426 return (1); 1427 } 1428 #endif 1429 1430 /* Set and remove the DTE XS INTLoopBackN */ 1431 PIF_WCSR(DTX_CONTROL, 0x0000051500000000ULL); DELAY(50); 1432 PIF_WCSR(DTX_CONTROL, 0x00000515604000e0ULL); DELAY(50); 1433 PIF_WCSR(DTX_CONTROL, 0x00000515604000e4ULL); DELAY(50); 1434 PIF_WCSR(DTX_CONTROL, 0x00000515204000e4ULL); DELAY(50); 1435 PIF_WCSR(DTX_CONTROL, 0x00000515204000ecULL); DELAY(50); 1436 1437 #if 0 1438 /* Reading the DTX control register Should be 0x5152040001c */ 1439 val = PIF_RCSR(DTX_CONTROL); 1440 if (val != 0x5152040001cULL) { 1441 printf("%s: DTX_CONTROL: %llx != %llx\n", 1442 XNAME, val, 0x5152040001cULL); 1443 return (1); 1444 } 1445 #endif 1446 1447 PIF_WCSR(MDIO_CONTROL, 0x0018040000000000ULL); DELAY(50); 1448 PIF_WCSR(MDIO_CONTROL, 0x00180400000000e0ULL); DELAY(50); 1449 PIF_WCSR(MDIO_CONTROL, 0x00180400000000ecULL); DELAY(50); 1450 1451 #if 0 1452 /* Reading the MIOD control should be 0x1804001c0f001c */ 1453 val = PIF_RCSR(MDIO_CONTROL); 1454 if (val != 0x1804001c0f001cULL) { 1455 printf("%s: MDIO_CONTROL2: %llx != %llx\n", 1456 XNAME, val, 0x1804001c0f001cULL); 1457 return (1); 1458 } 1459 #endif 1460 return (0); 1461 } 1462 1463 int 1464 xge_setup_xgxs_herc(struct xge_softc *sc) 1465 { 1466 int dtx_cnt = 0; 1467 1468 while (herc_dtx_cfg[dtx_cnt] != END_SIGN) { 1469 PIF_WCSR(DTX_CONTROL, herc_dtx_cfg[dtx_cnt]); 1470 DELAY(100); 1471 dtx_cnt++; 1472 } 1473 1474 return (0); 1475 } 1476