1 /* $OpenBSD: if_xl_pci.c,v 1.36 2011/04/17 20:52:43 stsp Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_xl.c,v 1.72 2000/01/09 21:12:59 wpaul Exp $ 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/protosw.h> 43 #include <sys/socket.h> 44 #include <sys/ioctl.h> 45 #include <sys/errno.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_media.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_ether.h> 61 #endif 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcidevs.h> 68 69 #if NBPFILTER > 0 70 #include <net/bpf.h> 71 #endif 72 73 /* 74 * The following #define causes the code to use PIO to access the 75 * chip's registers instead of memory mapped mode. The reason PIO mode 76 * is on by default is that the Etherlink XL manual seems to indicate 77 * that only the newer revision chips (3c905B) support both PIO and 78 * memory mapped access. Since we want to be compatible with the older 79 * bus master chips, we use PIO here. If you comment this out, the 80 * driver will use memory mapped I/O, which may be faster but which 81 * might not work on some devices. 82 */ 83 #define XL_USEIOSPACE 84 85 #define XL_PCI_FUNCMEM 0x0018 86 #define XL_PCI_INTR 0x0004 87 #define XL_PCI_INTRACK 0x8000 88 89 #include <dev/ic/xlreg.h> 90 91 int xl_pci_match(struct device *, void *, void *); 92 void xl_pci_attach(struct device *, struct device *, void *); 93 int xl_pci_detach(struct device *, int); 94 void xl_pci_intr_ack(struct xl_softc *); 95 #ifndef SMALL_KERNEL 96 void xl_pci_wol_power(void *); 97 #endif 98 99 struct xl_pci_softc { 100 struct xl_softc psc_softc; 101 pci_chipset_tag_t psc_pc; 102 pcitag_t psc_tag; 103 bus_size_t psc_iosize; 104 bus_size_t psc_funsize; 105 }; 106 107 struct cfattach xl_pci_ca = { 108 sizeof(struct xl_pci_softc), xl_pci_match, xl_pci_attach, 109 xl_pci_detach, xl_activate 110 }; 111 112 const struct pci_matchid xl_pci_devices[] = { 113 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CSOHO100TX }, 114 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900TPO }, 115 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900COMBO }, 116 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900B }, 117 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900BCOMBO }, 118 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900BTPC }, 119 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900BFL }, 120 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905TX }, 121 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905T4 }, 122 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BTX }, 123 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BT4 }, 124 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BCOMBO }, 125 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BFX }, 126 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C980TX }, 127 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C980CTX }, 128 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905CTX }, 129 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C450 }, 130 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C555 }, 131 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C556 }, 132 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C556B }, 133 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C9201 }, 134 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C920BEMBW }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C575 }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFE575BT }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFE575CT }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFEM656 }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFEM656B }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFEM656C }, 141 }; 142 143 int 144 xl_pci_match(struct device *parent, void *match, void *aux) 145 { 146 return (pci_matchbyid((struct pci_attach_args *)aux, xl_pci_devices, 147 nitems(xl_pci_devices))); 148 } 149 150 void 151 xl_pci_attach(struct device *parent, struct device *self, void *aux) 152 { 153 struct xl_pci_softc *psc = (void *)self; 154 struct xl_softc *sc = &psc->psc_softc; 155 struct pci_attach_args *pa = aux; 156 pci_chipset_tag_t pc = pa->pa_pc; 157 pci_intr_handle_t ih; 158 const char *intrstr = NULL; 159 bus_size_t iosize, funsize; 160 u_int32_t command; 161 162 psc->psc_pc = pc; 163 psc->psc_tag = pa->pa_tag; 164 sc->sc_dmat = pa->pa_dmat; 165 166 sc->xl_flags = 0; 167 sc->wol_power = sc->wol_power_arg = NULL; 168 169 /* set required flags */ 170 switch (PCI_PRODUCT(pa->pa_id)) { 171 case TC_DEVICEID_HURRICANE_555: 172 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 173 break; 174 case TC_DEVICEID_HURRICANE_556: 175 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 176 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET; 177 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR|XL_FLAG_INVERT_MII_PWR; 178 sc->xl_flags |= XL_FLAG_8BITROM; 179 break; 180 case TC_DEVICEID_HURRICANE_556B: 181 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 182 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET; 183 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR|XL_FLAG_INVERT_MII_PWR; 184 break; 185 case PCI_PRODUCT_3COM_3C9201: 186 case PCI_PRODUCT_3COM_3C920BEMBW: 187 sc->xl_flags |= XL_FLAG_PHYOK; 188 break; 189 case TC_DEVICEID_BOOMERANG_10_100BT: 190 sc->xl_flags |= XL_FLAG_NO_MMIO; 191 break; 192 case PCI_PRODUCT_3COM_3C575: 193 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 194 XL_FLAG_8BITROM; 195 break; 196 case PCI_PRODUCT_3COM_3CCFE575BT: 197 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 198 XL_FLAG_8BITROM | XL_FLAG_INVERT_LED_PWR; 199 sc->xl_flags |= XL_FLAG_FUNCREG; 200 break; 201 case PCI_PRODUCT_3COM_3CCFE575CT: 202 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 203 XL_FLAG_8BITROM | XL_FLAG_INVERT_MII_PWR; 204 sc->xl_flags |= XL_FLAG_FUNCREG; 205 break; 206 case PCI_PRODUCT_3COM_3CCFEM656: 207 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 208 XL_FLAG_8BITROM | XL_FLAG_INVERT_LED_PWR | 209 XL_FLAG_INVERT_MII_PWR; 210 sc->xl_flags |= XL_FLAG_FUNCREG; 211 break; 212 case PCI_PRODUCT_3COM_3CCFEM656B: 213 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 214 XL_FLAG_8BITROM | XL_FLAG_INVERT_LED_PWR | 215 XL_FLAG_INVERT_MII_PWR; 216 sc->xl_flags |= XL_FLAG_FUNCREG; 217 break; 218 case PCI_PRODUCT_3COM_3CCFEM656C: 219 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 220 XL_FLAG_8BITROM | XL_FLAG_INVERT_MII_PWR; 221 sc->xl_flags |= XL_FLAG_FUNCREG; 222 break; 223 default: 224 break; 225 } 226 227 /* 228 * If this is a 3c905B, we have to check one extra thing. 229 * The 905B supports power management and may be placed in 230 * a low-power mode (D3 mode), typically by certain operating 231 * systems which shall not be named. The PCI BIOS is supposed 232 * to reset the NIC and bring it out of low-power mode, but 233 * some do not. Consequently, we have to see if this chip 234 * supports power management, and if so, make sure it's not 235 * in low-power mode. If power management is available, the 236 * capid byte will be 0x01. 237 * 238 * I _think_ that what actually happens is that the chip 239 * loses its PCI configuration during the transition from 240 * D3 back to D0; this means that it should be possible for 241 * us to save the PCI iobase, membase and IRQ, put the chip 242 * back in the D0 state, then restore the PCI config ourselves. 243 */ 244 command = pci_conf_read(pc, pa->pa_tag, XL_PCI_CAPID) & 0xff; 245 if (command == 0x01) { 246 247 command = pci_conf_read(pc, pa->pa_tag, 248 XL_PCI_PWRMGMTCTRL); 249 if (command & XL_PSTATE_MASK) { 250 u_int32_t io, mem, irq; 251 252 /* Save PCI config */ 253 io = pci_conf_read(pc, pa->pa_tag, XL_PCI_LOIO); 254 mem = pci_conf_read(pc, pa->pa_tag, XL_PCI_LOMEM); 255 irq = pci_conf_read(pc, pa->pa_tag, XL_PCI_INTLINE); 256 257 /* Reset the power state. */ 258 printf("%s: chip is in D%d power mode " 259 "-- setting to D0\n", 260 sc->sc_dev.dv_xname, command & XL_PSTATE_MASK); 261 command &= 0xFFFFFFFC; 262 pci_conf_write(pc, pa->pa_tag, 263 XL_PCI_PWRMGMTCTRL, command); 264 265 pci_conf_write(pc, pa->pa_tag, XL_PCI_LOIO, io); 266 pci_conf_write(pc, pa->pa_tag, XL_PCI_LOMEM, mem); 267 pci_conf_write(pc, pa->pa_tag, XL_PCI_INTLINE, irq); 268 } 269 270 #ifndef SMALL_KERNEL 271 /* The card is WOL-capable if it supports PME# assertion 272 * from D3hot power state. Install a callback to configure 273 * PCI power state for WOL. It will be invoked when the 274 * interface stops and WOL was enabled. */ 275 command = pci_conf_read(pc, pa->pa_tag, XL_PCI_PWRMGMTCAP); 276 if (command & XL_PME_CAP_D3_HOT) { 277 sc->wol_power = xl_pci_wol_power; 278 sc->wol_power_arg = psc; 279 } 280 #endif 281 } 282 283 /* 284 * Map control/status registers. 285 */ 286 #ifdef XL_USEIOSPACE 287 if (pci_mapreg_map(pa, XL_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 288 &sc->xl_btag, &sc->xl_bhandle, NULL, &iosize, 0)) { 289 printf(": can't map i/o space\n"); 290 return; 291 } 292 #else 293 if (pci_mapreg_map(pa, XL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 294 &sc->xl_btag, &sc->xl_bhandle, NULL, &iosize, 0)) { 295 printf(": can't map i/o space\n"); 296 return; 297 } 298 #endif 299 psc->psc_iosize = iosize; 300 301 if (sc->xl_flags & XL_FLAG_FUNCREG) { 302 if (pci_mapreg_map(pa, XL_PCI_FUNCMEM, PCI_MAPREG_TYPE_MEM, 0, 303 &sc->xl_funct, &sc->xl_funch, NULL, &funsize, 0)) { 304 printf(": can't map i/o space\n"); 305 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, iosize); 306 return; 307 } 308 psc->psc_funsize = funsize; 309 sc->intr_ack = xl_pci_intr_ack; 310 } 311 312 /* 313 * Allocate our interrupt. 314 */ 315 if (pci_intr_map(pa, &ih)) { 316 printf(": couldn't map interrupt\n"); 317 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, iosize); 318 if (sc->xl_flags & XL_FLAG_FUNCREG) 319 bus_space_unmap(sc->xl_funct, sc->xl_funch, funsize); 320 return; 321 } 322 323 intrstr = pci_intr_string(pc, ih); 324 sc->xl_intrhand = pci_intr_establish(pc, ih, IPL_NET, xl_intr, sc, 325 self->dv_xname); 326 if (sc->xl_intrhand == NULL) { 327 printf(": couldn't establish interrupt"); 328 if (intrstr != NULL) 329 printf(" at %s", intrstr); 330 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, iosize); 331 if (sc->xl_flags & XL_FLAG_FUNCREG) 332 bus_space_unmap(sc->xl_funct, sc->xl_funch, funsize); 333 return; 334 } 335 printf(": %s", intrstr); 336 337 xl_attach(sc); 338 } 339 340 int 341 xl_pci_detach(struct device *self, int flags) 342 { 343 struct xl_pci_softc *psc = (void *)self; 344 struct xl_softc *sc = &psc->psc_softc; 345 346 if (sc->xl_intrhand != NULL) { 347 pci_intr_disestablish(psc->psc_pc, sc->xl_intrhand); 348 xl_detach(sc); 349 } 350 if (psc->psc_iosize > 0) 351 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, psc->psc_iosize); 352 if (psc->psc_funsize > 0) 353 bus_space_unmap(sc->xl_funct, sc->xl_funch, psc->psc_funsize); 354 return (0); 355 } 356 357 void 358 xl_pci_intr_ack(struct xl_softc *sc) 359 { 360 bus_space_write_4(sc->xl_funct, sc->xl_funch, XL_PCI_INTR, 361 XL_PCI_INTRACK); 362 } 363 364 #ifndef SMALL_KERNEL 365 void 366 xl_pci_wol_power(void *ppsc) 367 { 368 u_int32_t command; 369 struct xl_pci_softc *psc = (struct xl_pci_softc*)ppsc; 370 371 /* Make sure power management is enabled, and set the card into 372 * D3hot power state so it stays active after system shutdown. */ 373 command = pci_conf_read(psc->psc_pc, psc->psc_tag, XL_PCI_PWRMGMTCTRL); 374 command |= XL_PME_EN | XL_PSTATE_D3; 375 pci_conf_write(psc->psc_pc, psc->psc_tag, XL_PCI_PWRMGMTCTRL, command); 376 } 377 #endif 378