1 /* $OpenBSD: if_xl_pci.c,v 1.25 2009/06/02 05:29:47 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_xl.c,v 1.72 2000/01/09 21:12:59 wpaul Exp $ 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/protosw.h> 43 #include <sys/socket.h> 44 #include <sys/ioctl.h> 45 #include <sys/errno.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 49 #include <sys/device.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_types.h> 54 #include <net/if_media.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_ether.h> 62 #endif 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 /* 75 * The following #define causes the code to use PIO to access the 76 * chip's registers instead of memory mapped mode. The reason PIO mode 77 * is on by default is that the Etherlink XL manual seems to indicate 78 * that only the newer revision chips (3c905B) support both PIO and 79 * memory mapped access. Since we want to be compatible with the older 80 * bus master chips, we use PIO here. If you comment this out, the 81 * driver will use memory mapped I/O, which may be faster but which 82 * might not work on some devices. 83 */ 84 #define XL_USEIOSPACE 85 86 #define XL_PCI_FUNCMEM 0x0018 87 #define XL_PCI_INTR 0x0004 88 #define XL_PCI_INTRACK 0x8000 89 90 #include <dev/ic/xlreg.h> 91 92 int xl_pci_match(struct device *, void *, void *); 93 void xl_pci_attach(struct device *, struct device *, void *); 94 int xl_pci_detach(struct device *, int); 95 void xl_pci_intr_ack(struct xl_softc *); 96 97 struct xl_pci_softc { 98 struct xl_softc psc_softc; 99 pci_chipset_tag_t psc_pc; 100 bus_size_t psc_iosize; 101 }; 102 103 struct cfattach xl_pci_ca = { 104 sizeof(struct xl_pci_softc), xl_pci_match, xl_pci_attach, xl_pci_detach 105 }; 106 107 const struct pci_matchid xl_pci_devices[] = { 108 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CSOHO100TX }, 109 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900TPO }, 110 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900COMBO }, 111 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900B }, 112 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900BCOMBO }, 113 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900BTPC }, 114 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900BFL }, 115 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905TX }, 116 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905T4 }, 117 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BTX }, 118 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BT4 }, 119 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BCOMBO }, 120 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BFX }, 121 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C980TX }, 122 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C980CTX }, 123 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905CTX }, 124 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C450 }, 125 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C555 }, 126 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C556 }, 127 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C556B }, 128 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C9201 }, 129 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C920BEMBW }, 130 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C575 }, 131 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFE575BT }, 132 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFE575CT }, 133 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFEM656 }, 134 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFEM656B }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFEM656C }, 136 }; 137 138 int 139 xl_pci_match(struct device *parent, void *match, void *aux) 140 { 141 return (pci_matchbyid((struct pci_attach_args *)aux, xl_pci_devices, 142 sizeof(xl_pci_devices)/sizeof(xl_pci_devices[0]))); 143 } 144 145 void 146 xl_pci_attach(struct device *parent, struct device *self, void *aux) 147 { 148 struct xl_pci_softc *psc = (void *)self; 149 struct xl_softc *sc = &psc->psc_softc; 150 struct pci_attach_args *pa = aux; 151 pci_chipset_tag_t pc = pa->pa_pc; 152 pci_intr_handle_t ih; 153 const char *intrstr = NULL; 154 bus_size_t iosize, funsize; 155 u_int32_t command; 156 157 psc->psc_pc = pc; 158 sc->sc_dmat = pa->pa_dmat; 159 160 sc->xl_flags = 0; 161 162 /* set required flags */ 163 switch (PCI_PRODUCT(pa->pa_id)) { 164 case TC_DEVICEID_HURRICANE_555: 165 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 166 break; 167 case TC_DEVICEID_HURRICANE_556: 168 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 169 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET; 170 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR|XL_FLAG_INVERT_MII_PWR; 171 sc->xl_flags |= XL_FLAG_8BITROM; 172 break; 173 case TC_DEVICEID_HURRICANE_556B: 174 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 175 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET; 176 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR|XL_FLAG_INVERT_MII_PWR; 177 break; 178 case PCI_PRODUCT_3COM_3C9201: 179 case PCI_PRODUCT_3COM_3C920BEMBW: 180 sc->xl_flags |= XL_FLAG_PHYOK; 181 break; 182 case TC_DEVICEID_BOOMERANG_10_100BT: 183 sc->xl_flags |= XL_FLAG_NO_MMIO; 184 break; 185 case PCI_PRODUCT_3COM_3C575: 186 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 187 XL_FLAG_8BITROM; 188 break; 189 case PCI_PRODUCT_3COM_3CCFE575BT: 190 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 191 XL_FLAG_8BITROM | XL_FLAG_INVERT_LED_PWR; 192 break; 193 case PCI_PRODUCT_3COM_3CCFE575CT: 194 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 195 XL_FLAG_8BITROM | XL_FLAG_INVERT_MII_PWR; 196 break; 197 case PCI_PRODUCT_3COM_3CCFEM656: 198 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 199 XL_FLAG_8BITROM | XL_FLAG_INVERT_LED_PWR | 200 XL_FLAG_INVERT_MII_PWR; 201 break; 202 case PCI_PRODUCT_3COM_3CCFEM656B: 203 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 204 XL_FLAG_8BITROM | XL_FLAG_INVERT_LED_PWR | 205 XL_FLAG_INVERT_MII_PWR; 206 break; 207 case PCI_PRODUCT_3COM_3CCFEM656C: 208 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 209 XL_FLAG_8BITROM | XL_FLAG_INVERT_MII_PWR; 210 break; 211 default: 212 break; 213 } 214 215 /* 216 * If this is a 3c905B, we have to check one extra thing. 217 * The 905B supports power management and may be placed in 218 * a low-power mode (D3 mode), typically by certain operating 219 * systems which shall not be named. The PCI BIOS is supposed 220 * to reset the NIC and bring it out of low-power mode, but 221 * some do not. Consequently, we have to see if this chip 222 * supports power management, and if so, make sure it's not 223 * in low-power mode. If power management is available, the 224 * capid byte will be 0x01. 225 * 226 * I _think_ that what actually happens is that the chip 227 * loses its PCI configuration during the transition from 228 * D3 back to D0; this means that it should be possible for 229 * us to save the PCI iobase, membase and IRQ, put the chip 230 * back in the D0 state, then restore the PCI config ourselves. 231 */ 232 command = pci_conf_read(pc, pa->pa_tag, XL_PCI_CAPID) & 0xff; 233 if (command == 0x01) { 234 235 command = pci_conf_read(pc, pa->pa_tag, 236 XL_PCI_PWRMGMTCTRL); 237 if (command & XL_PSTATE_MASK) { 238 u_int32_t io, mem, irq; 239 240 /* Save PCI config */ 241 io = pci_conf_read(pc, pa->pa_tag, XL_PCI_LOIO); 242 mem = pci_conf_read(pc, pa->pa_tag, XL_PCI_LOMEM); 243 irq = pci_conf_read(pc, pa->pa_tag, XL_PCI_INTLINE); 244 245 /* Reset the power state. */ 246 printf("%s: chip is in D%d power mode " 247 "-- setting to D0\n", 248 sc->sc_dev.dv_xname, command & XL_PSTATE_MASK); 249 command &= 0xFFFFFFFC; 250 pci_conf_write(pc, pa->pa_tag, 251 XL_PCI_PWRMGMTCTRL, command); 252 253 pci_conf_write(pc, pa->pa_tag, XL_PCI_LOIO, io); 254 pci_conf_write(pc, pa->pa_tag, XL_PCI_LOMEM, mem); 255 pci_conf_write(pc, pa->pa_tag, XL_PCI_INTLINE, irq); 256 } 257 } 258 259 /* 260 * Map control/status registers. 261 */ 262 #ifdef XL_USEIOSPACE 263 if (pci_mapreg_map(pa, XL_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 264 &sc->xl_btag, &sc->xl_bhandle, NULL, &iosize, 0)) { 265 printf(": can't map i/o space\n"); 266 return; 267 } 268 #else 269 if (pci_mapreg_map(pa, XL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 270 &sc->xl_btag, &sc->xl_bhandle, NULL, &iosize, 0)) { 271 printf(": can't map i/o space\n"); 272 return; 273 } 274 #endif 275 276 if (sc->xl_flags & XL_FLAG_FUNCREG) { 277 if (pci_mapreg_map(pa, XL_PCI_FUNCMEM, PCI_MAPREG_TYPE_MEM, 0, 278 &sc->xl_funct, &sc->xl_funch, NULL, &funsize, 0)) { 279 printf(": can't map i/o space\n"); 280 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, iosize); 281 return; 282 } 283 sc->intr_ack = xl_pci_intr_ack; 284 } 285 286 /* 287 * Allocate our interrupt. 288 */ 289 if (pci_intr_map(pa, &ih)) { 290 printf(": couldn't map interrupt\n"); 291 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, iosize); 292 if (sc->xl_flags & XL_FLAG_FUNCREG) 293 bus_space_unmap(sc->xl_funct, sc->xl_funch, funsize); 294 return; 295 } 296 297 intrstr = pci_intr_string(pc, ih); 298 sc->xl_intrhand = pci_intr_establish(pc, ih, IPL_NET, xl_intr, sc, 299 self->dv_xname); 300 if (sc->xl_intrhand == NULL) { 301 printf(": couldn't establish interrupt"); 302 if (intrstr != NULL) 303 printf(" at %s", intrstr); 304 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, iosize); 305 if (sc->xl_flags & XL_FLAG_FUNCREG) 306 bus_space_unmap(sc->xl_funct, sc->xl_funch, funsize); 307 return; 308 } 309 psc->psc_iosize = iosize; 310 printf(": %s", intrstr); 311 312 xl_attach(sc); 313 } 314 315 int 316 xl_pci_detach(struct device *self, int flags) 317 { 318 struct xl_pci_softc *psc = (void *)self; 319 struct xl_softc *sc = &psc->psc_softc; 320 int rv = 0; 321 322 rv = xl_detach(sc); 323 if (rv == 0) { 324 pci_intr_disestablish(psc->psc_pc, sc->xl_intrhand); 325 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, psc->psc_iosize); 326 } 327 328 return (rv); 329 } 330 331 void 332 xl_pci_intr_ack(struct xl_softc *sc) 333 { 334 bus_space_write_4(sc->xl_funct, sc->xl_funch, XL_PCI_INTR, 335 XL_PCI_INTRACK); 336 } 337