1 /* $OpenBSD: igc_hw.h,v 1.1 2021/10/31 14:52:57 patrick Exp $ */ 2 /*- 3 * Copyright 2021 Intel Corp 4 * Copyright 2021 Rubicon Communications, LLC (Netgate) 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * $FreeBSD$ 8 */ 9 10 #ifndef _IGC_HW_H_ 11 #define _IGC_HW_H_ 12 13 #include "bpfilter.h" 14 #include "vlan.h" 15 16 #include <sys/param.h> 17 #include <sys/systm.h> 18 #include <sys/sockio.h> 19 #include <sys/mbuf.h> 20 #include <sys/malloc.h> 21 #include <sys/kernel.h> 22 #include <sys/socket.h> 23 #include <sys/device.h> 24 #include <sys/endian.h> 25 #include <sys/intrmap.h> 26 27 #include <net/if.h> 28 #include <net/if_media.h> 29 #include <net/toeplitz.h> 30 31 #include <netinet/in.h> 32 #include <netinet/if_ether.h> 33 34 #if NBPFILTER > 0 35 #include <net/bpf.h> 36 #endif 37 38 #include <machine/bus.h> 39 #include <machine/intr.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcidevs.h> 44 45 #include <dev/pci/igc_base.h> 46 #include <dev/pci/igc_defines.h> 47 #include <dev/pci/igc_i225.h> 48 #include <dev/pci/igc_mac.h> 49 #include <dev/pci/igc_nvm.h> 50 #include <dev/pci/igc_phy.h> 51 #include <dev/pci/igc_regs.h> 52 53 #if 0 54 /* Enable/disable debugging statements in shared code */ 55 #define DBG 0 56 57 #define DEBUGOUT(...) \ 58 do { if (DBG) printf(__VA_ARGS__); } while (0) 59 #define DEBUGOUT1(...) DEBUGOUT(__VA_ARGS__) 60 #define DEBUGOUT2(...) DEBUGOUT(__VA_ARGS__) 61 #define DEBUGOUT3(...) DEBUGOUT(__VA_ARGS__) 62 #define DEBUGOUT7(...) DEBUGOUT(__VA_ARGS__) 63 #define DEBUGFUNC(F) DEBUGOUT(F "\n") 64 #endif 65 66 struct igc_hw; 67 68 #define IGC_FUNC_1 1 69 70 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0 71 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3 72 73 enum igc_mac_type { 74 igc_undefined = 0, 75 igc_i225, 76 igc_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 77 }; 78 79 enum igc_media_type { 80 igc_media_type_unknown = 0, 81 igc_media_type_copper = 1, 82 igc_num_media_types 83 }; 84 85 enum igc_nvm_type { 86 igc_nvm_unknown = 0, 87 igc_nvm_eeprom_spi, 88 igc_nvm_flash_hw, 89 igc_nvm_invm 90 }; 91 92 enum igc_phy_type { 93 igc_phy_unknown = 0, 94 igc_phy_none, 95 igc_phy_i225 96 }; 97 98 enum igc_bus_type { 99 igc_bus_type_unknown = 0, 100 igc_bus_type_pci, 101 igc_bus_type_pcix, 102 igc_bus_type_pci_express, 103 igc_bus_type_reserved 104 }; 105 106 enum igc_bus_speed { 107 igc_bus_speed_unknown = 0, 108 igc_bus_speed_33, 109 igc_bus_speed_66, 110 igc_bus_speed_100, 111 igc_bus_speed_120, 112 igc_bus_speed_133, 113 igc_bus_speed_2500, 114 igc_bus_speed_5000, 115 igc_bus_speed_reserved 116 }; 117 118 enum igc_bus_width { 119 igc_bus_width_unknown = 0, 120 igc_bus_width_pcie_x1, 121 igc_bus_width_pcie_x2, 122 igc_bus_width_pcie_x4 = 4, 123 igc_bus_width_pcie_x8 = 8, 124 igc_bus_width_32, 125 igc_bus_width_64, 126 igc_bus_width_reserved 127 }; 128 129 enum igc_fc_mode { 130 igc_fc_none = 0, 131 igc_fc_rx_pause, 132 igc_fc_tx_pause, 133 igc_fc_full, 134 igc_fc_default = 0xFF 135 }; 136 137 enum igc_ms_type { 138 igc_ms_hw_default = 0, 139 igc_ms_force_master, 140 igc_ms_force_slave, 141 igc_ms_auto 142 }; 143 144 enum igc_smart_speed { 145 igc_smart_speed_default = 0, 146 igc_smart_speed_on, 147 igc_smart_speed_off 148 }; 149 150 /* Receive Descriptor */ 151 struct igc_rx_desc { 152 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 153 uint64_t length; /* Length of data DMAed into data buffer */ 154 uint16_t csum; /* Packet checksum */ 155 uint8_t status; /* Descriptor status */ 156 uint8_t errors; /* Descriptor errors */ 157 uint16_t special; 158 }; 159 160 /* Receive Descriptor - Extended */ 161 union igc_rx_desc_extended { 162 struct { 163 uint64_t buffer_addr; 164 uint64_t reserved; 165 } read; 166 struct { 167 struct { 168 uint32_t mrq; /* Multiple Rx queues */ 169 union { 170 uint32_t rss; /* RSS hash */ 171 struct { 172 uint16_t ip_id; /* IP id */ 173 uint16_t csum; /* Packet checksum */ 174 } csum_ip; 175 } hi_dword; 176 } lower; 177 struct { 178 uint32_t status_error; /* ext status/error */ 179 uint16_t length; 180 uint16_t vlan; /* VLAN tag */ 181 } upper; 182 } wb; /* writeback */ 183 }; 184 185 /* Transmit Descriptor */ 186 struct igc_tx_desc { 187 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 188 union { 189 uint32_t data; 190 struct { 191 uint16_t length; /* Data buffer length */ 192 uint8_t cso; /* Checksum offset */ 193 uint8_t cmd; /* Descriptor control */ 194 } flags; 195 } lower; 196 union { 197 uint32_t data; 198 struct { 199 uint8_t status; /* Descriptor status */ 200 uint8_t css; /* Checksum start */ 201 uint16_t special; 202 } fields; 203 } upper; 204 }; 205 206 /* Function pointers for the MAC. */ 207 struct igc_mac_operations { 208 int (*init_params)(struct igc_hw *); 209 int (*check_for_link)(struct igc_hw *); 210 void (*clear_hw_cntrs)(struct igc_hw *); 211 void (*clear_vfta)(struct igc_hw *); 212 int (*get_bus_info)(struct igc_hw *); 213 void (*set_lan_id)(struct igc_hw *); 214 int (*get_link_up_info)(struct igc_hw *, uint16_t *, uint16_t *); 215 void (*update_mc_addr_list)(struct igc_hw *, uint8_t *, uint32_t); 216 int (*reset_hw)(struct igc_hw *); 217 int (*init_hw)(struct igc_hw *); 218 int (*setup_link)(struct igc_hw *); 219 int (*setup_physical_interface)(struct igc_hw *); 220 void (*write_vfta)(struct igc_hw *, uint32_t, uint32_t); 221 void (*config_collision_dist)(struct igc_hw *); 222 int (*rar_set)(struct igc_hw *, uint8_t *, uint32_t); 223 int (*read_mac_addr)(struct igc_hw *); 224 int (*validate_mdi_setting)(struct igc_hw *); 225 int (*acquire_swfw_sync)(struct igc_hw *, uint16_t); 226 void (*release_swfw_sync)(struct igc_hw *, uint16_t); 227 }; 228 229 /* When to use various PHY register access functions: 230 * 231 * Func Caller 232 * Function Does Does When to use 233 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 234 * X_reg L,P,A n/a for simple PHY reg accesses 235 * X_reg_locked P,A L for multiple accesses of different regs 236 * on different pages 237 * X_reg_page A L,P for multiple accesses of different regs 238 * on the same page 239 * 240 * Where X=[read|write], L=locking, P=sets page, A=register access 241 * 242 */ 243 struct igc_phy_operations { 244 int (*init_params)(struct igc_hw *); 245 int (*acquire)(struct igc_hw *); 246 int (*check_reset_block)(struct igc_hw *); 247 int (*commit)(struct igc_hw *); 248 int (*force_speed_duplex)(struct igc_hw *); 249 int (*get_info)(struct igc_hw *); 250 int (*set_page)(struct igc_hw *, uint16_t); 251 int (*read_reg)(struct igc_hw *, uint32_t, uint16_t *); 252 int (*read_reg_locked)(struct igc_hw *, uint32_t, uint16_t *); 253 int (*read_reg_page)(struct igc_hw *, uint32_t, uint16_t *); 254 void (*release)(struct igc_hw *); 255 int (*reset)(struct igc_hw *); 256 int (*set_d0_lplu_state)(struct igc_hw *, bool); 257 int (*set_d3_lplu_state)(struct igc_hw *, bool); 258 int (*write_reg)(struct igc_hw *, uint32_t, uint16_t); 259 int (*write_reg_locked)(struct igc_hw *, uint32_t, uint16_t); 260 int (*write_reg_page)(struct igc_hw *, uint32_t, uint16_t); 261 void (*power_up)(struct igc_hw *); 262 void (*power_down)(struct igc_hw *); 263 }; 264 265 /* Function pointers for the NVM. */ 266 struct igc_nvm_operations { 267 int (*init_params)(struct igc_hw *); 268 int (*acquire)(struct igc_hw *); 269 int (*read)(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 270 void (*release)(struct igc_hw *); 271 void (*reload)(struct igc_hw *); 272 int (*update)(struct igc_hw *); 273 int (*validate)(struct igc_hw *); 274 int (*write)(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 275 }; 276 277 struct igc_info { 278 int (*get_invariants)(struct igc_hw *hw); 279 struct igc_mac_operations *mac_ops; 280 const struct igc_phy_operations *phy_ops; 281 struct igc_nvm_operations *nvm_ops; 282 }; 283 284 extern const struct igc_info igc_i225_info; 285 286 struct igc_mac_info { 287 struct igc_mac_operations ops; 288 uint8_t addr[ETHER_ADDR_LEN]; 289 uint8_t perm_addr[ETHER_ADDR_LEN]; 290 291 enum igc_mac_type type; 292 293 uint32_t mc_filter_type; 294 295 uint16_t current_ifs_val; 296 uint16_t ifs_max_val; 297 uint16_t ifs_min_val; 298 uint16_t ifs_ratio; 299 uint16_t ifs_step_size; 300 uint16_t mta_reg_count; 301 uint16_t uta_reg_count; 302 303 /* Maximum size of the MTA register table in all supported adapters */ 304 #define MAX_MTA_REG 128 305 uint32_t mta_shadow[MAX_MTA_REG]; 306 uint16_t rar_entry_count; 307 308 uint8_t forced_speed_duplex; 309 310 bool asf_firmware_present; 311 bool autoneg; 312 bool get_link_status; 313 uint32_t max_frame_size; 314 }; 315 316 struct igc_phy_info { 317 struct igc_phy_operations ops; 318 enum igc_phy_type type; 319 320 enum igc_smart_speed smart_speed; 321 322 uint32_t addr; 323 uint32_t id; 324 uint32_t reset_delay_us; /* in usec */ 325 uint32_t revision; 326 327 enum igc_media_type media_type; 328 329 uint16_t autoneg_advertised; 330 uint16_t autoneg_mask; 331 332 uint8_t mdix; 333 334 bool polarity_correction; 335 bool speed_downgraded; 336 bool autoneg_wait_to_complete; 337 }; 338 339 struct igc_nvm_info { 340 struct igc_nvm_operations ops; 341 enum igc_nvm_type type; 342 343 uint16_t word_size; 344 uint16_t delay_usec; 345 uint16_t address_bits; 346 uint16_t opcode_bits; 347 uint16_t page_size; 348 }; 349 350 struct igc_bus_info { 351 enum igc_bus_type type; 352 enum igc_bus_speed speed; 353 enum igc_bus_width width; 354 355 uint16_t func; 356 uint16_t pci_cmd_word; 357 }; 358 359 struct igc_fc_info { 360 uint32_t high_water; 361 uint32_t low_water; 362 uint16_t pause_time; 363 uint16_t refresh_time; 364 bool send_xon; 365 bool strict_ieee; 366 enum igc_fc_mode current_mode; 367 enum igc_fc_mode requested_mode; 368 }; 369 370 struct igc_dev_spec_i225 { 371 bool eee_disable; 372 bool clear_semaphore_once; 373 uint32_t mtu; 374 }; 375 376 struct igc_hw { 377 void *back; 378 379 uint8_t *hw_addr; 380 381 struct igc_mac_info mac; 382 struct igc_fc_info fc; 383 struct igc_phy_info phy; 384 struct igc_nvm_info nvm; 385 struct igc_bus_info bus; 386 387 union { 388 struct igc_dev_spec_i225 _i225; 389 } dev_spec; 390 391 uint16_t device_id; 392 }; 393 394 #endif /* _IGC_HW_H_ */ 395