1 /* $OpenBSD: igc_i225.h,v 1.1 2021/10/31 14:52:57 patrick Exp $ */ 2 /*- 3 * Copyright 2021 Intel Corp 4 * Copyright 2021 Rubicon Communications, LLC (Netgate) 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * $FreeBSD$ 8 */ 9 10 #ifndef _IGC_I225_H_ 11 #define _IGC_I225_H_ 12 13 #include <dev/pci/igc_hw.h> 14 15 bool igc_get_flash_presence_i225(struct igc_hw *); 16 int igc_update_flash_i225(struct igc_hw *); 17 int igc_update_nvm_checksum_i225(struct igc_hw *); 18 int igc_validate_nvm_checksum_i225(struct igc_hw *); 19 int igc_write_nvm_srwr_i225(struct igc_hw *, uint16_t, uint16_t, 20 uint16_t *); 21 int igc_read_nvm_srrd_i225(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 22 int igc_set_flsw_flash_burst_counter_i225(struct igc_hw *, uint32_t); 23 int igc_write_erase_flash_command_i225(struct igc_hw *, uint32_t, uint32_t); 24 int igc_check_for_link_i225(struct igc_hw *); 25 int igc_acquire_swfw_sync_i225(struct igc_hw *, uint16_t); 26 void igc_release_swfw_sync_i225(struct igc_hw *, uint16_t); 27 int igc_set_ltr_i225(struct igc_hw *, bool); 28 int igc_init_hw_i225(struct igc_hw *); 29 int igc_setup_copper_link_i225(struct igc_hw *); 30 int igc_set_d0_lplu_state_i225(struct igc_hw *, bool); 31 int igc_set_d3_lplu_state_i225(struct igc_hw *, bool); 32 int igc_set_eee_i225(struct igc_hw *, bool, bool, bool); 33 34 #define ID_LED_DEFAULT_I225 \ 35 ((ID_LED_OFF1_ON2 << 8) | (ID_LED_DEF1_DEF2 << 4) | (ID_LED_OFF1_OFF2)) 36 37 #define ID_LED_DEFAULT_I225_SERDES \ 38 ((ID_LED_DEF1_DEF2 << 8) | (ID_LED_DEF1_DEF2 << 4) | (ID_LED_OFF1_ON2)) 39 40 /* NVM offset defaults for I225 devices */ 41 #define NVM_INIT_CTRL_2_DEFAULT_I225 0x7243 42 #define NVM_INIT_CTRL_4_DEFAULT_I225 0x00C1 43 #define NVM_LED_1_CFG_DEFAULT_I225 0x0184 44 #define NVM_LED_0_2_CFG_DEFAULT_I225 0x200C 45 46 #define IGC_MRQC_ENABLE_RSS_4Q 0x00000002 47 #define IGC_MRQC_ENABLE_VMDQ 0x00000003 48 #define IGC_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 49 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 50 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 51 #define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 52 #define IGC_I225_SHADOW_RAM_SIZE 4096 53 #define IGC_I225_ERASE_CMD_OPCODE 0x02000000 54 #define IGC_I225_WRITE_CMD_OPCODE 0x01000000 55 #define IGC_FLSWCTL_DONE 0x40000000 56 #define IGC_FLSWCTL_CMDV 0x10000000 57 58 /* SRRCTL bit definitions */ 59 #define IGC_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 60 #define IGC_SRRCTL_DESCTYPE_LEGACY 0x00000000 61 #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 62 #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 63 #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 64 #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 65 #define IGC_SRRCTL_DESCTYPE_MASK 0x0E000000 66 #define IGC_SRRCTL_DROP_EN 0x80000000 67 #define IGC_SRRCTL_BSIZEPKT_MASK 0x0000007F 68 #define IGC_SRRCTL_BSIZEHDR_MASK 0x00003F00 69 70 #define IGC_RXDADV_RSSTYPE_MASK 0x0000000F 71 #define IGC_RXDADV_RSSTYPE_SHIFT 12 72 #define IGC_RXDADV_HDRBUFLEN_MASK 0x7FE0 73 #define IGC_RXDADV_HDRBUFLEN_SHIFT 5 74 #define IGC_RXDADV_SPLITHEADER_EN 0x00001000 75 #define IGC_RXDADV_SPH 0x8000 76 #define IGC_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 77 #define IGC_RXDADV_ERR_HBO 0x00800000 78 79 /* RSS Hash results */ 80 #define IGC_RXDADV_RSSTYPE_NONE 0x00000000 81 #define IGC_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 82 #define IGC_RXDADV_RSSTYPE_IPV4 0x00000002 83 #define IGC_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 84 #define IGC_RXDADV_RSSTYPE_IPV6_EX 0x00000004 85 #define IGC_RXDADV_RSSTYPE_IPV6 0x00000005 86 #define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 87 #define IGC_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 88 #define IGC_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 89 #define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 90 91 /* RSS Packet Types as indicated in the receive descriptor */ 92 #define IGC_RXDADV_PKTTYPE_ILMASK 0x000000F0 93 #define IGC_RXDADV_PKTTYPE_TLMASK 0x00000F00 94 #define IGC_RXDADV_PKTTYPE_NONE 0x00000000 95 #define IGC_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ 96 #define IGC_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ 97 #define IGC_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ 98 #define IGC_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ 99 #define IGC_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 100 #define IGC_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 101 #define IGC_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 102 #define IGC_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 103 104 #define IGC_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 105 #define IGC_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 106 #define IGC_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 107 #define IGC_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 108 #define IGC_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 109 #define IGC_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 110 111 #endif /* _IGC_I225_H_ */ 112