1 /* $OpenBSD: ixgbe_phy.c,v 1.19 2016/11/18 12:36:41 mikeb Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2015, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 303032 2016-07-19 17:31:48Z sbruno $*/ 36 37 #include <dev/pci/ixgbe.h> 38 39 void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 int32_t ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, uint8_t *data); 42 int32_t ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, uint8_t data); 43 int32_t ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl); 47 void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl); 48 int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, bool data); 49 bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl); 50 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 54 * @hw: pointer to the hardware structure 55 * @byte: byte to send 56 * 57 * Returns an error code on error. 58 */ 59 static int32_t ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, uint8_t byte) 60 { 61 int32_t status; 62 63 status = ixgbe_clock_out_i2c_byte(hw, byte); 64 if (status) 65 return status; 66 return ixgbe_get_i2c_ack(hw); 67 } 68 69 /** 70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 71 * @hw: pointer to the hardware structure 72 * @byte: pointer to a uint8_t to receive the byte 73 * 74 * Returns an error code on error. 75 */ 76 static int32_t ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, uint8_t *byte) 77 { 78 int32_t status; 79 80 status = ixgbe_clock_in_i2c_byte(hw, byte); 81 if (status) 82 return status; 83 /* ACK */ 84 return ixgbe_clock_out_i2c_bit(hw, FALSE); 85 } 86 87 /** 88 * ixgbe_ones_comp_byte_add - Perform one's complement addition 89 * @add1 - addend 1 90 * @add2 - addend 2 91 * 92 * Returns one's complement 8-bit sum. 93 */ 94 static uint8_t ixgbe_ones_comp_byte_add(uint8_t add1, uint8_t add2) 95 { 96 uint16_t sum = add1 + add2; 97 98 sum = (sum & 0xFF) + (sum >> 8); 99 return sum & 0xFF; 100 } 101 102 /** 103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 104 * @hw: pointer to the hardware structure 105 * @addr: I2C bus address to read from 106 * @reg: I2C device register to read from 107 * @val: pointer to location to receive read value 108 * @lock: TRUE if to take and release semaphore 109 * 110 * Returns an error code on error. 111 */ 112 int32_t ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, uint8_t addr, 113 uint16_t reg, uint16_t *val, 114 bool lock) 115 { 116 uint32_t swfw_mask = hw->phy.phy_semaphore_mask; 117 int max_retry = 10; 118 int retry = 0; 119 uint8_t csum_byte; 120 uint8_t high_bits; 121 uint8_t low_bits; 122 uint8_t reg_high; 123 uint8_t csum; 124 125 if (hw->mac.type >= ixgbe_mac_X550) 126 max_retry = 3; 127 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 128 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 129 csum = ~csum; 130 do { 131 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 132 return IXGBE_ERR_SWFW_SYNC; 133 ixgbe_i2c_start(hw); 134 /* Device Address and write indication */ 135 if (ixgbe_out_i2c_byte_ack(hw, addr)) 136 goto fail; 137 /* Write bits 14:8 */ 138 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 139 goto fail; 140 /* Write bits 7:0 */ 141 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 142 goto fail; 143 /* Write csum */ 144 if (ixgbe_out_i2c_byte_ack(hw, csum)) 145 goto fail; 146 /* Re-start condition */ 147 ixgbe_i2c_start(hw); 148 /* Device Address and read indication */ 149 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 150 goto fail; 151 /* Get upper bits */ 152 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 153 goto fail; 154 /* Get low bits */ 155 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 156 goto fail; 157 /* Get csum */ 158 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 159 goto fail; 160 /* NACK */ 161 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 162 goto fail; 163 ixgbe_i2c_stop(hw); 164 if (lock) 165 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 166 *val = (high_bits << 8) | low_bits; 167 return 0; 168 169 fail: 170 ixgbe_i2c_bus_clear(hw); 171 if (lock) 172 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 173 retry++; 174 if (retry < max_retry) 175 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 176 else 177 DEBUGOUT("I2C byte read combined error.\n"); 178 } while (retry < max_retry); 179 180 return IXGBE_ERR_I2C; 181 } 182 183 /** 184 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 185 * @hw: pointer to the hardware structure 186 * @addr: I2C bus address to read from 187 * @reg: I2C device register to read from 188 * @val: pointer to location to receive read value 189 * 190 * Returns an error code on error. 191 **/ 192 int32_t ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, uint8_t addr, 193 uint16_t reg, uint16_t *val) 194 { 195 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 196 } 197 198 /** 199 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 200 * @hw: pointer to the hardware structure 201 * @addr: I2C bus address to read from 202 * @reg: I2C device register to read from 203 * @val: pointer to location to receive read value 204 * 205 * Returns an error code on error. 206 **/ 207 int32_t ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, uint8_t addr, 208 uint16_t reg, uint16_t *val) 209 { 210 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 211 } 212 213 /** 214 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 215 * @hw: pointer to the hardware structure 216 * @addr: I2C bus address to write to 217 * @reg: I2C device register to write to 218 * @val: value to write 219 * @lock: TRUE if to take and release semaphore 220 * 221 * Returns an error code on error. 222 */ 223 int32_t ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, uint8_t addr, 224 uint16_t reg, uint16_t val, bool lock) 225 { 226 uint32_t swfw_mask = hw->phy.phy_semaphore_mask; 227 int max_retry = 1; 228 int retry = 0; 229 uint8_t reg_high; 230 uint8_t csum; 231 232 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 233 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 234 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 235 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 236 csum = ~csum; 237 do { 238 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 239 return IXGBE_ERR_SWFW_SYNC; 240 ixgbe_i2c_start(hw); 241 /* Device Address and write indication */ 242 if (ixgbe_out_i2c_byte_ack(hw, addr)) 243 goto fail; 244 /* Write bits 14:8 */ 245 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 246 goto fail; 247 /* Write bits 7:0 */ 248 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 249 goto fail; 250 /* Write data 15:8 */ 251 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 252 goto fail; 253 /* Write data 7:0 */ 254 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 255 goto fail; 256 /* Write csum */ 257 if (ixgbe_out_i2c_byte_ack(hw, csum)) 258 goto fail; 259 ixgbe_i2c_stop(hw); 260 if (lock) 261 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 262 return 0; 263 264 fail: 265 ixgbe_i2c_bus_clear(hw); 266 if (lock) 267 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 268 retry++; 269 if (retry < max_retry) 270 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 271 else 272 DEBUGOUT("I2C byte write combined error.\n"); 273 } while (retry < max_retry); 274 275 return IXGBE_ERR_I2C; 276 } 277 278 /** 279 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 280 * @hw: pointer to the hardware structure 281 * @addr: I2C bus address to write to 282 * @reg: I2C device register to write to 283 * @val: value to write 284 * 285 * Returns an error code on error. 286 **/ 287 int32_t ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 288 uint8_t addr, uint16_t reg, uint16_t val) 289 { 290 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 291 } 292 293 /** 294 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 295 * @hw: pointer to the hardware structure 296 * @addr: I2C bus address to write to 297 * @reg: I2C device register to write to 298 * @val: value to write 299 * 300 * Returns an error code on error. 301 **/ 302 int32_t 303 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 304 uint8_t addr, uint16_t reg, uint16_t val) 305 { 306 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 307 } 308 309 /** 310 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 311 * @hw: pointer to the hardware structure 312 * 313 * Initialize the function pointers. 314 **/ 315 int32_t ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 316 { 317 struct ixgbe_phy_info *phy = &hw->phy; 318 319 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 320 321 /* PHY */ 322 phy->ops.identify = ixgbe_identify_phy_generic; 323 phy->ops.reset = ixgbe_reset_phy_generic; 324 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 325 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 326 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 327 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 328 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 329 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 330 phy->ops.check_link = NULL; 331 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 332 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 333 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 334 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 335 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 336 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 337 phy->ops.identify_sfp = ixgbe_identify_module_generic; 338 phy->sfp_type = ixgbe_sfp_type_unknown; 339 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic; 340 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic; 341 phy->ops.read_i2c_combined_unlocked = 342 ixgbe_read_i2c_combined_generic_unlocked; 343 phy->ops.write_i2c_combined_unlocked = 344 ixgbe_write_i2c_combined_generic_unlocked; 345 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 346 phy->ops.write_i2c_byte_unlocked = 347 ixgbe_write_i2c_byte_generic_unlocked; 348 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 349 return IXGBE_SUCCESS; 350 } 351 352 /** 353 * ixgbe_identify_phy_generic - Get physical layer module 354 * @hw: pointer to hardware structure 355 * 356 * Determines the physical layer module found on the current adapter. 357 **/ 358 int32_t ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 359 { 360 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 361 uint32_t phy_addr; 362 uint16_t ext_ability = 0; 363 364 DEBUGFUNC("ixgbe_identify_phy_generic"); 365 366 if (!hw->phy.phy_semaphore_mask) { 367 if (hw->bus.lan_id) 368 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 369 else 370 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 371 } 372 373 if (hw->phy.type == ixgbe_phy_unknown) { 374 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 375 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 376 hw->phy.addr = phy_addr; 377 ixgbe_get_phy_id(hw); 378 hw->phy.type = 379 ixgbe_get_phy_type_from_id(hw->phy.id); 380 381 if (hw->phy.type == ixgbe_phy_unknown) { 382 hw->phy.ops.read_reg(hw, 383 IXGBE_MDIO_PHY_EXT_ABILITY, 384 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 385 &ext_ability); 386 if (ext_ability & 387 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 388 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 389 hw->phy.type = 390 ixgbe_phy_cu_unknown; 391 else 392 hw->phy.type = 393 ixgbe_phy_generic; 394 } 395 396 status = IXGBE_SUCCESS; 397 break; 398 } 399 } 400 401 /* Certain media types do not have a phy so an address will not 402 * be found and the code will take this path. Caller has to 403 * decide if it is an error or not. 404 */ 405 if (status != IXGBE_SUCCESS) { 406 hw->phy.addr = 0; 407 } 408 } else { 409 status = IXGBE_SUCCESS; 410 } 411 412 return status; 413 } 414 415 /** 416 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 417 * @hw: pointer to the hardware structure 418 * 419 * This function checks the MMNGC.MNG_VETO bit to see if there are 420 * any constraints on link from manageability. For MAC's that don't 421 * have this bit just return faluse since the link can not be blocked 422 * via this method. 423 **/ 424 int32_t ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 425 { 426 uint32_t mmngc; 427 428 DEBUGFUNC("ixgbe_check_reset_blocked"); 429 430 /* If we don't have this bit, it can't be blocking */ 431 if (hw->mac.type == ixgbe_mac_82598EB) 432 return FALSE; 433 434 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 435 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 436 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 437 "MNG_VETO bit detected.\n"); 438 return TRUE; 439 } 440 441 return FALSE; 442 } 443 444 /** 445 * ixgbe_validate_phy_addr - Determines phy address is valid 446 * @hw: pointer to hardware structure 447 * 448 **/ 449 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr) 450 { 451 uint16_t phy_id = 0; 452 bool valid = FALSE; 453 454 DEBUGFUNC("ixgbe_validate_phy_addr"); 455 456 hw->phy.addr = phy_addr; 457 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 458 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 459 460 if (phy_id != 0xFFFF && phy_id != 0x0) 461 valid = TRUE; 462 463 return valid; 464 } 465 466 /** 467 * ixgbe_get_phy_id - Get the phy type 468 * @hw: pointer to hardware structure 469 * 470 **/ 471 int32_t ixgbe_get_phy_id(struct ixgbe_hw *hw) 472 { 473 uint32_t status; 474 uint16_t phy_id_high = 0; 475 uint16_t phy_id_low = 0; 476 477 DEBUGFUNC("ixgbe_get_phy_id"); 478 479 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 480 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 481 &phy_id_high); 482 483 if (status == IXGBE_SUCCESS) { 484 hw->phy.id = (uint32_t)(phy_id_high << 16); 485 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 486 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 487 &phy_id_low); 488 hw->phy.id |= (uint32_t)(phy_id_low & IXGBE_PHY_REVISION_MASK); 489 hw->phy.revision = 490 (uint32_t)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 491 } 492 return status; 493 } 494 495 /** 496 * ixgbe_get_phy_type_from_id - Get the phy type 497 * @hw: pointer to hardware structure 498 * 499 **/ 500 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(uint32_t phy_id) 501 { 502 enum ixgbe_phy_type phy_type; 503 504 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 505 506 switch (phy_id) { 507 case TN1010_PHY_ID: 508 phy_type = ixgbe_phy_tn; 509 break; 510 case X550_PHY_ID1: 511 case X550_PHY_ID2: 512 case X550_PHY_ID3: 513 case X540_PHY_ID: 514 phy_type = ixgbe_phy_aq; 515 break; 516 case QT2022_PHY_ID: 517 phy_type = ixgbe_phy_qt; 518 break; 519 case ATH_PHY_ID: 520 phy_type = ixgbe_phy_nl; 521 break; 522 case X557_PHY_ID: 523 phy_type = ixgbe_phy_x550em_ext_t; 524 break; 525 default: 526 phy_type = ixgbe_phy_unknown; 527 break; 528 } 529 530 DEBUGOUT1("phy type found is %d\n", phy_type); 531 return phy_type; 532 } 533 534 /** 535 * ixgbe_reset_phy_generic - Performs a PHY reset 536 * @hw: pointer to hardware structure 537 **/ 538 int32_t ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 539 { 540 uint32_t i; 541 uint16_t ctrl = 0; 542 int32_t status = IXGBE_SUCCESS; 543 544 DEBUGFUNC("ixgbe_reset_phy_generic"); 545 546 if (hw->phy.type == ixgbe_phy_unknown) 547 status = ixgbe_identify_phy_generic(hw); 548 549 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 550 goto out; 551 552 /* Don't reset PHY if it's shut down due to overtemp. */ 553 if (!hw->phy.reset_if_overtemp && 554 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 555 goto out; 556 557 /* Blocked by MNG FW so bail */ 558 if (ixgbe_check_reset_blocked(hw)) 559 goto out; 560 561 /* 562 * Perform soft PHY reset to the PHY_XS. 563 * This will cause a soft reset to the PHY 564 */ 565 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 566 IXGBE_MDIO_PHY_XS_DEV_TYPE, 567 IXGBE_MDIO_PHY_XS_RESET); 568 569 /* 570 * Poll for reset bit to self-clear indicating reset is complete. 571 * Some PHYs could take up to 3 seconds to complete and need about 572 * 1.7 usec delay after the reset is complete. 573 */ 574 for (i = 0; i < 30; i++) { 575 msec_delay(100); 576 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 577 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 578 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 579 usec_delay(2); 580 break; 581 } 582 } 583 584 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 585 status = IXGBE_ERR_RESET_FAILED; 586 ERROR_REPORT1(IXGBE_ERROR_POLLING, 587 "PHY reset polling failed to complete.\n"); 588 } 589 590 out: 591 return status; 592 } 593 594 /** 595 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 596 * the SWFW lock 597 * @hw: pointer to hardware structure 598 * @reg_addr: 32 bit address of PHY register to read 599 * @phy_data: Pointer to read data from PHY register 600 **/ 601 int32_t ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr, 602 uint32_t device_type, uint16_t *phy_data) 603 { 604 uint32_t i, data, command; 605 606 /* Setup and write the address cycle command */ 607 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 608 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 609 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 610 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 611 612 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 613 614 /* 615 * Check every 10 usec to see if the address cycle completed. 616 * The MDI Command bit will clear when the operation is 617 * complete 618 */ 619 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 620 usec_delay(10); 621 622 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 623 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 624 break; 625 } 626 627 628 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 629 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 630 return IXGBE_ERR_PHY; 631 } 632 633 /* 634 * Address cycle complete, setup and write the read 635 * command 636 */ 637 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 638 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 639 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 640 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 641 642 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 643 644 /* 645 * Check every 10 usec to see if the address cycle 646 * completed. The MDI Command bit will clear when the 647 * operation is complete 648 */ 649 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 650 usec_delay(10); 651 652 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 653 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 654 break; 655 } 656 657 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 658 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 659 return IXGBE_ERR_PHY; 660 } 661 662 /* 663 * Read operation is complete. Get the data 664 * from MSRWD 665 */ 666 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 667 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 668 *phy_data = (uint16_t)(data); 669 670 return IXGBE_SUCCESS; 671 } 672 673 /** 674 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 675 * using the SWFW lock - this function is needed in most cases 676 * @hw: pointer to hardware structure 677 * @reg_addr: 32 bit address of PHY register to read 678 * @phy_data: Pointer to read data from PHY register 679 **/ 680 int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, 681 uint32_t device_type, uint16_t *phy_data) 682 { 683 int32_t status; 684 uint32_t gssr = hw->phy.phy_semaphore_mask; 685 686 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 687 688 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 689 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 690 phy_data); 691 hw->mac.ops.release_swfw_sync(hw, gssr); 692 } else { 693 status = IXGBE_ERR_SWFW_SYNC; 694 } 695 696 return status; 697 } 698 699 /** 700 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 701 * without SWFW lock 702 * @hw: pointer to hardware structure 703 * @reg_addr: 32 bit PHY register to write 704 * @device_type: 5 bit device type 705 * @phy_data: Data to write to the PHY register 706 **/ 707 int32_t ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr, 708 uint32_t device_type, uint16_t phy_data) 709 { 710 uint32_t i, command; 711 712 /* Put the data in the MDI single read and write data register*/ 713 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (uint32_t)phy_data); 714 715 /* Setup and write the address cycle command */ 716 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 717 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 718 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 719 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 720 721 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 722 723 /* 724 * Check every 10 usec to see if the address cycle completed. 725 * The MDI Command bit will clear when the operation is 726 * complete 727 */ 728 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 729 usec_delay(10); 730 731 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 732 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 733 break; 734 } 735 736 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 737 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 738 return IXGBE_ERR_PHY; 739 } 740 741 /* 742 * Address cycle complete, setup and write the write 743 * command 744 */ 745 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 746 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 747 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 748 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 749 750 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 751 752 /* 753 * Check every 10 usec to see if the address cycle 754 * completed. The MDI Command bit will clear when the 755 * operation is complete 756 */ 757 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 758 usec_delay(10); 759 760 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 761 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 762 break; 763 } 764 765 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 766 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 767 return IXGBE_ERR_PHY; 768 } 769 770 return IXGBE_SUCCESS; 771 } 772 773 /** 774 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 775 * using SWFW lock- this function is needed in most cases 776 * @hw: pointer to hardware structure 777 * @reg_addr: 32 bit PHY register to write 778 * @device_type: 5 bit device type 779 * @phy_data: Data to write to the PHY register 780 **/ 781 int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, 782 uint32_t device_type, uint16_t phy_data) 783 { 784 int32_t status; 785 uint32_t gssr = hw->phy.phy_semaphore_mask; 786 787 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 788 789 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 790 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 791 phy_data); 792 hw->mac.ops.release_swfw_sync(hw, gssr); 793 } else { 794 status = IXGBE_ERR_SWFW_SYNC; 795 } 796 797 return status; 798 } 799 800 /** 801 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 802 * @hw: pointer to hardware structure 803 * 804 * Restart auto-negotiation and PHY and waits for completion. 805 **/ 806 int32_t ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 807 { 808 int32_t status = IXGBE_SUCCESS; 809 uint16_t autoneg_reg = IXGBE_MII_AUTONEG_REG; 810 bool autoneg = FALSE; 811 ixgbe_link_speed speed; 812 813 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 814 815 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 816 817 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 818 /* Set or unset auto-negotiation 10G advertisement */ 819 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 820 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 821 &autoneg_reg); 822 823 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 824 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 825 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 826 827 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 829 autoneg_reg); 830 } 831 832 if (hw->mac.type == ixgbe_mac_X550) { 833 if (speed & IXGBE_LINK_SPEED_5GB_FULL) { 834 /* Set or unset auto-negotiation 5G advertisement */ 835 hw->phy.ops.read_reg(hw, 836 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 837 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 838 &autoneg_reg); 839 840 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 841 if (hw->phy.autoneg_advertised & 842 IXGBE_LINK_SPEED_5GB_FULL) 843 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 844 845 hw->phy.ops.write_reg(hw, 846 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 847 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 848 autoneg_reg); 849 } 850 851 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) { 852 /* Set or unset auto-negotiation 2.5G advertisement */ 853 hw->phy.ops.read_reg(hw, 854 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 855 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 856 &autoneg_reg); 857 858 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 859 if (hw->phy.autoneg_advertised & 860 IXGBE_LINK_SPEED_2_5GB_FULL) 861 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 862 863 hw->phy.ops.write_reg(hw, 864 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 865 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 866 autoneg_reg); 867 } 868 } 869 870 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 871 /* Set or unset auto-negotiation 1G advertisement */ 872 hw->phy.ops.read_reg(hw, 873 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 874 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 875 &autoneg_reg); 876 877 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 878 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 879 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 880 881 hw->phy.ops.write_reg(hw, 882 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 883 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 884 autoneg_reg); 885 } 886 887 if (speed & IXGBE_LINK_SPEED_100_FULL) { 888 /* Set or unset auto-negotiation 100M advertisement */ 889 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 890 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 891 &autoneg_reg); 892 893 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 894 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 895 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 896 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 897 898 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 899 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 900 autoneg_reg); 901 } 902 903 /* Blocked by MNG FW so don't reset PHY */ 904 if (ixgbe_check_reset_blocked(hw)) 905 return status; 906 907 /* Restart PHY auto-negotiation. */ 908 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 909 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 910 911 autoneg_reg |= IXGBE_MII_RESTART; 912 913 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 914 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 915 916 return status; 917 } 918 919 /** 920 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 921 * @hw: pointer to hardware structure 922 * @speed: new link speed 923 **/ 924 int32_t ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 925 ixgbe_link_speed speed, 926 bool autoneg_wait_to_complete) 927 { 928 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 929 930 /* 931 * Clear autoneg_advertised and set new values based on input link 932 * speed. 933 */ 934 hw->phy.autoneg_advertised = 0; 935 936 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 937 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 938 939 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 940 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 941 942 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 943 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 944 945 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 946 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 947 948 if (speed & IXGBE_LINK_SPEED_100_FULL) 949 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 950 951 /* Setup link based on the new speed settings */ 952 hw->phy.ops.setup_link(hw); 953 954 return IXGBE_SUCCESS; 955 } 956 957 /** 958 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 959 * @hw: pointer to hardware structure 960 * 961 * Determines the supported link capabilities by reading the PHY auto 962 * negotiation register. 963 **/ 964 int32_t ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 965 { 966 int32_t status; 967 uint16_t speed_ability; 968 969 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 970 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 971 &speed_ability); 972 if (status) 973 return status; 974 975 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 976 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 977 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 978 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 979 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 980 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 981 982 switch (hw->mac.type) { 983 case ixgbe_mac_X550: 984 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 985 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 986 break; 987 case ixgbe_mac_X550EM_x: 988 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 989 break; 990 default: 991 break; 992 } 993 994 return status; 995 } 996 997 /** 998 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 999 * @hw: pointer to hardware structure 1000 * @speed: pointer to link speed 1001 * @autoneg: boolean auto-negotiation value 1002 **/ 1003 int32_t ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 1004 ixgbe_link_speed *speed, 1005 bool *autoneg) 1006 { 1007 int32_t status = IXGBE_SUCCESS; 1008 1009 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 1010 1011 *autoneg = TRUE; 1012 if (!hw->phy.speeds_supported) 1013 status = ixgbe_get_copper_speeds_supported(hw); 1014 1015 *speed = hw->phy.speeds_supported; 1016 return status; 1017 } 1018 1019 /** 1020 * ixgbe_check_phy_link_tnx - Determine link and speed status 1021 * @hw: pointer to hardware structure 1022 * 1023 * Reads the VS1 register to determine if link is up and the current speed for 1024 * the PHY. 1025 **/ 1026 int32_t ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1027 bool *link_up) 1028 { 1029 int32_t status = IXGBE_SUCCESS; 1030 uint32_t time_out; 1031 uint32_t max_time_out = 10; 1032 uint16_t phy_link = 0; 1033 uint16_t phy_speed = 0; 1034 uint16_t phy_data = 0; 1035 1036 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1037 1038 /* Initialize speed and link to default case */ 1039 *link_up = FALSE; 1040 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1041 1042 /* 1043 * Check current speed and link status of the PHY register. 1044 * This is a vendor specific register and may have to 1045 * be changed for other copper PHYs. 1046 */ 1047 for (time_out = 0; time_out < max_time_out; time_out++) { 1048 usec_delay(10); 1049 status = hw->phy.ops.read_reg(hw, 1050 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1051 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1052 &phy_data); 1053 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1054 phy_speed = phy_data & 1055 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1056 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1057 *link_up = TRUE; 1058 if (phy_speed == 1059 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1060 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1061 break; 1062 } 1063 } 1064 1065 return status; 1066 } 1067 1068 /** 1069 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1070 * @hw: pointer to hardware structure 1071 * 1072 * Restart auto-negotiation and PHY and waits for completion. 1073 **/ 1074 int32_t ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1075 { 1076 int32_t status = IXGBE_SUCCESS; 1077 uint16_t autoneg_reg = IXGBE_MII_AUTONEG_REG; 1078 bool autoneg = FALSE; 1079 ixgbe_link_speed speed; 1080 1081 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1082 1083 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1084 1085 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1086 /* Set or unset auto-negotiation 10G advertisement */ 1087 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1088 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1089 &autoneg_reg); 1090 1091 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1092 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1093 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1094 1095 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1096 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1097 autoneg_reg); 1098 } 1099 1100 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1101 /* Set or unset auto-negotiation 1G advertisement */ 1102 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1103 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1104 &autoneg_reg); 1105 1106 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1107 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1108 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1109 1110 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1111 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1112 autoneg_reg); 1113 } 1114 1115 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1116 /* Set or unset auto-negotiation 100M advertisement */ 1117 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1118 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1119 &autoneg_reg); 1120 1121 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1122 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1123 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1124 1125 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1126 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1127 autoneg_reg); 1128 } 1129 1130 /* Blocked by MNG FW so don't reset PHY */ 1131 if (ixgbe_check_reset_blocked(hw)) 1132 return status; 1133 1134 /* Restart PHY auto-negotiation. */ 1135 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1136 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1137 1138 autoneg_reg |= IXGBE_MII_RESTART; 1139 1140 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1141 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1142 1143 return status; 1144 } 1145 1146 /** 1147 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1148 * @hw: pointer to hardware structure 1149 * @firmware_version: pointer to the PHY Firmware Version 1150 **/ 1151 int32_t ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1152 uint16_t *firmware_version) 1153 { 1154 int32_t status; 1155 1156 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1157 1158 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1159 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1160 firmware_version); 1161 1162 return status; 1163 } 1164 1165 /** 1166 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1167 * @hw: pointer to hardware structure 1168 * @firmware_version: pointer to the PHY Firmware Version 1169 **/ 1170 int32_t ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1171 uint16_t *firmware_version) 1172 { 1173 int32_t status; 1174 1175 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1176 1177 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1178 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1179 firmware_version); 1180 1181 return status; 1182 } 1183 1184 /** 1185 * ixgbe_reset_phy_nl - Performs a PHY reset 1186 * @hw: pointer to hardware structure 1187 **/ 1188 int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1189 { 1190 uint16_t phy_offset, control, eword, edata, block_crc; 1191 bool end_data = FALSE; 1192 uint16_t list_offset, data_offset; 1193 uint16_t phy_data = 0; 1194 int32_t ret_val = IXGBE_SUCCESS; 1195 uint32_t i; 1196 1197 DEBUGFUNC("ixgbe_reset_phy_nl"); 1198 1199 /* Blocked by MNG FW so bail */ 1200 if (ixgbe_check_reset_blocked(hw)) 1201 goto out; 1202 1203 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1204 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1205 1206 /* reset the PHY and poll for completion */ 1207 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1208 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1209 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1210 1211 for (i = 0; i < 100; i++) { 1212 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1213 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1214 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1215 break; 1216 msec_delay(10); 1217 } 1218 1219 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1220 DEBUGOUT("PHY reset did not complete.\n"); 1221 ret_val = IXGBE_ERR_PHY; 1222 goto out; 1223 } 1224 1225 /* Get init offsets */ 1226 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1227 &data_offset); 1228 if (ret_val != IXGBE_SUCCESS) 1229 goto out; 1230 1231 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1232 data_offset++; 1233 while (!end_data) { 1234 /* 1235 * Read control word from PHY init contents offset 1236 */ 1237 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1238 if (ret_val) 1239 goto err_eeprom; 1240 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1241 IXGBE_CONTROL_SHIFT_NL; 1242 edata = eword & IXGBE_DATA_MASK_NL; 1243 switch (control) { 1244 case IXGBE_DELAY_NL: 1245 data_offset++; 1246 DEBUGOUT1("DELAY: %d MS\n", edata); 1247 msec_delay(edata); 1248 break; 1249 case IXGBE_DATA_NL: 1250 DEBUGOUT("DATA:\n"); 1251 data_offset++; 1252 ret_val = hw->eeprom.ops.read(hw, data_offset, 1253 &phy_offset); 1254 if (ret_val) 1255 goto err_eeprom; 1256 data_offset++; 1257 for (i = 0; i < edata; i++) { 1258 ret_val = hw->eeprom.ops.read(hw, data_offset, 1259 &eword); 1260 if (ret_val) 1261 goto err_eeprom; 1262 hw->phy.ops.write_reg(hw, phy_offset, 1263 IXGBE_TWINAX_DEV, eword); 1264 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1265 phy_offset); 1266 data_offset++; 1267 phy_offset++; 1268 } 1269 break; 1270 case IXGBE_CONTROL_NL: 1271 data_offset++; 1272 DEBUGOUT("CONTROL:\n"); 1273 if (edata == IXGBE_CONTROL_EOL_NL) { 1274 DEBUGOUT("EOL\n"); 1275 end_data = TRUE; 1276 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1277 DEBUGOUT("SOL\n"); 1278 } else { 1279 DEBUGOUT("Bad control value\n"); 1280 ret_val = IXGBE_ERR_PHY; 1281 goto out; 1282 } 1283 break; 1284 default: 1285 DEBUGOUT("Bad control type\n"); 1286 ret_val = IXGBE_ERR_PHY; 1287 goto out; 1288 } 1289 } 1290 1291 out: 1292 return ret_val; 1293 1294 err_eeprom: 1295 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1296 "eeprom read at offset %d failed", data_offset); 1297 return IXGBE_ERR_PHY; 1298 } 1299 1300 bool 1301 ixgbe_is_sfp(struct ixgbe_hw *hw) 1302 { 1303 switch (hw->phy.type) { 1304 case ixgbe_phy_sfp_avago: 1305 case ixgbe_phy_sfp_ftl: 1306 case ixgbe_phy_sfp_intel: 1307 case ixgbe_phy_sfp_unknown: 1308 case ixgbe_phy_sfp_passive_tyco: 1309 case ixgbe_phy_sfp_passive_unknown: 1310 case ixgbe_phy_qsfp_passive_unknown: 1311 case ixgbe_phy_qsfp_active_unknown: 1312 case ixgbe_phy_qsfp_intel: 1313 case ixgbe_phy_qsfp_unknown: 1314 return TRUE; 1315 default: 1316 return FALSE; 1317 } 1318 } 1319 1320 /** 1321 * ixgbe_identify_module_generic - Identifies module type 1322 * @hw: pointer to hardware structure 1323 * 1324 * Determines HW type and calls appropriate function. 1325 **/ 1326 int32_t ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1327 { 1328 int32_t status = IXGBE_ERR_SFP_NOT_PRESENT; 1329 1330 DEBUGFUNC("ixgbe_identify_module_generic"); 1331 1332 switch (hw->mac.ops.get_media_type(hw)) { 1333 case ixgbe_media_type_fiber: 1334 status = ixgbe_identify_sfp_module_generic(hw); 1335 break; 1336 1337 case ixgbe_media_type_fiber_qsfp: 1338 status = ixgbe_identify_qsfp_module_generic(hw); 1339 break; 1340 1341 default: 1342 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1343 status = IXGBE_ERR_SFP_NOT_PRESENT; 1344 break; 1345 } 1346 1347 return status; 1348 } 1349 1350 /** 1351 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1352 * @hw: pointer to hardware structure 1353 * 1354 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1355 **/ 1356 int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1357 { 1358 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 1359 uint32_t vendor_oui = 0; 1360 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1361 uint8_t identifier = 0; 1362 uint8_t comp_codes_1g = 0; 1363 uint8_t comp_codes_10g = 0; 1364 uint8_t oui_bytes[3] = {0, 0, 0}; 1365 uint8_t cable_tech = 0; 1366 uint8_t cable_spec = 0; 1367 1368 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1369 1370 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1371 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1372 status = IXGBE_ERR_SFP_NOT_PRESENT; 1373 goto out; 1374 } 1375 1376 /* LAN ID is needed for I2C access */ 1377 hw->mac.ops.set_lan_id(hw); 1378 1379 status = hw->phy.ops.read_i2c_eeprom(hw, 1380 IXGBE_SFF_IDENTIFIER, 1381 &identifier); 1382 1383 if (status != IXGBE_SUCCESS) 1384 goto err_read_i2c_eeprom; 1385 1386 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1387 hw->phy.type = ixgbe_phy_sfp_unsupported; 1388 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1389 } else { 1390 status = hw->phy.ops.read_i2c_eeprom(hw, 1391 IXGBE_SFF_1GBE_COMP_CODES, 1392 &comp_codes_1g); 1393 1394 if (status != IXGBE_SUCCESS) 1395 goto err_read_i2c_eeprom; 1396 1397 status = hw->phy.ops.read_i2c_eeprom(hw, 1398 IXGBE_SFF_10GBE_COMP_CODES, 1399 &comp_codes_10g); 1400 1401 if (status != IXGBE_SUCCESS) 1402 goto err_read_i2c_eeprom; 1403 status = hw->phy.ops.read_i2c_eeprom(hw, 1404 IXGBE_SFF_CABLE_TECHNOLOGY, 1405 &cable_tech); 1406 1407 if (status != IXGBE_SUCCESS) 1408 goto err_read_i2c_eeprom; 1409 1410 /* ID Module 1411 * ========= 1412 * 0 SFP_DA_CU 1413 * 1 SFP_SR 1414 * 2 SFP_LR 1415 * 3 SFP_DA_CORE0 - 82599-specific 1416 * 4 SFP_DA_CORE1 - 82599-specific 1417 * 5 SFP_SR/LR_CORE0 - 82599-specific 1418 * 6 SFP_SR/LR_CORE1 - 82599-specific 1419 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1420 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1421 * 9 SFP_1g_cu_CORE0 - 82599-specific 1422 * 10 SFP_1g_cu_CORE1 - 82599-specific 1423 * 11 SFP_1g_sx_CORE0 - 82599-specific 1424 * 12 SFP_1g_sx_CORE1 - 82599-specific 1425 */ 1426 if (hw->mac.type == ixgbe_mac_82598EB) { 1427 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1428 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1429 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1430 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1431 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1432 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1433 else if (comp_codes_10g & IXGBE_SFF_DA_BAD_HP_CABLE) 1434 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1435 else 1436 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1437 } else { 1438 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1439 if (hw->bus.lan_id == 0) 1440 hw->phy.sfp_type = 1441 ixgbe_sfp_type_da_cu_core0; 1442 else 1443 hw->phy.sfp_type = 1444 ixgbe_sfp_type_da_cu_core1; 1445 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1446 hw->phy.ops.read_i2c_eeprom( 1447 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1448 &cable_spec); 1449 if (cable_spec & 1450 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1451 if (hw->bus.lan_id == 0) 1452 hw->phy.sfp_type = 1453 ixgbe_sfp_type_da_act_lmt_core0; 1454 else 1455 hw->phy.sfp_type = 1456 ixgbe_sfp_type_da_act_lmt_core1; 1457 } else { 1458 hw->phy.sfp_type = 1459 ixgbe_sfp_type_unknown; 1460 } 1461 } else if (comp_codes_10g & 1462 (IXGBE_SFF_10GBASESR_CAPABLE | 1463 IXGBE_SFF_10GBASELR_CAPABLE)) { 1464 if (hw->bus.lan_id == 0) 1465 hw->phy.sfp_type = 1466 ixgbe_sfp_type_srlr_core0; 1467 else 1468 hw->phy.sfp_type = 1469 ixgbe_sfp_type_srlr_core1; 1470 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1471 if (hw->bus.lan_id == 0) 1472 hw->phy.sfp_type = 1473 ixgbe_sfp_type_1g_cu_core0; 1474 else 1475 hw->phy.sfp_type = 1476 ixgbe_sfp_type_1g_cu_core1; 1477 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1478 if (hw->bus.lan_id == 0) 1479 hw->phy.sfp_type = 1480 ixgbe_sfp_type_1g_sx_core0; 1481 else 1482 hw->phy.sfp_type = 1483 ixgbe_sfp_type_1g_sx_core1; 1484 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1485 if (hw->bus.lan_id == 0) 1486 hw->phy.sfp_type = 1487 ixgbe_sfp_type_1g_lx_core0; 1488 else 1489 hw->phy.sfp_type = 1490 ixgbe_sfp_type_1g_lx_core1; 1491 } else { 1492 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1493 } 1494 } 1495 1496 if (hw->phy.sfp_type != stored_sfp_type) 1497 hw->phy.sfp_setup_needed = TRUE; 1498 1499 /* Determine if the SFP+ PHY is dual speed or not. */ 1500 hw->phy.multispeed_fiber = FALSE; 1501 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1502 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1503 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1504 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1505 hw->phy.multispeed_fiber = TRUE; 1506 1507 /* Determine PHY vendor */ 1508 if (hw->phy.type != ixgbe_phy_nl) { 1509 hw->phy.id = identifier; 1510 status = hw->phy.ops.read_i2c_eeprom(hw, 1511 IXGBE_SFF_VENDOR_OUI_BYTE0, 1512 &oui_bytes[0]); 1513 1514 if (status != IXGBE_SUCCESS) 1515 goto err_read_i2c_eeprom; 1516 1517 status = hw->phy.ops.read_i2c_eeprom(hw, 1518 IXGBE_SFF_VENDOR_OUI_BYTE1, 1519 &oui_bytes[1]); 1520 1521 if (status != IXGBE_SUCCESS) 1522 goto err_read_i2c_eeprom; 1523 1524 status = hw->phy.ops.read_i2c_eeprom(hw, 1525 IXGBE_SFF_VENDOR_OUI_BYTE2, 1526 &oui_bytes[2]); 1527 1528 if (status != IXGBE_SUCCESS) 1529 goto err_read_i2c_eeprom; 1530 1531 vendor_oui = 1532 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1533 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1534 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1535 1536 switch (vendor_oui) { 1537 case IXGBE_SFF_VENDOR_OUI_TYCO: 1538 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1539 hw->phy.type = 1540 ixgbe_phy_sfp_passive_tyco; 1541 break; 1542 case IXGBE_SFF_VENDOR_OUI_FTL: 1543 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1544 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1545 else 1546 hw->phy.type = ixgbe_phy_sfp_ftl; 1547 break; 1548 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1549 hw->phy.type = ixgbe_phy_sfp_avago; 1550 break; 1551 case IXGBE_SFF_VENDOR_OUI_INTEL: 1552 hw->phy.type = ixgbe_phy_sfp_intel; 1553 break; 1554 default: 1555 hw->phy.type = ixgbe_phy_sfp_unknown; 1556 break; 1557 } 1558 } 1559 1560 /* Allow any DA cable vendor */ 1561 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1562 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1563 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1564 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1565 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1566 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1567 status = IXGBE_SUCCESS; 1568 goto out; 1569 } 1570 1571 /* Verify supported 1G SFP modules */ 1572 if (comp_codes_10g == 0 && 1573 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1574 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1575 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1576 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1577 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1578 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1579 hw->phy.type = ixgbe_phy_sfp_unsupported; 1580 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1581 goto out; 1582 } 1583 1584 /* 1585 * We do not limit the definition of "supported SPF modules" 1586 * to the vendor/make whitelist. 1587 */ 1588 status = IXGBE_SUCCESS; 1589 } 1590 1591 out: 1592 return status; 1593 1594 err_read_i2c_eeprom: 1595 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1596 if (hw->phy.type != ixgbe_phy_nl) { 1597 hw->phy.id = 0; 1598 hw->phy.type = ixgbe_phy_unknown; 1599 } 1600 return IXGBE_ERR_SFP_NOT_PRESENT; 1601 } 1602 1603 /** 1604 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1605 * @hw: pointer to hardware structure 1606 * 1607 * Determines physical layer capabilities of the current SFP. 1608 */ 1609 int32_t ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1610 { 1611 uint32_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1612 uint8_t comp_codes_10g = 0; 1613 uint8_t comp_codes_1g = 0; 1614 1615 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1616 1617 hw->phy.ops.identify_sfp(hw); 1618 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1619 return physical_layer; 1620 1621 switch (hw->phy.type) { 1622 case ixgbe_phy_sfp_passive_tyco: 1623 case ixgbe_phy_sfp_passive_unknown: 1624 case ixgbe_phy_qsfp_passive_unknown: 1625 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1626 break; 1627 case ixgbe_phy_sfp_ftl_active: 1628 case ixgbe_phy_sfp_active_unknown: 1629 case ixgbe_phy_qsfp_active_unknown: 1630 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1631 break; 1632 case ixgbe_phy_sfp_avago: 1633 case ixgbe_phy_sfp_ftl: 1634 case ixgbe_phy_sfp_intel: 1635 case ixgbe_phy_sfp_unknown: 1636 hw->phy.ops.read_i2c_eeprom(hw, 1637 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1638 hw->phy.ops.read_i2c_eeprom(hw, 1639 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1640 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1641 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1642 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1643 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1644 else if (comp_codes_10g & 1645 (IXGBE_SFF_DA_PASSIVE_CABLE | IXGBE_SFF_DA_BAD_HP_CABLE)) 1646 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1647 else if (comp_codes_10g & IXGBE_SFF_DA_ACTIVE_CABLE) 1648 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1649 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1650 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1651 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1652 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1653 else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) 1654 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_LX; 1655 break; 1656 case ixgbe_phy_qsfp_intel: 1657 case ixgbe_phy_qsfp_unknown: 1658 hw->phy.ops.read_i2c_eeprom(hw, 1659 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1660 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1661 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1662 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1663 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1664 break; 1665 default: 1666 break; 1667 } 1668 1669 return physical_layer; 1670 } 1671 1672 /** 1673 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1674 * @hw: pointer to hardware structure 1675 * 1676 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1677 **/ 1678 int32_t ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1679 { 1680 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 1681 uint32_t vendor_oui = 0; 1682 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1683 uint8_t identifier = 0; 1684 uint8_t comp_codes_1g = 0; 1685 uint8_t comp_codes_10g = 0; 1686 uint8_t oui_bytes[3] = {0, 0, 0}; 1687 uint8_t connector = 0; 1688 uint8_t cable_length = 0; 1689 uint8_t device_tech = 0; 1690 bool active_cable = FALSE; 1691 1692 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1693 1694 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1695 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1696 status = IXGBE_ERR_SFP_NOT_PRESENT; 1697 goto out; 1698 } 1699 1700 /* LAN ID is needed for I2C access */ 1701 hw->mac.ops.set_lan_id(hw); 1702 1703 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1704 &identifier); 1705 1706 if (status != IXGBE_SUCCESS) 1707 goto err_read_i2c_eeprom; 1708 1709 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1710 hw->phy.type = ixgbe_phy_sfp_unsupported; 1711 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1712 goto out; 1713 } 1714 1715 hw->phy.id = identifier; 1716 1717 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1718 &comp_codes_10g); 1719 1720 if (status != IXGBE_SUCCESS) 1721 goto err_read_i2c_eeprom; 1722 1723 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1724 &comp_codes_1g); 1725 1726 if (status != IXGBE_SUCCESS) 1727 goto err_read_i2c_eeprom; 1728 1729 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1730 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1731 if (hw->bus.lan_id == 0) 1732 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1733 else 1734 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1735 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1736 IXGBE_SFF_10GBASELR_CAPABLE)) { 1737 if (hw->bus.lan_id == 0) 1738 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1739 else 1740 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1741 } else { 1742 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1743 active_cable = TRUE; 1744 1745 if (!active_cable) { 1746 /* check for active DA cables that pre-date 1747 * SFF-8436 v3.6 */ 1748 hw->phy.ops.read_i2c_eeprom(hw, 1749 IXGBE_SFF_QSFP_CONNECTOR, 1750 &connector); 1751 1752 hw->phy.ops.read_i2c_eeprom(hw, 1753 IXGBE_SFF_QSFP_CABLE_LENGTH, 1754 &cable_length); 1755 1756 hw->phy.ops.read_i2c_eeprom(hw, 1757 IXGBE_SFF_QSFP_DEVICE_TECH, 1758 &device_tech); 1759 1760 if ((connector == 1761 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1762 (cable_length > 0) && 1763 ((device_tech >> 4) == 1764 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1765 active_cable = TRUE; 1766 } 1767 1768 if (active_cable) { 1769 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1770 if (hw->bus.lan_id == 0) 1771 hw->phy.sfp_type = 1772 ixgbe_sfp_type_da_act_lmt_core0; 1773 else 1774 hw->phy.sfp_type = 1775 ixgbe_sfp_type_da_act_lmt_core1; 1776 } else { 1777 /* unsupported module type */ 1778 hw->phy.type = ixgbe_phy_sfp_unsupported; 1779 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1780 goto out; 1781 } 1782 } 1783 1784 if (hw->phy.sfp_type != stored_sfp_type) 1785 hw->phy.sfp_setup_needed = TRUE; 1786 1787 /* Determine if the QSFP+ PHY is dual speed or not. */ 1788 hw->phy.multispeed_fiber = FALSE; 1789 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1790 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1791 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1792 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1793 hw->phy.multispeed_fiber = TRUE; 1794 1795 /* Determine PHY vendor for optical modules */ 1796 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1797 IXGBE_SFF_10GBASELR_CAPABLE)) { 1798 status = hw->phy.ops.read_i2c_eeprom(hw, 1799 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1800 &oui_bytes[0]); 1801 1802 if (status != IXGBE_SUCCESS) 1803 goto err_read_i2c_eeprom; 1804 1805 status = hw->phy.ops.read_i2c_eeprom(hw, 1806 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1807 &oui_bytes[1]); 1808 1809 if (status != IXGBE_SUCCESS) 1810 goto err_read_i2c_eeprom; 1811 1812 status = hw->phy.ops.read_i2c_eeprom(hw, 1813 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1814 &oui_bytes[2]); 1815 1816 if (status != IXGBE_SUCCESS) 1817 goto err_read_i2c_eeprom; 1818 1819 vendor_oui = 1820 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1821 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1822 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1823 1824 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1825 hw->phy.type = ixgbe_phy_qsfp_intel; 1826 else 1827 hw->phy.type = ixgbe_phy_qsfp_unknown; 1828 1829 /* 1830 * We do not limit the definition of "supported SPF modules" 1831 * to the vendor/make whitelist. 1832 */ 1833 status = IXGBE_SUCCESS; 1834 } 1835 1836 out: 1837 return status; 1838 1839 err_read_i2c_eeprom: 1840 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1841 hw->phy.id = 0; 1842 hw->phy.type = ixgbe_phy_unknown; 1843 1844 return IXGBE_ERR_SFP_NOT_PRESENT; 1845 } 1846 1847 1848 /** 1849 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1850 * @hw: pointer to hardware structure 1851 * @list_offset: offset to the SFP ID list 1852 * @data_offset: offset to the SFP data block 1853 * 1854 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1855 * so it returns the offsets to the phy init sequence block. 1856 **/ 1857 int32_t ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1858 uint16_t *list_offset, 1859 uint16_t *data_offset) 1860 { 1861 uint16_t sfp_id; 1862 uint16_t sfp_type = hw->phy.sfp_type; 1863 1864 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1865 1866 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1867 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1868 1869 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1870 return IXGBE_ERR_SFP_NOT_PRESENT; 1871 1872 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1873 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1874 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1875 1876 /* 1877 * Limiting active cables and 1G Phys must be initialized as 1878 * SR modules 1879 */ 1880 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1881 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1882 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1883 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1884 sfp_type = ixgbe_sfp_type_srlr_core0; 1885 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1886 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1887 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1888 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1889 sfp_type = ixgbe_sfp_type_srlr_core1; 1890 1891 /* Read offset to PHY init contents */ 1892 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1893 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1894 "eeprom read at offset %d failed", 1895 IXGBE_PHY_INIT_OFFSET_NL); 1896 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1897 } 1898 1899 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1900 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1901 1902 /* Shift offset to first ID word */ 1903 (*list_offset)++; 1904 1905 /* 1906 * Find the matching SFP ID in the EEPROM 1907 * and program the init sequence 1908 */ 1909 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1910 goto err_phy; 1911 1912 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1913 if (sfp_id == sfp_type) { 1914 (*list_offset)++; 1915 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1916 goto err_phy; 1917 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1918 DEBUGOUT("SFP+ module not supported\n"); 1919 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1920 } else { 1921 break; 1922 } 1923 } else { 1924 (*list_offset) += 2; 1925 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1926 goto err_phy; 1927 } 1928 } 1929 1930 /* 1931 * the 82598EB SFP+ card offically supports only direct attached cables 1932 * but works fine with optical SFP+ modules as well. Even though the 1933 * EEPROM has no matching ID for them. So just accept the module. 1934 */ 1935 if (sfp_id == IXGBE_PHY_INIT_END_NL && 1936 hw->mac.type == ixgbe_mac_82598EB) { 1937 /* refetch offset for the first phy entry */ 1938 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1939 (*list_offset) += 2; 1940 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1941 } else if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1942 DEBUGOUT("No matching SFP+ module found\n"); 1943 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1944 } 1945 1946 return IXGBE_SUCCESS; 1947 1948 err_phy: 1949 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1950 "eeprom read at offset %d failed", *list_offset); 1951 return IXGBE_ERR_PHY; 1952 } 1953 1954 /** 1955 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1956 * @hw: pointer to hardware structure 1957 * @byte_offset: EEPROM byte offset to read 1958 * @eeprom_data: value read 1959 * 1960 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1961 **/ 1962 int32_t ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1963 uint8_t *eeprom_data) 1964 { 1965 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1966 1967 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1968 IXGBE_I2C_EEPROM_DEV_ADDR, 1969 eeprom_data); 1970 } 1971 1972 /** 1973 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1974 * @hw: pointer to hardware structure 1975 * @byte_offset: EEPROM byte offset to write 1976 * @eeprom_data: value to write 1977 * 1978 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1979 **/ 1980 int32_t ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1981 uint8_t eeprom_data) 1982 { 1983 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1984 1985 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1986 IXGBE_I2C_EEPROM_DEV_ADDR, 1987 eeprom_data); 1988 } 1989 1990 /** 1991 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 1992 * @hw: pointer to hardware structure 1993 * @offset: eeprom offset to be read 1994 * @addr: I2C address to be read 1995 */ 1996 bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, uint8_t offset, uint8_t addr) 1997 { 1998 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1999 offset == IXGBE_SFF_IDENTIFIER && 2000 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2001 return TRUE; 2002 return FALSE; 2003 } 2004 2005 /** 2006 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2007 * @hw: pointer to hardware structure 2008 * @byte_offset: byte offset to read 2009 * @data: value read 2010 * 2011 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2012 * a specified device address. 2013 **/ 2014 int32_t ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, uint8_t byte_offset, 2015 uint8_t dev_addr, uint8_t *data, bool lock) 2016 { 2017 int32_t status; 2018 uint32_t max_retry = 10; 2019 uint32_t retry = 0; 2020 uint32_t swfw_mask = hw->phy.phy_semaphore_mask; 2021 bool nack = 1; 2022 *data = 0; 2023 2024 DEBUGFUNC("ixgbe_read_i2c_byte_generic_int"); 2025 2026 if (hw->mac.type >= ixgbe_mac_X550) 2027 max_retry = 3; 2028 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2029 max_retry = IXGBE_SFP_DETECT_RETRIES; 2030 2031 do { 2032 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2033 return IXGBE_ERR_SWFW_SYNC; 2034 2035 ixgbe_i2c_start(hw); 2036 2037 /* Device Address and write indication */ 2038 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2039 if (status != IXGBE_SUCCESS) 2040 goto fail; 2041 2042 status = ixgbe_get_i2c_ack(hw); 2043 if (status != IXGBE_SUCCESS) 2044 goto fail; 2045 2046 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2047 if (status != IXGBE_SUCCESS) 2048 goto fail; 2049 2050 status = ixgbe_get_i2c_ack(hw); 2051 if (status != IXGBE_SUCCESS) 2052 goto fail; 2053 2054 ixgbe_i2c_start(hw); 2055 2056 /* Device Address and read indication */ 2057 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2058 if (status != IXGBE_SUCCESS) 2059 goto fail; 2060 2061 status = ixgbe_get_i2c_ack(hw); 2062 if (status != IXGBE_SUCCESS) 2063 goto fail; 2064 2065 status = ixgbe_clock_in_i2c_byte(hw, data); 2066 if (status != IXGBE_SUCCESS) 2067 goto fail; 2068 2069 status = ixgbe_clock_out_i2c_bit(hw, nack); 2070 if (status != IXGBE_SUCCESS) 2071 goto fail; 2072 2073 ixgbe_i2c_stop(hw); 2074 if (lock) 2075 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2076 return IXGBE_SUCCESS; 2077 2078 fail: 2079 ixgbe_i2c_bus_clear(hw); 2080 if (lock) { 2081 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2082 msec_delay(100); 2083 } 2084 retry++; 2085 if (retry < max_retry) 2086 DEBUGOUT("I2C byte read error - Retrying.\n"); 2087 else 2088 DEBUGOUT("I2C byte read error.\n"); 2089 2090 } while (retry < max_retry); 2091 2092 return status; 2093 } 2094 2095 /** 2096 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2097 * @hw: pointer to hardware structure 2098 * @byte_offset: byte offset to read 2099 * @data: value read 2100 * 2101 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2102 * a specified device address. 2103 **/ 2104 int32_t ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 2105 uint8_t dev_addr, uint8_t *data) 2106 { 2107 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2108 data, TRUE); 2109 } 2110 2111 /** 2112 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2113 * @hw: pointer to hardware structure 2114 * @byte_offset: byte offset to read 2115 * @data: value read 2116 * 2117 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2118 * a specified device address. 2119 **/ 2120 int32_t ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, uint8_t byte_offset, 2121 uint8_t dev_addr, uint8_t *data) 2122 { 2123 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2124 data, FALSE); 2125 } 2126 2127 /** 2128 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2129 * @hw: pointer to hardware structure 2130 * @byte_offset: byte offset to write 2131 * @data: value to write 2132 * @lock: TRUE if to take and release semaphore 2133 * 2134 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2135 * a specified device address. 2136 **/ 2137 int32_t ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, uint8_t byte_offset, 2138 uint8_t dev_addr, uint8_t data, bool lock) 2139 { 2140 int32_t status; 2141 uint32_t max_retry = 1; 2142 uint32_t retry = 0; 2143 uint32_t swfw_mask = hw->phy.phy_semaphore_mask; 2144 2145 DEBUGFUNC("ixgbe_write_i2c_byte_generic_int"); 2146 2147 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2148 IXGBE_SUCCESS) 2149 return IXGBE_ERR_SWFW_SYNC; 2150 2151 do { 2152 ixgbe_i2c_start(hw); 2153 2154 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2155 if (status != IXGBE_SUCCESS) 2156 goto fail; 2157 2158 status = ixgbe_get_i2c_ack(hw); 2159 if (status != IXGBE_SUCCESS) 2160 goto fail; 2161 2162 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2163 if (status != IXGBE_SUCCESS) 2164 goto fail; 2165 2166 status = ixgbe_get_i2c_ack(hw); 2167 if (status != IXGBE_SUCCESS) 2168 goto fail; 2169 2170 status = ixgbe_clock_out_i2c_byte(hw, data); 2171 if (status != IXGBE_SUCCESS) 2172 goto fail; 2173 2174 status = ixgbe_get_i2c_ack(hw); 2175 if (status != IXGBE_SUCCESS) 2176 goto fail; 2177 2178 ixgbe_i2c_stop(hw); 2179 if (lock) 2180 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2181 return IXGBE_SUCCESS; 2182 2183 fail: 2184 ixgbe_i2c_bus_clear(hw); 2185 retry++; 2186 if (retry < max_retry) 2187 DEBUGOUT("I2C byte write error - Retrying.\n"); 2188 else 2189 DEBUGOUT("I2C byte write error.\n"); 2190 } while (retry < max_retry); 2191 2192 if (lock) 2193 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2194 2195 return status; 2196 } 2197 2198 /** 2199 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2200 * @hw: pointer to hardware structure 2201 * @byte_offset: byte offset to write 2202 * @data: value to write 2203 * 2204 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2205 * a specified device address. 2206 **/ 2207 int32_t ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 2208 uint8_t dev_addr, uint8_t data) 2209 { 2210 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2211 data, TRUE); 2212 } 2213 2214 /** 2215 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2216 * @hw: pointer to hardware structure 2217 * @byte_offset: byte offset to write 2218 * @data: value to write 2219 * 2220 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2221 * a specified device address. 2222 **/ 2223 int32_t ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, uint8_t byte_offset, 2224 uint8_t dev_addr, uint8_t data) 2225 { 2226 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2227 data, FALSE); 2228 } 2229 2230 /** 2231 * ixgbe_i2c_start - Sets I2C start condition 2232 * @hw: pointer to hardware structure 2233 * 2234 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2235 * Set bit-bang mode on X550 hardware. 2236 **/ 2237 void ixgbe_i2c_start(struct ixgbe_hw *hw) 2238 { 2239 uint32_t i2cctl; 2240 2241 DEBUGFUNC("ixgbe_i2c_start"); 2242 2243 if (hw->mac.type == ixgbe_mac_X550 || 2244 hw->mac.type == ixgbe_mac_X550EM_x) { 2245 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_X550); 2246 i2cctl |= IXGBE_I2C_BB_EN_X550; 2247 } else 2248 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 2249 2250 /* Start condition must begin with data and clock high */ 2251 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2252 ixgbe_raise_i2c_clk(hw, &i2cctl); 2253 2254 /* Setup time for start condition (4.7us) */ 2255 usec_delay(IXGBE_I2C_T_SU_STA); 2256 2257 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2258 2259 /* Hold time for start condition (4us) */ 2260 usec_delay(IXGBE_I2C_T_HD_STA); 2261 2262 ixgbe_lower_i2c_clk(hw, &i2cctl); 2263 2264 /* Minimum low period of clock is 4.7 us */ 2265 usec_delay(IXGBE_I2C_T_LOW); 2266 2267 } 2268 2269 /** 2270 * ixgbe_i2c_stop - Sets I2C stop condition 2271 * @hw: pointer to hardware structure 2272 * 2273 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2274 * Disables bit-bang mode and negates data output enable on X550 2275 * hardware. 2276 **/ 2277 void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2278 { 2279 uint32_t i2cctl; 2280 2281 DEBUGFUNC("ixgbe_i2c_stop"); 2282 2283 if (hw->mac.type == ixgbe_mac_X550 || 2284 hw->mac.type == ixgbe_mac_X550EM_x) 2285 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_X550); 2286 else 2287 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 2288 2289 /* Stop condition must begin with data low and clock high */ 2290 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2291 ixgbe_raise_i2c_clk(hw, &i2cctl); 2292 2293 /* Setup time for stop condition (4us) */ 2294 usec_delay(IXGBE_I2C_T_SU_STO); 2295 2296 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2297 2298 /* bus free time between stop and start (4.7us)*/ 2299 usec_delay(IXGBE_I2C_T_BUF); 2300 2301 if (hw->mac.type == ixgbe_mac_X550 || 2302 hw->mac.type == ixgbe_mac_X550EM_x) { 2303 i2cctl &= ~IXGBE_I2C_BB_EN_X550; 2304 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_X550 | 2305 IXGBE_I2C_CLK_OE_N_EN_X550; 2306 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_X550, i2cctl); 2307 IXGBE_WRITE_FLUSH(hw); 2308 } 2309 } 2310 2311 /** 2312 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2313 * @hw: pointer to hardware structure 2314 * @data: data byte to clock in 2315 * 2316 * Clocks in one byte data via I2C data/clock 2317 **/ 2318 int32_t ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, uint8_t *data) 2319 { 2320 int32_t i; 2321 bool bit = 0; 2322 2323 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2324 2325 *data = 0; 2326 for (i = 7; i >= 0; i--) { 2327 ixgbe_clock_in_i2c_bit(hw, &bit); 2328 *data |= bit << i; 2329 } 2330 2331 return IXGBE_SUCCESS; 2332 } 2333 2334 /** 2335 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2336 * @hw: pointer to hardware structure 2337 * @data: data byte clocked out 2338 * 2339 * Clocks out one byte data via I2C data/clock 2340 **/ 2341 int32_t ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, uint8_t data) 2342 { 2343 int32_t status = IXGBE_SUCCESS; 2344 int32_t i; 2345 uint32_t i2cctl; 2346 bool bit; 2347 2348 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2349 2350 for (i = 7; i >= 0; i--) { 2351 bit = (data >> i) & 0x1; 2352 status = ixgbe_clock_out_i2c_bit(hw, bit); 2353 2354 if (status != IXGBE_SUCCESS) 2355 break; 2356 } 2357 2358 /* Release SDA line (set high) */ 2359 if (hw->mac.type == ixgbe_mac_X550 || 2360 hw->mac.type == ixgbe_mac_X550EM_x) { 2361 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_X550); 2362 i2cctl |= IXGBE_I2C_DATA_OUT_X550 | IXGBE_I2C_DATA_OE_N_EN_X550; 2363 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_X550, i2cctl); 2364 } else { 2365 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 2366 i2cctl |= IXGBE_I2C_DATA_OUT; 2367 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 2368 } 2369 IXGBE_WRITE_FLUSH(hw); 2370 2371 return status; 2372 } 2373 2374 /** 2375 * ixgbe_get_i2c_ack - Polls for I2C ACK 2376 * @hw: pointer to hardware structure 2377 * 2378 * Clocks in/out one bit via I2C data/clock 2379 **/ 2380 int32_t ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2381 { 2382 int32_t status = IXGBE_SUCCESS; 2383 uint32_t i = 0; 2384 uint32_t i2cctl, i2cctl_reg; 2385 uint32_t timeout = 10; 2386 bool ack = 1; 2387 2388 DEBUGFUNC("ixgbe_get_i2c_ack"); 2389 2390 if (hw->mac.type == ixgbe_mac_X550 || 2391 hw->mac.type == ixgbe_mac_X550EM_x) { 2392 i2cctl_reg = IXGBE_I2CCTL_X550; 2393 i2cctl = IXGBE_READ_REG(hw, i2cctl_reg); 2394 i2cctl |= IXGBE_I2C_DATA_OUT_X550 | IXGBE_I2C_DATA_OE_N_EN_X550; 2395 IXGBE_WRITE_REG(hw, i2cctl_reg, i2cctl); 2396 IXGBE_WRITE_FLUSH(hw); 2397 } else { 2398 i2cctl_reg = IXGBE_I2CCTL; 2399 i2cctl = IXGBE_READ_REG(hw, i2cctl_reg); 2400 } 2401 ixgbe_raise_i2c_clk(hw, &i2cctl); 2402 2403 /* Minimum high period of clock is 4us */ 2404 usec_delay(IXGBE_I2C_T_HIGH); 2405 2406 /* Poll for ACK. Note that ACK in I2C spec is 2407 * transition from 1 to 0 */ 2408 for (i = 0; i < timeout; i++) { 2409 i2cctl = IXGBE_READ_REG(hw, i2cctl_reg); 2410 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2411 2412 usec_delay(1); 2413 if (!ack) 2414 break; 2415 } 2416 2417 if (ack) { 2418 DEBUGOUT("I2C ack was not received.\n"); 2419 status = IXGBE_ERR_I2C; 2420 } 2421 2422 ixgbe_lower_i2c_clk(hw, &i2cctl); 2423 2424 /* Minimum low period of clock is 4.7 us */ 2425 usec_delay(IXGBE_I2C_T_LOW); 2426 2427 return status; 2428 } 2429 2430 /** 2431 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2432 * @hw: pointer to hardware structure 2433 * @data: read data value 2434 * 2435 * Clocks in one bit via I2C data/clock 2436 **/ 2437 int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2438 { 2439 uint32_t i2cctl, i2cctl_reg; 2440 2441 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2442 2443 if (hw->mac.type == ixgbe_mac_X550 || 2444 hw->mac.type == ixgbe_mac_X550EM_x) { 2445 i2cctl_reg = IXGBE_I2CCTL_X550; 2446 i2cctl = IXGBE_READ_REG(hw, i2cctl_reg); 2447 i2cctl |= IXGBE_I2C_DATA_OUT_X550 | IXGBE_I2C_DATA_OE_N_EN_X550; 2448 IXGBE_WRITE_REG(hw, i2cctl_reg, i2cctl); 2449 IXGBE_WRITE_FLUSH(hw); 2450 } else { 2451 i2cctl_reg = IXGBE_I2CCTL; 2452 i2cctl = IXGBE_READ_REG(hw, i2cctl_reg); 2453 } 2454 2455 ixgbe_raise_i2c_clk(hw, &i2cctl); 2456 2457 /* Minimum high period of clock is 4us */ 2458 usec_delay(IXGBE_I2C_T_HIGH); 2459 2460 i2cctl = IXGBE_READ_REG(hw, i2cctl_reg); 2461 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2462 2463 ixgbe_lower_i2c_clk(hw, &i2cctl); 2464 2465 /* Minimum low period of clock is 4.7 us */ 2466 usec_delay(IXGBE_I2C_T_LOW); 2467 2468 return IXGBE_SUCCESS; 2469 } 2470 2471 /** 2472 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2473 * @hw: pointer to hardware structure 2474 * @data: data value to write 2475 * 2476 * Clocks out one bit via I2C data/clock 2477 **/ 2478 int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2479 { 2480 int32_t status; 2481 uint32_t i2cctl; 2482 2483 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2484 2485 if (hw->mac.type == ixgbe_mac_X550 || 2486 hw->mac.type == ixgbe_mac_X550EM_x) 2487 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_X550); 2488 else 2489 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 2490 2491 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2492 if (status == IXGBE_SUCCESS) { 2493 ixgbe_raise_i2c_clk(hw, &i2cctl); 2494 2495 /* Minimum high period of clock is 4us */ 2496 usec_delay(IXGBE_I2C_T_HIGH); 2497 2498 ixgbe_lower_i2c_clk(hw, &i2cctl); 2499 2500 /* Minimum low period of clock is 4.7 us. 2501 * This also takes care of the data hold time. 2502 */ 2503 usec_delay(IXGBE_I2C_T_LOW); 2504 } else { 2505 status = IXGBE_ERR_I2C; 2506 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2507 "I2C data was not set to %X\n", data); 2508 } 2509 2510 return status; 2511 } 2512 2513 /** 2514 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2515 * @hw: pointer to hardware structure 2516 * @i2cctl: Current value of I2CCTL register 2517 * 2518 * Raises the I2C clock line '0'->'1' 2519 * Negates the I2C clock output enable on X550 hardware. 2520 **/ 2521 void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl) 2522 { 2523 uint32_t i2cctl_clk_in, i2cctl_reg; 2524 uint32_t i = 0; 2525 uint32_t timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2526 2527 if (hw->mac.type == ixgbe_mac_X550 || 2528 hw->mac.type == ixgbe_mac_X550EM_x) { 2529 i2cctl_reg = IXGBE_I2CCTL_X550; 2530 *i2cctl |= IXGBE_I2C_CLK_OE_N_EN_X550; 2531 IXGBE_WRITE_REG(hw, i2cctl_reg, *i2cctl); 2532 *i2cctl |= IXGBE_I2C_CLK_OUT_X550; 2533 i2cctl_clk_in = IXGBE_I2C_CLK_IN_X550; 2534 } else { 2535 i2cctl_reg = IXGBE_I2CCTL; 2536 *i2cctl |= IXGBE_I2C_CLK_OUT; 2537 i2cctl_clk_in = IXGBE_I2C_CLK_IN; 2538 } 2539 2540 for (i = 0; i < timeout; i++) { 2541 IXGBE_WRITE_REG(hw, i2cctl_reg, *i2cctl); 2542 IXGBE_WRITE_FLUSH(hw); 2543 /* SCL rise time (1000ns) */ 2544 usec_delay(IXGBE_I2C_T_RISE); 2545 2546 if (IXGBE_READ_REG(hw, i2cctl_reg) & i2cctl_clk_in) 2547 break; 2548 } 2549 } 2550 2551 /** 2552 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2553 * @hw: pointer to hardware structure 2554 * @i2cctl: Current value of I2CCTL register 2555 * 2556 * Lowers the I2C clock line '1'->'0' 2557 * Asserts the I2C clock output enable on X550 hardware. 2558 **/ 2559 void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl) 2560 { 2561 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2562 2563 if (hw->mac.type == ixgbe_mac_X550 || 2564 hw->mac.type == ixgbe_mac_X550EM_x) { 2565 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_X550 | 2566 IXGBE_I2C_CLK_OE_N_EN_X550); 2567 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_X550, *i2cctl); 2568 } else { 2569 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 2570 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 2571 } 2572 IXGBE_WRITE_FLUSH(hw); 2573 2574 /* SCL fall time (300ns) */ 2575 usec_delay(IXGBE_I2C_T_FALL); 2576 } 2577 2578 /** 2579 * ixgbe_set_i2c_data - Sets the I2C data bit 2580 * @hw: pointer to hardware structure 2581 * @i2cctl: Current value of I2CCTL register 2582 * @data: I2C data value (0 or 1) to set 2583 * 2584 * Sets the I2C data bit 2585 * Asserts the I2C data output enable on X550 hardware. 2586 **/ 2587 int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, bool data) 2588 { 2589 uint32_t i2cctl_reg; 2590 int32_t status = IXGBE_SUCCESS; 2591 2592 DEBUGFUNC("ixgbe_set_i2c_data"); 2593 2594 if (hw->mac.type == ixgbe_mac_X550 || 2595 hw->mac.type == ixgbe_mac_X550EM_x) { 2596 i2cctl_reg = IXGBE_I2CCTL_X550; 2597 if (data) 2598 *i2cctl |= IXGBE_I2C_DATA_OUT_X550; 2599 else 2600 *i2cctl &= ~IXGBE_I2C_DATA_OUT_X550; 2601 *i2cctl &= ~IXGBE_I2C_DATA_OE_N_EN_X550; 2602 } else { 2603 i2cctl_reg = IXGBE_I2CCTL; 2604 if (data) 2605 *i2cctl |= IXGBE_I2C_DATA_OUT; 2606 else 2607 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 2608 } 2609 2610 IXGBE_WRITE_REG(hw, i2cctl_reg, *i2cctl); 2611 IXGBE_WRITE_FLUSH(hw); 2612 2613 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2614 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2615 2616 if (!data) /* Can't verify data in this case */ 2617 return IXGBE_SUCCESS; 2618 if (hw->mac.type == ixgbe_mac_X550 || 2619 hw->mac.type == ixgbe_mac_X550EM_x) { 2620 *i2cctl |= IXGBE_I2C_DATA_OE_N_EN_X550; 2621 IXGBE_WRITE_REG(hw, i2cctl_reg, *i2cctl); 2622 IXGBE_WRITE_FLUSH(hw); 2623 } 2624 2625 /* Verify data was set correctly */ 2626 *i2cctl = IXGBE_READ_REG(hw, i2cctl_reg); 2627 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2628 status = IXGBE_ERR_I2C; 2629 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2630 "Error - I2C data was not set to %X.\n", 2631 data); 2632 } 2633 2634 return status; 2635 } 2636 2637 /** 2638 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2639 * @hw: pointer to hardware structure 2640 * @i2cctl: Current value of I2CCTL register 2641 * 2642 * Returns the I2C data bit value 2643 * Negates the I2C data output enable on X550 hardware. 2644 **/ 2645 bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl) 2646 { 2647 uint32_t i2cctl_data_in; 2648 bool data; 2649 2650 DEBUGFUNC("ixgbe_get_i2c_data"); 2651 2652 if (hw->mac.type == ixgbe_mac_X550 || 2653 hw->mac.type == ixgbe_mac_X550EM_x) { 2654 i2cctl_data_in = IXGBE_I2C_DATA_IN_X550; 2655 *i2cctl |= IXGBE_I2C_DATA_OE_N_EN_X550; 2656 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_X550, *i2cctl); 2657 IXGBE_WRITE_FLUSH(hw); 2658 usec_delay(IXGBE_I2C_T_FALL); 2659 } else 2660 i2cctl_data_in = IXGBE_I2C_DATA_IN; 2661 2662 if (*i2cctl & i2cctl_data_in) 2663 data = 1; 2664 else 2665 data = 0; 2666 2667 return data; 2668 } 2669 2670 /** 2671 * ixgbe_i2c_bus_clear - Clears the I2C bus 2672 * @hw: pointer to hardware structure 2673 * 2674 * Clears the I2C bus by sending nine clock pulses. 2675 * Used when data line is stuck low. 2676 **/ 2677 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2678 { 2679 uint32_t i2cctl; 2680 uint32_t i; 2681 2682 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2683 2684 ixgbe_i2c_start(hw); 2685 2686 if (hw->mac.type == ixgbe_mac_X550 || 2687 hw->mac.type == ixgbe_mac_X550EM_x) 2688 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_X550); 2689 else 2690 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 2691 2692 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2693 2694 for (i = 0; i < 9; i++) { 2695 ixgbe_raise_i2c_clk(hw, &i2cctl); 2696 2697 /* Min high period of clock is 4us */ 2698 usec_delay(IXGBE_I2C_T_HIGH); 2699 2700 ixgbe_lower_i2c_clk(hw, &i2cctl); 2701 2702 /* Min low period of clock is 4.7us*/ 2703 usec_delay(IXGBE_I2C_T_LOW); 2704 } 2705 2706 ixgbe_i2c_start(hw); 2707 2708 /* Put the i2c bus back to default state */ 2709 ixgbe_i2c_stop(hw); 2710 } 2711 2712 /** 2713 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2714 * @hw: pointer to hardware structure 2715 * 2716 * Checks if the LASI temp alarm status was triggered due to overtemp 2717 **/ 2718 int32_t ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2719 { 2720 int32_t status = IXGBE_SUCCESS; 2721 uint16_t phy_data = 0; 2722 2723 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2724 2725 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2726 goto out; 2727 2728 /* Check that the LASI temp alarm status was triggered */ 2729 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2730 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2731 2732 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2733 goto out; 2734 2735 status = IXGBE_ERR_OVERTEMP; 2736 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2737 out: 2738 return status; 2739 } 2740 2741 /** 2742 * ixgbe_set_copper_phy_power - Control power for copper phy 2743 * @hw: pointer to hardware structure 2744 * @on: TRUE for on, FALSE for off 2745 */ 2746 int32_t ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2747 { 2748 uint32_t status; 2749 uint16_t reg; 2750 2751 if (!on && ixgbe_mng_present(hw)) 2752 return 0; 2753 2754 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2755 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2756 ®); 2757 if (status) 2758 return status; 2759 2760 if (on) { 2761 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2762 } else { 2763 if (ixgbe_check_reset_blocked(hw)) 2764 return 0; 2765 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2766 } 2767 2768 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2769 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2770 reg); 2771 return status; 2772 } 2773