1 /* $OpenBSD: ixgbe_phy.c,v 1.13 2015/04/30 13:24:36 sthen Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2013, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /* FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c 251964 Jun 18 21:28:19 2013 UTC */ 36 37 #include <dev/pci/ixgbe.h> 38 39 void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 int32_t ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, uint8_t *data); 42 int32_t ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, uint8_t data); 43 int32_t ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, int *data); 45 int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, int data); 46 void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl); 47 void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl); 48 int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, int data); 49 int ixgbe_get_i2c_data(uint32_t *i2cctl); 50 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 54 * @hw: pointer to the hardware structure 55 * 56 * Initialize the function pointers. 57 **/ 58 int32_t ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_phy_info *phy = &hw->phy; 61 62 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 63 64 /* PHY */ 65 phy->ops.identify = &ixgbe_identify_phy_generic; 66 phy->ops.reset = &ixgbe_reset_phy_generic; 67 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 68 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 69 phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi; 70 phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi; 71 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 72 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 73 phy->ops.check_link = NULL; 74 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 75 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 76 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 77 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 78 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 79 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 80 phy->ops.identify_sfp = &ixgbe_identify_module_generic; 81 phy->sfp_type = ixgbe_sfp_type_unknown; 82 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; 83 return IXGBE_SUCCESS; 84 } 85 86 /** 87 * ixgbe_identify_phy_generic - Get physical layer module 88 * @hw: pointer to hardware structure 89 * 90 * Determines the physical layer module found on the current adapter. 91 **/ 92 int32_t ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 93 { 94 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 95 uint32_t phy_addr; 96 uint16_t ext_ability = 0; 97 98 DEBUGFUNC("ixgbe_identify_phy_generic"); 99 100 if (hw->phy.type == ixgbe_phy_unknown) { 101 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 102 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 103 hw->phy.addr = phy_addr; 104 ixgbe_get_phy_id(hw); 105 hw->phy.type = 106 ixgbe_get_phy_type_from_id(hw->phy.id); 107 108 if (hw->phy.type == ixgbe_phy_unknown) { 109 hw->phy.ops.read_reg(hw, 110 IXGBE_MDIO_PHY_EXT_ABILITY, 111 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 112 &ext_ability); 113 if (ext_ability & 114 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 115 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 116 hw->phy.type = 117 ixgbe_phy_cu_unknown; 118 else 119 hw->phy.type = 120 ixgbe_phy_generic; 121 } 122 123 status = IXGBE_SUCCESS; 124 break; 125 } 126 } 127 /* clear value if nothing found */ 128 if (status != IXGBE_SUCCESS) { 129 hw->phy.addr = 0; 130 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 131 "Could not identify valid PHY address"); 132 } 133 } else { 134 status = IXGBE_SUCCESS; 135 } 136 137 return status; 138 } 139 140 /** 141 * ixgbe_validate_phy_addr - Determines phy address is valid 142 * @hw: pointer to hardware structure 143 * 144 **/ 145 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr) 146 { 147 uint16_t phy_id = 0; 148 bool valid = FALSE; 149 150 DEBUGFUNC("ixgbe_validate_phy_addr"); 151 152 hw->phy.addr = phy_addr; 153 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 154 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 155 156 if (phy_id != 0xFFFF && phy_id != 0x0) 157 valid = TRUE; 158 159 return valid; 160 } 161 162 /** 163 * ixgbe_get_phy_id - Get the phy type 164 * @hw: pointer to hardware structure 165 * 166 **/ 167 int32_t ixgbe_get_phy_id(struct ixgbe_hw *hw) 168 { 169 uint32_t status; 170 uint16_t phy_id_high = 0; 171 uint16_t phy_id_low = 0; 172 173 DEBUGFUNC("ixgbe_get_phy_id"); 174 175 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 176 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 177 &phy_id_high); 178 179 if (status == IXGBE_SUCCESS) { 180 hw->phy.id = (uint32_t)(phy_id_high << 16); 181 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 182 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 183 &phy_id_low); 184 hw->phy.id |= (uint32_t)(phy_id_low & IXGBE_PHY_REVISION_MASK); 185 hw->phy.revision = (uint32_t)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 186 } 187 return status; 188 } 189 190 /** 191 * ixgbe_get_phy_type_from_id - Get the phy type 192 * @hw: pointer to hardware structure 193 * 194 **/ 195 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(uint32_t phy_id) 196 { 197 enum ixgbe_phy_type phy_type; 198 199 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 200 201 switch (phy_id) { 202 case TN1010_PHY_ID: 203 phy_type = ixgbe_phy_tn; 204 break; 205 case X540_PHY_ID: 206 phy_type = ixgbe_phy_aq; 207 break; 208 case QT2022_PHY_ID: 209 phy_type = ixgbe_phy_qt; 210 break; 211 case ATH_PHY_ID: 212 phy_type = ixgbe_phy_nl; 213 break; 214 default: 215 phy_type = ixgbe_phy_unknown; 216 break; 217 } 218 219 DEBUGOUT1("phy type found is %d\n", phy_type); 220 return phy_type; 221 } 222 223 /** 224 * ixgbe_reset_phy_generic - Performs a PHY reset 225 * @hw: pointer to hardware structure 226 **/ 227 int32_t ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 228 { 229 uint32_t i; 230 uint16_t ctrl = 0; 231 int32_t status = IXGBE_SUCCESS; 232 233 DEBUGFUNC("ixgbe_reset_phy_generic"); 234 235 if (hw->phy.type == ixgbe_phy_unknown) 236 status = ixgbe_identify_phy_generic(hw); 237 238 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 239 goto out; 240 241 /* Don't reset PHY if it's shut down due to overtemp. */ 242 if (!hw->phy.reset_if_overtemp && 243 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 244 goto out; 245 246 /* 247 * Perform soft PHY reset to the PHY_XS. 248 * This will cause a soft reset to the PHY 249 */ 250 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 251 IXGBE_MDIO_PHY_XS_DEV_TYPE, 252 IXGBE_MDIO_PHY_XS_RESET); 253 254 /* 255 * Poll for reset bit to self-clear indicating reset is complete. 256 * Some PHYs could take up to 3 seconds to complete and need about 257 * 1.7 usec delay after the reset is complete. 258 */ 259 for (i = 0; i < 30; i++) { 260 msec_delay(100); 261 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 262 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 263 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 264 usec_delay(2); 265 break; 266 } 267 } 268 269 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 270 status = IXGBE_ERR_RESET_FAILED; 271 ERROR_REPORT1(IXGBE_ERROR_POLLING, 272 "PHY reset polling failed to complete.\n"); 273 } 274 275 out: 276 return status; 277 } 278 279 /** 280 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 281 * the SWFW lock 282 * @hw: pointer to hardware structure 283 * @reg_addr: 32 bit address of PHY register to read 284 * @phy_data: Pointer to read data from PHY register 285 **/ 286 int32_t ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr, 287 uint32_t device_type, uint16_t *phy_data) 288 { 289 uint32_t i, data, command; 290 291 /* Setup and write the address cycle command */ 292 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 293 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 294 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 295 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 296 297 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 298 299 /* 300 * Check every 10 usec to see if the address cycle completed. 301 * The MDI Command bit will clear when the operation is 302 * complete 303 */ 304 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 305 usec_delay(10); 306 307 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 308 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 309 break; 310 } 311 312 313 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 314 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 315 return IXGBE_ERR_PHY; 316 } 317 318 /* 319 * Address cycle complete, setup and write the read 320 * command 321 */ 322 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 323 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 324 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 325 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 326 327 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 328 329 /* 330 * Check every 10 usec to see if the address cycle 331 * completed. The MDI Command bit will clear when the 332 * operation is complete 333 */ 334 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 335 usec_delay(10); 336 337 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 338 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 339 break; 340 } 341 342 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 343 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 344 return IXGBE_ERR_PHY; 345 } 346 347 /* 348 * Read operation is complete. Get the data 349 * from MSRWD 350 */ 351 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 352 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 353 *phy_data = (uint16_t)(data); 354 355 return IXGBE_SUCCESS; 356 } 357 358 /** 359 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 360 * using the SWFW lock - this function is needed in most cases 361 * @hw: pointer to hardware structure 362 * @reg_addr: 32 bit address of PHY register to read 363 * @phy_data: Pointer to read data from PHY register 364 **/ 365 int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, 366 uint32_t device_type, uint16_t *phy_data) 367 { 368 int32_t status; 369 uint16_t gssr; 370 371 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 372 373 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 374 gssr = IXGBE_GSSR_PHY1_SM; 375 else 376 gssr = IXGBE_GSSR_PHY0_SM; 377 378 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 379 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 380 phy_data); 381 hw->mac.ops.release_swfw_sync(hw, gssr); 382 } else { 383 status = IXGBE_ERR_SWFW_SYNC; 384 } 385 386 return status; 387 } 388 389 /** 390 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 391 * without SWFW lock 392 * @hw: pointer to hardware structure 393 * @reg_addr: 32 bit PHY register to write 394 * @device_type: 5 bit device type 395 * @phy_data: Data to write to the PHY register 396 **/ 397 int32_t ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr, 398 uint32_t device_type, uint16_t phy_data) 399 { 400 uint32_t i, command; 401 402 /* Put the data in the MDI single read and write data register*/ 403 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (uint32_t)phy_data); 404 405 /* Setup and write the address cycle command */ 406 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 407 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 408 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 409 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 410 411 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 412 413 /* 414 * Check every 10 usec to see if the address cycle completed. 415 * The MDI Command bit will clear when the operation is 416 * complete 417 */ 418 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 419 usec_delay(10); 420 421 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 422 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 423 break; 424 } 425 426 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 427 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 428 return IXGBE_ERR_PHY; 429 } 430 431 /* 432 * Address cycle complete, setup and write the write 433 * command 434 */ 435 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 436 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 437 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 438 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 439 440 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 441 442 /* 443 * Check every 10 usec to see if the address cycle 444 * completed. The MDI Command bit will clear when the 445 * operation is complete 446 */ 447 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 448 usec_delay(10); 449 450 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 451 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 452 break; 453 } 454 455 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 456 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 457 return IXGBE_ERR_PHY; 458 } 459 460 return IXGBE_SUCCESS; 461 } 462 463 /** 464 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 465 * using SWFW lock- this function is needed in most cases 466 * @hw: pointer to hardware structure 467 * @reg_addr: 32 bit PHY register to write 468 * @device_type: 5 bit device type 469 * @phy_data: Data to write to the PHY register 470 **/ 471 int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, 472 uint32_t device_type, uint16_t phy_data) 473 { 474 int32_t status; 475 uint16_t gssr; 476 477 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 478 479 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 480 gssr = IXGBE_GSSR_PHY1_SM; 481 else 482 gssr = IXGBE_GSSR_PHY0_SM; 483 484 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 485 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 486 phy_data); 487 hw->mac.ops.release_swfw_sync(hw, gssr); 488 } else { 489 status = IXGBE_ERR_SWFW_SYNC; 490 } 491 492 return status; 493 } 494 495 /** 496 * ixgbe_setup_phy_link_generic - Set and restart autoneg 497 * @hw: pointer to hardware structure 498 * 499 * Restart autonegotiation and PHY and waits for completion. 500 **/ 501 int32_t ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 502 { 503 int32_t status = IXGBE_SUCCESS; 504 uint32_t time_out; 505 uint32_t max_time_out = 10; 506 uint16_t autoneg_reg = IXGBE_MII_AUTONEG_REG; 507 bool autoneg = FALSE; 508 ixgbe_link_speed speed; 509 510 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 511 512 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 513 514 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 515 /* Set or unset auto-negotiation 10G advertisement */ 516 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 517 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 518 &autoneg_reg); 519 520 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 521 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 522 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 523 524 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 525 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 526 autoneg_reg); 527 } 528 529 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 530 /* Set or unset auto-negotiation 1G advertisement */ 531 hw->phy.ops.read_reg(hw, 532 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 533 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 534 &autoneg_reg); 535 536 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 537 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 538 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 539 540 hw->phy.ops.write_reg(hw, 541 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 542 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 543 autoneg_reg); 544 } 545 546 if (speed & IXGBE_LINK_SPEED_100_FULL) { 547 /* Set or unset auto-negotiation 100M advertisement */ 548 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 549 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 550 &autoneg_reg); 551 552 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 553 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 554 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 555 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 556 557 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 558 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 559 autoneg_reg); 560 } 561 562 /* Restart PHY autonegotiation and wait for completion */ 563 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 564 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 565 566 autoneg_reg |= IXGBE_MII_RESTART; 567 568 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 569 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 570 571 /* Wait for autonegotiation to finish */ 572 for (time_out = 0; time_out < max_time_out; time_out++) { 573 usec_delay(10); 574 /* Restart PHY autonegotiation and wait for completion */ 575 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 576 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 577 &autoneg_reg); 578 579 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 580 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 581 break; 582 } 583 584 if (time_out == max_time_out) { 585 status = IXGBE_ERR_LINK_SETUP; 586 ERROR_REPORT1(IXGBE_ERROR_POLLING, 587 "PHY autonegotiation time out"); 588 } 589 590 return status; 591 } 592 593 /** 594 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 595 * @hw: pointer to hardware structure 596 * @speed: new link speed 597 **/ 598 int32_t ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 599 ixgbe_link_speed speed, 600 bool autoneg_wait_to_complete) 601 { 602 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 603 604 /* 605 * Clear autoneg_advertised and set new values based on input link 606 * speed. 607 */ 608 hw->phy.autoneg_advertised = 0; 609 610 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 611 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 612 613 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 614 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 615 616 if (speed & IXGBE_LINK_SPEED_100_FULL) 617 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 618 619 /* Setup link based on the new speed settings */ 620 hw->phy.ops.setup_link(hw); 621 622 return IXGBE_SUCCESS; 623 } 624 625 /** 626 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 627 * @hw: pointer to hardware structure 628 * @speed: pointer to link speed 629 * @autoneg: boolean auto-negotiation value 630 * 631 * Determines the link capabilities by reading the AUTOC register. 632 **/ 633 int32_t ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 634 ixgbe_link_speed *speed, 635 bool *autoneg) 636 { 637 int32_t status = IXGBE_ERR_LINK_SETUP; 638 uint16_t speed_ability; 639 640 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 641 642 *speed = 0; 643 *autoneg = TRUE; 644 645 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 646 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 647 &speed_ability); 648 649 if (status == IXGBE_SUCCESS) { 650 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 651 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 652 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 653 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 654 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 655 *speed |= IXGBE_LINK_SPEED_100_FULL; 656 } 657 658 return status; 659 } 660 661 /** 662 * ixgbe_check_phy_link_tnx - Determine link and speed status 663 * @hw: pointer to hardware structure 664 * 665 * Reads the VS1 register to determine if link is up and the current speed for 666 * the PHY. 667 **/ 668 int32_t ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 669 bool *link_up) 670 { 671 int32_t status = IXGBE_SUCCESS; 672 uint32_t time_out; 673 uint32_t max_time_out = 10; 674 uint16_t phy_link = 0; 675 uint16_t phy_speed = 0; 676 uint16_t phy_data = 0; 677 678 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 679 680 /* Initialize speed and link to default case */ 681 *link_up = FALSE; 682 *speed = IXGBE_LINK_SPEED_10GB_FULL; 683 684 /* 685 * Check current speed and link status of the PHY register. 686 * This is a vendor specific register and may have to 687 * be changed for other copper PHYs. 688 */ 689 for (time_out = 0; time_out < max_time_out; time_out++) { 690 usec_delay(10); 691 status = hw->phy.ops.read_reg(hw, 692 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 693 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 694 &phy_data); 695 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 696 phy_speed = phy_data & 697 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 698 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 699 *link_up = TRUE; 700 if (phy_speed == 701 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 702 *speed = IXGBE_LINK_SPEED_1GB_FULL; 703 break; 704 } 705 } 706 707 return status; 708 } 709 710 /** 711 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 712 * @hw: pointer to hardware structure 713 * 714 * Restart autonegotiation and PHY and waits for completion. 715 **/ 716 int32_t ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 717 { 718 int32_t status = IXGBE_SUCCESS; 719 uint32_t time_out; 720 uint32_t max_time_out = 10; 721 uint16_t autoneg_reg = IXGBE_MII_AUTONEG_REG; 722 bool autoneg = FALSE; 723 ixgbe_link_speed speed; 724 725 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 726 727 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 728 729 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 730 /* Set or unset auto-negotiation 10G advertisement */ 731 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 732 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 733 &autoneg_reg); 734 735 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 736 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 737 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 738 739 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 740 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 741 autoneg_reg); 742 } 743 744 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 745 /* Set or unset auto-negotiation 1G advertisement */ 746 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 747 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 748 &autoneg_reg); 749 750 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 751 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 752 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 753 754 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 755 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 756 autoneg_reg); 757 } 758 759 if (speed & IXGBE_LINK_SPEED_100_FULL) { 760 /* Set or unset auto-negotiation 100M advertisement */ 761 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 762 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 763 &autoneg_reg); 764 765 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 766 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 767 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 768 769 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 770 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 771 autoneg_reg); 772 } 773 774 /* Restart PHY autonegotiation and wait for completion */ 775 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 776 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 777 778 autoneg_reg |= IXGBE_MII_RESTART; 779 780 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 781 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 782 783 /* Wait for autonegotiation to finish */ 784 for (time_out = 0; time_out < max_time_out; time_out++) { 785 usec_delay(10); 786 /* Restart PHY autonegotiation and wait for completion */ 787 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 788 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 789 &autoneg_reg); 790 791 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 792 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 793 break; 794 } 795 796 if (time_out == max_time_out) { 797 status = IXGBE_ERR_LINK_SETUP; 798 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 799 } 800 801 return status; 802 } 803 804 /** 805 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 806 * @hw: pointer to hardware structure 807 * @firmware_version: pointer to the PHY Firmware Version 808 **/ 809 int32_t ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 810 uint16_t *firmware_version) 811 { 812 int32_t status = IXGBE_SUCCESS; 813 814 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 815 816 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 817 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 818 firmware_version); 819 820 return status; 821 } 822 823 /** 824 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 825 * @hw: pointer to hardware structure 826 * @firmware_version: pointer to the PHY Firmware Version 827 **/ 828 int32_t ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 829 uint16_t *firmware_version) 830 { 831 int32_t status = IXGBE_SUCCESS; 832 833 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 834 835 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 836 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 837 firmware_version); 838 839 return status; 840 } 841 842 /** 843 * ixgbe_reset_phy_nl - Performs a PHY reset 844 * @hw: pointer to hardware structure 845 **/ 846 int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 847 { 848 uint16_t phy_offset, control, eword, edata, block_crc; 849 bool end_data = FALSE; 850 uint16_t list_offset, data_offset; 851 uint16_t phy_data = 0; 852 int32_t ret_val = IXGBE_SUCCESS; 853 uint32_t i; 854 855 DEBUGFUNC("ixgbe_reset_phy_nl"); 856 857 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 858 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 859 860 /* reset the PHY and poll for completion */ 861 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 862 IXGBE_MDIO_PHY_XS_DEV_TYPE, 863 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 864 865 for (i = 0; i < 100; i++) { 866 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 867 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 868 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 869 break; 870 msec_delay(10); 871 } 872 873 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 874 DEBUGOUT("PHY reset did not complete.\n"); 875 ret_val = IXGBE_ERR_PHY; 876 goto out; 877 } 878 879 /* Get init offsets */ 880 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 881 &data_offset); 882 if (ret_val != IXGBE_SUCCESS) 883 goto out; 884 885 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 886 data_offset++; 887 while (!end_data) { 888 /* 889 * Read control word from PHY init contents offset 890 */ 891 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 892 if (ret_val) 893 goto err_eeprom; 894 control = (eword & IXGBE_CONTROL_MASK_NL) >> 895 IXGBE_CONTROL_SHIFT_NL; 896 edata = eword & IXGBE_DATA_MASK_NL; 897 switch (control) { 898 case IXGBE_DELAY_NL: 899 data_offset++; 900 DEBUGOUT1("DELAY: %d MS\n", edata); 901 msec_delay(edata); 902 break; 903 case IXGBE_DATA_NL: 904 DEBUGOUT("DATA:\n"); 905 data_offset++; 906 ret_val = hw->eeprom.ops.read(hw, data_offset, 907 &phy_offset); 908 if (ret_val) 909 goto err_eeprom; 910 data_offset++; 911 for (i = 0; i < edata; i++) { 912 ret_val = hw->eeprom.ops.read(hw, data_offset, 913 &eword); 914 if (ret_val) 915 goto err_eeprom; 916 hw->phy.ops.write_reg(hw, phy_offset, 917 IXGBE_TWINAX_DEV, eword); 918 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 919 phy_offset); 920 data_offset++; 921 phy_offset++; 922 } 923 break; 924 case IXGBE_CONTROL_NL: 925 data_offset++; 926 DEBUGOUT("CONTROL:\n"); 927 if (edata == IXGBE_CONTROL_EOL_NL) { 928 DEBUGOUT("EOL\n"); 929 end_data = TRUE; 930 } else if (edata == IXGBE_CONTROL_SOL_NL) { 931 DEBUGOUT("SOL\n"); 932 } else { 933 DEBUGOUT("Bad control value\n"); 934 ret_val = IXGBE_ERR_PHY; 935 goto out; 936 } 937 break; 938 default: 939 DEBUGOUT("Bad control type\n"); 940 ret_val = IXGBE_ERR_PHY; 941 goto out; 942 } 943 } 944 945 out: 946 return ret_val; 947 948 err_eeprom: 949 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 950 "eeprom read at offset %d failed", data_offset); 951 return IXGBE_ERR_PHY; 952 } 953 954 /** 955 * ixgbe_identify_module_generic - Identifies module type 956 * @hw: pointer to hardware structure 957 * 958 * Determines HW type and calls appropriate function. 959 **/ 960 int32_t ixgbe_identify_module_generic(struct ixgbe_hw *hw) 961 { 962 int32_t status = IXGBE_ERR_SFP_NOT_PRESENT; 963 964 DEBUGFUNC("ixgbe_identify_module_generic"); 965 966 switch (hw->mac.ops.get_media_type(hw)) { 967 case ixgbe_media_type_fiber: 968 status = ixgbe_identify_sfp_module_generic(hw); 969 break; 970 971 972 default: 973 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 974 status = IXGBE_ERR_SFP_NOT_PRESENT; 975 break; 976 } 977 978 return status; 979 } 980 981 /** 982 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 983 * @hw: pointer to hardware structure 984 * 985 * Searches for and identifies the SFP module and assigns appropriate PHY type. 986 **/ 987 int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 988 { 989 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 990 uint32_t vendor_oui = 0; 991 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 992 uint8_t identifier = 0; 993 uint8_t comp_codes_1g = 0; 994 uint8_t comp_codes_10g = 0; 995 uint8_t oui_bytes[3] = {0, 0, 0}; 996 uint8_t cable_tech = 0; 997 uint8_t cable_spec = 0; 998 999 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1000 1001 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1002 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1003 status = IXGBE_ERR_SFP_NOT_PRESENT; 1004 goto out; 1005 } 1006 1007 status = hw->phy.ops.read_i2c_eeprom(hw, 1008 IXGBE_SFF_IDENTIFIER, 1009 &identifier); 1010 1011 if (status != IXGBE_SUCCESS) 1012 goto err_read_i2c_eeprom; 1013 1014 /* LAN ID is needed for sfp_type determination */ 1015 hw->mac.ops.set_lan_id(hw); 1016 1017 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1018 hw->phy.type = ixgbe_phy_sfp_unsupported; 1019 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1020 } else { 1021 status = hw->phy.ops.read_i2c_eeprom(hw, 1022 IXGBE_SFF_1GBE_COMP_CODES, 1023 &comp_codes_1g); 1024 1025 if (status != IXGBE_SUCCESS) 1026 goto err_read_i2c_eeprom; 1027 1028 status = hw->phy.ops.read_i2c_eeprom(hw, 1029 IXGBE_SFF_10GBE_COMP_CODES, 1030 &comp_codes_10g); 1031 1032 if (status != IXGBE_SUCCESS) 1033 goto err_read_i2c_eeprom; 1034 status = hw->phy.ops.read_i2c_eeprom(hw, 1035 IXGBE_SFF_CABLE_TECHNOLOGY, 1036 &cable_tech); 1037 1038 if (status != IXGBE_SUCCESS) 1039 goto err_read_i2c_eeprom; 1040 1041 /* ID Module 1042 * ========= 1043 * 0 SFP_DA_CU 1044 * 1 SFP_SR 1045 * 2 SFP_LR 1046 * 3 SFP_DA_CORE0 - 82599-specific 1047 * 4 SFP_DA_CORE1 - 82599-specific 1048 * 5 SFP_SR/LR_CORE0 - 82599-specific 1049 * 6 SFP_SR/LR_CORE1 - 82599-specific 1050 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1051 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1052 * 9 SFP_1g_cu_CORE0 - 82599-specific 1053 * 10 SFP_1g_cu_CORE1 - 82599-specific 1054 * 11 SFP_1g_sx_CORE0 - 82599-specific 1055 * 12 SFP_1g_sx_CORE1 - 82599-specific 1056 */ 1057 if (hw->mac.type == ixgbe_mac_82598EB) { 1058 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1059 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1060 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1061 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1062 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1063 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1064 else if (comp_codes_10g & IXGBE_SFF_DA_BAD_HP_CABLE) 1065 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1066 else 1067 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1068 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1069 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1070 if (hw->bus.lan_id == 0) 1071 hw->phy.sfp_type = 1072 ixgbe_sfp_type_da_cu_core0; 1073 else 1074 hw->phy.sfp_type = 1075 ixgbe_sfp_type_da_cu_core1; 1076 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1077 hw->phy.ops.read_i2c_eeprom( 1078 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1079 &cable_spec); 1080 if (cable_spec & 1081 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1082 if (hw->bus.lan_id == 0) 1083 hw->phy.sfp_type = 1084 ixgbe_sfp_type_da_act_lmt_core0; 1085 else 1086 hw->phy.sfp_type = 1087 ixgbe_sfp_type_da_act_lmt_core1; 1088 } else { 1089 hw->phy.sfp_type = 1090 ixgbe_sfp_type_unknown; 1091 } 1092 } else if (comp_codes_10g & 1093 (IXGBE_SFF_10GBASESR_CAPABLE | 1094 IXGBE_SFF_10GBASELR_CAPABLE)) { 1095 if (hw->bus.lan_id == 0) 1096 hw->phy.sfp_type = 1097 ixgbe_sfp_type_srlr_core0; 1098 else 1099 hw->phy.sfp_type = 1100 ixgbe_sfp_type_srlr_core1; 1101 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1102 if (hw->bus.lan_id == 0) 1103 hw->phy.sfp_type = 1104 ixgbe_sfp_type_1g_cu_core0; 1105 else 1106 hw->phy.sfp_type = 1107 ixgbe_sfp_type_1g_cu_core1; 1108 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1109 if (hw->bus.lan_id == 0) 1110 hw->phy.sfp_type = 1111 ixgbe_sfp_type_1g_sx_core0; 1112 else 1113 hw->phy.sfp_type = 1114 ixgbe_sfp_type_1g_sx_core1; 1115 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1116 if (hw->bus.lan_id == 0) 1117 hw->phy.sfp_type = 1118 ixgbe_sfp_type_1g_lx_core0; 1119 else 1120 hw->phy.sfp_type = 1121 ixgbe_sfp_type_1g_lx_core1; 1122 } else { 1123 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1124 } 1125 } 1126 1127 if (hw->phy.sfp_type != stored_sfp_type) 1128 hw->phy.sfp_setup_needed = TRUE; 1129 1130 /* Determine if the SFP+ PHY is dual speed or not. */ 1131 hw->phy.multispeed_fiber = FALSE; 1132 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1133 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1134 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1135 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1136 hw->phy.multispeed_fiber = TRUE; 1137 1138 /* Determine PHY vendor */ 1139 if (hw->phy.type != ixgbe_phy_nl) { 1140 hw->phy.id = identifier; 1141 status = hw->phy.ops.read_i2c_eeprom(hw, 1142 IXGBE_SFF_VENDOR_OUI_BYTE0, 1143 &oui_bytes[0]); 1144 1145 if (status != IXGBE_SUCCESS) 1146 goto err_read_i2c_eeprom; 1147 1148 status = hw->phy.ops.read_i2c_eeprom(hw, 1149 IXGBE_SFF_VENDOR_OUI_BYTE1, 1150 &oui_bytes[1]); 1151 1152 if (status != IXGBE_SUCCESS) 1153 goto err_read_i2c_eeprom; 1154 1155 status = hw->phy.ops.read_i2c_eeprom(hw, 1156 IXGBE_SFF_VENDOR_OUI_BYTE2, 1157 &oui_bytes[2]); 1158 1159 if (status != IXGBE_SUCCESS) 1160 goto err_read_i2c_eeprom; 1161 1162 vendor_oui = 1163 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1164 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1165 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1166 1167 switch (vendor_oui) { 1168 case IXGBE_SFF_VENDOR_OUI_TYCO: 1169 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1170 hw->phy.type = 1171 ixgbe_phy_sfp_passive_tyco; 1172 break; 1173 case IXGBE_SFF_VENDOR_OUI_FTL: 1174 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1175 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1176 else 1177 hw->phy.type = ixgbe_phy_sfp_ftl; 1178 break; 1179 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1180 hw->phy.type = ixgbe_phy_sfp_avago; 1181 break; 1182 case IXGBE_SFF_VENDOR_OUI_INTEL: 1183 hw->phy.type = ixgbe_phy_sfp_intel; 1184 break; 1185 default: 1186 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1187 hw->phy.type = 1188 ixgbe_phy_sfp_passive_unknown; 1189 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1190 hw->phy.type = 1191 ixgbe_phy_sfp_active_unknown; 1192 else 1193 hw->phy.type = ixgbe_phy_sfp_unknown; 1194 break; 1195 } 1196 } 1197 1198 /* Allow any DA cable vendor */ 1199 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1200 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1201 status = IXGBE_SUCCESS; 1202 goto out; 1203 } 1204 1205 /* Verify supported 1G SFP modules */ 1206 if (comp_codes_10g == 0 && 1207 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1208 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1209 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1210 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1211 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1212 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1213 hw->phy.type = ixgbe_phy_sfp_unsupported; 1214 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1215 goto out; 1216 } 1217 1218 /* 1219 * We do not limit the definition of "supported SPF modules" 1220 * to the vendor/make whitelist. 1221 */ 1222 status = IXGBE_SUCCESS; 1223 } 1224 1225 out: 1226 return status; 1227 1228 err_read_i2c_eeprom: 1229 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1230 if (hw->phy.type != ixgbe_phy_nl) { 1231 hw->phy.id = 0; 1232 hw->phy.type = ixgbe_phy_unknown; 1233 } 1234 return IXGBE_ERR_SFP_NOT_PRESENT; 1235 } 1236 1237 /** 1238 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1239 * @hw: pointer to hardware structure 1240 * @list_offset: offset to the SFP ID list 1241 * @data_offset: offset to the SFP data block 1242 * 1243 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1244 * so it returns the offsets to the phy init sequence block. 1245 **/ 1246 int32_t ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1247 uint16_t *list_offset, 1248 uint16_t *data_offset) 1249 { 1250 uint16_t sfp_id; 1251 uint16_t sfp_type = hw->phy.sfp_type; 1252 1253 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1254 1255 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1256 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1257 1258 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1259 return IXGBE_ERR_SFP_NOT_PRESENT; 1260 1261 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1262 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1263 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1264 1265 /* 1266 * Limiting active cables and 1G Phys must be initialized as 1267 * SR modules 1268 */ 1269 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1270 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1271 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1272 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1273 sfp_type = ixgbe_sfp_type_srlr_core0; 1274 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1275 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1276 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1277 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1278 sfp_type = ixgbe_sfp_type_srlr_core1; 1279 1280 /* Read offset to PHY init contents */ 1281 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1282 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1283 "eeprom read at offset %d failed", 1284 IXGBE_PHY_INIT_OFFSET_NL); 1285 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1286 } 1287 1288 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1289 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1290 1291 /* Shift offset to first ID word */ 1292 (*list_offset)++; 1293 1294 /* 1295 * Find the matching SFP ID in the EEPROM 1296 * and program the init sequence 1297 */ 1298 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1299 goto err_phy; 1300 1301 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1302 if (sfp_id == sfp_type) { 1303 (*list_offset)++; 1304 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1305 goto err_phy; 1306 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1307 DEBUGOUT("SFP+ module not supported\n"); 1308 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1309 } else { 1310 break; 1311 } 1312 } else { 1313 (*list_offset) += 2; 1314 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1315 goto err_phy; 1316 } 1317 } 1318 1319 /* 1320 * the 82598EB SFP+ card offically supports only direct attached cables 1321 * but works fine with optical SFP+ modules as well. Even though the 1322 * EEPROM has no matching ID for them. So just accept the module. 1323 */ 1324 if (sfp_id == IXGBE_PHY_INIT_END_NL && 1325 hw->mac.type == ixgbe_mac_82598EB) { 1326 /* refetch offset for the first phy entry */ 1327 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1328 (*list_offset) += 2; 1329 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1330 } else if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1331 DEBUGOUT("No matching SFP+ module found\n"); 1332 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1333 } 1334 1335 return IXGBE_SUCCESS; 1336 1337 err_phy: 1338 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1339 "eeprom read at offset %d failed", *list_offset); 1340 return IXGBE_ERR_PHY; 1341 } 1342 1343 /** 1344 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1345 * @hw: pointer to hardware structure 1346 * @byte_offset: EEPROM byte offset to read 1347 * @eeprom_data: value read 1348 * 1349 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1350 **/ 1351 int32_t ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1352 uint8_t *eeprom_data) 1353 { 1354 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1355 1356 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1357 IXGBE_I2C_EEPROM_DEV_ADDR, 1358 eeprom_data); 1359 } 1360 1361 /** 1362 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1363 * @hw: pointer to hardware structure 1364 * @byte_offset: EEPROM byte offset to write 1365 * @eeprom_data: value to write 1366 * 1367 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1368 **/ 1369 int32_t ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1370 uint8_t eeprom_data) 1371 { 1372 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1373 1374 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1375 IXGBE_I2C_EEPROM_DEV_ADDR, 1376 eeprom_data); 1377 } 1378 1379 /** 1380 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1381 * @hw: pointer to hardware structure 1382 * @byte_offset: byte offset to read 1383 * @data: value read 1384 * 1385 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1386 * a specified device address. 1387 **/ 1388 int32_t ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1389 uint8_t dev_addr, uint8_t *data) 1390 { 1391 int32_t status = IXGBE_SUCCESS; 1392 uint32_t max_retry = 10; 1393 uint32_t retry = 0; 1394 uint16_t swfw_mask = 0; 1395 int nack = 1; 1396 *data = 0; 1397 1398 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1399 1400 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1401 swfw_mask = IXGBE_GSSR_PHY1_SM; 1402 else 1403 swfw_mask = IXGBE_GSSR_PHY0_SM; 1404 1405 do { 1406 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 1407 != IXGBE_SUCCESS) { 1408 status = IXGBE_ERR_SWFW_SYNC; 1409 goto read_byte_out; 1410 } 1411 1412 ixgbe_i2c_start(hw); 1413 1414 /* Device Address and write indication */ 1415 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1416 if (status != IXGBE_SUCCESS) 1417 goto fail; 1418 1419 status = ixgbe_get_i2c_ack(hw); 1420 if (status != IXGBE_SUCCESS) 1421 goto fail; 1422 1423 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1424 if (status != IXGBE_SUCCESS) 1425 goto fail; 1426 1427 status = ixgbe_get_i2c_ack(hw); 1428 if (status != IXGBE_SUCCESS) 1429 goto fail; 1430 1431 ixgbe_i2c_start(hw); 1432 1433 /* Device Address and read indication */ 1434 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1435 if (status != IXGBE_SUCCESS) 1436 goto fail; 1437 1438 status = ixgbe_get_i2c_ack(hw); 1439 if (status != IXGBE_SUCCESS) 1440 goto fail; 1441 1442 status = ixgbe_clock_in_i2c_byte(hw, data); 1443 if (status != IXGBE_SUCCESS) 1444 goto fail; 1445 1446 status = ixgbe_clock_out_i2c_bit(hw, nack); 1447 if (status != IXGBE_SUCCESS) 1448 goto fail; 1449 1450 ixgbe_i2c_stop(hw); 1451 break; 1452 1453 fail: 1454 ixgbe_i2c_bus_clear(hw); 1455 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1456 msec_delay(100); 1457 retry++; 1458 if (retry < max_retry) 1459 DEBUGOUT("I2C byte read error - Retrying.\n"); 1460 else 1461 DEBUGOUT("I2C byte read error.\n"); 1462 1463 } while (retry < max_retry); 1464 1465 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1466 1467 read_byte_out: 1468 return status; 1469 } 1470 1471 /** 1472 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1473 * @hw: pointer to hardware structure 1474 * @byte_offset: byte offset to write 1475 * @data: value to write 1476 * 1477 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1478 * a specified device address. 1479 **/ 1480 int32_t ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1481 uint8_t dev_addr, uint8_t data) 1482 { 1483 int32_t status = IXGBE_SUCCESS; 1484 uint32_t max_retry = 1; 1485 uint32_t retry = 0; 1486 uint16_t swfw_mask = 0; 1487 1488 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1489 1490 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1491 swfw_mask = IXGBE_GSSR_PHY1_SM; 1492 else 1493 swfw_mask = IXGBE_GSSR_PHY0_SM; 1494 1495 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1496 status = IXGBE_ERR_SWFW_SYNC; 1497 goto write_byte_out; 1498 } 1499 1500 do { 1501 ixgbe_i2c_start(hw); 1502 1503 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1504 if (status != IXGBE_SUCCESS) 1505 goto fail; 1506 1507 status = ixgbe_get_i2c_ack(hw); 1508 if (status != IXGBE_SUCCESS) 1509 goto fail; 1510 1511 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1512 if (status != IXGBE_SUCCESS) 1513 goto fail; 1514 1515 status = ixgbe_get_i2c_ack(hw); 1516 if (status != IXGBE_SUCCESS) 1517 goto fail; 1518 1519 status = ixgbe_clock_out_i2c_byte(hw, data); 1520 if (status != IXGBE_SUCCESS) 1521 goto fail; 1522 1523 status = ixgbe_get_i2c_ack(hw); 1524 if (status != IXGBE_SUCCESS) 1525 goto fail; 1526 1527 ixgbe_i2c_stop(hw); 1528 break; 1529 1530 fail: 1531 ixgbe_i2c_bus_clear(hw); 1532 retry++; 1533 if (retry < max_retry) 1534 DEBUGOUT("I2C byte write error - Retrying.\n"); 1535 else 1536 DEBUGOUT("I2C byte write error.\n"); 1537 } while (retry < max_retry); 1538 1539 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1540 1541 write_byte_out: 1542 return status; 1543 } 1544 1545 /** 1546 * ixgbe_i2c_start - Sets I2C start condition 1547 * @hw: pointer to hardware structure 1548 * 1549 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1550 **/ 1551 void ixgbe_i2c_start(struct ixgbe_hw *hw) 1552 { 1553 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1554 1555 DEBUGFUNC("ixgbe_i2c_start"); 1556 1557 /* Start condition must begin with data and clock high */ 1558 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1559 ixgbe_raise_i2c_clk(hw, &i2cctl); 1560 1561 /* Setup time for start condition (4.7us) */ 1562 usec_delay(IXGBE_I2C_T_SU_STA); 1563 1564 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1565 1566 /* Hold time for start condition (4us) */ 1567 usec_delay(IXGBE_I2C_T_HD_STA); 1568 1569 ixgbe_lower_i2c_clk(hw, &i2cctl); 1570 1571 /* Minimum low period of clock is 4.7 us */ 1572 usec_delay(IXGBE_I2C_T_LOW); 1573 1574 } 1575 1576 /** 1577 * ixgbe_i2c_stop - Sets I2C stop condition 1578 * @hw: pointer to hardware structure 1579 * 1580 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1581 **/ 1582 void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1583 { 1584 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1585 1586 DEBUGFUNC("ixgbe_i2c_stop"); 1587 1588 /* Stop condition must begin with data low and clock high */ 1589 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1590 ixgbe_raise_i2c_clk(hw, &i2cctl); 1591 1592 /* Setup time for stop condition (4us) */ 1593 usec_delay(IXGBE_I2C_T_SU_STO); 1594 1595 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1596 1597 /* bus free time between stop and start (4.7us)*/ 1598 usec_delay(IXGBE_I2C_T_BUF); 1599 } 1600 1601 /** 1602 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1603 * @hw: pointer to hardware structure 1604 * @data: data byte to clock in 1605 * 1606 * Clocks in one byte data via I2C data/clock 1607 **/ 1608 int32_t ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, uint8_t *data) 1609 { 1610 int32_t i; 1611 int bit = 0; 1612 1613 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1614 1615 for (i = 7; i >= 0; i--) { 1616 ixgbe_clock_in_i2c_bit(hw, &bit); 1617 *data |= bit << i; 1618 } 1619 1620 return IXGBE_SUCCESS; 1621 } 1622 1623 /** 1624 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1625 * @hw: pointer to hardware structure 1626 * @data: data byte clocked out 1627 * 1628 * Clocks out one byte data via I2C data/clock 1629 **/ 1630 int32_t ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, uint8_t data) 1631 { 1632 int32_t status = IXGBE_SUCCESS; 1633 int32_t i; 1634 uint32_t i2cctl; 1635 int bit = 0; 1636 1637 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1638 1639 for (i = 7; i >= 0; i--) { 1640 bit = (data >> i) & 0x1; 1641 status = ixgbe_clock_out_i2c_bit(hw, bit); 1642 1643 if (status != IXGBE_SUCCESS) 1644 break; 1645 } 1646 1647 /* Release SDA line (set high) */ 1648 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1649 i2cctl |= IXGBE_I2C_DATA_OUT; 1650 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1651 IXGBE_WRITE_FLUSH(hw); 1652 1653 return status; 1654 } 1655 1656 /** 1657 * ixgbe_get_i2c_ack - Polls for I2C ACK 1658 * @hw: pointer to hardware structure 1659 * 1660 * Clocks in/out one bit via I2C data/clock 1661 **/ 1662 int32_t ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1663 { 1664 int32_t status = IXGBE_SUCCESS; 1665 uint32_t i = 0; 1666 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1667 uint32_t timeout = 10; 1668 int ack = 1; 1669 1670 DEBUGFUNC("ixgbe_get_i2c_ack"); 1671 1672 ixgbe_raise_i2c_clk(hw, &i2cctl); 1673 1674 /* Minimum high period of clock is 4us */ 1675 usec_delay(IXGBE_I2C_T_HIGH); 1676 1677 /* Poll for ACK. Note that ACK in I2C spec is 1678 * transition from 1 to 0 */ 1679 for (i = 0; i < timeout; i++) { 1680 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1681 ack = ixgbe_get_i2c_data(&i2cctl); 1682 1683 usec_delay(1); 1684 if (ack == 0) 1685 break; 1686 } 1687 1688 if (ack == 1) { 1689 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1690 "I2C ack was not received.\n"); 1691 status = IXGBE_ERR_I2C; 1692 } 1693 1694 ixgbe_lower_i2c_clk(hw, &i2cctl); 1695 1696 /* Minimum low period of clock is 4.7 us */ 1697 usec_delay(IXGBE_I2C_T_LOW); 1698 1699 return status; 1700 } 1701 1702 /** 1703 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1704 * @hw: pointer to hardware structure 1705 * @data: read data value 1706 * 1707 * Clocks in one bit via I2C data/clock 1708 **/ 1709 int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, int *data) 1710 { 1711 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1712 1713 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1714 1715 ixgbe_raise_i2c_clk(hw, &i2cctl); 1716 1717 /* Minimum high period of clock is 4us */ 1718 usec_delay(IXGBE_I2C_T_HIGH); 1719 1720 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1721 *data = ixgbe_get_i2c_data(&i2cctl); 1722 1723 ixgbe_lower_i2c_clk(hw, &i2cctl); 1724 1725 /* Minimum low period of clock is 4.7 us */ 1726 usec_delay(IXGBE_I2C_T_LOW); 1727 1728 return IXGBE_SUCCESS; 1729 } 1730 1731 /** 1732 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1733 * @hw: pointer to hardware structure 1734 * @data: data value to write 1735 * 1736 * Clocks out one bit via I2C data/clock 1737 **/ 1738 int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, int data) 1739 { 1740 int32_t status; 1741 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1742 1743 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1744 1745 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1746 if (status == IXGBE_SUCCESS) { 1747 ixgbe_raise_i2c_clk(hw, &i2cctl); 1748 1749 /* Minimum high period of clock is 4us */ 1750 usec_delay(IXGBE_I2C_T_HIGH); 1751 1752 ixgbe_lower_i2c_clk(hw, &i2cctl); 1753 1754 /* Minimum low period of clock is 4.7 us. 1755 * This also takes care of the data hold time. 1756 */ 1757 usec_delay(IXGBE_I2C_T_LOW); 1758 } else { 1759 status = IXGBE_ERR_I2C; 1760 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1761 "I2C data was not set to %X\n", data); 1762 } 1763 1764 return status; 1765 } 1766 /** 1767 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1768 * @hw: pointer to hardware structure 1769 * @i2cctl: Current value of I2CCTL register 1770 * 1771 * Raises the I2C clock line '0'->'1' 1772 **/ 1773 void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl) 1774 { 1775 int i; 1776 1777 *i2cctl |= IXGBE_I2C_CLK_OUT; 1778 1779 for (i = 0; i < IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; i++) { 1780 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1781 IXGBE_WRITE_FLUSH(hw); 1782 /* SCL rise time (1000ns) */ 1783 usec_delay(IXGBE_I2C_T_RISE); 1784 1785 if (IXGBE_READ_REG(hw, IXGBE_I2CCTL) & IXGBE_I2C_CLK_IN) 1786 break; 1787 } 1788 } 1789 1790 /** 1791 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1792 * @hw: pointer to hardware structure 1793 * @i2cctl: Current value of I2CCTL register 1794 * 1795 * Lowers the I2C clock line '1'->'0' 1796 **/ 1797 void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl) 1798 { 1799 1800 DEBUGFUNC("ixgbe_lower_i2c_clk"); 1801 1802 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1803 1804 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1805 IXGBE_WRITE_FLUSH(hw); 1806 1807 /* SCL fall time (300ns) */ 1808 usec_delay(IXGBE_I2C_T_FALL); 1809 } 1810 1811 /** 1812 * ixgbe_set_i2c_data - Sets the I2C data bit 1813 * @hw: pointer to hardware structure 1814 * @i2cctl: Current value of I2CCTL register 1815 * @data: I2C data value (0 or 1) to set 1816 * 1817 * Sets the I2C data bit 1818 **/ 1819 int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, int data) 1820 { 1821 int32_t status = IXGBE_SUCCESS; 1822 1823 DEBUGFUNC("ixgbe_set_i2c_data"); 1824 1825 if (data) 1826 *i2cctl |= IXGBE_I2C_DATA_OUT; 1827 else 1828 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1829 1830 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1831 IXGBE_WRITE_FLUSH(hw); 1832 1833 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1834 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1835 1836 /* Verify data was set correctly */ 1837 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1838 if (data != ixgbe_get_i2c_data(i2cctl)) { 1839 status = IXGBE_ERR_I2C; 1840 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1841 "Error - I2C data was not set to %X.\n", 1842 data); 1843 } 1844 1845 return status; 1846 } 1847 1848 /** 1849 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1850 * @hw: pointer to hardware structure 1851 * @i2cctl: Current value of I2CCTL register 1852 * 1853 * Returns the I2C data bit value 1854 **/ 1855 int ixgbe_get_i2c_data(uint32_t *i2cctl) 1856 { 1857 int data; 1858 1859 DEBUGFUNC("ixgbe_get_i2c_data"); 1860 1861 if (*i2cctl & IXGBE_I2C_DATA_IN) 1862 data = 1; 1863 else 1864 data = 0; 1865 1866 return data; 1867 } 1868 1869 /** 1870 * ixgbe_i2c_bus_clear - Clears the I2C bus 1871 * @hw: pointer to hardware structure 1872 * 1873 * Clears the I2C bus by sending nine clock pulses. 1874 * Used when data line is stuck low. 1875 **/ 1876 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1877 { 1878 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1879 uint32_t i; 1880 1881 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1882 1883 ixgbe_i2c_start(hw); 1884 1885 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1886 1887 for (i = 0; i < 9; i++) { 1888 ixgbe_raise_i2c_clk(hw, &i2cctl); 1889 1890 /* Min high period of clock is 4us */ 1891 usec_delay(IXGBE_I2C_T_HIGH); 1892 1893 ixgbe_lower_i2c_clk(hw, &i2cctl); 1894 1895 /* Min low period of clock is 4.7us*/ 1896 usec_delay(IXGBE_I2C_T_LOW); 1897 } 1898 1899 ixgbe_i2c_start(hw); 1900 1901 /* Put the i2c bus back to default state */ 1902 ixgbe_i2c_stop(hw); 1903 } 1904 1905 /** 1906 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 1907 * @hw: pointer to hardware structure 1908 * 1909 * Checks if the LASI temp alarm status was triggered due to overtemp 1910 **/ 1911 int32_t ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1912 { 1913 int32_t status = IXGBE_SUCCESS; 1914 uint16_t phy_data = 0; 1915 1916 DEBUGFUNC("ixgbe_tn_check_overtemp"); 1917 1918 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1919 goto out; 1920 1921 /* Check that the LASI temp alarm status was triggered */ 1922 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1923 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1924 1925 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1926 goto out; 1927 1928 status = IXGBE_ERR_OVERTEMP; 1929 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 1930 out: 1931 return status; 1932 } 1933