1 /* $OpenBSD: maestro.c,v 1.28 2010/04/08 00:23:53 tedu Exp $ */ 2 /* $FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro.c,v 1.3 2000/11/21 12:22:11 julian Exp $ */ 3 /* 4 * FreeBSD's ESS Agogo/Maestro driver 5 * Converted from FreeBSD's pcm to OpenBSD's audio. 6 * Copyright (c) 2000, 2001 David Leonard & Marc Espie 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 /*- 31 * (FreeBSD) Credits: 32 * Copyright (c) 2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp> 33 * 34 * Part of this code (especially in many magic numbers) was heavily inspired 35 * by the Linux driver originally written by 36 * Alan Cox <alan.cox@linux.org>, modified heavily by 37 * Zach Brown <zab@zabbo.net>. 38 * 39 * busdma()-ize and buffer size reduction were suggested by 40 * Cameron Grant <gandalf@vilnya.demon.co.uk>. 41 * Also he showed me the way to use busdma() suite. 42 * 43 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500 44 * were looked at by 45 * Munehiro Matsuda <haro@tk.kubota.co.jp>, 46 * who brought patches based on the Linux driver with some simplification. 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/queue.h> 55 #include <sys/fcntl.h> 56 57 #include <dev/pci/pcidevs.h> 58 #include <dev/pci/pcivar.h> 59 60 #include <sys/audioio.h> 61 #include <dev/audio_if.h> 62 #include <dev/mulaw.h> 63 #include <dev/auconv.h> 64 65 #include <dev/ic/ac97.h> 66 67 /* ----------------------------- 68 * PCI config registers 69 */ 70 71 /* Legacy emulation */ 72 #define CONF_LEGACY 0x40 73 74 #define LEGACY_DISABLED 0x8000 75 76 /* Chip configurations */ 77 #define CONF_MAESTRO 0x50 78 #define MAESTRO_CHIBUS 0x00100000 79 #define MAESTRO_POSTEDWRITE 0x00000080 80 #define MAESTRO_DMA_PCITIMING 0x00000040 81 #define MAESTRO_SWAP_LR 0x00000010 82 83 /* ACPI configurations */ 84 #define CONF_ACPI_STOPCLOCK 0x54 85 #define ACPI_PART_2ndC_CLOCK 15 86 #define ACPI_PART_CODEC_CLOCK 14 87 #define ACPI_PART_978 13 /* Docking station or something */ 88 #define ACPI_PART_SPDIF 12 89 #define ACPI_PART_GLUE 11 /* What? */ 90 #define ACPI_PART_DAA 10 91 #define ACPI_PART_PCI_IF 9 92 #define ACPI_PART_HW_VOL 8 93 #define ACPI_PART_GPIO 7 94 #define ACPI_PART_ASSP 6 95 #define ACPI_PART_SB 5 96 #define ACPI_PART_FM 4 97 #define ACPI_PART_RINGBUS 3 98 #define ACPI_PART_MIDI 2 99 #define ACPI_PART_GAME_PORT 1 100 #define ACPI_PART_WP 0 101 102 /* Power management */ 103 #define CONF_PM_PTR 0x34 /* BYTE R */ 104 #define PM_CID 0 /* BYTE R */ 105 #define PPMI_CID 1 106 #define PM_CTRL 4 /* BYTE RW */ 107 #define PPMI_D0 0 /* Full power */ 108 #define PPMI_D1 1 /* Medium power */ 109 #define PPMI_D2 2 /* Low power */ 110 #define PPMI_D3 3 /* Turned off */ 111 112 113 /* ----------------------------- 114 * I/O ports 115 */ 116 117 /* Direct Sound Processor (aka Wave Processor) */ 118 #define PORT_DSP_DATA 0x00 /* WORD RW */ 119 #define PORT_DSP_INDEX 0x02 /* WORD RW */ 120 #define PORT_INT_STAT 0x04 /* WORD RW */ 121 #define PORT_SAMPLE_CNT 0x06 /* WORD RO */ 122 123 /* WaveCache */ 124 #define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */ 125 #define PORT_WAVCACHE_DATA 0x12 /* WORD RW */ 126 #define WAVCACHE_PCMBAR 0x1fc 127 #define WAVCACHE_WTBAR 0x1f0 128 #define WAVCACHE_BASEADDR_SHIFT 12 129 130 #define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8 131 #define WAVCACHE_CHCTL_U8 0x0004 132 #define WAVCACHE_CHCTL_STEREO 0x0002 133 #define WAVCACHE_CHCTL_DECREMENTAL 0x0001 134 135 #define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */ 136 #define WAVCACHE_EXTRA_CH_ENABLED 0x0200 137 #define WAVCACHE_ENABLED 0x0100 138 #define WAVCACHE_CH_60_ENABLED 0x0080 139 #define WAVCACHE_WTSIZE_MASK 0x0060 140 #define WAVCACHE_WTSIZE_1MB 0x0000 141 #define WAVCACHE_WTSIZE_2MB 0x0020 142 #define WAVCACHE_WTSIZE_4MB 0x0040 143 #define WAVCACHE_WTSIZE_8MB 0x0060 144 #define WAVCACHE_SGC_MASK 0x000c 145 #define WAVCACHE_SGC_DISABLED 0x0000 146 #define WAVCACHE_SGC_40_47 0x0004 147 #define WAVCACHE_SGC_32_47 0x0008 148 #define WAVCACHE_TESTMODE 0x0001 149 150 /* Host Interruption */ 151 #define PORT_HOSTINT_CTRL 0x18 /* WORD RW */ 152 #define HOSTINT_CTRL_SOFT_RESET 0x8000 153 #define HOSTINT_CTRL_DSOUND_RESET 0x4000 154 #define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400 155 #define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100 156 #define HOSTINT_CTRL_HWVOL_ENABLED 0x0040 157 #define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010 158 #define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008 159 #define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004 160 #define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002 161 #define HOSTINT_CTRL_SB_INT_ENABLED 0x0001 162 163 #define PORT_HOSTINT_STAT 0x1a /* BYTE RW */ 164 #define HOSTINT_STAT_HWVOL 0x40 165 #define HOSTINT_STAT_ASSP 0x10 166 #define HOSTINT_STAT_ISDN 0x08 167 #define HOSTINT_STAT_DSOUND 0x04 168 #define HOSTINT_STAT_MPU401 0x02 169 #define HOSTINT_STAT_SB 0x01 170 171 /* Hardware volume */ 172 #define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */ 173 #define PORT_HWVOL_VOICE 0x1d /* BYTE RW */ 174 #define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */ 175 #define PORT_HWVOL_MASTER 0x1f /* BYTE RW */ 176 177 /* CODEC */ 178 #define PORT_CODEC_CMD 0x30 /* BYTE W */ 179 #define CODEC_CMD_READ 0x80 180 #define CODEC_CMD_WRITE 0x00 181 #define CODEC_CMD_ADDR_MASK 0x7f 182 183 #define PORT_CODEC_STAT 0x30 /* BYTE R */ 184 #define CODEC_STAT_MASK 0x01 185 #define CODEC_STAT_RW_DONE 0x00 186 #define CODEC_STAT_PROGLESS 0x01 187 188 #define PORT_CODEC_REG 0x32 /* WORD RW */ 189 190 /* Ring bus control */ 191 #define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */ 192 #define RINGBUS_CTRL_I2S_ENABLED 0x80000000 193 #define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000 194 #define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000 195 #define RINGBUS_CTRL_AC97_SWRESET 0x08000000 196 #define RINGBUS_CTRL_IODMA_PLAYBACK_ENABLED 0x04000000 197 #define RINGBUS_CTRL_IODMA_RECORD_ENABLED 0x02000000 198 199 #define RINGBUS_SRC_MIC 20 200 #define RINGBUS_SRC_I2S 16 201 #define RINGBUS_SRC_ADC 12 202 #define RINGBUS_SRC_MODEM 8 203 #define RINGBUS_SRC_DSOUND 4 204 #define RINGBUS_SRC_ASSP 0 205 206 #define RINGBUS_DEST_MONORAL 000 207 #define RINGBUS_DEST_STEREO 010 208 #define RINGBUS_DEST_NONE 0 209 #define RINGBUS_DEST_DAC 1 210 #define RINGBUS_DEST_MODEM_IN 2 211 #define RINGBUS_DEST_RESERVED3 3 212 #define RINGBUS_DEST_DSOUND_IN 4 213 #define RINGBUS_DEST_ASSP_IN 5 214 215 /* General Purpose I/O */ 216 #define PORT_GPIO_DATA 0x60 /* WORD RW */ 217 #define PORT_GPIO_MASK 0x64 /* WORD RW */ 218 #define PORT_GPIO_DIR 0x68 /* WORD RW */ 219 220 /* Application Specific Signal Processor */ 221 #define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */ 222 #define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */ 223 #define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */ 224 #define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */ 225 #define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */ 226 #define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */ 227 #define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */ 228 #define PORT_ASSP_INT_STAT 0xac /* BYTE RW */ 229 230 231 /* ----------------------------- 232 * Wave Processor Indexed Data Registers. 233 */ 234 235 #define WPREG_DATA_PORT 0 236 #define WPREG_CRAM_PTR 1 237 #define WPREG_CRAM_DATA 2 238 #define WPREG_WAVE_DATA 3 239 #define WPREG_WAVE_PTR_LOW 4 240 #define WPREG_WAVE_PTR_HIGH 5 241 242 #define WPREG_TIMER_FREQ 6 243 #define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */ 244 #define WP_TIMER_FREQ_PRESCALE_SHIFT 5 245 #define WP_TIMER_FREQ_DIVIDE_MASK 0x001f 246 #define WP_TIMER_FREQ_DIVIDE_SHIFT 0 247 248 #define WPREG_WAVE_ROMRAM 7 249 #define WP_WAVE_VIRTUAL_ENABLED 0x0400 250 #define WP_WAVE_8BITRAM_ENABLED 0x0200 251 #define WP_WAVE_DRAM_ENABLED 0x0100 252 #define WP_WAVE_RAMSPLIT_MASK 0x00ff 253 #define WP_WAVE_RAMSPLIT_SHIFT 0 254 255 #define WPREG_BASE 12 256 #define WP_PARAOUT_BASE_MASK 0xf000 257 #define WP_PARAOUT_BASE_SHIFT 12 258 #define WP_PARAIN_BASE_MASK 0x0f00 259 #define WP_PARAIN_BASE_SHIFT 8 260 #define WP_SERIAL0_BASE_MASK 0x00f0 261 #define WP_SERIAL0_BASE_SHIFT 4 262 #define WP_SERIAL1_BASE_MASK 0x000f 263 #define WP_SERIAL1_BASE_SHIFT 0 264 265 #define WPREG_TIMER_ENABLE 17 266 #define WPREG_TIMER_START 23 267 268 269 /* ----------------------------- 270 * Audio Processing Unit. 271 */ 272 #define APUREG_APUTYPE 0 273 #define APU_DMA_ENABLED 0x4000 274 #define APU_INT_ON_LOOP 0x2000 275 #define APU_ENDCURVE 0x1000 276 #define APU_APUTYPE_MASK 0x00f0 277 #define APU_FILTERTYPE_MASK 0x000c 278 #define APU_FILTERQ_MASK 0x0003 279 280 /* APU types */ 281 #define APU_APUTYPE_SHIFT 4 282 283 #define APUTYPE_INACTIVE 0 284 #define APUTYPE_16BITLINEAR 1 285 #define APUTYPE_16BITSTEREO 2 286 #define APUTYPE_8BITLINEAR 3 287 #define APUTYPE_8BITSTEREO 4 288 #define APUTYPE_8BITDIFF 5 289 #define APUTYPE_DIGITALDELAY 6 290 #define APUTYPE_DUALTAP_READER 7 291 #define APUTYPE_CORRELATOR 8 292 #define APUTYPE_INPUTMIXER 9 293 #define APUTYPE_WAVETABLE 10 294 #define APUTYPE_RATECONV 11 295 #define APUTYPE_16BITPINGPONG 12 296 /* APU type 13 through 15 are reserved. */ 297 298 /* Filter types */ 299 #define APU_FILTERTYPE_SHIFT 2 300 301 #define FILTERTYPE_2POLE_LOPASS 0 302 #define FILTERTYPE_2POLE_BANDPASS 1 303 #define FILTERTYPE_2POLE_HIPASS 2 304 #define FILTERTYPE_1POLE_LOPASS 3 305 #define FILTERTYPE_1POLE_HIPASS 4 306 #define FILTERTYPE_PASSTHROUGH 5 307 308 /* Filter Q */ 309 #define APU_FILTERQ_SHIFT 0 310 311 #define FILTERQ_LESSQ 0 312 #define FILTERQ_MOREQ 3 313 314 /* APU register 2 */ 315 #define APUREG_FREQ_LOBYTE 2 316 #define APU_FREQ_LOBYTE_MASK 0xff00 317 #define APU_plus6dB 0x0010 318 319 /* APU register 3 */ 320 #define APUREG_FREQ_HIWORD 3 321 #define APU_FREQ_HIWORD_MASK 0x0fff 322 323 /* Frequency */ 324 #define APU_FREQ_LOBYTE_SHIFT 8 325 #define APU_FREQ_HIWORD_SHIFT 0 326 #define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000) 327 328 /* APU register 4 */ 329 #define APUREG_WAVESPACE 4 330 #define APU_STEREO 0x8000 331 #define APU_USE_SYSMEM 0x4000 332 #define APU_PCMBAR_MASK 0x6000 333 #define APU_64KPAGE_MASK 0xff00 334 335 /* PCM Base Address Register selection */ 336 #define APU_PCMBAR_SHIFT 13 337 338 /* 64KW (==128KB) Page */ 339 #define APU_64KPAGE_SHIFT 8 340 341 /* APU register 5 - 7 */ 342 #define APUREG_CURPTR 5 343 #define APUREG_ENDPTR 6 344 #define APUREG_LOOPLEN 7 345 346 /* APU register 9 */ 347 #define APUREG_AMPLITUDE 9 348 #define APU_AMPLITUDE_NOW_MASK 0xff00 349 #define APU_AMPLITUDE_DEST_MASK 0x00ff 350 351 /* Amplitude now? */ 352 #define APU_AMPLITUDE_NOW_SHIFT 8 353 354 /* APU register 10 */ 355 #define APUREG_POSITION 10 356 #define APU_RADIUS_MASK 0x00c0 357 #define APU_PAN_MASK 0x003f 358 359 /* Radius control. */ 360 #define APU_RADIUS_SHIFT 6 361 #define RADIUS_CENTERCIRCLE 0 362 #define RADIUS_MIDDLE 1 363 #define RADIUS_OUTSIDE 2 364 365 /* Polar pan. */ 366 #define APU_PAN_SHIFT 0 367 #define PAN_RIGHT 0x00 368 #define PAN_FRONT 0x08 369 #define PAN_LEFT 0x10 370 371 372 /* ----------------------------- 373 * Limits. 374 */ 375 #define WPWA_MAX ((1 << 22) - 1) 376 #define WPWA_MAXADDR ((1 << 23) - 1) 377 #define MAESTRO_MAXADDR ((1 << 28) - 1) 378 379 380 381 #ifdef AUDIO_DEBUG 382 #define DPRINTF(x) if (maestrodebug) printf x 383 #define DLPRINTF(i, x) if (maestrodebug & i) printf x 384 int maestrodebug = 0; 385 u_long maestrointr_called; 386 u_long maestrodma_effective; 387 388 #define MAESTRODEBUG_INTR 1 389 #define MAESTRODEBUG_TIMER 2 390 #else 391 #define DPRINTF(x) 392 #define DLPRINTF(i, x) 393 #endif 394 395 #define MAESTRO_BUFSIZ 0x4000 396 #define lengthof(array) (sizeof (array) / sizeof (array)[0]) 397 398 #define STEP_VOLUME 0x22 399 #define MIDDLE_VOLUME (STEP_VOLUME * 4) 400 401 typedef struct salloc_pool { 402 struct salloc_zone { 403 SLIST_ENTRY(salloc_zone) link; 404 caddr_t addr; 405 size_t size; 406 } *zones; 407 SLIST_HEAD(salloc_head, salloc_zone) free, used, spare; 408 } *salloc_t; 409 410 struct maestro_softc; 411 412 #define MAESTRO_PLAY 1 413 #define MAESTRO_STEREO 2 414 #define MAESTRO_8BIT 4 415 #define MAESTRO_UNSIGNED 8 416 #define MAESTRO_RUNNING 16 417 418 struct maestro_channel { 419 struct maestro_softc *sc; 420 int num; 421 u_int32_t blocksize; 422 u_int16_t mode; 423 u_int32_t speed; 424 u_int32_t dv; 425 u_int16_t start; 426 u_int16_t threshold; 427 u_int16_t end; 428 u_int16_t current; 429 u_int wpwa; 430 void (*intr)(void *); 431 void *intr_arg; 432 }; 433 434 struct maestro_softc { 435 struct device dev; 436 437 void *ih; 438 pci_chipset_tag_t pc; 439 pcitag_t pt; 440 441 #define MAESTRO_FLAG_SETUPGPIO 0x0001 442 int flags; 443 bus_space_tag_t iot; 444 bus_space_handle_t ioh; 445 bus_dma_tag_t dmat; 446 447 caddr_t dmabase; 448 bus_addr_t physaddr; 449 size_t dmasize; 450 bus_dmamap_t dmamap; 451 bus_dma_segment_t dmaseg; 452 salloc_t dmapool; 453 454 struct ac97_codec_if *codec_if; 455 struct ac97_host_if host_if; 456 struct audio_device *sc_audev; 457 458 void *powerhook; 459 int suspend; 460 461 struct maestro_channel play; 462 struct maestro_channel record; 463 }; 464 465 466 typedef u_int16_t wpreg_t; 467 typedef u_int16_t wcreg_t; 468 469 salloc_t salloc_new(caddr_t, size_t, int); 470 void salloc_destroy(salloc_t); 471 caddr_t salloc_alloc(salloc_t, size_t); 472 void salloc_free(salloc_t, caddr_t); 473 void salloc_insert(salloc_t, struct salloc_head *, 474 struct salloc_zone *, int); 475 476 int maestro_match(struct device *, void *, void *); 477 void maestro_attach(struct device *, struct device *, void *); 478 int maestro_intr(void *); 479 480 int maestro_open(void *, int); 481 void maestro_close(void *); 482 int maestro_query_encoding(void *, struct audio_encoding *); 483 int maestro_set_params(void *, int, int, struct audio_params *, 484 struct audio_params *); 485 void maestro_get_default_params(void *, int, struct audio_params *); 486 int maestro_round_blocksize(void *, int); 487 int maestro_halt_output(void *); 488 int maestro_halt_input(void *); 489 int maestro_getdev(void *, struct audio_device *); 490 int maestro_set_port(void *, mixer_ctrl_t *); 491 int maestro_get_port(void *, mixer_ctrl_t *); 492 int maestro_query_devinfo(void *, mixer_devinfo_t *); 493 void *maestro_malloc(void *, int, size_t, int, int); 494 void maestro_free(void *, void *, int); 495 paddr_t maestro_mappage(void *, void *, off_t, int); 496 int maestro_get_props(void *); 497 int maestro_trigger_output(void *, void *, void *, int, void (*)(void *), 498 void *, struct audio_params *); 499 int maestro_trigger_input(void *, void *, void *, int, void (*)(void *), 500 void *, struct audio_params *); 501 502 int maestro_attach_codec(void *, struct ac97_codec_if *); 503 enum ac97_host_flags maestro_codec_flags(void *); 504 int maestro_read_codec(void *, u_int8_t, u_int16_t *); 505 int maestro_write_codec(void *, u_int8_t, u_int16_t); 506 void maestro_reset_codec(void *); 507 508 void maestro_initcodec(void *); 509 510 void maestro_set_speed(struct maestro_channel *, u_long *); 511 void maestro_init(struct maestro_softc *); 512 void maestro_power(struct maestro_softc *, int); 513 void maestro_powerhook(int, void *); 514 515 void maestro_channel_start(struct maestro_channel *); 516 void maestro_channel_stop(struct maestro_channel *); 517 void maestro_channel_advance_dma(struct maestro_channel *); 518 void maestro_channel_suppress_jitter(struct maestro_channel *); 519 520 int maestro_get_flags(struct pci_attach_args *); 521 522 void ringbus_setdest(struct maestro_softc *, int, int); 523 524 wpreg_t wp_reg_read(struct maestro_softc *, int); 525 void wp_reg_write(struct maestro_softc *, int, wpreg_t); 526 wpreg_t wp_apu_read(struct maestro_softc *, int, int); 527 void wp_apu_write(struct maestro_softc *, int, int, wpreg_t); 528 void wp_settimer(struct maestro_softc *, u_int); 529 void wp_starttimer(struct maestro_softc *); 530 void wp_stoptimer(struct maestro_softc *); 531 532 wcreg_t wc_reg_read(struct maestro_softc *, int); 533 void wc_reg_write(struct maestro_softc *, int, wcreg_t); 534 wcreg_t wc_ctrl_read(struct maestro_softc *, int); 535 void wc_ctrl_write(struct maestro_softc *, int, wcreg_t); 536 537 u_int maestro_calc_timer_freq(struct maestro_channel *); 538 void maestro_update_timer(struct maestro_softc *); 539 540 struct cfdriver maestro_cd = { 541 NULL, "maestro", DV_DULL 542 }; 543 544 struct cfattach maestro_ca = { 545 sizeof (struct maestro_softc), maestro_match, maestro_attach 546 }; 547 548 struct audio_hw_if maestro_hw_if = { 549 maestro_open, 550 maestro_close, 551 NULL, 552 maestro_query_encoding, 553 maestro_set_params, 554 maestro_round_blocksize, 555 NULL, 556 NULL, 557 NULL, 558 NULL, 559 NULL, 560 maestro_halt_output, 561 maestro_halt_input, 562 NULL, 563 maestro_getdev, 564 NULL, 565 maestro_set_port, 566 maestro_get_port, 567 maestro_query_devinfo, 568 maestro_malloc, 569 maestro_free, 570 NULL, 571 maestro_mappage, 572 maestro_get_props, 573 maestro_trigger_output, 574 maestro_trigger_input, 575 maestro_get_default_params 576 }; 577 578 struct audio_device maestro_audev = { 579 "ESS Maestro", "", "maestro" 580 }; 581 582 struct { 583 u_short vendor, product; 584 int flags; 585 } maestro_pcitab[] = { 586 { PCI_VENDOR_ESSTECH, PCI_PRODUCT_ESSTECH_MAESTROII, 0 }, 587 { PCI_VENDOR_ESSTECH, PCI_PRODUCT_ESSTECH_MAESTRO2E, 0 }, 588 { PCI_VENDOR_PLATFORM, PCI_PRODUCT_PLATFORM_ES1849, 0 }, 589 { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSAMAESTRO, MAESTRO_FLAG_SETUPGPIO }, 590 { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSAPRONXVA26D, MAESTRO_FLAG_SETUPGPIO } 591 }; 592 #define NMAESTRO_PCITAB lengthof(maestro_pcitab) 593 594 int 595 maestro_get_flags(pa) 596 struct pci_attach_args *pa; 597 { 598 int i; 599 600 /* Distinguish audio devices from modems with the same manfid */ 601 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_MULTIMEDIA) 602 return (-1); 603 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MULTIMEDIA_AUDIO) 604 return (-1); 605 for (i = 0; i < NMAESTRO_PCITAB; i++) 606 if (PCI_VENDOR(pa->pa_id) == maestro_pcitab[i].vendor && 607 PCI_PRODUCT(pa->pa_id) == maestro_pcitab[i].product) 608 return (maestro_pcitab[i].flags); 609 return (-1); 610 } 611 612 /* ----------------------------- 613 * Driver interface. 614 */ 615 616 int 617 maestro_match(parent, match, aux) 618 struct device *parent; 619 void *match; 620 void *aux; 621 { 622 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 623 624 if (maestro_get_flags(pa) == -1) 625 return (0); 626 else 627 return (1); 628 } 629 630 void 631 maestro_attach(parent, self, aux) 632 struct device *parent; 633 struct device *self; 634 void *aux; 635 { 636 struct maestro_softc *sc = (struct maestro_softc *)self; 637 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 638 pci_chipset_tag_t pc = pa->pa_pc; 639 char const *intrstr; 640 pci_intr_handle_t ih; 641 int error; 642 u_int16_t cdata; 643 int dmastage = 0; 644 int rseg; 645 646 sc->sc_audev = &maestro_audev; 647 sc->flags = maestro_get_flags(pa); 648 649 sc->pc = pa->pa_pc; 650 sc->pt = pa->pa_tag; 651 sc->dmat = pa->pa_dmat; 652 653 /* Map interrupt */ 654 if (pci_intr_map(pa, &ih)) { 655 printf(": can't map interrupt\n"); 656 return; 657 } 658 intrstr = pci_intr_string(pc, ih); 659 sc->ih = pci_intr_establish(pc, ih, IPL_AUDIO, maestro_intr, sc, 660 sc->dev.dv_xname); 661 if (sc->ih == NULL) { 662 printf(": can't establish interrupt"); 663 if (intrstr != NULL) 664 printf(" at %s\n", intrstr); 665 return; 666 } 667 printf(": %s", intrstr); 668 669 /* Rangers, power up */ 670 maestro_power(sc, PPMI_D0); 671 DELAY(100000); 672 673 /* Map i/o */ 674 if ((error = pci_mapreg_map(pa, PCI_MAPS, PCI_MAPREG_TYPE_IO, 675 0, &sc->iot, &sc->ioh, NULL, NULL, 0)) != 0) { 676 printf(", can't map i/o space\n"); 677 goto bad; 678 }; 679 680 /* Allocate fixed DMA segment :-( */ 681 sc->dmasize = MAESTRO_BUFSIZ * 16; 682 if ((error = bus_dmamem_alloc(sc->dmat, sc->dmasize, NBPG, 0, 683 &sc->dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 684 printf(", unable to alloc dma, error %d\n", error); 685 goto bad; 686 } 687 dmastage = 1; 688 if ((error = bus_dmamem_map(sc->dmat, &sc->dmaseg, 1, 689 sc->dmasize, &sc->dmabase, BUS_DMA_NOWAIT | 690 BUS_DMA_COHERENT)) != 0) { 691 printf(", unable to map dma, error %d\n", error); 692 goto bad; 693 } 694 dmastage = 2; 695 if ((error = bus_dmamap_create(sc->dmat, sc->dmasize, 1, 696 sc->dmasize, 0, BUS_DMA_NOWAIT, &sc->dmamap)) != 0) { 697 printf(", unable to create dma map, error %d\n", error); 698 goto bad; 699 } 700 dmastage = 3; 701 if ((error = bus_dmamap_load(sc->dmat, sc->dmamap, 702 sc->dmabase, sc->dmasize, NULL, BUS_DMA_NOWAIT)) != 0) { 703 printf(", unable to load dma map, error %d\n", error); 704 goto bad; 705 } 706 707 /* XXX 708 * The first byte of the allocated memory is not usable, 709 * the WP sometimes uses it to store status. 710 */ 711 /* Make DMA memory pool */ 712 if ((sc->dmapool = salloc_new(sc->dmabase+16, sc->dmasize-16, 713 128/*overkill?*/)) == NULL) { 714 printf(", unable to make dma pool\n"); 715 goto bad; 716 } 717 718 sc->physaddr = sc->dmamap->dm_segs[0].ds_addr; 719 720 printf("\n"); 721 722 /* Kick device */ 723 maestro_init(sc); 724 maestro_read_codec(sc, 0, &cdata); 725 if (cdata == 0x80) { 726 printf("%s: PT101 codec unsupported, no mixer\n", 727 sc->dev.dv_xname); 728 /* Init values from Linux, no idea what this does. */ 729 maestro_write_codec(sc, 0x2a, 0x0001); 730 maestro_write_codec(sc, 0x2C, 0x0000); 731 maestro_write_codec(sc, 0x2C, 0xFFFF); 732 maestro_write_codec(sc, 0x10, 0x9F1F); 733 maestro_write_codec(sc, 0x12, 0x0808); 734 maestro_write_codec(sc, 0x14, 0x9F1F); 735 maestro_write_codec(sc, 0x16, 0x9F1F); 736 maestro_write_codec(sc, 0x18, 0x0404); 737 maestro_write_codec(sc, 0x1A, 0x0000); 738 maestro_write_codec(sc, 0x1C, 0x0000); 739 maestro_write_codec(sc, 0x02, 0x0404); 740 maestro_write_codec(sc, 0x04, 0x0808); 741 maestro_write_codec(sc, 0x0C, 0x801F); 742 maestro_write_codec(sc, 0x0E, 0x801F); 743 /* no control over the mixer, sorry */ 744 sc->codec_if = NULL; 745 } else { 746 /* Attach the AC'97 */ 747 sc->host_if.arg = sc; 748 sc->host_if.attach = maestro_attach_codec; 749 sc->host_if.flags = maestro_codec_flags; 750 sc->host_if.read = maestro_read_codec; 751 sc->host_if.write = maestro_write_codec; 752 sc->host_if.reset = maestro_reset_codec; 753 if (ac97_attach(&sc->host_if) != 0) { 754 printf("%s: can't attach codec\n", sc->dev.dv_xname); 755 goto bad; 756 } 757 } 758 759 sc->play.mode = MAESTRO_PLAY; 760 sc->play.sc = sc; 761 sc->play.num = 0; 762 sc->record.sc = sc; 763 sc->record.num = 2; 764 sc->record.mode = 0; 765 766 /* Attach audio */ 767 audio_attach_mi(&maestro_hw_if, sc, &sc->dev); 768 769 /* Hook power changes */ 770 sc->suspend = PWR_RESUME; 771 sc->powerhook = powerhook_establish(maestro_powerhook, sc); 772 773 return; 774 775 bad: 776 /* Power down. */ 777 maestro_power(sc, PPMI_D3); 778 if (sc->ih) 779 pci_intr_disestablish(pc, sc->ih); 780 printf("%s: disabled\n", sc->dev.dv_xname); 781 if (sc->dmapool) 782 salloc_destroy(sc->dmapool); 783 if (dmastage >= 3) 784 bus_dmamap_destroy(sc->dmat, sc->dmamap); 785 if (dmastage >= 2) 786 bus_dmamem_unmap(sc->dmat, sc->dmabase, sc->dmasize); 787 if (dmastage >= 1) 788 bus_dmamem_free(sc->dmat, &sc->dmaseg, 1); 789 } 790 791 void 792 maestro_init(sc) 793 struct maestro_softc *sc; 794 { 795 int reg; 796 pcireg_t data; 797 798 /* Disable all legacy emulations. */ 799 data = pci_conf_read(sc->pc, sc->pt, CONF_LEGACY); 800 data |= LEGACY_DISABLED; 801 pci_conf_write(sc->pc, sc->pt, CONF_LEGACY, data); 802 803 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?) 804 * Enable posted write. 805 * Prefer PCI timing rather than that of ISA. 806 * Don't swap L/R. */ 807 data = pci_conf_read(sc->pc, sc->pt, CONF_MAESTRO); 808 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING; 809 data &= ~MAESTRO_SWAP_LR; 810 pci_conf_write(sc->pc, sc->pt, CONF_MAESTRO, data); 811 /* Reset direct sound. */ 812 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 813 HOSTINT_CTRL_DSOUND_RESET); 814 DELAY(10000); /* XXX - too long? */ 815 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 0); 816 DELAY(10000); 817 818 /* Enable direct sound and hardware volume control interruptions. */ 819 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 820 HOSTINT_CTRL_DSOUND_INT_ENABLED | HOSTINT_CTRL_HWVOL_ENABLED); 821 822 /* Setup Wave Processor. */ 823 824 /* Enable WaveCache, set DMA base address. */ 825 wp_reg_write(sc, WPREG_WAVE_ROMRAM, 826 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED); 827 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_CTRL, 828 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB); 829 830 for (reg = WAVCACHE_PCMBAR; reg < WAVCACHE_PCMBAR + 4; reg++) 831 wc_reg_write(sc, reg, 832 sc->physaddr >> WAVCACHE_BASEADDR_SHIFT); 833 834 /* Setup Codec/Ringbus. */ 835 maestro_initcodec(sc); 836 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, 837 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED); 838 839 wp_reg_write(sc, WPREG_BASE, 0x8500); /* Parallel I/O */ 840 ringbus_setdest(sc, RINGBUS_SRC_ADC, 841 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN); 842 ringbus_setdest(sc, RINGBUS_SRC_DSOUND, 843 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC); 844 845 /* Setup ASSP. Needed for Dell Inspiron 7500? */ 846 bus_space_write_1(sc->iot, sc->ioh, PORT_ASSP_CTRL_B, 0x00); 847 bus_space_write_1(sc->iot, sc->ioh, PORT_ASSP_CTRL_A, 0x03); 848 bus_space_write_1(sc->iot, sc->ioh, PORT_ASSP_CTRL_C, 0x00); 849 850 /* 851 * Reset hw volume to a known value so that we may handle diffs 852 * off to AC'97. 853 */ 854 855 bus_space_write_1(sc->iot, sc->ioh, PORT_HWVOL_MASTER, MIDDLE_VOLUME); 856 /* Setup GPIO if needed (NEC systems) */ 857 if (sc->flags & MAESTRO_FLAG_SETUPGPIO) { 858 /* Matthew Braithwaite <matt@braithwaite.net> reported that 859 * NEC Versa LX doesn't need GPIO operation. */ 860 bus_space_write_2(sc->iot, sc->ioh, 861 PORT_GPIO_MASK, 0x9ff); 862 bus_space_write_2(sc->iot, sc->ioh, PORT_GPIO_DIR, 863 bus_space_read_2(sc->iot, sc->ioh, PORT_GPIO_DIR) | 0x600); 864 bus_space_write_2(sc->iot, sc->ioh, 865 PORT_GPIO_DATA, 0x200); 866 } 867 } 868 869 /* ----------------------------- 870 * Audio interface 871 */ 872 873 int 874 maestro_round_blocksize(self, blk) 875 void *self; 876 int blk; 877 { 878 return ((blk + 0xf) & ~0xf); 879 } 880 881 void * 882 maestro_malloc(arg, dir, size, pool, flags) 883 void *arg; 884 int dir; 885 size_t size; 886 int pool, flags; 887 { 888 struct maestro_softc *sc = (struct maestro_softc *)arg; 889 890 return (salloc_alloc(sc->dmapool, size)); 891 } 892 893 void 894 maestro_free(self, ptr, pool) 895 void *self, *ptr; 896 int pool; 897 { 898 struct maestro_softc *sc = (struct maestro_softc *)self; 899 900 salloc_free(sc->dmapool, ptr); 901 } 902 903 paddr_t 904 maestro_mappage(self, mem, off, prot) 905 void *self, *mem; 906 off_t off; 907 int prot; 908 { 909 struct maestro_softc *sc = (struct maestro_softc *)self; 910 911 if (off < 0) 912 return -1; 913 return bus_dmamem_mmap(sc->dmat, &sc->dmaseg, 1, 914 off, prot, BUS_DMA_WAITOK); 915 } 916 917 int 918 maestro_get_props(self) 919 void *self; 920 { 921 /* struct maestro_softc *sc = (struct maestro_softc *)self; */ 922 923 return (AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT); /* XXX */ 924 } 925 926 int 927 maestro_getdev(self, retp) 928 void *self; 929 struct audio_device *retp; 930 { 931 struct maestro_softc *sc = (struct maestro_softc *)self; 932 933 *retp = *sc->sc_audev; 934 return 0; 935 } 936 937 int 938 maestro_set_port(self, cp) 939 void *self; 940 mixer_ctrl_t *cp; 941 { 942 struct ac97_codec_if *c = ((struct maestro_softc *)self)->codec_if; 943 944 if (c) 945 return (c->vtbl->mixer_set_port(c, cp)); 946 else 947 return (ENXIO); 948 } 949 950 int 951 maestro_get_port(self, cp) 952 void *self; 953 mixer_ctrl_t *cp; 954 { 955 struct ac97_codec_if *c = ((struct maestro_softc *)self)->codec_if; 956 957 if (c) 958 return (c->vtbl->mixer_get_port(c, cp)); 959 else 960 return (ENXIO); 961 } 962 963 int 964 maestro_query_devinfo(self, cp) 965 void *self; 966 mixer_devinfo_t *cp; 967 { 968 struct ac97_codec_if *c = ((struct maestro_softc *)self)->codec_if; 969 970 if (c) 971 return (c->vtbl->query_devinfo(c, cp)); 972 else 973 return (ENXIO); 974 } 975 976 struct audio_encoding maestro_tab[] = { 977 {0, AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 16, 0}, 978 {1, AudioEslinear, AUDIO_ENCODING_SLINEAR, 8, 0}, 979 {2, AudioEulinear, AUDIO_ENCODING_ULINEAR, 8, 0}, 980 {3, AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 16, 981 AUDIO_ENCODINGFLAG_EMULATED}, 982 {4, AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 16, 983 AUDIO_ENCODINGFLAG_EMULATED}, 984 {5, AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 16, 985 AUDIO_ENCODINGFLAG_EMULATED}, 986 {6, AudioEmulaw, AUDIO_ENCODING_ULAW, 8, 987 AUDIO_ENCODINGFLAG_EMULATED}, 988 {7, AudioEalaw, AUDIO_ENCODING_ALAW, 8, 989 AUDIO_ENCODINGFLAG_EMULATED} 990 }; 991 992 int 993 maestro_query_encoding(hdl, fp) 994 void *hdl; 995 struct audio_encoding *fp; 996 { 997 if (fp->index < 0 || fp->index >= lengthof(maestro_tab)) 998 return (EINVAL); 999 *fp = maestro_tab[fp->index]; 1000 return (0); 1001 } 1002 1003 void 1004 maestro_get_default_params(void *addr, int mode, struct audio_params *params) 1005 { 1006 ac97_get_default_params(params); 1007 } 1008 1009 #define UNUSED __attribute__((unused)) 1010 1011 void 1012 maestro_set_speed(ch, prate) 1013 struct maestro_channel *ch; 1014 u_long *prate; 1015 { 1016 ch->speed = *prate; 1017 if ((ch->mode & (MAESTRO_8BIT | MAESTRO_STEREO)) == MAESTRO_8BIT) 1018 ch->speed /= 2; 1019 1020 /* special common case */ 1021 if (ch->speed == 48000) { 1022 ch->dv = 0x10000; 1023 } else { 1024 /* compute 16 bits fixed point value of speed/48000, 1025 * being careful not to overflow */ 1026 ch->dv = (((ch->speed % 48000) << 16U) + 24000) / 48000 1027 + ((ch->speed / 48000) << 16U); 1028 /* And this is the real rate obtained */ 1029 ch->speed = (ch->dv >> 16U) * 48000 + 1030 (((ch->dv & 0xffff)*48000)>>16U); 1031 } 1032 *prate = ch->speed; 1033 if ((ch->mode & (MAESTRO_8BIT | MAESTRO_STEREO)) == MAESTRO_8BIT) 1034 *prate *= 2; 1035 } 1036 1037 u_int 1038 maestro_calc_timer_freq(ch) 1039 struct maestro_channel *ch; 1040 { 1041 u_int ss = 2; 1042 1043 if (ch->mode & MAESTRO_8BIT) 1044 ss = 1; 1045 return (ch->speed * ss) / ch->blocksize; 1046 } 1047 1048 void 1049 maestro_update_timer(sc) 1050 struct maestro_softc *sc; 1051 { 1052 u_int freq = 0; 1053 u_int n; 1054 1055 if (sc->play.mode & MAESTRO_RUNNING) 1056 freq = maestro_calc_timer_freq(&sc->play); 1057 if (sc->record.mode & MAESTRO_RUNNING) { 1058 n = maestro_calc_timer_freq(&sc->record); 1059 if (freq < n) 1060 freq = n; 1061 } 1062 if (freq) { 1063 wp_settimer(sc, freq); 1064 wp_starttimer(sc); 1065 } else 1066 wp_stoptimer(sc); 1067 } 1068 1069 1070 int 1071 maestro_set_params(hdl, setmode, usemode, play, rec) 1072 void *hdl; 1073 int setmode, usemode; 1074 struct audio_params *play, *rec; 1075 { 1076 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1077 1078 if ((setmode & AUMODE_PLAY) == 0) 1079 return (0); 1080 1081 /* Disallow parameter change on a running audio for now */ 1082 if (sc->play.mode & MAESTRO_RUNNING) 1083 return (EINVAL); 1084 1085 if (play->sample_rate < 4000) 1086 play->sample_rate = 4000; 1087 else if (play->sample_rate > 48000) 1088 play->sample_rate = 48000; 1089 1090 play->factor = 1; 1091 play->sw_code = NULL; 1092 if (play->channels > 2) 1093 play->channels = 2; 1094 1095 sc->play.mode = MAESTRO_PLAY; 1096 if (play->channels == 2) 1097 sc->play.mode |= MAESTRO_STEREO; 1098 1099 if (play->encoding == AUDIO_ENCODING_ULAW) { 1100 play->factor = 2; 1101 play->sw_code = mulaw_to_slinear16_le; 1102 } else if (play->encoding == AUDIO_ENCODING_ALAW) { 1103 play->factor = 2; 1104 play->sw_code = alaw_to_slinear16_le; 1105 } else if (play->precision == 8) { 1106 sc->play.mode |= MAESTRO_8BIT; 1107 if (play->encoding == AUDIO_ENCODING_ULINEAR_LE || 1108 play->encoding == AUDIO_ENCODING_ULINEAR_BE) 1109 sc->play.mode |= MAESTRO_UNSIGNED; 1110 } 1111 else if (play->encoding == AUDIO_ENCODING_ULINEAR_LE) 1112 play->sw_code = change_sign16_le; 1113 else if (play->encoding == AUDIO_ENCODING_SLINEAR_BE) 1114 play->sw_code = swap_bytes; 1115 else if (play->encoding == AUDIO_ENCODING_ULINEAR_BE) 1116 play->sw_code = change_sign16_swap_bytes_le; 1117 else if (play->encoding != AUDIO_ENCODING_SLINEAR_LE) 1118 return (EINVAL); 1119 1120 maestro_set_speed(&sc->play, &play->sample_rate); 1121 return (0); 1122 } 1123 1124 int 1125 maestro_open(hdl, flags) 1126 void *hdl; 1127 int flags; 1128 { 1129 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1130 DPRINTF(("%s: open(%d)\n", sc->dev.dv_xname, flags)); 1131 1132 /* XXX work around VM brokeness */ 1133 #if 0 1134 if ((OFLAGS(flags) & O_ACCMODE) != O_WRONLY) 1135 return (EINVAL); 1136 #endif 1137 sc->play.mode = MAESTRO_PLAY; 1138 sc->record.mode = 0; 1139 #ifdef AUDIO_DEBUG 1140 maestrointr_called = 0; 1141 maestrodma_effective = 0; 1142 #endif 1143 return (0); 1144 } 1145 1146 void 1147 maestro_close(hdl) 1148 void *hdl; 1149 { 1150 struct maestro_softc *sc UNUSED = (struct maestro_softc *)hdl; 1151 /* nothing to do */ 1152 } 1153 1154 1155 void 1156 maestro_channel_stop(ch) 1157 struct maestro_channel *ch; 1158 { 1159 wp_apu_write(ch->sc, ch->num, APUREG_APUTYPE, 1160 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1161 if (ch->mode & MAESTRO_STEREO) 1162 wp_apu_write(ch->sc, ch->num+1, APUREG_APUTYPE, 1163 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1164 /* four channels for record... */ 1165 if (ch->mode & MAESTRO_PLAY) 1166 return; 1167 wp_apu_write(ch->sc, ch->num+2, APUREG_APUTYPE, 1168 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1169 if (ch->mode & MAESTRO_STEREO) 1170 wp_apu_write(ch->sc, ch->num+3, APUREG_APUTYPE, 1171 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1172 1173 } 1174 1175 int 1176 maestro_halt_input(hdl) 1177 void *hdl; 1178 { 1179 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1180 maestro_channel_stop(&sc->record); 1181 sc->record.mode &= ~MAESTRO_RUNNING; 1182 maestro_update_timer(sc); 1183 return 0; 1184 } 1185 1186 int 1187 maestro_halt_output(hdl) 1188 void *hdl; 1189 { 1190 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1191 1192 maestro_channel_stop(&sc->play); 1193 sc->play.mode &= ~MAESTRO_RUNNING; 1194 maestro_update_timer(sc); 1195 return 0; 1196 } 1197 1198 int 1199 maestro_trigger_input(hdl, start, end, blksize, intr, arg, param) 1200 void *hdl; 1201 void *start, *end; 1202 int blksize; 1203 void (*intr)(void *); 1204 void *arg; 1205 struct audio_params *param; 1206 { 1207 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1208 1209 sc->record.mode |= MAESTRO_RUNNING; 1210 sc->record.blocksize = blksize; 1211 1212 maestro_channel_start(&sc->record); 1213 1214 sc->record.threshold = sc->record.start; 1215 maestro_update_timer(sc); 1216 return 0; 1217 } 1218 1219 void 1220 maestro_channel_start(ch) 1221 struct maestro_channel *ch; 1222 { 1223 struct maestro_softc *sc = ch->sc; 1224 int n = ch->num; 1225 int aputype; 1226 wcreg_t wcreg = (sc->physaddr - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK; 1227 1228 switch(ch->mode & (MAESTRO_STEREO | MAESTRO_8BIT)) { 1229 case 0: 1230 aputype = APUTYPE_16BITLINEAR; 1231 break; 1232 case MAESTRO_STEREO: 1233 aputype = APUTYPE_16BITSTEREO; 1234 break; 1235 case MAESTRO_8BIT: 1236 aputype = APUTYPE_8BITLINEAR; 1237 break; 1238 case MAESTRO_8BIT|MAESTRO_STEREO: 1239 aputype = APUTYPE_8BITSTEREO; 1240 break; 1241 } 1242 if (ch->mode & MAESTRO_UNSIGNED) 1243 wcreg |= WAVCACHE_CHCTL_U8; 1244 if ((ch->mode & MAESTRO_STEREO) == 0) { 1245 DPRINTF(("Setting mono parameters\n")); 1246 wp_apu_write(sc, n, APUREG_WAVESPACE, ch->wpwa & 0xff00); 1247 wp_apu_write(sc, n, APUREG_CURPTR, ch->current); 1248 wp_apu_write(sc, n, APUREG_ENDPTR, ch->end); 1249 wp_apu_write(sc, n, APUREG_LOOPLEN, ch->end - ch->start); 1250 wp_apu_write(sc, n, APUREG_AMPLITUDE, 0xe800); 1251 wp_apu_write(sc, n, APUREG_POSITION, 0x8f00 1252 | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 1253 | (PAN_FRONT << APU_PAN_SHIFT)); 1254 wp_apu_write(sc, n, APUREG_FREQ_LOBYTE, APU_plus6dB 1255 | ((ch->dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); 1256 wp_apu_write(sc, n, APUREG_FREQ_HIWORD, ch->dv >> 8); 1257 wc_ctrl_write(sc, n, wcreg); 1258 wp_apu_write(sc, n, APUREG_APUTYPE, 1259 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); 1260 } else { 1261 wcreg |= WAVCACHE_CHCTL_STEREO; 1262 DPRINTF(("Setting stereo parameters\n")); 1263 wp_apu_write(sc, n+1, APUREG_WAVESPACE, ch->wpwa & 0xff00); 1264 wp_apu_write(sc, n+1, APUREG_CURPTR, ch->current); 1265 wp_apu_write(sc, n+1, APUREG_ENDPTR, ch->end); 1266 wp_apu_write(sc, n+1, APUREG_LOOPLEN, ch->end - ch->start); 1267 wp_apu_write(sc, n+1, APUREG_AMPLITUDE, 0xe800); 1268 wp_apu_write(sc, n+1, APUREG_POSITION, 0x8f00 1269 | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 1270 | (PAN_LEFT << APU_PAN_SHIFT)); 1271 wp_apu_write(sc, n+1, APUREG_FREQ_LOBYTE, APU_plus6dB 1272 | ((ch->dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); 1273 wp_apu_write(sc, n+1, APUREG_FREQ_HIWORD, ch->dv >> 8); 1274 if (ch->mode & MAESTRO_8BIT) 1275 wp_apu_write(sc, n, APUREG_WAVESPACE, 1276 ch->wpwa & 0xff00); 1277 else 1278 wp_apu_write(sc, n, APUREG_WAVESPACE, 1279 (ch->wpwa|(APU_STEREO >> 1)) & 0xff00); 1280 wp_apu_write(sc, n, APUREG_CURPTR, ch->current); 1281 wp_apu_write(sc, n, APUREG_ENDPTR, ch->end); 1282 wp_apu_write(sc, n, APUREG_LOOPLEN, ch->end - ch->start); 1283 wp_apu_write(sc, n, APUREG_AMPLITUDE, 0xe800); 1284 wp_apu_write(sc, n, APUREG_POSITION, 0x8f00 1285 | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 1286 | (PAN_RIGHT << APU_PAN_SHIFT)); 1287 wp_apu_write(sc, n, APUREG_FREQ_LOBYTE, APU_plus6dB 1288 | ((ch->dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); 1289 wp_apu_write(sc, n, APUREG_FREQ_HIWORD, ch->dv >> 8); 1290 wc_ctrl_write(sc, n, wcreg); 1291 wc_ctrl_write(sc, n+1, wcreg); 1292 wp_apu_write(sc, n, APUREG_APUTYPE, 1293 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); 1294 wp_apu_write(sc, n+1, APUREG_APUTYPE, 1295 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); 1296 } 1297 } 1298 1299 int 1300 maestro_trigger_output(hdl, start, end, blksize, intr, arg, param) 1301 void *hdl; 1302 void *start, *end; 1303 int blksize; 1304 void (*intr)(void *); 1305 void *arg; 1306 struct audio_params *param; 1307 { 1308 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1309 1310 u_int offset = ((caddr_t)start - sc->dmabase) >> 1; 1311 u_int size = ((char *)end - (char *)start) >> 1; 1312 sc->play.mode |= MAESTRO_RUNNING; 1313 sc->play.wpwa = APU_USE_SYSMEM | (offset >> 8); 1314 DPRINTF(("maestro_trigger_output: start=%x, end=%x, blksize=%x ", 1315 start, end, blksize)); 1316 DPRINTF(("offset = %x, size=%x\n", offset, size)); 1317 1318 sc->play.intr = intr; 1319 sc->play.intr_arg = arg; 1320 sc->play.blocksize = blksize; 1321 sc->play.end = offset+size; 1322 sc->play.start = offset; 1323 sc->play.current = sc->play.start; 1324 if ((sc->play.mode & (MAESTRO_STEREO | MAESTRO_8BIT)) == MAESTRO_STEREO) { 1325 sc->play.wpwa >>= 1; 1326 sc->play.start >>= 1; 1327 sc->play.end >>= 1; 1328 sc->play.blocksize >>= 1; 1329 } 1330 maestro_channel_start(&sc->play); 1331 1332 sc->play.threshold = sc->play.start; 1333 maestro_update_timer(sc); 1334 1335 return 0; 1336 } 1337 1338 /* ----------------------------- 1339 * Codec interface 1340 */ 1341 1342 enum ac97_host_flags 1343 maestro_codec_flags(self) 1344 void *self; 1345 { 1346 return AC97_HOST_DONT_READ; 1347 } 1348 1349 int 1350 maestro_read_codec(self, regno, datap) 1351 void *self; 1352 u_int8_t regno; 1353 u_int16_t *datap; 1354 { 1355 struct maestro_softc *sc = (struct maestro_softc *)self; 1356 int t; 1357 1358 /* We have to wait for a SAFE time to write addr/data */ 1359 for (t = 0; t < 20; t++) { 1360 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1361 & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS) 1362 break; 1363 DELAY(2); /* 20.8us / 13 */ 1364 } 1365 if (t == 20) 1366 printf("%s: maestro_read_codec() PROGLESS timed out.\n", 1367 sc->dev.dv_xname); 1368 /* XXX return 1 */ 1369 1370 bus_space_write_1(sc->iot, sc->ioh, PORT_CODEC_CMD, 1371 CODEC_CMD_READ | regno); 1372 DELAY(21); /* AC97 cycle = 20.8usec */ 1373 1374 /* Wait for data retrieve */ 1375 for (t = 0; t < 20; t++) { 1376 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1377 & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE) 1378 break; 1379 DELAY(2); /* 20.8us / 13 */ 1380 } 1381 if (t == 20) 1382 /* Timed out, but perform dummy read. */ 1383 printf("%s: maestro_read_codec() RW_DONE timed out.\n", 1384 sc->dev.dv_xname); 1385 1386 *datap = bus_space_read_2(sc->iot, sc->ioh, PORT_CODEC_REG); 1387 return 0; 1388 } 1389 1390 int 1391 maestro_write_codec(self, regno, data) 1392 void *self; 1393 u_int8_t regno; 1394 u_int16_t data; 1395 { 1396 struct maestro_softc *sc = (struct maestro_softc *)self; 1397 int t; 1398 1399 /* We have to wait for a SAFE time to write addr/data */ 1400 for (t = 0; t < 20; t++) { 1401 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1402 & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS) 1403 break; 1404 DELAY(2); /* 20.8us / 13 */ 1405 } 1406 if (t == 20) { 1407 /* Timed out. Abort writing. */ 1408 printf("%s: maestro_write_codec() PROGLESS timed out.\n", 1409 sc->dev.dv_xname); 1410 return 1; 1411 } 1412 1413 bus_space_write_2(sc->iot, sc->ioh, PORT_CODEC_REG, data); 1414 bus_space_write_1(sc->iot, sc->ioh, PORT_CODEC_CMD, 1415 CODEC_CMD_WRITE | regno); 1416 1417 return 0; 1418 } 1419 1420 int 1421 maestro_attach_codec(self, cif) 1422 void *self; 1423 struct ac97_codec_if *cif; 1424 { 1425 struct maestro_softc *sc = (struct maestro_softc *)self; 1426 1427 sc->codec_if = cif; 1428 return 0; 1429 } 1430 1431 void 1432 maestro_reset_codec(self) 1433 void *self UNUSED; 1434 { 1435 } 1436 1437 void 1438 maestro_initcodec(self) 1439 void *self; 1440 { 1441 struct maestro_softc *sc = (struct maestro_softc *)self; 1442 u_int16_t data; 1443 1444 if (bus_space_read_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL) 1445 & RINGBUS_CTRL_ACLINK_ENABLED) { 1446 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, 0); 1447 DELAY(104); /* 20.8us * (4 + 1) */ 1448 } 1449 /* XXX - 2nd codec should be looked at. */ 1450 bus_space_write_4(sc->iot, sc->ioh, 1451 PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET); 1452 DELAY(2); 1453 bus_space_write_4(sc->iot, sc->ioh, 1454 PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED); 1455 DELAY(21); 1456 1457 maestro_read_codec(sc, 0, &data); 1458 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1459 & CODEC_STAT_MASK) != 0) { 1460 bus_space_write_4(sc->iot, sc->ioh, 1461 PORT_RINGBUS_CTRL, 0); 1462 DELAY(21); 1463 1464 /* Try cold reset. */ 1465 printf("%s: resetting codec\n", sc->dev.dv_xname); 1466 1467 data = bus_space_read_2(sc->iot, sc->ioh, PORT_GPIO_DIR); 1468 if (pci_conf_read(sc->pc, sc->pt, 0x58) & 1) 1469 data |= 0x10; 1470 data |= 0x009 & 1471 ~bus_space_read_2(sc->iot, sc->ioh, PORT_GPIO_DATA); 1472 bus_space_write_2(sc->iot, sc->ioh, 1473 PORT_GPIO_MASK, 0xff6); 1474 bus_space_write_2(sc->iot, sc->ioh, 1475 PORT_GPIO_DIR, data | 0x009); 1476 bus_space_write_2(sc->iot, sc->ioh, 1477 PORT_GPIO_DATA, 0x000); 1478 DELAY(2); 1479 bus_space_write_2(sc->iot, sc->ioh, 1480 PORT_GPIO_DATA, 0x001); 1481 DELAY(1); 1482 bus_space_write_2(sc->iot, sc->ioh, 1483 PORT_GPIO_DATA, 0x009); 1484 DELAY(500000); 1485 bus_space_write_2(sc->iot, sc->ioh, 1486 PORT_GPIO_DIR, data); 1487 DELAY(84); /* 20.8us * 4 */ 1488 bus_space_write_4(sc->iot, sc->ioh, 1489 PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED); 1490 DELAY(21); 1491 } 1492 1493 /* Check the codec to see is still busy */ 1494 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) & 1495 CODEC_STAT_MASK) != 0) { 1496 printf("%s: codec failure\n", sc->dev.dv_xname); 1497 } 1498 } 1499 1500 /* ----------------------------- 1501 * Power management interface 1502 */ 1503 1504 void 1505 maestro_powerhook(why, self) 1506 int why; 1507 void *self; 1508 { 1509 struct maestro_softc *sc = (struct maestro_softc *)self; 1510 1511 if (why != PWR_RESUME) { 1512 /* Power down device on shutdown. */ 1513 DPRINTF(("maestro: power down\n")); 1514 sc->suspend = why; 1515 if (sc->record.mode & MAESTRO_RUNNING) { 1516 sc->record.current = wp_apu_read(sc, sc->record.num, APUREG_CURPTR); 1517 maestro_channel_stop(&sc->record); 1518 } 1519 if (sc->play.mode & MAESTRO_RUNNING) { 1520 sc->play.current = wp_apu_read(sc, sc->play.num, APUREG_CURPTR); 1521 maestro_channel_stop(&sc->play); 1522 } 1523 1524 wp_stoptimer(sc); 1525 1526 /* Power down everything except clock. */ 1527 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 0); 1528 maestro_write_codec(sc, AC97_REG_POWER, 0xdf00); 1529 DELAY(20); 1530 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, 0); 1531 DELAY(1); 1532 maestro_power(sc, PPMI_D3); 1533 } else { 1534 /* Power up device on resume. */ 1535 DPRINTF(("maestro: power resume\n")); 1536 if (sc->suspend == PWR_RESUME) { 1537 printf("%s: resume without suspend?\n", 1538 sc->dev.dv_xname); 1539 sc->suspend = why; 1540 return; 1541 } 1542 sc->suspend = why; 1543 maestro_power(sc, PPMI_D0); 1544 DELAY(100000); 1545 maestro_init(sc); 1546 /* Restore codec settings */ 1547 if (sc->codec_if) 1548 sc->codec_if->vtbl->restore_ports(sc->codec_if); 1549 if (sc->play.mode & MAESTRO_RUNNING) 1550 maestro_channel_start(&sc->play); 1551 if (sc->record.mode & MAESTRO_RUNNING) 1552 maestro_channel_start(&sc->record); 1553 maestro_update_timer(sc); 1554 } 1555 } 1556 1557 void 1558 maestro_power(sc, status) 1559 struct maestro_softc *sc; 1560 int status; 1561 { 1562 int data; 1563 1564 /* Set the power state of the device. */ 1565 data = pci_conf_read(sc->pc, sc->pt, CONF_PM_PTR); 1566 data = pci_conf_read(sc->pc, sc->pt, data); 1567 if (data == PPMI_CID) 1568 pci_conf_write(sc->pc, sc->pt, data + PM_CTRL, status); 1569 } 1570 1571 void 1572 maestro_channel_advance_dma(ch) 1573 struct maestro_channel *ch; 1574 { 1575 wpreg_t pos; 1576 #ifdef AUDIO_DEBUG 1577 maestrointr_called++; 1578 #endif 1579 for (;;) { 1580 pos = wp_apu_read(ch->sc, ch->num, APUREG_CURPTR); 1581 /* Are we still processing the current dma block ? */ 1582 if (pos >= ch->threshold && 1583 pos < ch->threshold + ch->blocksize/2) 1584 break; 1585 ch->threshold += ch->blocksize/2; 1586 if (ch->threshold >= ch->end) 1587 ch->threshold = ch->start; 1588 (*ch->intr)(ch->intr_arg); 1589 #ifdef AUDIO_DEBUG 1590 maestrodma_effective++; 1591 #endif 1592 } 1593 1594 #ifdef AUDIO_DEBUG 1595 if (maestrodebug && maestrointr_called % 64 == 0) 1596 printf("maestro: dma advanced %lu for %lu calls\n", 1597 maestrodma_effective, maestrointr_called); 1598 #endif 1599 } 1600 1601 /* Some maestro makes sometimes get desynchronized in stereo mode. */ 1602 void 1603 maestro_channel_suppress_jitter(ch) 1604 struct maestro_channel *ch; 1605 { 1606 int cp, diff; 1607 1608 /* Verify that both channels are not too far off. */ 1609 cp = wp_apu_read(ch->sc, ch->num, APUREG_CURPTR); 1610 diff = wp_apu_read(ch->sc, ch->num+1, APUREG_CURPTR) - cp; 1611 if (diff > 4 || diff < -4) 1612 /* Otherwise, directly resynch the 2nd channel. */ 1613 bus_space_write_2(ch->sc->iot, ch->sc->ioh, 1614 PORT_DSP_DATA, cp); 1615 } 1616 1617 /* ----------------------------- 1618 * Interrupt handler interface 1619 */ 1620 int 1621 maestro_intr(arg) 1622 void *arg; 1623 { 1624 struct maestro_softc *sc = (struct maestro_softc *)arg; 1625 u_int16_t status; 1626 1627 status = bus_space_read_1(sc->iot, sc->ioh, PORT_HOSTINT_STAT); 1628 if (status == 0) 1629 return 0; /* Not for us? */ 1630 1631 /* Acknowledge all. */ 1632 bus_space_write_2(sc->iot, sc->ioh, PORT_INT_STAT, 1); 1633 bus_space_write_1(sc->iot, sc->ioh, PORT_HOSTINT_STAT, status); 1634 1635 /* Hardware volume support */ 1636 if (status & HOSTINT_STAT_HWVOL && sc->codec_if != NULL) { 1637 int n, i, delta, v; 1638 mixer_ctrl_t hwvol; 1639 1640 n = bus_space_read_1(sc->iot, sc->ioh, PORT_HWVOL_MASTER); 1641 /* Special case: Mute key */ 1642 if (n & 0x11) { 1643 hwvol.type = AUDIO_MIXER_ENUM; 1644 hwvol.dev = 1645 sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, 1646 AudioCoutputs, AudioNmaster, AudioNmute); 1647 sc->codec_if->vtbl->mixer_get_port(sc->codec_if, &hwvol); 1648 hwvol.un.ord = !hwvol.un.ord; 1649 } else { 1650 hwvol.type = AUDIO_MIXER_VALUE; 1651 hwvol.un.value.num_channels = 2; 1652 hwvol.dev = 1653 sc->codec_if->vtbl->get_portnum_by_name( 1654 sc->codec_if, AudioCoutputs, AudioNmaster, 1655 NULL); 1656 sc->codec_if->vtbl->mixer_get_port(sc->codec_if, &hwvol); 1657 /* XXX AC'97 yields five bits for master volume. */ 1658 delta = (n - MIDDLE_VOLUME)/STEP_VOLUME * 8; 1659 for (i = 0; i < hwvol.un.value.num_channels; i++) { 1660 v = ((int)hwvol.un.value.level[i]) + delta; 1661 if (v < 0) 1662 v = 0; 1663 else if (v > 255) 1664 v = 255; 1665 hwvol.un.value.level[i] = v; 1666 } 1667 } 1668 sc->codec_if->vtbl->mixer_set_port(sc->codec_if, &hwvol); 1669 /* Reset to compute next diffs */ 1670 bus_space_write_1(sc->iot, sc->ioh, PORT_HWVOL_MASTER, 1671 MIDDLE_VOLUME); 1672 } 1673 1674 if (sc->play.mode & MAESTRO_RUNNING) { 1675 maestro_channel_advance_dma(&sc->play); 1676 if (sc->play.mode & MAESTRO_STEREO) 1677 maestro_channel_suppress_jitter(&sc->play); 1678 } 1679 1680 if (sc->record.mode & MAESTRO_RUNNING) 1681 maestro_channel_advance_dma(&sc->record); 1682 1683 return 1; 1684 } 1685 1686 /* ----------------------------- 1687 * Hardware interface 1688 */ 1689 1690 /* Codec/Ringbus */ 1691 1692 void 1693 ringbus_setdest(struct maestro_softc *sc, int src, int dest) 1694 { 1695 u_int32_t data; 1696 1697 data = bus_space_read_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL); 1698 data &= ~(0xfU << src); 1699 data |= (0xfU & dest) << src; 1700 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, data); 1701 } 1702 1703 /* Wave Processor */ 1704 1705 wpreg_t 1706 wp_reg_read(struct maestro_softc *sc, int reg) 1707 { 1708 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_INDEX, reg); 1709 return bus_space_read_2(sc->iot, sc->ioh, PORT_DSP_DATA); 1710 } 1711 1712 void 1713 wp_reg_write(struct maestro_softc *sc, int reg, wpreg_t data) 1714 { 1715 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_INDEX, reg); 1716 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_DATA, data); 1717 } 1718 1719 static void 1720 apu_setindex(struct maestro_softc *sc, int reg) 1721 { 1722 int t; 1723 1724 wp_reg_write(sc, WPREG_CRAM_PTR, reg); 1725 /* Sometimes WP fails to set apu register index. */ 1726 for (t = 0; t < 1000; t++) { 1727 if (bus_space_read_2(sc->iot, sc->ioh, 1728 PORT_DSP_DATA) == reg) 1729 break; 1730 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_DATA, reg); 1731 } 1732 if (t == 1000) 1733 printf("%s: apu_setindex() timeout\n", sc->dev.dv_xname); 1734 } 1735 1736 wpreg_t 1737 wp_apu_read(struct maestro_softc *sc, int ch, int reg) 1738 { 1739 wpreg_t ret; 1740 1741 apu_setindex(sc, ((unsigned)ch << 4) + reg); 1742 ret = wp_reg_read(sc, WPREG_DATA_PORT); 1743 return ret; 1744 } 1745 1746 void 1747 wp_apu_write(struct maestro_softc *sc, int ch, int reg, wpreg_t data) 1748 { 1749 int t; 1750 1751 apu_setindex(sc, ((unsigned)ch << 4) + reg); 1752 wp_reg_write(sc, WPREG_DATA_PORT, data); 1753 for (t = 0; t < 1000; t++) { 1754 if (bus_space_read_2(sc->iot, sc->ioh, PORT_DSP_DATA) == data) 1755 break; 1756 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_DATA, data); 1757 } 1758 if (t == 1000) 1759 printf("%s: wp_apu_write() timeout\n", sc->dev.dv_xname); 1760 } 1761 1762 void 1763 wp_settimer(struct maestro_softc *sc, u_int freq) 1764 { 1765 u_int clock = 48000 << 2; 1766 u_int prescale = 0, divide = (freq != 0) ? (clock / freq) : ~0; 1767 1768 if (divide < 4) 1769 divide = 4; 1770 else if (divide > 32 << 8) 1771 divide = 32 << 8; 1772 1773 for (; divide > 32 << 1; divide >>= 1) 1774 prescale++; 1775 divide = (divide + 1) >> 1; 1776 1777 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1) 1778 prescale++; 1779 1780 wp_reg_write(sc, WPREG_TIMER_ENABLE, 0); 1781 wp_reg_write(sc, WPREG_TIMER_FREQ, 1782 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1)); 1783 wp_reg_write(sc, WPREG_TIMER_ENABLE, 1); 1784 } 1785 1786 void 1787 wp_starttimer(struct maestro_softc *sc) 1788 { 1789 wp_reg_write(sc, WPREG_TIMER_START, 1); 1790 } 1791 1792 void 1793 wp_stoptimer(struct maestro_softc *sc) 1794 { 1795 wp_reg_write(sc, WPREG_TIMER_START, 0); 1796 bus_space_write_2(sc->iot, sc->ioh, PORT_INT_STAT, 1); 1797 } 1798 1799 /* WaveCache */ 1800 1801 wcreg_t 1802 wc_reg_read(struct maestro_softc *sc, int reg) 1803 { 1804 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_INDEX, reg); 1805 return bus_space_read_2(sc->iot, sc->ioh, PORT_WAVCACHE_DATA); 1806 } 1807 1808 void 1809 wc_reg_write(struct maestro_softc *sc, int reg, wcreg_t data) 1810 { 1811 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_INDEX, reg); 1812 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_DATA, data); 1813 } 1814 1815 u_int16_t 1816 wc_ctrl_read(struct maestro_softc *sc, int ch) 1817 { 1818 return wc_reg_read(sc, ch << 3); 1819 } 1820 1821 void 1822 wc_ctrl_write(struct maestro_softc *sc, int ch, wcreg_t data) 1823 { 1824 wc_reg_write(sc, ch << 3, data); 1825 } 1826 1827 /* ----------------------------- 1828 * Simple zone allocator. 1829 * (All memory allocated in advance) 1830 */ 1831 1832 salloc_t 1833 salloc_new(addr, size, nzones) 1834 caddr_t addr; 1835 size_t size; 1836 int nzones; 1837 { 1838 struct salloc_pool *pool; 1839 struct salloc_zone *space; 1840 int i; 1841 1842 pool = malloc(sizeof *pool + nzones * sizeof pool->zones[0], 1843 M_TEMP, M_NOWAIT); 1844 if (pool == NULL) 1845 return NULL; 1846 SLIST_INIT(&pool->free); 1847 SLIST_INIT(&pool->used); 1848 SLIST_INIT(&pool->spare); 1849 /* Espie says the following line is obvious */ 1850 pool->zones = (struct salloc_zone *)(pool + 1); 1851 for (i = 1; i < nzones; i++) 1852 SLIST_INSERT_HEAD(&pool->spare, &pool->zones[i], link); 1853 space = &pool->zones[0]; 1854 space->addr = addr; 1855 space->size = size; 1856 SLIST_INSERT_HEAD(&pool->free, space, link); 1857 return pool; 1858 } 1859 1860 void 1861 salloc_destroy(pool) 1862 salloc_t pool; 1863 { 1864 free(pool, M_TEMP); 1865 } 1866 1867 void 1868 salloc_insert(pool, head, zone, merge) 1869 salloc_t pool; 1870 struct salloc_head *head; 1871 struct salloc_zone *zone; 1872 int merge; 1873 { 1874 struct salloc_zone *prev, *next; 1875 1876 /* 1877 * Insert a zone into an ordered list of zones, possibly 1878 * merging adjacent zones. 1879 */ 1880 prev = NULL; 1881 SLIST_FOREACH(next, head, link) { 1882 if (next->addr > zone->addr) 1883 break; 1884 prev = next; 1885 } 1886 1887 if (merge && prev && prev->addr + prev->size == zone->addr) { 1888 prev->size += zone->size; 1889 SLIST_INSERT_HEAD(&pool->spare, zone, link); 1890 zone = prev; 1891 } else if (prev) 1892 SLIST_INSERT_AFTER(prev, zone, link); 1893 else 1894 SLIST_INSERT_HEAD(head, zone, link); 1895 if (merge && next && zone->addr + zone->size == next->addr) { 1896 zone->size += next->size; 1897 SLIST_REMOVE(head, next, salloc_zone, link); 1898 SLIST_INSERT_HEAD(&pool->spare, next, link); 1899 } 1900 } 1901 1902 caddr_t 1903 salloc_alloc(pool, size) 1904 salloc_t pool; 1905 size_t size; 1906 { 1907 struct salloc_zone *zone, *uzone; 1908 1909 SLIST_FOREACH(zone, &pool->free, link) 1910 if (zone->size >= size) 1911 break; 1912 if (zone == SLIST_END(&pool->free)) 1913 return NULL; 1914 if (zone->size == size) { 1915 SLIST_REMOVE(&pool->free, zone, salloc_zone, link); 1916 uzone = zone; 1917 } else { 1918 uzone = SLIST_FIRST(&pool->spare); 1919 if (uzone == NULL) 1920 return NULL; /* XXX */ 1921 SLIST_REMOVE_HEAD(&pool->spare, link); 1922 uzone->size = size; 1923 uzone->addr = zone->addr; 1924 zone->size -= size; 1925 zone->addr += size; 1926 } 1927 salloc_insert(pool, &pool->used, uzone, 0); 1928 return uzone->addr; 1929 } 1930 1931 void 1932 salloc_free(pool, addr) 1933 salloc_t pool; 1934 caddr_t addr; 1935 { 1936 struct salloc_zone *zone; 1937 1938 SLIST_FOREACH(zone, &pool->used, link) 1939 if (zone->addr == addr) 1940 break; 1941 #ifdef DIAGNOSTIC 1942 if (zone == SLIST_END(&pool->used)) 1943 panic("salloc_free: freeing unallocated memory"); 1944 #endif 1945 SLIST_REMOVE(&pool->used, zone, salloc_zone, link); 1946 salloc_insert(pool, &pool->free, zone, 1); 1947 } 1948