1 /* $OpenBSD: maestro.c,v 1.31 2010/09/07 16:21:45 deraadt Exp $ */ 2 /* $FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro.c,v 1.3 2000/11/21 12:22:11 julian Exp $ */ 3 /* 4 * FreeBSD's ESS Agogo/Maestro driver 5 * Converted from FreeBSD's pcm to OpenBSD's audio. 6 * Copyright (c) 2000, 2001 David Leonard & Marc Espie 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 /*- 31 * (FreeBSD) Credits: 32 * Copyright (c) 2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp> 33 * 34 * Part of this code (especially in many magic numbers) was heavily inspired 35 * by the Linux driver originally written by 36 * Alan Cox <alan.cox@linux.org>, modified heavily by 37 * Zach Brown <zab@zabbo.net>. 38 * 39 * busdma()-ize and buffer size reduction were suggested by 40 * Cameron Grant <gandalf@vilnya.demon.co.uk>. 41 * Also he showed me the way to use busdma() suite. 42 * 43 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500 44 * were looked at by 45 * Munehiro Matsuda <haro@tk.kubota.co.jp>, 46 * who brought patches based on the Linux driver with some simplification. 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/queue.h> 55 #include <sys/fcntl.h> 56 57 #include <dev/pci/pcidevs.h> 58 #include <dev/pci/pcivar.h> 59 60 #include <sys/audioio.h> 61 #include <dev/audio_if.h> 62 #include <dev/mulaw.h> 63 #include <dev/auconv.h> 64 65 #include <dev/ic/ac97.h> 66 67 /* ----------------------------- 68 * PCI config registers 69 */ 70 71 /* Legacy emulation */ 72 #define CONF_LEGACY 0x40 73 74 #define LEGACY_DISABLED 0x8000 75 76 /* Chip configurations */ 77 #define CONF_MAESTRO 0x50 78 #define MAESTRO_CHIBUS 0x00100000 79 #define MAESTRO_POSTEDWRITE 0x00000080 80 #define MAESTRO_DMA_PCITIMING 0x00000040 81 #define MAESTRO_SWAP_LR 0x00000010 82 83 /* ACPI configurations */ 84 #define CONF_ACPI_STOPCLOCK 0x54 85 #define ACPI_PART_2ndC_CLOCK 15 86 #define ACPI_PART_CODEC_CLOCK 14 87 #define ACPI_PART_978 13 /* Docking station or something */ 88 #define ACPI_PART_SPDIF 12 89 #define ACPI_PART_GLUE 11 /* What? */ 90 #define ACPI_PART_DAA 10 91 #define ACPI_PART_PCI_IF 9 92 #define ACPI_PART_HW_VOL 8 93 #define ACPI_PART_GPIO 7 94 #define ACPI_PART_ASSP 6 95 #define ACPI_PART_SB 5 96 #define ACPI_PART_FM 4 97 #define ACPI_PART_RINGBUS 3 98 #define ACPI_PART_MIDI 2 99 #define ACPI_PART_GAME_PORT 1 100 #define ACPI_PART_WP 0 101 102 /* Power management */ 103 #define CONF_PM_PTR 0x34 /* BYTE R */ 104 #define PM_CID 0 /* BYTE R */ 105 #define PPMI_CID 1 106 #define PM_CTRL 4 /* BYTE RW */ 107 #define PPMI_D0 0 /* Full power */ 108 #define PPMI_D1 1 /* Medium power */ 109 #define PPMI_D2 2 /* Low power */ 110 #define PPMI_D3 3 /* Turned off */ 111 112 113 /* ----------------------------- 114 * I/O ports 115 */ 116 117 /* Direct Sound Processor (aka Wave Processor) */ 118 #define PORT_DSP_DATA 0x00 /* WORD RW */ 119 #define PORT_DSP_INDEX 0x02 /* WORD RW */ 120 #define PORT_INT_STAT 0x04 /* WORD RW */ 121 #define PORT_SAMPLE_CNT 0x06 /* WORD RO */ 122 123 /* WaveCache */ 124 #define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */ 125 #define PORT_WAVCACHE_DATA 0x12 /* WORD RW */ 126 #define WAVCACHE_PCMBAR 0x1fc 127 #define WAVCACHE_WTBAR 0x1f0 128 #define WAVCACHE_BASEADDR_SHIFT 12 129 130 #define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8 131 #define WAVCACHE_CHCTL_U8 0x0004 132 #define WAVCACHE_CHCTL_STEREO 0x0002 133 #define WAVCACHE_CHCTL_DECREMENTAL 0x0001 134 135 #define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */ 136 #define WAVCACHE_EXTRA_CH_ENABLED 0x0200 137 #define WAVCACHE_ENABLED 0x0100 138 #define WAVCACHE_CH_60_ENABLED 0x0080 139 #define WAVCACHE_WTSIZE_MASK 0x0060 140 #define WAVCACHE_WTSIZE_1MB 0x0000 141 #define WAVCACHE_WTSIZE_2MB 0x0020 142 #define WAVCACHE_WTSIZE_4MB 0x0040 143 #define WAVCACHE_WTSIZE_8MB 0x0060 144 #define WAVCACHE_SGC_MASK 0x000c 145 #define WAVCACHE_SGC_DISABLED 0x0000 146 #define WAVCACHE_SGC_40_47 0x0004 147 #define WAVCACHE_SGC_32_47 0x0008 148 #define WAVCACHE_TESTMODE 0x0001 149 150 /* Host Interruption */ 151 #define PORT_HOSTINT_CTRL 0x18 /* WORD RW */ 152 #define HOSTINT_CTRL_SOFT_RESET 0x8000 153 #define HOSTINT_CTRL_DSOUND_RESET 0x4000 154 #define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400 155 #define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100 156 #define HOSTINT_CTRL_HWVOL_ENABLED 0x0040 157 #define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010 158 #define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008 159 #define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004 160 #define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002 161 #define HOSTINT_CTRL_SB_INT_ENABLED 0x0001 162 163 #define PORT_HOSTINT_STAT 0x1a /* BYTE RW */ 164 #define HOSTINT_STAT_HWVOL 0x40 165 #define HOSTINT_STAT_ASSP 0x10 166 #define HOSTINT_STAT_ISDN 0x08 167 #define HOSTINT_STAT_DSOUND 0x04 168 #define HOSTINT_STAT_MPU401 0x02 169 #define HOSTINT_STAT_SB 0x01 170 171 /* Hardware volume */ 172 #define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */ 173 #define PORT_HWVOL_VOICE 0x1d /* BYTE RW */ 174 #define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */ 175 #define PORT_HWVOL_MASTER 0x1f /* BYTE RW */ 176 177 /* CODEC */ 178 #define PORT_CODEC_CMD 0x30 /* BYTE W */ 179 #define CODEC_CMD_READ 0x80 180 #define CODEC_CMD_WRITE 0x00 181 #define CODEC_CMD_ADDR_MASK 0x7f 182 183 #define PORT_CODEC_STAT 0x30 /* BYTE R */ 184 #define CODEC_STAT_MASK 0x01 185 #define CODEC_STAT_RW_DONE 0x00 186 #define CODEC_STAT_PROGLESS 0x01 187 188 #define PORT_CODEC_REG 0x32 /* WORD RW */ 189 190 /* Ring bus control */ 191 #define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */ 192 #define RINGBUS_CTRL_I2S_ENABLED 0x80000000 193 #define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000 194 #define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000 195 #define RINGBUS_CTRL_AC97_SWRESET 0x08000000 196 #define RINGBUS_CTRL_IODMA_PLAYBACK_ENABLED 0x04000000 197 #define RINGBUS_CTRL_IODMA_RECORD_ENABLED 0x02000000 198 199 #define RINGBUS_SRC_MIC 20 200 #define RINGBUS_SRC_I2S 16 201 #define RINGBUS_SRC_ADC 12 202 #define RINGBUS_SRC_MODEM 8 203 #define RINGBUS_SRC_DSOUND 4 204 #define RINGBUS_SRC_ASSP 0 205 206 #define RINGBUS_DEST_MONORAL 000 207 #define RINGBUS_DEST_STEREO 010 208 #define RINGBUS_DEST_NONE 0 209 #define RINGBUS_DEST_DAC 1 210 #define RINGBUS_DEST_MODEM_IN 2 211 #define RINGBUS_DEST_RESERVED3 3 212 #define RINGBUS_DEST_DSOUND_IN 4 213 #define RINGBUS_DEST_ASSP_IN 5 214 215 /* General Purpose I/O */ 216 #define PORT_GPIO_DATA 0x60 /* WORD RW */ 217 #define PORT_GPIO_MASK 0x64 /* WORD RW */ 218 #define PORT_GPIO_DIR 0x68 /* WORD RW */ 219 220 /* Application Specific Signal Processor */ 221 #define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */ 222 #define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */ 223 #define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */ 224 #define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */ 225 #define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */ 226 #define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */ 227 #define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */ 228 #define PORT_ASSP_INT_STAT 0xac /* BYTE RW */ 229 230 231 /* ----------------------------- 232 * Wave Processor Indexed Data Registers. 233 */ 234 235 #define WPREG_DATA_PORT 0 236 #define WPREG_CRAM_PTR 1 237 #define WPREG_CRAM_DATA 2 238 #define WPREG_WAVE_DATA 3 239 #define WPREG_WAVE_PTR_LOW 4 240 #define WPREG_WAVE_PTR_HIGH 5 241 242 #define WPREG_TIMER_FREQ 6 243 #define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */ 244 #define WP_TIMER_FREQ_PRESCALE_SHIFT 5 245 #define WP_TIMER_FREQ_DIVIDE_MASK 0x001f 246 #define WP_TIMER_FREQ_DIVIDE_SHIFT 0 247 248 #define WPREG_WAVE_ROMRAM 7 249 #define WP_WAVE_VIRTUAL_ENABLED 0x0400 250 #define WP_WAVE_8BITRAM_ENABLED 0x0200 251 #define WP_WAVE_DRAM_ENABLED 0x0100 252 #define WP_WAVE_RAMSPLIT_MASK 0x00ff 253 #define WP_WAVE_RAMSPLIT_SHIFT 0 254 255 #define WPREG_BASE 12 256 #define WP_PARAOUT_BASE_MASK 0xf000 257 #define WP_PARAOUT_BASE_SHIFT 12 258 #define WP_PARAIN_BASE_MASK 0x0f00 259 #define WP_PARAIN_BASE_SHIFT 8 260 #define WP_SERIAL0_BASE_MASK 0x00f0 261 #define WP_SERIAL0_BASE_SHIFT 4 262 #define WP_SERIAL1_BASE_MASK 0x000f 263 #define WP_SERIAL1_BASE_SHIFT 0 264 265 #define WPREG_TIMER_ENABLE 17 266 #define WPREG_TIMER_START 23 267 268 269 /* ----------------------------- 270 * Audio Processing Unit. 271 */ 272 #define APUREG_APUTYPE 0 273 #define APU_DMA_ENABLED 0x4000 274 #define APU_INT_ON_LOOP 0x2000 275 #define APU_ENDCURVE 0x1000 276 #define APU_APUTYPE_MASK 0x00f0 277 #define APU_FILTERTYPE_MASK 0x000c 278 #define APU_FILTERQ_MASK 0x0003 279 280 /* APU types */ 281 #define APU_APUTYPE_SHIFT 4 282 283 #define APUTYPE_INACTIVE 0 284 #define APUTYPE_16BITLINEAR 1 285 #define APUTYPE_16BITSTEREO 2 286 #define APUTYPE_8BITLINEAR 3 287 #define APUTYPE_8BITSTEREO 4 288 #define APUTYPE_8BITDIFF 5 289 #define APUTYPE_DIGITALDELAY 6 290 #define APUTYPE_DUALTAP_READER 7 291 #define APUTYPE_CORRELATOR 8 292 #define APUTYPE_INPUTMIXER 9 293 #define APUTYPE_WAVETABLE 10 294 #define APUTYPE_RATECONV 11 295 #define APUTYPE_16BITPINGPONG 12 296 /* APU type 13 through 15 are reserved. */ 297 298 /* Filter types */ 299 #define APU_FILTERTYPE_SHIFT 2 300 301 #define FILTERTYPE_2POLE_LOPASS 0 302 #define FILTERTYPE_2POLE_BANDPASS 1 303 #define FILTERTYPE_2POLE_HIPASS 2 304 #define FILTERTYPE_1POLE_LOPASS 3 305 #define FILTERTYPE_1POLE_HIPASS 4 306 #define FILTERTYPE_PASSTHROUGH 5 307 308 /* Filter Q */ 309 #define APU_FILTERQ_SHIFT 0 310 311 #define FILTERQ_LESSQ 0 312 #define FILTERQ_MOREQ 3 313 314 /* APU register 2 */ 315 #define APUREG_FREQ_LOBYTE 2 316 #define APU_FREQ_LOBYTE_MASK 0xff00 317 #define APU_plus6dB 0x0010 318 319 /* APU register 3 */ 320 #define APUREG_FREQ_HIWORD 3 321 #define APU_FREQ_HIWORD_MASK 0x0fff 322 323 /* Frequency */ 324 #define APU_FREQ_LOBYTE_SHIFT 8 325 #define APU_FREQ_HIWORD_SHIFT 0 326 #define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000) 327 328 /* APU register 4 */ 329 #define APUREG_WAVESPACE 4 330 #define APU_STEREO 0x8000 331 #define APU_USE_SYSMEM 0x4000 332 #define APU_PCMBAR_MASK 0x6000 333 #define APU_64KPAGE_MASK 0xff00 334 335 /* PCM Base Address Register selection */ 336 #define APU_PCMBAR_SHIFT 13 337 338 /* 64KW (==128KB) Page */ 339 #define APU_64KPAGE_SHIFT 8 340 341 /* APU register 5 - 7 */ 342 #define APUREG_CURPTR 5 343 #define APUREG_ENDPTR 6 344 #define APUREG_LOOPLEN 7 345 346 /* APU register 9 */ 347 #define APUREG_AMPLITUDE 9 348 #define APU_AMPLITUDE_NOW_MASK 0xff00 349 #define APU_AMPLITUDE_DEST_MASK 0x00ff 350 351 /* Amplitude now? */ 352 #define APU_AMPLITUDE_NOW_SHIFT 8 353 354 /* APU register 10 */ 355 #define APUREG_POSITION 10 356 #define APU_RADIUS_MASK 0x00c0 357 #define APU_PAN_MASK 0x003f 358 359 /* Radius control. */ 360 #define APU_RADIUS_SHIFT 6 361 #define RADIUS_CENTERCIRCLE 0 362 #define RADIUS_MIDDLE 1 363 #define RADIUS_OUTSIDE 2 364 365 /* Polar pan. */ 366 #define APU_PAN_SHIFT 0 367 #define PAN_RIGHT 0x00 368 #define PAN_FRONT 0x08 369 #define PAN_LEFT 0x10 370 371 372 /* ----------------------------- 373 * Limits. 374 */ 375 #define WPWA_MAX ((1 << 22) - 1) 376 #define WPWA_MAXADDR ((1 << 23) - 1) 377 #define MAESTRO_MAXADDR ((1 << 28) - 1) 378 379 380 381 #ifdef AUDIO_DEBUG 382 #define DPRINTF(x) if (maestrodebug) printf x 383 #define DLPRINTF(i, x) if (maestrodebug & i) printf x 384 int maestrodebug = 0; 385 u_long maestrointr_called; 386 u_long maestrodma_effective; 387 388 #define MAESTRODEBUG_INTR 1 389 #define MAESTRODEBUG_TIMER 2 390 #else 391 #define DPRINTF(x) 392 #define DLPRINTF(i, x) 393 #endif 394 395 #define MAESTRO_BUFSIZ 0x4000 396 #define lengthof(array) (sizeof (array) / sizeof (array)[0]) 397 398 #define STEP_VOLUME 0x22 399 #define MIDDLE_VOLUME (STEP_VOLUME * 4) 400 401 typedef struct salloc_pool { 402 struct salloc_zone { 403 SLIST_ENTRY(salloc_zone) link; 404 caddr_t addr; 405 size_t size; 406 } *zones; 407 SLIST_HEAD(salloc_head, salloc_zone) free, used, spare; 408 } *salloc_t; 409 410 struct maestro_softc; 411 412 #define MAESTRO_PLAY 1 413 #define MAESTRO_STEREO 2 414 #define MAESTRO_8BIT 4 415 #define MAESTRO_UNSIGNED 8 416 #define MAESTRO_RUNNING 16 417 418 struct maestro_channel { 419 struct maestro_softc *sc; 420 int num; 421 u_int32_t blocksize; 422 u_int16_t mode; 423 u_int32_t speed; 424 u_int32_t dv; 425 u_int16_t start; 426 u_int16_t threshold; 427 u_int16_t end; 428 u_int16_t current; 429 u_int wpwa; 430 void (*intr)(void *); 431 void *intr_arg; 432 }; 433 434 struct maestro_softc { 435 struct device dev; 436 437 void *ih; 438 pci_chipset_tag_t pc; 439 pcitag_t pt; 440 441 #define MAESTRO_FLAG_SETUPGPIO 0x0001 442 int flags; 443 bus_space_tag_t iot; 444 bus_space_handle_t ioh; 445 bus_dma_tag_t dmat; 446 447 caddr_t dmabase; 448 bus_addr_t physaddr; 449 size_t dmasize; 450 bus_dmamap_t dmamap; 451 bus_dma_segment_t dmaseg; 452 salloc_t dmapool; 453 454 struct ac97_codec_if *codec_if; 455 struct ac97_host_if host_if; 456 struct audio_device *sc_audev; 457 458 int suspend; 459 460 struct maestro_channel play; 461 struct maestro_channel record; 462 }; 463 464 465 typedef u_int16_t wpreg_t; 466 typedef u_int16_t wcreg_t; 467 468 salloc_t salloc_new(caddr_t, size_t, int); 469 void salloc_destroy(salloc_t); 470 caddr_t salloc_alloc(salloc_t, size_t); 471 void salloc_free(salloc_t, caddr_t); 472 void salloc_insert(salloc_t, struct salloc_head *, 473 struct salloc_zone *, int); 474 475 int maestro_match(struct device *, void *, void *); 476 void maestro_attach(struct device *, struct device *, void *); 477 int maestro_activate(struct device *, int); 478 int maestro_intr(void *); 479 480 int maestro_open(void *, int); 481 void maestro_close(void *); 482 int maestro_query_encoding(void *, struct audio_encoding *); 483 int maestro_set_params(void *, int, int, struct audio_params *, 484 struct audio_params *); 485 void maestro_get_default_params(void *, int, struct audio_params *); 486 int maestro_round_blocksize(void *, int); 487 int maestro_halt_output(void *); 488 int maestro_halt_input(void *); 489 int maestro_getdev(void *, struct audio_device *); 490 int maestro_set_port(void *, mixer_ctrl_t *); 491 int maestro_get_port(void *, mixer_ctrl_t *); 492 int maestro_query_devinfo(void *, mixer_devinfo_t *); 493 void *maestro_malloc(void *, int, size_t, int, int); 494 void maestro_free(void *, void *, int); 495 paddr_t maestro_mappage(void *, void *, off_t, int); 496 int maestro_get_props(void *); 497 int maestro_trigger_output(void *, void *, void *, int, void (*)(void *), 498 void *, struct audio_params *); 499 int maestro_trigger_input(void *, void *, void *, int, void (*)(void *), 500 void *, struct audio_params *); 501 502 int maestro_attach_codec(void *, struct ac97_codec_if *); 503 enum ac97_host_flags maestro_codec_flags(void *); 504 int maestro_read_codec(void *, u_int8_t, u_int16_t *); 505 int maestro_write_codec(void *, u_int8_t, u_int16_t); 506 void maestro_reset_codec(void *); 507 508 void maestro_initcodec(void *); 509 510 void maestro_set_speed(struct maestro_channel *, u_long *); 511 void maestro_init(struct maestro_softc *); 512 void maestro_power(struct maestro_softc *, int); 513 514 void maestro_channel_start(struct maestro_channel *); 515 void maestro_channel_stop(struct maestro_channel *); 516 void maestro_channel_advance_dma(struct maestro_channel *); 517 void maestro_channel_suppress_jitter(struct maestro_channel *); 518 519 int maestro_get_flags(struct pci_attach_args *); 520 521 void ringbus_setdest(struct maestro_softc *, int, int); 522 523 wpreg_t wp_reg_read(struct maestro_softc *, int); 524 void wp_reg_write(struct maestro_softc *, int, wpreg_t); 525 wpreg_t wp_apu_read(struct maestro_softc *, int, int); 526 void wp_apu_write(struct maestro_softc *, int, int, wpreg_t); 527 void wp_settimer(struct maestro_softc *, u_int); 528 void wp_starttimer(struct maestro_softc *); 529 void wp_stoptimer(struct maestro_softc *); 530 531 wcreg_t wc_reg_read(struct maestro_softc *, int); 532 void wc_reg_write(struct maestro_softc *, int, wcreg_t); 533 wcreg_t wc_ctrl_read(struct maestro_softc *, int); 534 void wc_ctrl_write(struct maestro_softc *, int, wcreg_t); 535 536 u_int maestro_calc_timer_freq(struct maestro_channel *); 537 void maestro_update_timer(struct maestro_softc *); 538 539 struct cfdriver maestro_cd = { 540 NULL, "maestro", DV_DULL 541 }; 542 543 struct cfattach maestro_ca = { 544 sizeof (struct maestro_softc), maestro_match, maestro_attach, 545 NULL, maestro_activate 546 }; 547 548 struct audio_hw_if maestro_hw_if = { 549 maestro_open, 550 maestro_close, 551 NULL, 552 maestro_query_encoding, 553 maestro_set_params, 554 maestro_round_blocksize, 555 NULL, 556 NULL, 557 NULL, 558 NULL, 559 NULL, 560 maestro_halt_output, 561 maestro_halt_input, 562 NULL, 563 maestro_getdev, 564 NULL, 565 maestro_set_port, 566 maestro_get_port, 567 maestro_query_devinfo, 568 maestro_malloc, 569 maestro_free, 570 NULL, 571 maestro_mappage, 572 maestro_get_props, 573 maestro_trigger_output, 574 maestro_trigger_input, 575 maestro_get_default_params 576 }; 577 578 struct audio_device maestro_audev = { 579 "ESS Maestro", "", "maestro" 580 }; 581 582 struct { 583 u_short vendor, product; 584 int flags; 585 } maestro_pcitab[] = { 586 { PCI_VENDOR_ESSTECH, PCI_PRODUCT_ESSTECH_MAESTROII, 0 }, 587 { PCI_VENDOR_ESSTECH, PCI_PRODUCT_ESSTECH_MAESTRO2E, 0 }, 588 { PCI_VENDOR_PLATFORM, PCI_PRODUCT_PLATFORM_ES1849, 0 }, 589 { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSAMAESTRO, MAESTRO_FLAG_SETUPGPIO }, 590 { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSAPRONXVA26D, MAESTRO_FLAG_SETUPGPIO } 591 }; 592 #define NMAESTRO_PCITAB lengthof(maestro_pcitab) 593 594 int 595 maestro_get_flags(pa) 596 struct pci_attach_args *pa; 597 { 598 int i; 599 600 /* Distinguish audio devices from modems with the same manfid */ 601 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_MULTIMEDIA) 602 return (-1); 603 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MULTIMEDIA_AUDIO) 604 return (-1); 605 for (i = 0; i < NMAESTRO_PCITAB; i++) 606 if (PCI_VENDOR(pa->pa_id) == maestro_pcitab[i].vendor && 607 PCI_PRODUCT(pa->pa_id) == maestro_pcitab[i].product) 608 return (maestro_pcitab[i].flags); 609 return (-1); 610 } 611 612 /* ----------------------------- 613 * Driver interface. 614 */ 615 616 int 617 maestro_match(parent, match, aux) 618 struct device *parent; 619 void *match; 620 void *aux; 621 { 622 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 623 624 if (maestro_get_flags(pa) == -1) 625 return (0); 626 else 627 return (1); 628 } 629 630 void 631 maestro_attach(parent, self, aux) 632 struct device *parent; 633 struct device *self; 634 void *aux; 635 { 636 struct maestro_softc *sc = (struct maestro_softc *)self; 637 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 638 pci_chipset_tag_t pc = pa->pa_pc; 639 char const *intrstr; 640 pci_intr_handle_t ih; 641 int error; 642 u_int16_t cdata; 643 int dmastage = 0; 644 int rseg; 645 646 sc->sc_audev = &maestro_audev; 647 sc->flags = maestro_get_flags(pa); 648 649 sc->pc = pa->pa_pc; 650 sc->pt = pa->pa_tag; 651 sc->dmat = pa->pa_dmat; 652 653 /* Map interrupt */ 654 if (pci_intr_map(pa, &ih)) { 655 printf(": can't map interrupt\n"); 656 return; 657 } 658 intrstr = pci_intr_string(pc, ih); 659 sc->ih = pci_intr_establish(pc, ih, IPL_AUDIO, maestro_intr, sc, 660 sc->dev.dv_xname); 661 if (sc->ih == NULL) { 662 printf(": can't establish interrupt"); 663 if (intrstr != NULL) 664 printf(" at %s\n", intrstr); 665 return; 666 } 667 printf(": %s", intrstr); 668 669 /* Rangers, power up */ 670 maestro_power(sc, PPMI_D0); 671 DELAY(100000); 672 673 /* Map i/o */ 674 if ((error = pci_mapreg_map(pa, PCI_MAPS, PCI_MAPREG_TYPE_IO, 675 0, &sc->iot, &sc->ioh, NULL, NULL, 0)) != 0) { 676 printf(", can't map i/o space\n"); 677 goto bad; 678 }; 679 680 /* Allocate fixed DMA segment :-( */ 681 sc->dmasize = MAESTRO_BUFSIZ * 16; 682 if ((error = bus_dmamem_alloc(sc->dmat, sc->dmasize, NBPG, 0, 683 &sc->dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 684 printf(", unable to alloc dma, error %d\n", error); 685 goto bad; 686 } 687 dmastage = 1; 688 if ((error = bus_dmamem_map(sc->dmat, &sc->dmaseg, 1, 689 sc->dmasize, &sc->dmabase, BUS_DMA_NOWAIT | 690 BUS_DMA_COHERENT)) != 0) { 691 printf(", unable to map dma, error %d\n", error); 692 goto bad; 693 } 694 dmastage = 2; 695 if ((error = bus_dmamap_create(sc->dmat, sc->dmasize, 1, 696 sc->dmasize, 0, BUS_DMA_NOWAIT, &sc->dmamap)) != 0) { 697 printf(", unable to create dma map, error %d\n", error); 698 goto bad; 699 } 700 dmastage = 3; 701 if ((error = bus_dmamap_load(sc->dmat, sc->dmamap, 702 sc->dmabase, sc->dmasize, NULL, BUS_DMA_NOWAIT)) != 0) { 703 printf(", unable to load dma map, error %d\n", error); 704 goto bad; 705 } 706 707 /* XXX 708 * The first byte of the allocated memory is not usable, 709 * the WP sometimes uses it to store status. 710 */ 711 /* Make DMA memory pool */ 712 if ((sc->dmapool = salloc_new(sc->dmabase+16, sc->dmasize-16, 713 128/*overkill?*/)) == NULL) { 714 printf(", unable to make dma pool\n"); 715 goto bad; 716 } 717 718 sc->physaddr = sc->dmamap->dm_segs[0].ds_addr; 719 720 printf("\n"); 721 722 /* Kick device */ 723 maestro_init(sc); 724 maestro_read_codec(sc, 0, &cdata); 725 if (cdata == 0x80) { 726 printf("%s: PT101 codec unsupported, no mixer\n", 727 sc->dev.dv_xname); 728 /* Init values from Linux, no idea what this does. */ 729 maestro_write_codec(sc, 0x2a, 0x0001); 730 maestro_write_codec(sc, 0x2C, 0x0000); 731 maestro_write_codec(sc, 0x2C, 0xFFFF); 732 maestro_write_codec(sc, 0x10, 0x9F1F); 733 maestro_write_codec(sc, 0x12, 0x0808); 734 maestro_write_codec(sc, 0x14, 0x9F1F); 735 maestro_write_codec(sc, 0x16, 0x9F1F); 736 maestro_write_codec(sc, 0x18, 0x0404); 737 maestro_write_codec(sc, 0x1A, 0x0000); 738 maestro_write_codec(sc, 0x1C, 0x0000); 739 maestro_write_codec(sc, 0x02, 0x0404); 740 maestro_write_codec(sc, 0x04, 0x0808); 741 maestro_write_codec(sc, 0x0C, 0x801F); 742 maestro_write_codec(sc, 0x0E, 0x801F); 743 /* no control over the mixer, sorry */ 744 sc->codec_if = NULL; 745 } else { 746 /* Attach the AC'97 */ 747 sc->host_if.arg = sc; 748 sc->host_if.attach = maestro_attach_codec; 749 sc->host_if.flags = maestro_codec_flags; 750 sc->host_if.read = maestro_read_codec; 751 sc->host_if.write = maestro_write_codec; 752 sc->host_if.reset = maestro_reset_codec; 753 if (ac97_attach(&sc->host_if) != 0) { 754 printf("%s: can't attach codec\n", sc->dev.dv_xname); 755 goto bad; 756 } 757 } 758 759 sc->play.mode = MAESTRO_PLAY; 760 sc->play.sc = sc; 761 sc->play.num = 0; 762 sc->record.sc = sc; 763 sc->record.num = 2; 764 sc->record.mode = 0; 765 766 /* Attach audio */ 767 audio_attach_mi(&maestro_hw_if, sc, &sc->dev); 768 return; 769 770 bad: 771 /* Power down. */ 772 maestro_power(sc, PPMI_D3); 773 if (sc->ih) 774 pci_intr_disestablish(pc, sc->ih); 775 printf("%s: disabled\n", sc->dev.dv_xname); 776 if (sc->dmapool) 777 salloc_destroy(sc->dmapool); 778 if (dmastage >= 3) 779 bus_dmamap_destroy(sc->dmat, sc->dmamap); 780 if (dmastage >= 2) 781 bus_dmamem_unmap(sc->dmat, sc->dmabase, sc->dmasize); 782 if (dmastage >= 1) 783 bus_dmamem_free(sc->dmat, &sc->dmaseg, 1); 784 } 785 786 void 787 maestro_init(sc) 788 struct maestro_softc *sc; 789 { 790 int reg; 791 pcireg_t data; 792 793 /* Disable all legacy emulations. */ 794 data = pci_conf_read(sc->pc, sc->pt, CONF_LEGACY); 795 data |= LEGACY_DISABLED; 796 pci_conf_write(sc->pc, sc->pt, CONF_LEGACY, data); 797 798 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?) 799 * Enable posted write. 800 * Prefer PCI timing rather than that of ISA. 801 * Don't swap L/R. */ 802 data = pci_conf_read(sc->pc, sc->pt, CONF_MAESTRO); 803 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING; 804 data &= ~MAESTRO_SWAP_LR; 805 pci_conf_write(sc->pc, sc->pt, CONF_MAESTRO, data); 806 /* Reset direct sound. */ 807 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 808 HOSTINT_CTRL_DSOUND_RESET); 809 DELAY(10000); /* XXX - too long? */ 810 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 0); 811 DELAY(10000); 812 813 /* Enable direct sound and hardware volume control interruptions. */ 814 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 815 HOSTINT_CTRL_DSOUND_INT_ENABLED | HOSTINT_CTRL_HWVOL_ENABLED); 816 817 /* Setup Wave Processor. */ 818 819 /* Enable WaveCache, set DMA base address. */ 820 wp_reg_write(sc, WPREG_WAVE_ROMRAM, 821 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED); 822 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_CTRL, 823 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB); 824 825 for (reg = WAVCACHE_PCMBAR; reg < WAVCACHE_PCMBAR + 4; reg++) 826 wc_reg_write(sc, reg, 827 sc->physaddr >> WAVCACHE_BASEADDR_SHIFT); 828 829 /* Setup Codec/Ringbus. */ 830 maestro_initcodec(sc); 831 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, 832 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED); 833 834 wp_reg_write(sc, WPREG_BASE, 0x8500); /* Parallel I/O */ 835 ringbus_setdest(sc, RINGBUS_SRC_ADC, 836 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN); 837 ringbus_setdest(sc, RINGBUS_SRC_DSOUND, 838 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC); 839 840 /* Setup ASSP. Needed for Dell Inspiron 7500? */ 841 bus_space_write_1(sc->iot, sc->ioh, PORT_ASSP_CTRL_B, 0x00); 842 bus_space_write_1(sc->iot, sc->ioh, PORT_ASSP_CTRL_A, 0x03); 843 bus_space_write_1(sc->iot, sc->ioh, PORT_ASSP_CTRL_C, 0x00); 844 845 /* 846 * Reset hw volume to a known value so that we may handle diffs 847 * off to AC'97. 848 */ 849 850 bus_space_write_1(sc->iot, sc->ioh, PORT_HWVOL_MASTER, MIDDLE_VOLUME); 851 /* Setup GPIO if needed (NEC systems) */ 852 if (sc->flags & MAESTRO_FLAG_SETUPGPIO) { 853 /* Matthew Braithwaite <matt@braithwaite.net> reported that 854 * NEC Versa LX doesn't need GPIO operation. */ 855 bus_space_write_2(sc->iot, sc->ioh, 856 PORT_GPIO_MASK, 0x9ff); 857 bus_space_write_2(sc->iot, sc->ioh, PORT_GPIO_DIR, 858 bus_space_read_2(sc->iot, sc->ioh, PORT_GPIO_DIR) | 0x600); 859 bus_space_write_2(sc->iot, sc->ioh, 860 PORT_GPIO_DATA, 0x200); 861 } 862 } 863 864 /* ----------------------------- 865 * Audio interface 866 */ 867 868 int 869 maestro_round_blocksize(self, blk) 870 void *self; 871 int blk; 872 { 873 return ((blk + 0xf) & ~0xf); 874 } 875 876 void * 877 maestro_malloc(arg, dir, size, pool, flags) 878 void *arg; 879 int dir; 880 size_t size; 881 int pool, flags; 882 { 883 struct maestro_softc *sc = (struct maestro_softc *)arg; 884 885 return (salloc_alloc(sc->dmapool, size)); 886 } 887 888 void 889 maestro_free(self, ptr, pool) 890 void *self, *ptr; 891 int pool; 892 { 893 struct maestro_softc *sc = (struct maestro_softc *)self; 894 895 salloc_free(sc->dmapool, ptr); 896 } 897 898 paddr_t 899 maestro_mappage(self, mem, off, prot) 900 void *self, *mem; 901 off_t off; 902 int prot; 903 { 904 struct maestro_softc *sc = (struct maestro_softc *)self; 905 906 if (off < 0) 907 return -1; 908 return bus_dmamem_mmap(sc->dmat, &sc->dmaseg, 1, 909 off, prot, BUS_DMA_WAITOK); 910 } 911 912 int 913 maestro_get_props(self) 914 void *self; 915 { 916 /* struct maestro_softc *sc = (struct maestro_softc *)self; */ 917 918 return (AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT); /* XXX */ 919 } 920 921 int 922 maestro_getdev(self, retp) 923 void *self; 924 struct audio_device *retp; 925 { 926 struct maestro_softc *sc = (struct maestro_softc *)self; 927 928 *retp = *sc->sc_audev; 929 return 0; 930 } 931 932 int 933 maestro_set_port(self, cp) 934 void *self; 935 mixer_ctrl_t *cp; 936 { 937 struct ac97_codec_if *c = ((struct maestro_softc *)self)->codec_if; 938 939 if (c) 940 return (c->vtbl->mixer_set_port(c, cp)); 941 else 942 return (ENXIO); 943 } 944 945 int 946 maestro_get_port(self, cp) 947 void *self; 948 mixer_ctrl_t *cp; 949 { 950 struct ac97_codec_if *c = ((struct maestro_softc *)self)->codec_if; 951 952 if (c) 953 return (c->vtbl->mixer_get_port(c, cp)); 954 else 955 return (ENXIO); 956 } 957 958 int 959 maestro_query_devinfo(self, cp) 960 void *self; 961 mixer_devinfo_t *cp; 962 { 963 struct ac97_codec_if *c = ((struct maestro_softc *)self)->codec_if; 964 965 if (c) 966 return (c->vtbl->query_devinfo(c, cp)); 967 else 968 return (ENXIO); 969 } 970 971 struct audio_encoding maestro_tab[] = { 972 {0, AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 16, 2, 1, 0}, 973 {1, AudioEslinear, AUDIO_ENCODING_SLINEAR, 8, 1, 1, 0}, 974 {2, AudioEulinear, AUDIO_ENCODING_ULINEAR, 8, 1, 1, 0}, 975 {3, AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 16, 2, 1, 976 AUDIO_ENCODINGFLAG_EMULATED}, 977 {4, AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 16, 2, 1, 978 AUDIO_ENCODINGFLAG_EMULATED}, 979 {5, AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 16, 2, 1, 980 AUDIO_ENCODINGFLAG_EMULATED}, 981 {6, AudioEmulaw, AUDIO_ENCODING_ULAW, 8, 1, 1, 982 AUDIO_ENCODINGFLAG_EMULATED}, 983 {7, AudioEalaw, AUDIO_ENCODING_ALAW, 8, 1, 1, 984 AUDIO_ENCODINGFLAG_EMULATED} 985 }; 986 987 int 988 maestro_query_encoding(hdl, fp) 989 void *hdl; 990 struct audio_encoding *fp; 991 { 992 if (fp->index < 0 || fp->index >= lengthof(maestro_tab)) 993 return (EINVAL); 994 *fp = maestro_tab[fp->index]; 995 return (0); 996 } 997 998 void 999 maestro_get_default_params(void *addr, int mode, struct audio_params *params) 1000 { 1001 ac97_get_default_params(params); 1002 } 1003 1004 #define UNUSED __attribute__((unused)) 1005 1006 void 1007 maestro_set_speed(ch, prate) 1008 struct maestro_channel *ch; 1009 u_long *prate; 1010 { 1011 ch->speed = *prate; 1012 if ((ch->mode & (MAESTRO_8BIT | MAESTRO_STEREO)) == MAESTRO_8BIT) 1013 ch->speed /= 2; 1014 1015 /* special common case */ 1016 if (ch->speed == 48000) { 1017 ch->dv = 0x10000; 1018 } else { 1019 /* compute 16 bits fixed point value of speed/48000, 1020 * being careful not to overflow */ 1021 ch->dv = (((ch->speed % 48000) << 16U) + 24000) / 48000 1022 + ((ch->speed / 48000) << 16U); 1023 /* And this is the real rate obtained */ 1024 ch->speed = (ch->dv >> 16U) * 48000 + 1025 (((ch->dv & 0xffff)*48000)>>16U); 1026 } 1027 *prate = ch->speed; 1028 if ((ch->mode & (MAESTRO_8BIT | MAESTRO_STEREO)) == MAESTRO_8BIT) 1029 *prate *= 2; 1030 } 1031 1032 u_int 1033 maestro_calc_timer_freq(ch) 1034 struct maestro_channel *ch; 1035 { 1036 u_int ss = 2; 1037 1038 if (ch->mode & MAESTRO_8BIT) 1039 ss = 1; 1040 return (ch->speed * ss) / ch->blocksize; 1041 } 1042 1043 void 1044 maestro_update_timer(sc) 1045 struct maestro_softc *sc; 1046 { 1047 u_int freq = 0; 1048 u_int n; 1049 1050 if (sc->play.mode & MAESTRO_RUNNING) 1051 freq = maestro_calc_timer_freq(&sc->play); 1052 if (sc->record.mode & MAESTRO_RUNNING) { 1053 n = maestro_calc_timer_freq(&sc->record); 1054 if (freq < n) 1055 freq = n; 1056 } 1057 if (freq) { 1058 wp_settimer(sc, freq); 1059 wp_starttimer(sc); 1060 } else 1061 wp_stoptimer(sc); 1062 } 1063 1064 1065 int 1066 maestro_set_params(hdl, setmode, usemode, play, rec) 1067 void *hdl; 1068 int setmode, usemode; 1069 struct audio_params *play, *rec; 1070 { 1071 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1072 1073 if ((setmode & AUMODE_PLAY) == 0) 1074 return (0); 1075 1076 /* Disallow parameter change on a running audio for now */ 1077 if (sc->play.mode & MAESTRO_RUNNING) 1078 return (EINVAL); 1079 1080 if (play->sample_rate < 4000) 1081 play->sample_rate = 4000; 1082 else if (play->sample_rate > 48000) 1083 play->sample_rate = 48000; 1084 1085 play->factor = 1; 1086 play->sw_code = NULL; 1087 if (play->channels > 2) 1088 play->channels = 2; 1089 1090 sc->play.mode = MAESTRO_PLAY; 1091 if (play->channels == 2) 1092 sc->play.mode |= MAESTRO_STEREO; 1093 1094 if (play->encoding == AUDIO_ENCODING_ULAW) { 1095 play->factor = 2; 1096 play->sw_code = mulaw_to_slinear16_le; 1097 } else if (play->encoding == AUDIO_ENCODING_ALAW) { 1098 play->factor = 2; 1099 play->sw_code = alaw_to_slinear16_le; 1100 } else if (play->precision == 8) { 1101 sc->play.mode |= MAESTRO_8BIT; 1102 if (play->encoding == AUDIO_ENCODING_ULINEAR_LE || 1103 play->encoding == AUDIO_ENCODING_ULINEAR_BE) 1104 sc->play.mode |= MAESTRO_UNSIGNED; 1105 } 1106 else if (play->encoding == AUDIO_ENCODING_ULINEAR_LE) 1107 play->sw_code = change_sign16_le; 1108 else if (play->encoding == AUDIO_ENCODING_SLINEAR_BE) 1109 play->sw_code = swap_bytes; 1110 else if (play->encoding == AUDIO_ENCODING_ULINEAR_BE) 1111 play->sw_code = change_sign16_swap_bytes_le; 1112 else if (play->encoding != AUDIO_ENCODING_SLINEAR_LE) 1113 return (EINVAL); 1114 1115 play->bps = AUDIO_BPS(play->precision); 1116 play->msb = 1; 1117 1118 maestro_set_speed(&sc->play, &play->sample_rate); 1119 return (0); 1120 } 1121 1122 int 1123 maestro_open(hdl, flags) 1124 void *hdl; 1125 int flags; 1126 { 1127 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1128 DPRINTF(("%s: open(%d)\n", sc->dev.dv_xname, flags)); 1129 1130 /* XXX work around VM brokeness */ 1131 #if 0 1132 if ((OFLAGS(flags) & O_ACCMODE) != O_WRONLY) 1133 return (EINVAL); 1134 #endif 1135 sc->play.mode = MAESTRO_PLAY; 1136 sc->record.mode = 0; 1137 #ifdef AUDIO_DEBUG 1138 maestrointr_called = 0; 1139 maestrodma_effective = 0; 1140 #endif 1141 return (0); 1142 } 1143 1144 void 1145 maestro_close(hdl) 1146 void *hdl; 1147 { 1148 struct maestro_softc *sc UNUSED = (struct maestro_softc *)hdl; 1149 /* nothing to do */ 1150 } 1151 1152 1153 void 1154 maestro_channel_stop(ch) 1155 struct maestro_channel *ch; 1156 { 1157 wp_apu_write(ch->sc, ch->num, APUREG_APUTYPE, 1158 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1159 if (ch->mode & MAESTRO_STEREO) 1160 wp_apu_write(ch->sc, ch->num+1, APUREG_APUTYPE, 1161 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1162 /* four channels for record... */ 1163 if (ch->mode & MAESTRO_PLAY) 1164 return; 1165 wp_apu_write(ch->sc, ch->num+2, APUREG_APUTYPE, 1166 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1167 if (ch->mode & MAESTRO_STEREO) 1168 wp_apu_write(ch->sc, ch->num+3, APUREG_APUTYPE, 1169 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1170 1171 } 1172 1173 int 1174 maestro_halt_input(hdl) 1175 void *hdl; 1176 { 1177 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1178 maestro_channel_stop(&sc->record); 1179 sc->record.mode &= ~MAESTRO_RUNNING; 1180 maestro_update_timer(sc); 1181 return 0; 1182 } 1183 1184 int 1185 maestro_halt_output(hdl) 1186 void *hdl; 1187 { 1188 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1189 1190 maestro_channel_stop(&sc->play); 1191 sc->play.mode &= ~MAESTRO_RUNNING; 1192 maestro_update_timer(sc); 1193 return 0; 1194 } 1195 1196 int 1197 maestro_trigger_input(hdl, start, end, blksize, intr, arg, param) 1198 void *hdl; 1199 void *start, *end; 1200 int blksize; 1201 void (*intr)(void *); 1202 void *arg; 1203 struct audio_params *param; 1204 { 1205 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1206 1207 sc->record.mode |= MAESTRO_RUNNING; 1208 sc->record.blocksize = blksize; 1209 1210 maestro_channel_start(&sc->record); 1211 1212 sc->record.threshold = sc->record.start; 1213 maestro_update_timer(sc); 1214 return 0; 1215 } 1216 1217 void 1218 maestro_channel_start(ch) 1219 struct maestro_channel *ch; 1220 { 1221 struct maestro_softc *sc = ch->sc; 1222 int n = ch->num; 1223 int aputype; 1224 wcreg_t wcreg = (sc->physaddr - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK; 1225 1226 switch(ch->mode & (MAESTRO_STEREO | MAESTRO_8BIT)) { 1227 case 0: 1228 aputype = APUTYPE_16BITLINEAR; 1229 break; 1230 case MAESTRO_STEREO: 1231 aputype = APUTYPE_16BITSTEREO; 1232 break; 1233 case MAESTRO_8BIT: 1234 aputype = APUTYPE_8BITLINEAR; 1235 break; 1236 case MAESTRO_8BIT|MAESTRO_STEREO: 1237 aputype = APUTYPE_8BITSTEREO; 1238 break; 1239 } 1240 if (ch->mode & MAESTRO_UNSIGNED) 1241 wcreg |= WAVCACHE_CHCTL_U8; 1242 if ((ch->mode & MAESTRO_STEREO) == 0) { 1243 DPRINTF(("Setting mono parameters\n")); 1244 wp_apu_write(sc, n, APUREG_WAVESPACE, ch->wpwa & 0xff00); 1245 wp_apu_write(sc, n, APUREG_CURPTR, ch->current); 1246 wp_apu_write(sc, n, APUREG_ENDPTR, ch->end); 1247 wp_apu_write(sc, n, APUREG_LOOPLEN, ch->end - ch->start); 1248 wp_apu_write(sc, n, APUREG_AMPLITUDE, 0xe800); 1249 wp_apu_write(sc, n, APUREG_POSITION, 0x8f00 1250 | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 1251 | (PAN_FRONT << APU_PAN_SHIFT)); 1252 wp_apu_write(sc, n, APUREG_FREQ_LOBYTE, APU_plus6dB 1253 | ((ch->dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); 1254 wp_apu_write(sc, n, APUREG_FREQ_HIWORD, ch->dv >> 8); 1255 wc_ctrl_write(sc, n, wcreg); 1256 wp_apu_write(sc, n, APUREG_APUTYPE, 1257 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); 1258 } else { 1259 wcreg |= WAVCACHE_CHCTL_STEREO; 1260 DPRINTF(("Setting stereo parameters\n")); 1261 wp_apu_write(sc, n+1, APUREG_WAVESPACE, ch->wpwa & 0xff00); 1262 wp_apu_write(sc, n+1, APUREG_CURPTR, ch->current); 1263 wp_apu_write(sc, n+1, APUREG_ENDPTR, ch->end); 1264 wp_apu_write(sc, n+1, APUREG_LOOPLEN, ch->end - ch->start); 1265 wp_apu_write(sc, n+1, APUREG_AMPLITUDE, 0xe800); 1266 wp_apu_write(sc, n+1, APUREG_POSITION, 0x8f00 1267 | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 1268 | (PAN_LEFT << APU_PAN_SHIFT)); 1269 wp_apu_write(sc, n+1, APUREG_FREQ_LOBYTE, APU_plus6dB 1270 | ((ch->dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); 1271 wp_apu_write(sc, n+1, APUREG_FREQ_HIWORD, ch->dv >> 8); 1272 if (ch->mode & MAESTRO_8BIT) 1273 wp_apu_write(sc, n, APUREG_WAVESPACE, 1274 ch->wpwa & 0xff00); 1275 else 1276 wp_apu_write(sc, n, APUREG_WAVESPACE, 1277 (ch->wpwa|(APU_STEREO >> 1)) & 0xff00); 1278 wp_apu_write(sc, n, APUREG_CURPTR, ch->current); 1279 wp_apu_write(sc, n, APUREG_ENDPTR, ch->end); 1280 wp_apu_write(sc, n, APUREG_LOOPLEN, ch->end - ch->start); 1281 wp_apu_write(sc, n, APUREG_AMPLITUDE, 0xe800); 1282 wp_apu_write(sc, n, APUREG_POSITION, 0x8f00 1283 | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 1284 | (PAN_RIGHT << APU_PAN_SHIFT)); 1285 wp_apu_write(sc, n, APUREG_FREQ_LOBYTE, APU_plus6dB 1286 | ((ch->dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); 1287 wp_apu_write(sc, n, APUREG_FREQ_HIWORD, ch->dv >> 8); 1288 wc_ctrl_write(sc, n, wcreg); 1289 wc_ctrl_write(sc, n+1, wcreg); 1290 wp_apu_write(sc, n, APUREG_APUTYPE, 1291 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); 1292 wp_apu_write(sc, n+1, APUREG_APUTYPE, 1293 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); 1294 } 1295 } 1296 1297 int 1298 maestro_trigger_output(hdl, start, end, blksize, intr, arg, param) 1299 void *hdl; 1300 void *start, *end; 1301 int blksize; 1302 void (*intr)(void *); 1303 void *arg; 1304 struct audio_params *param; 1305 { 1306 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1307 1308 u_int offset = ((caddr_t)start - sc->dmabase) >> 1; 1309 u_int size = ((char *)end - (char *)start) >> 1; 1310 sc->play.mode |= MAESTRO_RUNNING; 1311 sc->play.wpwa = APU_USE_SYSMEM | (offset >> 8); 1312 DPRINTF(("maestro_trigger_output: start=%x, end=%x, blksize=%x ", 1313 start, end, blksize)); 1314 DPRINTF(("offset = %x, size=%x\n", offset, size)); 1315 1316 sc->play.intr = intr; 1317 sc->play.intr_arg = arg; 1318 sc->play.blocksize = blksize; 1319 sc->play.end = offset+size; 1320 sc->play.start = offset; 1321 sc->play.current = sc->play.start; 1322 if ((sc->play.mode & (MAESTRO_STEREO | MAESTRO_8BIT)) == MAESTRO_STEREO) { 1323 sc->play.wpwa >>= 1; 1324 sc->play.start >>= 1; 1325 sc->play.end >>= 1; 1326 sc->play.blocksize >>= 1; 1327 } 1328 maestro_channel_start(&sc->play); 1329 1330 sc->play.threshold = sc->play.start; 1331 maestro_update_timer(sc); 1332 1333 return 0; 1334 } 1335 1336 /* ----------------------------- 1337 * Codec interface 1338 */ 1339 1340 enum ac97_host_flags 1341 maestro_codec_flags(self) 1342 void *self; 1343 { 1344 return AC97_HOST_DONT_READ; 1345 } 1346 1347 int 1348 maestro_read_codec(self, regno, datap) 1349 void *self; 1350 u_int8_t regno; 1351 u_int16_t *datap; 1352 { 1353 struct maestro_softc *sc = (struct maestro_softc *)self; 1354 int t; 1355 1356 /* We have to wait for a SAFE time to write addr/data */ 1357 for (t = 0; t < 20; t++) { 1358 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1359 & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS) 1360 break; 1361 DELAY(2); /* 20.8us / 13 */ 1362 } 1363 if (t == 20) 1364 printf("%s: maestro_read_codec() PROGLESS timed out.\n", 1365 sc->dev.dv_xname); 1366 /* XXX return 1 */ 1367 1368 bus_space_write_1(sc->iot, sc->ioh, PORT_CODEC_CMD, 1369 CODEC_CMD_READ | regno); 1370 DELAY(21); /* AC97 cycle = 20.8usec */ 1371 1372 /* Wait for data retrieve */ 1373 for (t = 0; t < 20; t++) { 1374 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1375 & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE) 1376 break; 1377 DELAY(2); /* 20.8us / 13 */ 1378 } 1379 if (t == 20) 1380 /* Timed out, but perform dummy read. */ 1381 printf("%s: maestro_read_codec() RW_DONE timed out.\n", 1382 sc->dev.dv_xname); 1383 1384 *datap = bus_space_read_2(sc->iot, sc->ioh, PORT_CODEC_REG); 1385 return 0; 1386 } 1387 1388 int 1389 maestro_write_codec(self, regno, data) 1390 void *self; 1391 u_int8_t regno; 1392 u_int16_t data; 1393 { 1394 struct maestro_softc *sc = (struct maestro_softc *)self; 1395 int t; 1396 1397 /* We have to wait for a SAFE time to write addr/data */ 1398 for (t = 0; t < 20; t++) { 1399 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1400 & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS) 1401 break; 1402 DELAY(2); /* 20.8us / 13 */ 1403 } 1404 if (t == 20) { 1405 /* Timed out. Abort writing. */ 1406 printf("%s: maestro_write_codec() PROGLESS timed out.\n", 1407 sc->dev.dv_xname); 1408 return 1; 1409 } 1410 1411 bus_space_write_2(sc->iot, sc->ioh, PORT_CODEC_REG, data); 1412 bus_space_write_1(sc->iot, sc->ioh, PORT_CODEC_CMD, 1413 CODEC_CMD_WRITE | regno); 1414 1415 return 0; 1416 } 1417 1418 int 1419 maestro_attach_codec(self, cif) 1420 void *self; 1421 struct ac97_codec_if *cif; 1422 { 1423 struct maestro_softc *sc = (struct maestro_softc *)self; 1424 1425 sc->codec_if = cif; 1426 return 0; 1427 } 1428 1429 void 1430 maestro_reset_codec(self) 1431 void *self UNUSED; 1432 { 1433 } 1434 1435 void 1436 maestro_initcodec(self) 1437 void *self; 1438 { 1439 struct maestro_softc *sc = (struct maestro_softc *)self; 1440 u_int16_t data; 1441 1442 if (bus_space_read_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL) 1443 & RINGBUS_CTRL_ACLINK_ENABLED) { 1444 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, 0); 1445 DELAY(104); /* 20.8us * (4 + 1) */ 1446 } 1447 /* XXX - 2nd codec should be looked at. */ 1448 bus_space_write_4(sc->iot, sc->ioh, 1449 PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET); 1450 DELAY(2); 1451 bus_space_write_4(sc->iot, sc->ioh, 1452 PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED); 1453 DELAY(21); 1454 1455 maestro_read_codec(sc, 0, &data); 1456 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1457 & CODEC_STAT_MASK) != 0) { 1458 bus_space_write_4(sc->iot, sc->ioh, 1459 PORT_RINGBUS_CTRL, 0); 1460 DELAY(21); 1461 1462 /* Try cold reset. */ 1463 printf("%s: resetting codec\n", sc->dev.dv_xname); 1464 1465 data = bus_space_read_2(sc->iot, sc->ioh, PORT_GPIO_DIR); 1466 if (pci_conf_read(sc->pc, sc->pt, 0x58) & 1) 1467 data |= 0x10; 1468 data |= 0x009 & 1469 ~bus_space_read_2(sc->iot, sc->ioh, PORT_GPIO_DATA); 1470 bus_space_write_2(sc->iot, sc->ioh, 1471 PORT_GPIO_MASK, 0xff6); 1472 bus_space_write_2(sc->iot, sc->ioh, 1473 PORT_GPIO_DIR, data | 0x009); 1474 bus_space_write_2(sc->iot, sc->ioh, 1475 PORT_GPIO_DATA, 0x000); 1476 DELAY(2); 1477 bus_space_write_2(sc->iot, sc->ioh, 1478 PORT_GPIO_DATA, 0x001); 1479 DELAY(1); 1480 bus_space_write_2(sc->iot, sc->ioh, 1481 PORT_GPIO_DATA, 0x009); 1482 DELAY(500000); 1483 bus_space_write_2(sc->iot, sc->ioh, 1484 PORT_GPIO_DIR, data); 1485 DELAY(84); /* 20.8us * 4 */ 1486 bus_space_write_4(sc->iot, sc->ioh, 1487 PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED); 1488 DELAY(21); 1489 } 1490 1491 /* Check the codec to see is still busy */ 1492 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) & 1493 CODEC_STAT_MASK) != 0) { 1494 printf("%s: codec failure\n", sc->dev.dv_xname); 1495 } 1496 } 1497 1498 /* ----------------------------- 1499 * Power management interface 1500 */ 1501 1502 int 1503 maestro_activate(struct device *self, int act) 1504 { 1505 struct maestro_softc *sc = (struct maestro_softc *)self; 1506 1507 switch (act) { 1508 case DVACT_SUSPEND: 1509 /* Power down device on shutdown. */ 1510 DPRINTF(("maestro: power down\n")); 1511 if (sc->record.mode & MAESTRO_RUNNING) { 1512 sc->record.current = wp_apu_read(sc, sc->record.num, APUREG_CURPTR); 1513 maestro_channel_stop(&sc->record); 1514 } 1515 if (sc->play.mode & MAESTRO_RUNNING) { 1516 sc->play.current = wp_apu_read(sc, sc->play.num, APUREG_CURPTR); 1517 maestro_channel_stop(&sc->play); 1518 } 1519 1520 wp_stoptimer(sc); 1521 1522 /* Power down everything except clock. */ 1523 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 0); 1524 maestro_write_codec(sc, AC97_REG_POWER, 0xdf00); 1525 DELAY(20); 1526 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, 0); 1527 DELAY(1); 1528 maestro_power(sc, PPMI_D3); 1529 break; 1530 case DVACT_RESUME: 1531 /* Power up device on resume. */ 1532 DPRINTF(("maestro: power resume\n")); 1533 maestro_power(sc, PPMI_D0); 1534 DELAY(100000); 1535 maestro_init(sc); 1536 /* Restore codec settings */ 1537 if (sc->codec_if) 1538 sc->codec_if->vtbl->restore_ports(sc->codec_if); 1539 if (sc->play.mode & MAESTRO_RUNNING) 1540 maestro_channel_start(&sc->play); 1541 if (sc->record.mode & MAESTRO_RUNNING) 1542 maestro_channel_start(&sc->record); 1543 maestro_update_timer(sc); 1544 break; 1545 } 1546 return 0; 1547 } 1548 1549 void 1550 maestro_power(sc, status) 1551 struct maestro_softc *sc; 1552 int status; 1553 { 1554 int data; 1555 1556 /* Set the power state of the device. */ 1557 data = pci_conf_read(sc->pc, sc->pt, CONF_PM_PTR); 1558 data = pci_conf_read(sc->pc, sc->pt, data); 1559 if (data == PPMI_CID) 1560 pci_conf_write(sc->pc, sc->pt, data + PM_CTRL, status); 1561 } 1562 1563 void 1564 maestro_channel_advance_dma(ch) 1565 struct maestro_channel *ch; 1566 { 1567 wpreg_t pos; 1568 #ifdef AUDIO_DEBUG 1569 maestrointr_called++; 1570 #endif 1571 for (;;) { 1572 pos = wp_apu_read(ch->sc, ch->num, APUREG_CURPTR); 1573 /* Are we still processing the current dma block ? */ 1574 if (pos >= ch->threshold && 1575 pos < ch->threshold + ch->blocksize/2) 1576 break; 1577 ch->threshold += ch->blocksize/2; 1578 if (ch->threshold >= ch->end) 1579 ch->threshold = ch->start; 1580 (*ch->intr)(ch->intr_arg); 1581 #ifdef AUDIO_DEBUG 1582 maestrodma_effective++; 1583 #endif 1584 } 1585 1586 #ifdef AUDIO_DEBUG 1587 if (maestrodebug && maestrointr_called % 64 == 0) 1588 printf("maestro: dma advanced %lu for %lu calls\n", 1589 maestrodma_effective, maestrointr_called); 1590 #endif 1591 } 1592 1593 /* Some maestro makes sometimes get desynchronized in stereo mode. */ 1594 void 1595 maestro_channel_suppress_jitter(ch) 1596 struct maestro_channel *ch; 1597 { 1598 int cp, diff; 1599 1600 /* Verify that both channels are not too far off. */ 1601 cp = wp_apu_read(ch->sc, ch->num, APUREG_CURPTR); 1602 diff = wp_apu_read(ch->sc, ch->num+1, APUREG_CURPTR) - cp; 1603 if (diff > 4 || diff < -4) 1604 /* Otherwise, directly resynch the 2nd channel. */ 1605 bus_space_write_2(ch->sc->iot, ch->sc->ioh, 1606 PORT_DSP_DATA, cp); 1607 } 1608 1609 /* ----------------------------- 1610 * Interrupt handler interface 1611 */ 1612 int 1613 maestro_intr(arg) 1614 void *arg; 1615 { 1616 struct maestro_softc *sc = (struct maestro_softc *)arg; 1617 u_int16_t status; 1618 1619 status = bus_space_read_1(sc->iot, sc->ioh, PORT_HOSTINT_STAT); 1620 if (status == 0) 1621 return 0; /* Not for us? */ 1622 1623 /* Acknowledge all. */ 1624 bus_space_write_2(sc->iot, sc->ioh, PORT_INT_STAT, 1); 1625 bus_space_write_1(sc->iot, sc->ioh, PORT_HOSTINT_STAT, status); 1626 1627 /* Hardware volume support */ 1628 if (status & HOSTINT_STAT_HWVOL && sc->codec_if != NULL) { 1629 int n, i, delta, v; 1630 mixer_ctrl_t hwvol; 1631 1632 n = bus_space_read_1(sc->iot, sc->ioh, PORT_HWVOL_MASTER); 1633 /* Special case: Mute key */ 1634 if (n & 0x11) { 1635 hwvol.type = AUDIO_MIXER_ENUM; 1636 hwvol.dev = 1637 sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, 1638 AudioCoutputs, AudioNmaster, AudioNmute); 1639 sc->codec_if->vtbl->mixer_get_port(sc->codec_if, &hwvol); 1640 hwvol.un.ord = !hwvol.un.ord; 1641 } else { 1642 hwvol.type = AUDIO_MIXER_VALUE; 1643 hwvol.un.value.num_channels = 2; 1644 hwvol.dev = 1645 sc->codec_if->vtbl->get_portnum_by_name( 1646 sc->codec_if, AudioCoutputs, AudioNmaster, 1647 NULL); 1648 sc->codec_if->vtbl->mixer_get_port(sc->codec_if, &hwvol); 1649 /* XXX AC'97 yields five bits for master volume. */ 1650 delta = (n - MIDDLE_VOLUME)/STEP_VOLUME * 8; 1651 for (i = 0; i < hwvol.un.value.num_channels; i++) { 1652 v = ((int)hwvol.un.value.level[i]) + delta; 1653 if (v < 0) 1654 v = 0; 1655 else if (v > 255) 1656 v = 255; 1657 hwvol.un.value.level[i] = v; 1658 } 1659 } 1660 sc->codec_if->vtbl->mixer_set_port(sc->codec_if, &hwvol); 1661 /* Reset to compute next diffs */ 1662 bus_space_write_1(sc->iot, sc->ioh, PORT_HWVOL_MASTER, 1663 MIDDLE_VOLUME); 1664 } 1665 1666 if (sc->play.mode & MAESTRO_RUNNING) { 1667 maestro_channel_advance_dma(&sc->play); 1668 if (sc->play.mode & MAESTRO_STEREO) 1669 maestro_channel_suppress_jitter(&sc->play); 1670 } 1671 1672 if (sc->record.mode & MAESTRO_RUNNING) 1673 maestro_channel_advance_dma(&sc->record); 1674 1675 return 1; 1676 } 1677 1678 /* ----------------------------- 1679 * Hardware interface 1680 */ 1681 1682 /* Codec/Ringbus */ 1683 1684 void 1685 ringbus_setdest(struct maestro_softc *sc, int src, int dest) 1686 { 1687 u_int32_t data; 1688 1689 data = bus_space_read_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL); 1690 data &= ~(0xfU << src); 1691 data |= (0xfU & dest) << src; 1692 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, data); 1693 } 1694 1695 /* Wave Processor */ 1696 1697 wpreg_t 1698 wp_reg_read(struct maestro_softc *sc, int reg) 1699 { 1700 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_INDEX, reg); 1701 return bus_space_read_2(sc->iot, sc->ioh, PORT_DSP_DATA); 1702 } 1703 1704 void 1705 wp_reg_write(struct maestro_softc *sc, int reg, wpreg_t data) 1706 { 1707 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_INDEX, reg); 1708 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_DATA, data); 1709 } 1710 1711 static void 1712 apu_setindex(struct maestro_softc *sc, int reg) 1713 { 1714 int t; 1715 1716 wp_reg_write(sc, WPREG_CRAM_PTR, reg); 1717 /* Sometimes WP fails to set apu register index. */ 1718 for (t = 0; t < 1000; t++) { 1719 if (bus_space_read_2(sc->iot, sc->ioh, 1720 PORT_DSP_DATA) == reg) 1721 break; 1722 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_DATA, reg); 1723 } 1724 if (t == 1000) 1725 printf("%s: apu_setindex() timeout\n", sc->dev.dv_xname); 1726 } 1727 1728 wpreg_t 1729 wp_apu_read(struct maestro_softc *sc, int ch, int reg) 1730 { 1731 wpreg_t ret; 1732 1733 apu_setindex(sc, ((unsigned)ch << 4) + reg); 1734 ret = wp_reg_read(sc, WPREG_DATA_PORT); 1735 return ret; 1736 } 1737 1738 void 1739 wp_apu_write(struct maestro_softc *sc, int ch, int reg, wpreg_t data) 1740 { 1741 int t; 1742 1743 apu_setindex(sc, ((unsigned)ch << 4) + reg); 1744 wp_reg_write(sc, WPREG_DATA_PORT, data); 1745 for (t = 0; t < 1000; t++) { 1746 if (bus_space_read_2(sc->iot, sc->ioh, PORT_DSP_DATA) == data) 1747 break; 1748 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_DATA, data); 1749 } 1750 if (t == 1000) 1751 printf("%s: wp_apu_write() timeout\n", sc->dev.dv_xname); 1752 } 1753 1754 void 1755 wp_settimer(struct maestro_softc *sc, u_int freq) 1756 { 1757 u_int clock = 48000 << 2; 1758 u_int prescale = 0, divide = (freq != 0) ? (clock / freq) : ~0; 1759 1760 if (divide < 4) 1761 divide = 4; 1762 else if (divide > 32 << 8) 1763 divide = 32 << 8; 1764 1765 for (; divide > 32 << 1; divide >>= 1) 1766 prescale++; 1767 divide = (divide + 1) >> 1; 1768 1769 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1) 1770 prescale++; 1771 1772 wp_reg_write(sc, WPREG_TIMER_ENABLE, 0); 1773 wp_reg_write(sc, WPREG_TIMER_FREQ, 1774 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1)); 1775 wp_reg_write(sc, WPREG_TIMER_ENABLE, 1); 1776 } 1777 1778 void 1779 wp_starttimer(struct maestro_softc *sc) 1780 { 1781 wp_reg_write(sc, WPREG_TIMER_START, 1); 1782 } 1783 1784 void 1785 wp_stoptimer(struct maestro_softc *sc) 1786 { 1787 wp_reg_write(sc, WPREG_TIMER_START, 0); 1788 bus_space_write_2(sc->iot, sc->ioh, PORT_INT_STAT, 1); 1789 } 1790 1791 /* WaveCache */ 1792 1793 wcreg_t 1794 wc_reg_read(struct maestro_softc *sc, int reg) 1795 { 1796 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_INDEX, reg); 1797 return bus_space_read_2(sc->iot, sc->ioh, PORT_WAVCACHE_DATA); 1798 } 1799 1800 void 1801 wc_reg_write(struct maestro_softc *sc, int reg, wcreg_t data) 1802 { 1803 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_INDEX, reg); 1804 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_DATA, data); 1805 } 1806 1807 u_int16_t 1808 wc_ctrl_read(struct maestro_softc *sc, int ch) 1809 { 1810 return wc_reg_read(sc, ch << 3); 1811 } 1812 1813 void 1814 wc_ctrl_write(struct maestro_softc *sc, int ch, wcreg_t data) 1815 { 1816 wc_reg_write(sc, ch << 3, data); 1817 } 1818 1819 /* ----------------------------- 1820 * Simple zone allocator. 1821 * (All memory allocated in advance) 1822 */ 1823 1824 salloc_t 1825 salloc_new(addr, size, nzones) 1826 caddr_t addr; 1827 size_t size; 1828 int nzones; 1829 { 1830 struct salloc_pool *pool; 1831 struct salloc_zone *space; 1832 int i; 1833 1834 pool = malloc(sizeof *pool + nzones * sizeof pool->zones[0], 1835 M_TEMP, M_NOWAIT); 1836 if (pool == NULL) 1837 return NULL; 1838 SLIST_INIT(&pool->free); 1839 SLIST_INIT(&pool->used); 1840 SLIST_INIT(&pool->spare); 1841 /* Espie says the following line is obvious */ 1842 pool->zones = (struct salloc_zone *)(pool + 1); 1843 for (i = 1; i < nzones; i++) 1844 SLIST_INSERT_HEAD(&pool->spare, &pool->zones[i], link); 1845 space = &pool->zones[0]; 1846 space->addr = addr; 1847 space->size = size; 1848 SLIST_INSERT_HEAD(&pool->free, space, link); 1849 return pool; 1850 } 1851 1852 void 1853 salloc_destroy(pool) 1854 salloc_t pool; 1855 { 1856 free(pool, M_TEMP); 1857 } 1858 1859 void 1860 salloc_insert(pool, head, zone, merge) 1861 salloc_t pool; 1862 struct salloc_head *head; 1863 struct salloc_zone *zone; 1864 int merge; 1865 { 1866 struct salloc_zone *prev, *next; 1867 1868 /* 1869 * Insert a zone into an ordered list of zones, possibly 1870 * merging adjacent zones. 1871 */ 1872 prev = NULL; 1873 SLIST_FOREACH(next, head, link) { 1874 if (next->addr > zone->addr) 1875 break; 1876 prev = next; 1877 } 1878 1879 if (merge && prev && prev->addr + prev->size == zone->addr) { 1880 prev->size += zone->size; 1881 SLIST_INSERT_HEAD(&pool->spare, zone, link); 1882 zone = prev; 1883 } else if (prev) 1884 SLIST_INSERT_AFTER(prev, zone, link); 1885 else 1886 SLIST_INSERT_HEAD(head, zone, link); 1887 if (merge && next && zone->addr + zone->size == next->addr) { 1888 zone->size += next->size; 1889 SLIST_REMOVE(head, next, salloc_zone, link); 1890 SLIST_INSERT_HEAD(&pool->spare, next, link); 1891 } 1892 } 1893 1894 caddr_t 1895 salloc_alloc(pool, size) 1896 salloc_t pool; 1897 size_t size; 1898 { 1899 struct salloc_zone *zone, *uzone; 1900 1901 SLIST_FOREACH(zone, &pool->free, link) 1902 if (zone->size >= size) 1903 break; 1904 if (zone == SLIST_END(&pool->free)) 1905 return NULL; 1906 if (zone->size == size) { 1907 SLIST_REMOVE(&pool->free, zone, salloc_zone, link); 1908 uzone = zone; 1909 } else { 1910 uzone = SLIST_FIRST(&pool->spare); 1911 if (uzone == NULL) 1912 return NULL; /* XXX */ 1913 SLIST_REMOVE_HEAD(&pool->spare, link); 1914 uzone->size = size; 1915 uzone->addr = zone->addr; 1916 zone->size -= size; 1917 zone->addr += size; 1918 } 1919 salloc_insert(pool, &pool->used, uzone, 0); 1920 return uzone->addr; 1921 } 1922 1923 void 1924 salloc_free(pool, addr) 1925 salloc_t pool; 1926 caddr_t addr; 1927 { 1928 struct salloc_zone *zone; 1929 1930 SLIST_FOREACH(zone, &pool->used, link) 1931 if (zone->addr == addr) 1932 break; 1933 #ifdef DIAGNOSTIC 1934 if (zone == SLIST_END(&pool->used)) 1935 panic("salloc_free: freeing unallocated memory"); 1936 #endif 1937 SLIST_REMOVE(&pool->used, zone, salloc_zone, link); 1938 salloc_insert(pool, &pool->free, zone, 1); 1939 } 1940