1 /* $OpenBSD: mpiireg.h,v 1.9 2014/03/27 12:19:55 dlg Exp $ */ 2 /* 3 * Copyright (c) 2010 Mike Belopuhov 4 * Copyright (c) 2009 James Giannoules 5 * Copyright (c) 2005 - 2010 David Gwynne <dlg@openbsd.org> 6 * Copyright (c) 2005 - 2010 Marco Peereboom <marco@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #define MPII_DOORBELL (0x00) 22 /* doorbell read bits */ 23 #define MPII_DOORBELL_STATE (0xf<<28) /* ioc state */ 24 #define MPII_DOORBELL_STATE_RESET (0x0<<28) 25 #define MPII_DOORBELL_STATE_READY (0x1<<28) 26 #define MPII_DOORBELL_STATE_OPER (0x2<<28) 27 #define MPII_DOORBELL_STATE_FAULT (0x4<<28) 28 #define MPII_DOORBELL_INUSE (0x1<<27) /* doorbell used */ 29 #define MPII_DOORBELL_WHOINIT (0x7<<24) /* last to reset ioc */ 30 #define MPII_DOORBELL_WHOINIT_NOONE (0x0<<24) /* not initialized */ 31 #define MPII_DOORBELL_WHOINIT_SYSBIOS (0x1<<24) /* system bios */ 32 #define MPII_DOORBELL_WHOINIT_ROMBIOS (0x2<<24) /* rom bios */ 33 #define MPII_DOORBELL_WHOINIT_PCIPEER (0x3<<24) /* pci peer */ 34 #define MPII_DOORBELL_WHOINIT_DRIVER (0x4<<24) /* host driver */ 35 #define MPII_DOORBELL_WHOINIT_MANUFACT (0x5<<24) /* manufacturing */ 36 #define MPII_DOORBELL_FAULT (0xffff<<0) /* fault code */ 37 /* doorbell write bits */ 38 #define MPII_DOORBELL_FUNCTION_SHIFT (24) 39 #define MPII_DOORBELL_FUNCTION_MASK (0xff << MPII_DOORBELL_FUNCTION_SHIFT) 40 #define MPII_DOORBELL_FUNCTION(x) \ 41 (((x) << MPII_DOORBELL_FUNCTION_SHIFT) & MPII_DOORBELL_FUNCTION_MASK) 42 #define MPII_DOORBELL_DWORDS_SHIFT 16 43 #define MPII_DOORBELL_DWORDS_MASK (0xff << MPII_DOORBELL_DWORDS_SHIFT) 44 #define MPII_DOORBELL_DWORDS(x) \ 45 (((x) << MPII_DOORBELL_DWORDS_SHIFT) & MPII_DOORBELL_DWORDS_MASK) 46 #define MPII_DOORBELL_DATA_MASK (0xffff) 47 48 #define MPII_WRITESEQ (0x04) 49 #define MPII_WRITESEQ_KEY_VALUE_MASK (0x0000000f) /* key value */ 50 #define MPII_WRITESEQ_FLUSH (0x00) 51 #define MPII_WRITESEQ_1 (0x0f) 52 #define MPII_WRITESEQ_2 (0x04) 53 #define MPII_WRITESEQ_3 (0x0b) 54 #define MPII_WRITESEQ_4 (0x02) 55 #define MPII_WRITESEQ_5 (0x07) 56 #define MPII_WRITESEQ_6 (0x0d) 57 58 #define MPII_HOSTDIAG (0x08) 59 #define MPII_HOSTDIAG_BDS_MASK (0x00001800) /* boot device select */ 60 #define MPII_HOSTDIAG_BDS_DEFAULT (0<<11) /* default address map, flash */ 61 #define MPII_HOSTDIAG_BDS_HCDW (1<<11) /* host code and data window */ 62 #define MPII_HOSTDIAG_CLEARFBS (1<<10) /* clear flash bad sig */ 63 #define MPII_HOSTDIAG_FORCE_HCB_ONBOOT (1<<9) /* force host controlled boot */ 64 #define MPII_HOSTDIAG_HCB_MODE (1<<8) /* host controlled boot mode */ 65 #define MPII_HOSTDIAG_DWRE (1<<7) /* diag reg write enabled */ 66 #define MPII_HOSTDIAG_FBS (1<<6) /* flash bad sig */ 67 #define MPII_HOSTDIAG_RESET_HIST (1<<5) /* reset history */ 68 #define MPII_HOSTDIAG_DIAGWR_EN (1<<4) /* diagnostic write enabled */ 69 #define MPII_HOSTDIAG_RESET_ADAPTER (1<<2) /* reset adapter */ 70 #define MPII_HOSTDIAG_HOLD_IOC_RESET (1<<1) /* hold ioc in reset */ 71 #define MPII_HOSTDIAG_DIAGMEM_EN (1<<0) /* diag mem enable */ 72 73 #define MPII_DIAGRWDATA (0x10) 74 75 #define MPII_DIAGRWADDRLOW (0x14) 76 77 #define MPII_DIAGRWADDRHIGH (0x18) 78 79 #define MPII_INTR_STATUS (0x30) 80 #define MPII_INTR_STATUS_SYS2IOCDB (1<<31) /* ioc written to by host */ 81 #define MPII_INTR_STATUS_RESET (1<<30) /* physical ioc reset */ 82 #define MPII_INTR_STATUS_REPLY (1<<3) /* reply message interrupt */ 83 #define MPII_INTR_STATUS_IOC2SYSDB (1<<0) /* ioc write to doorbell */ 84 85 #define MPII_INTR_MASK (0x34) 86 #define MPII_INTR_MASK_RESET (1<<30) /* ioc reset intr mask */ 87 #define MPII_INTR_MASK_REPLY (1<<3) /* reply message intr mask */ 88 #define MPII_INTR_MASK_DOORBELL (1<<0) /* doorbell interrupt mask */ 89 90 #define MPII_DCR_DATA (0x38) 91 92 #define MPII_DCR_ADDRESS (0x3c) 93 94 #define MPII_REPLY_FREE_HOST_INDEX (0x48) 95 96 #define MPII_REPLY_POST_HOST_INDEX (0x6c) 97 98 #define MPII_HCB_SIZE (0x74) 99 100 #define MPII_HCB_ADDRESS_LOW (0x78) 101 #define MPII_HCB_ADDRESS_HIGH (0x7c) 102 103 #define MPII_REQ_DESCR_POST_LOW (0xc0) 104 #define MPII_REQ_DESCR_POST_HIGH (0xc4) 105 106 /* 107 * Scatter Gather Lists 108 */ 109 110 #define MPII_SGE_FL_LAST (0x1<<31) /* last element in segment */ 111 #define MPII_SGE_FL_EOB (0x1<<30) /* last element of buffer */ 112 #define MPII_SGE_FL_TYPE (0x3<<28) /* element type */ 113 #define MPII_SGE_FL_TYPE_SIMPLE (0x1<<28) /* simple element */ 114 #define MPII_SGE_FL_TYPE_CHAIN (0x3<<28) /* chain element */ 115 #define MPII_SGE_FL_TYPE_XACTCTX (0x0<<28) /* transaction context */ 116 #define MPII_SGE_FL_LOCAL (0x1<<27) /* local address */ 117 #define MPII_SGE_FL_DIR (0x1<<26) /* direction */ 118 #define MPII_SGE_FL_DIR_OUT (0x1<<26) 119 #define MPII_SGE_FL_DIR_IN (0x0<<26) 120 #define MPII_SGE_FL_SIZE (0x1<<25) /* address size */ 121 #define MPII_SGE_FL_SIZE_32 (0x0<<25) 122 #define MPII_SGE_FL_SIZE_64 (0x1<<25) 123 #define MPII_SGE_FL_EOL (0x1<<24) /* end of list */ 124 125 struct mpii_sge { 126 u_int32_t sg_hdr; 127 u_int32_t sg_addr_lo; 128 u_int32_t sg_addr_hi; 129 } __packed __aligned(4); 130 131 struct mpii_fw_tce { 132 u_int8_t reserved1; 133 u_int8_t context_size; 134 u_int8_t details_length; 135 u_int8_t flags; 136 137 u_int32_t reserved2; 138 139 u_int32_t image_offset; 140 141 u_int32_t image_size; 142 } __packed __aligned(4); 143 144 /* 145 * Messages 146 */ 147 148 /* functions */ 149 #define MPII_FUNCTION_SCSI_IO_REQUEST (0x00) 150 #define MPII_FUNCTION_SCSI_TASK_MGMT (0x01) 151 #define MPII_FUNCTION_IOC_INIT (0x02) 152 #define MPII_FUNCTION_IOC_FACTS (0x03) 153 #define MPII_FUNCTION_CONFIG (0x04) 154 #define MPII_FUNCTION_PORT_FACTS (0x05) 155 #define MPII_FUNCTION_PORT_ENABLE (0x06) 156 #define MPII_FUNCTION_EVENT_NOTIFICATION (0x07) 157 #define MPII_FUNCTION_EVENT_ACK (0x08) 158 #define MPII_FUNCTION_FW_DOWNLOAD (0x09) 159 #define MPII_FUNCTION_TARGET_CMD_BUFFER_POST (0x0a) 160 #define MPII_FUNCTION_TARGET_ASSIST (0x0b) 161 #define MPII_FUNCTION_TARGET_STATUS_SEND (0x0c) 162 #define MPII_FUNCTION_TARGET_MODE_ABORT (0x0d) 163 #define MPII_FUNCTION_FW_UPLOAD (0x12) 164 165 #define MPII_FUNCTION_RAID_ACTION (0x15) 166 #define MPII_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 167 168 #define MPII_FUNCTION_TOOLBOX (0x17) 169 170 #define MPII_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 171 172 #define MPII_FUNCTION_SMP_PASSTHROUGH (0x1a) 173 #define MPII_FUNCTION_SAS_IO_UNIT_CONTROL (0x1b) 174 #define MPII_FUNCTION_SATA_PASSTHROUGH (0x1c) 175 176 #define MPII_FUNCTION_DIAG_BUFFER_POST (0x1d) 177 #define MPII_FUNCTION_DIAG_RELEASE (0x1e) 178 179 #define MPII_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) 180 #define MPII_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) 181 182 #define MPII_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 183 #define MPII_FUNCTION_IO_UNIT_RESET (0x41) 184 #define MPII_FUNCTION_HANDSHAKE (0x42) 185 186 /* Common IOCStatus values for all replies */ 187 #define MPII_IOCSTATUS_MASK (0x7fff) 188 #define MPII_IOCSTATUS_SUCCESS (0x0000) 189 #define MPII_IOCSTATUS_INVALID_FUNCTION (0x0001) 190 #define MPII_IOCSTATUS_BUSY (0x0002) 191 #define MPII_IOCSTATUS_INVALID_SGL (0x0003) 192 #define MPII_IOCSTATUS_INTERNAL_ERROR (0x0004) 193 #define MPII_IOCSTATUS_INVALID_VPID (0x0005) 194 #define MPII_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 195 #define MPII_IOCSTATUS_INVALID_FIELD (0x0007) 196 #define MPII_IOCSTATUS_INVALID_STATE (0x0008) 197 #define MPII_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 198 /* Config IOCStatus values */ 199 #define MPII_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 200 #define MPII_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 201 #define MPII_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 202 #define MPII_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 203 #define MPII_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 204 #define MPII_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 205 /* SCSIIO Reply initiator values */ 206 #define MPII_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 207 #define MPII_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 208 #define MPII_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 209 #define MPII_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 210 #define MPII_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 211 #define MPII_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 212 #define MPII_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 213 #define MPII_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 214 #define MPII_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 215 #define MPII_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004a) 216 #define MPII_IOCSTATUS_SCSI_IOC_TERMINATED (0x004b) 217 #define MPII_IOCSTATUS_SCSI_EXT_TERMINATED (0x004c) 218 /* For use by SCSI Initiator and SCSI Target end-to-end data protection */ 219 #define MPII_IOCSTATUS_EEDP_GUARD_ERROR (0x004d) 220 #define MPII_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004e) 221 #define MPII_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004f) 222 /* SCSI (SPI & FCP) target values */ 223 #define MPII_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 224 #define MPII_IOCSTATUS_TARGET_ABORTED (0x0063) 225 #define MPII_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 226 #define MPII_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 227 #define MPII_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006a) 228 #define MPII_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006d) 229 #define MPII_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006e) 230 #define MPII_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006f) 231 #define MPII_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 232 #define MPII_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 233 /* Serial Attached SCSI values */ 234 #define MPII_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 235 #define MPII_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 236 /* Diagnostic Tools values */ 237 #define MPII_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00a0) 238 239 #define MPII_REP_IOCLOGINFO_TYPE (0xf<<28) 240 #define MPII_REP_IOCLOGINFO_TYPE_NONE (0x0<<28) 241 #define MPII_REP_IOCLOGINFO_TYPE_SCSI (0x1<<28) 242 #define MPII_REP_IOCLOGINFO_TYPE_FC (0x2<<28) 243 #define MPII_REP_IOCLOGINFO_TYPE_SAS (0x3<<28) 244 #define MPII_REP_IOCLOGINFO_TYPE_ISCSI (0x4<<28) 245 #define MPII_REP_IOCLOGINFO_DATA (0x0fffffff) 246 247 /* event notification types */ 248 #define MPII_EVENT_NONE (0x00) 249 #define MPII_EVENT_LOG_DATA (0x01) 250 #define MPII_EVENT_STATE_CHANGE (0x02) 251 #define MPII_EVENT_HARD_RESET_RECEIVED (0x05) 252 #define MPII_EVENT_EVENT_CHANGE (0x0a) 253 #define MPII_EVENT_TASK_SET_FULL (0x0e) 254 #define MPII_EVENT_SAS_DEVICE_STATUS_CHANGE (0x0f) 255 #define MPII_EVENT_IR_OPERATION_STATUS (0x14) 256 #define MPII_EVENT_SAS_DISCOVERY (0x16) 257 #define MPII_EVENT_SAS_BROADCAST_PRIMITIVE (0x17) 258 #define MPII_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x18) 259 #define MPII_EVENT_SAS_INIT_TABLE_OVERFLOW (0x19) 260 #define MPII_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x1c) 261 #define MPII_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x1d) 262 #define MPII_EVENT_IR_VOLUME (0x1e) 263 #define MPII_EVENT_IR_PHYSICAL_DISK (0x1f) 264 #define MPII_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x20) 265 #define MPII_EVENT_LOG_ENTRY_ADDED (0x21) 266 267 /* messages */ 268 269 #define MPII_WHOINIT_NOONE (0x00) 270 #define MPII_WHOINIT_SYSTEM_BIOS (0x01) 271 #define MPII_WHOINIT_ROM_BIOS (0x02) 272 #define MPII_WHOINIT_PCI_PEER (0x03) 273 #define MPII_WHOINIT_HOST_DRIVER (0x04) 274 #define MPII_WHOINIT_MANUFACTURER (0x05) 275 276 /* default messages */ 277 278 struct mpii_msg_request { 279 u_int8_t reserved1; 280 u_int8_t reserved2; 281 u_int8_t chain_offset; 282 u_int8_t function; 283 284 u_int8_t reserved3; 285 u_int8_t reserved4; 286 u_int8_t reserved5; 287 u_int8_t msg_flags; 288 289 u_int8_t vp_id; 290 u_int8_t vf_id; 291 u_int16_t reserved6; 292 } __packed __aligned(4); 293 294 struct mpii_msg_reply { 295 u_int16_t reserved1; 296 u_int8_t msg_length; 297 u_int8_t function; 298 299 u_int16_t reserved2; 300 u_int8_t reserved3; 301 u_int8_t msg_flags; 302 303 u_int8_t vp_id; 304 u_int8_t vf_if; 305 u_int16_t reserved4; 306 307 u_int16_t reserved5; 308 u_int16_t ioc_status; 309 310 u_int32_t ioc_loginfo; 311 } __packed __aligned(4); 312 313 /* ioc init */ 314 315 struct mpii_msg_iocinit_request { 316 u_int8_t whoinit; 317 u_int8_t reserved1; 318 u_int8_t chain_offset; 319 u_int8_t function; 320 321 u_int16_t reserved2; 322 u_int8_t reserved3; 323 u_int8_t msg_flags; 324 325 u_int8_t vp_id; 326 u_int8_t vf_id; 327 u_int16_t reserved4; 328 329 u_int8_t msg_version_min; 330 u_int8_t msg_version_maj; 331 u_int8_t hdr_version_unit; 332 u_int8_t hdr_version_dev; 333 334 u_int32_t reserved5; 335 336 u_int32_t reserved6; 337 338 u_int16_t reserved7; 339 u_int16_t system_request_frame_size; 340 341 u_int16_t reply_descriptor_post_queue_depth; 342 u_int16_t reply_free_queue_depth; 343 344 u_int32_t sense_buffer_address_high; 345 346 u_int32_t system_reply_address_high; 347 348 u_int32_t system_request_frame_base_address_lo; 349 u_int32_t system_request_frame_base_address_hi; 350 351 u_int32_t reply_descriptor_post_queue_address_lo; 352 u_int32_t reply_descriptor_post_queue_address_hi; 353 354 u_int32_t reply_free_queue_address_lo; 355 u_int32_t reply_free_queue_address_hi; 356 357 u_int64_t timestamp; 358 } __packed __aligned(4); 359 360 struct mpii_msg_iocinit_reply { 361 u_int8_t whoinit; 362 u_int8_t reserved1; 363 u_int8_t msg_length; 364 u_int8_t function; 365 366 u_int16_t reserved2; 367 u_int8_t reserved3; 368 u_int8_t msg_flags; 369 370 u_int8_t vp_id; 371 u_int8_t vf_id; 372 u_int16_t reserved4; 373 374 u_int16_t reserved5; 375 u_int16_t ioc_status; 376 377 u_int32_t ioc_loginfo; 378 } __packed __aligned(4); 379 380 struct mpii_msg_iocfacts_request { 381 u_int16_t reserved1; 382 u_int8_t chain_offset; 383 u_int8_t function; 384 385 u_int16_t reserved2; 386 u_int8_t reserved3; 387 u_int8_t msg_flags; 388 389 u_int8_t vp_id; 390 u_int8_t vf_id; 391 u_int16_t reserved4; 392 } __packed __aligned(4); 393 394 struct mpii_msg_iocfacts_reply { 395 u_int8_t msg_version_min; 396 u_int8_t msg_version_maj; 397 u_int8_t msg_length; 398 u_int8_t function; 399 400 u_int8_t header_version_dev; 401 u_int8_t header_version_unit; 402 u_int8_t ioc_number; 403 u_int8_t msg_flags; 404 405 u_int8_t vp_id; 406 u_int8_t vf_id; 407 u_int16_t reserved1; 408 409 u_int16_t ioc_exceptions; 410 #define MPII_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (1<<0) 411 #define MPII_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (1<<1) 412 #define MPII_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (1<<2) 413 #define MPII_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (1<<3) 414 #define MPII_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (1<<4) 415 #define MPII_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAC (1<<8) 416 /* XXX JPG BOOT_STATUS in bits[7:5] */ 417 /* XXX JPG all these #defines need to be fixed up */ 418 u_int16_t ioc_status; 419 420 u_int32_t ioc_loginfo; 421 422 u_int8_t max_chain_depth; 423 u_int8_t whoinit; 424 u_int8_t number_of_ports; 425 u_int8_t reserved2; 426 427 u_int16_t request_credit; 428 u_int16_t product_id; 429 430 u_int32_t ioc_capabilities; 431 #define MPII_IOCFACTS_CAPABILITY_EVENT_REPLAY (1<<13) 432 #define MPII_IOCFACTS_CAPABILITY_INTEGRATED_RAID (1<<12) 433 #define MPII_IOCFACTS_CAPABILITY_TLR (1<<11) 434 #define MPII_IOCFACTS_CAPABILITY_MULTICAST (1<<8) 435 #define MPII_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (1<<7) 436 #define MPII_IOCFACTS_CAPABILITY_EEDP (1<<6) 437 #define MPII_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (1<<4) 438 #define MPII_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (1<<3) 439 #define MPII_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (1<<2) 440 441 u_int8_t fw_version_dev; 442 u_int8_t fw_version_unit; 443 u_int8_t fw_version_min; 444 u_int8_t fw_version_maj; 445 446 u_int16_t ioc_request_frame_size; 447 u_int16_t reserved3; 448 449 u_int16_t max_initiators; 450 u_int16_t max_targets; 451 452 u_int16_t max_sas_expanders; 453 u_int16_t max_enclosures; 454 455 u_int16_t protocol_flags; 456 u_int16_t high_priority_credit; 457 458 u_int16_t max_reply_descriptor_post_queue_depth; 459 u_int8_t reply_frame_size; 460 u_int8_t max_volumes; 461 462 u_int16_t max_dev_handle; 463 u_int16_t max_persistent_entries; 464 465 u_int32_t reserved4; 466 } __packed __aligned(4); 467 468 struct mpii_msg_portfacts_request { 469 u_int16_t reserved1; 470 u_int8_t chain_offset; 471 u_int8_t function; 472 473 u_int16_t reserved2; 474 u_int8_t port_number; 475 u_int8_t msg_flags; 476 477 u_int8_t vp_id; 478 u_int8_t vf_id; 479 u_int16_t reserved3; 480 } __packed __aligned(4); 481 482 struct mpii_msg_portfacts_reply { 483 u_int16_t reserved1; 484 u_int8_t msg_length; 485 u_int8_t function; 486 487 u_int16_t reserved2; 488 u_int8_t port_number; 489 u_int8_t msg_flags; 490 491 u_int8_t vp_id; 492 u_int8_t vf_id; 493 u_int16_t reserved3; 494 495 u_int16_t reserved4; 496 u_int16_t ioc_status; 497 498 u_int32_t ioc_loginfo; 499 500 u_int8_t reserved5; 501 u_int8_t port_type; 502 #define MPII_PORTFACTS_PORTTYPE_INACTIVE (0x00) 503 #define MPII_PORTFACTS_PORTTYPE_FC (0x10) 504 #define MPII_PORTFACTS_PORTTYPE_ISCSI (0x20) 505 #define MPII_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 506 #define MPII_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 507 u_int16_t reserved6; 508 509 u_int16_t max_posted_cmd_buffers; 510 u_int16_t reserved7; 511 } __packed __aligned(4); 512 513 struct mpii_msg_portenable_request { 514 u_int16_t reserved1; 515 u_int8_t chain_offset; 516 u_int8_t function; 517 518 u_int8_t reserved2; 519 u_int8_t port_flags; 520 u_int8_t reserved3; 521 u_int8_t msg_flags; 522 523 u_int8_t vp_id; 524 u_int8_t vf_id; 525 u_int16_t reserved4; 526 } __packed __aligned(4); 527 528 struct mpii_msg_portenable_reply { 529 u_int16_t reserved1; 530 u_int8_t msg_length; 531 u_int8_t function; 532 533 u_int8_t reserved2; 534 u_int8_t port_flags; 535 u_int8_t reserved3; 536 u_int8_t msg_flags; 537 538 u_int8_t vp_id; 539 u_int8_t vf_id; 540 u_int16_t reserved4; 541 542 u_int16_t reserved5; 543 u_int16_t ioc_status; 544 545 u_int32_t ioc_loginfo; 546 } __packed __aligned(4); 547 548 struct mpii_msg_event_request { 549 u_int16_t reserved1; 550 u_int8_t chain_offset; 551 u_int8_t function; 552 553 u_int16_t reserved2; 554 u_int8_t reserved3; 555 u_int8_t msg_flags; 556 557 u_int8_t vp_id; 558 u_int8_t vf_id; 559 u_int16_t reserved4; 560 561 u_int32_t reserved5; 562 563 u_int32_t reserved6; 564 565 u_int32_t event_masks[4]; 566 567 u_int16_t sas_broadcase_primitive_masks; 568 u_int16_t reserved7; 569 570 u_int32_t reserved8; 571 } __packed __aligned(4); 572 573 struct mpii_msg_event_reply { 574 u_int16_t event_data_length; 575 u_int8_t msg_length; 576 u_int8_t function; 577 578 u_int16_t reserved1; 579 u_int8_t ack_required; 580 #define MPII_EVENT_ACK_REQUIRED (0x01) 581 u_int8_t msg_flags; 582 #define MPII_EVENT_FLAGS_REPLY_KEPT (1<<7) 583 584 u_int8_t vp_id; 585 u_int8_t vf_id; 586 u_int16_t reserved2; 587 588 u_int16_t reserved3; 589 u_int16_t ioc_status; 590 591 u_int32_t ioc_loginfo; 592 593 u_int16_t event; 594 u_int16_t reserved4; 595 596 u_int32_t event_context; 597 598 /* event data follows */ 599 } __packed __aligned(4); 600 601 struct mpii_msg_eventack_request { 602 u_int16_t reserved1; 603 u_int8_t chain_offset; 604 u_int8_t function; 605 606 u_int8_t reserved2[3]; 607 u_int8_t msg_flags; 608 609 u_int8_t vp_id; 610 u_int8_t vf_id; 611 u_int16_t reserved3; 612 613 u_int16_t event; 614 u_int16_t reserved4; 615 616 u_int32_t event_context; 617 } __packed __aligned(4); 618 619 struct mpii_msg_eventack_reply { 620 u_int16_t reserved1; 621 u_int8_t msg_length; 622 u_int8_t function; 623 624 u_int8_t reserved2[3]; 625 u_int8_t msg_flags; 626 627 u_int8_t vp_id; 628 u_int8_t vf_id; 629 u_int16_t reserved3; 630 631 u_int16_t reserved4; 632 u_int16_t ioc_status; 633 634 u_int32_t ioc_loginfo; 635 } __packed __aligned(4); 636 637 struct mpii_msg_fwupload_request { 638 u_int8_t image_type; 639 #define MPII_FWUPLOAD_IMAGETYPE_IOC_FW (0x00) 640 #define MPII_FWUPLOAD_IMAGETYPE_NV_FW (0x01) 641 #define MPII_FWUPLOAD_IMAGETYPE_NV_BACKUP (0x05) 642 #define MPII_FWUPLOAD_IMAGETYPE_NV_MANUFACTURING (0x06) 643 #define MPII_FWUPLOAD_IMAGETYPE_NV_CONFIG_1 (0x07) 644 #define MPII_FWUPLOAD_IMAGETYPE_NV_CONFIG_2 (0x08) 645 #define MPII_FWUPLOAD_IMAGETYPE_NV_MEGARAID (0x09) 646 #define MPII_FWUPLOAD_IMAGETYPE_NV_COMPLETE (0x0a) 647 #define MPII_FWUPLOAD_IMAGETYPE_COMMON_BOOT_BLOCK (0x0b) 648 u_int8_t reserved1; 649 u_int8_t chain_offset; 650 u_int8_t function; 651 652 u_int8_t reserved2[3]; 653 u_int8_t msg_flags; 654 655 u_int8_t vp_id; 656 u_int8_t vf_id; 657 u_int16_t reserved3; 658 659 u_int32_t reserved4; 660 661 u_int32_t reserved5; 662 663 struct mpii_fw_tce tce; 664 665 /* followed by an sgl */ 666 } __packed __aligned(4); 667 668 struct mpii_msg_fwupload_reply { 669 u_int8_t image_type; 670 u_int8_t reserved1; 671 u_int8_t msg_length; 672 u_int8_t function; 673 674 u_int8_t reserved2[3]; 675 u_int8_t msg_flags; 676 677 u_int8_t vp_id; 678 u_int8_t vf_id; 679 u_int16_t reserved3; 680 681 u_int16_t reserved4; 682 u_int16_t ioc_status; 683 684 u_int32_t ioc_loginfo; 685 686 u_int32_t actual_image_size; 687 } __packed __aligned(4); 688 689 struct mpii_msg_scsi_io { 690 u_int16_t dev_handle; 691 u_int8_t chain_offset; 692 u_int8_t function; 693 694 u_int16_t reserved1; 695 u_int8_t reserved2; 696 u_int8_t msg_flags; 697 698 u_int8_t vp_id; 699 u_int8_t vf_id; 700 u_int16_t reserved3; 701 702 u_int32_t sense_buffer_low_address; 703 704 u_int16_t sgl_flags; 705 u_int8_t sense_buffer_length; 706 u_int8_t reserved4; 707 708 u_int8_t sgl_offset0; 709 u_int8_t sgl_offset1; 710 u_int8_t sgl_offset2; 711 u_int8_t sgl_offset3; 712 713 u_int32_t skip_count; 714 715 u_int32_t data_length; 716 717 u_int32_t bidirectional_data_length; 718 719 u_int16_t io_flags; 720 u_int16_t eedp_flags; 721 722 u_int32_t eedp_block_size; 723 724 u_int32_t secondary_reference_tag; 725 726 u_int16_t secondary_application_tag; 727 u_int16_t application_tag_translation_mask; 728 729 u_int16_t lun[4]; 730 731 /* the following 16 bits are defined in MPI2 as the control field */ 732 u_int8_t reserved5; 733 u_int8_t tagging; 734 #define MPII_SCSIIO_ATTR_SIMPLE_Q (0x0) 735 #define MPII_SCSIIO_ATTR_HEAD_OF_Q (0x1) 736 #define MPII_SCSIIO_ATTR_ORDERED_Q (0x2) 737 #define MPII_SCSIIO_ATTR_ACA_Q (0x4) 738 #define MPII_SCSIIO_ATTR_UNTAGGED (0x5) 739 #define MPII_SCSIIO_ATTR_NO_DISCONNECT (0x7) 740 u_int8_t reserved6; 741 u_int8_t direction; 742 #define MPII_SCSIIO_DIR_NONE (0x0) 743 #define MPII_SCSIIO_DIR_WRITE (0x1) 744 #define MPII_SCSIIO_DIR_READ (0x2) 745 746 #define MPII_CDB_LEN (32) 747 u_int8_t cdb[MPII_CDB_LEN]; 748 749 /* followed by an sgl */ 750 } __packed __aligned(4); 751 752 struct mpii_msg_scsi_io_error { 753 u_int16_t dev_handle; 754 u_int8_t msg_length; 755 u_int8_t function; 756 757 u_int16_t reserved1; 758 u_int8_t reserved2; 759 u_int8_t msg_flags; 760 761 u_int8_t vp_id; 762 u_int8_t vf_id; 763 u_int16_t reserved3; 764 765 u_int8_t scsi_status; 766 /* XXX JPG validate this */ 767 #if notyet 768 #define MPII_SCSIIO_ERR_STATUS_SUCCESS 769 #define MPII_SCSIIO_ERR_STATUS_CHECK_COND 770 #define MPII_SCSIIO_ERR_STATUS_BUSY 771 #define MPII_SCSIIO_ERR_STATUS_INTERMEDIATE 772 #define MPII_SCSIIO_ERR_STATUS_INTERMEDIATE_CONDMET 773 #define MPII_SCSIIO_ERR_STATUS_RESERVATION_CONFLICT 774 #define MPII_SCSIIO_ERR_STATUS_CMD_TERM 775 #define MPII_SCSIIO_ERR_STATUS_TASK_SET_FULL 776 #define MPII_SCSIIO_ERR_STATUS_ACA_ACTIVE 777 #endif 778 u_int8_t scsi_state; 779 #define MPII_SCSIIO_ERR_STATE_AUTOSENSE_VALID (1<<0) 780 #define MPII_SCSIIO_ERR_STATE_AUTOSENSE_FAILED (1<<1) 781 #define MPII_SCSIIO_ERR_STATE_NO_SCSI_STATUS (1<<2) 782 #define MPII_SCSIIO_ERR_STATE_TERMINATED (1<<3) 783 #define MPII_SCSIIO_ERR_STATE_RESPONSE_INFO_VALID (1<<4) 784 #define MPII_SCSIIO_ERR_STATE_QUEUE_TAG_REJECTED (0xffff) 785 u_int16_t ioc_status; 786 787 u_int32_t ioc_loginfo; 788 789 u_int32_t transfer_count; 790 791 u_int32_t sense_count; 792 793 u_int32_t response_info; 794 795 u_int16_t task_tag; 796 u_int16_t reserved4; 797 798 u_int32_t bidirectional_transfer_count; 799 800 u_int32_t reserved5; 801 802 u_int32_t reserved6; 803 } __packed __aligned(4); 804 805 struct mpii_request_descr { 806 u_int8_t request_flags; 807 #define MPII_REQ_DESCR_TYPE_MASK (0x0e) 808 #define MPII_REQ_DESCR_SCSI_IO (0x00) 809 #define MPII_REQ_DESCR_SCSI_TARGET (0x02) 810 #define MPII_REQ_DESCR_HIGH_PRIORITY (0x06) 811 #define MPII_REQ_DESCR_DEFAULT (0x08) 812 u_int8_t vf_id; 813 u_int16_t smid; 814 815 u_int16_t lmid; 816 u_int16_t dev_handle; 817 } __packed __aligned(8); 818 819 struct mpii_reply_descr { 820 u_int8_t reply_flags; 821 #define MPII_REPLY_DESCR_TYPE_MASK (0x0f) 822 #define MPII_REPLY_DESCR_SCSI_IO_SUCCESS (0x00) 823 #define MPII_REPLY_DESCR_ADDRESS_REPLY (0x01) 824 #define MPII_REPLY_DESCR_TARGET_ASSIST_SUCCESS (0x02) 825 #define MPII_REPLY_DESCR_TARGET_COMMAND_BUFFER (0x03) 826 #define MPII_REPLY_DESCR_UNUSED (0x0f) 827 u_int8_t vf_id; 828 u_int16_t smid; 829 830 union { 831 u_int32_t data; 832 u_int32_t frame_addr; /* Address Reply */ 833 }; 834 } __packed __aligned(8); 835 836 struct mpii_request_header { 837 u_int16_t function_dependent1; 838 u_int8_t chain_offset; 839 u_int8_t function; 840 841 u_int16_t function_dependent2; 842 u_int8_t function_dependent3; 843 u_int8_t message_flags; 844 845 u_int8_t vp_id; 846 u_int8_t vf_id; 847 u_int16_t reserved; 848 } __packed __aligned(4); 849 850 struct mpii_msg_scsi_task_request { 851 u_int16_t dev_handle; 852 u_int8_t chain_offset; 853 u_int8_t function; 854 855 u_int8_t reserved1; 856 u_int8_t task_type; 857 #define MPII_SCSI_TASK_ABORT_TASK (0x01) 858 #define MPII_SCSI_TASK_ABRT_TASK_SET (0x02) 859 #define MPII_SCSI_TASK_TARGET_RESET (0x03) 860 #define MPII_SCSI_TASK_RESET_BUS (0x04) 861 #define MPII_SCSI_TASK_LOGICAL_UNIT_RESET (0x05) 862 u_int8_t reserved2; 863 u_int8_t msg_flags; 864 865 u_int8_t vp_id; 866 u_int8_t vf_id; 867 u_int16_t reserved3; 868 869 u_int16_t lun[4]; 870 871 u_int32_t reserved4[7]; 872 873 u_int16_t task_mid; 874 u_int16_t reserved5; 875 } __packed __aligned(4); 876 877 struct mpii_msg_scsi_task_reply { 878 u_int16_t dev_handle; 879 u_int8_t msg_length; 880 u_int8_t function; 881 882 u_int8_t response_code; 883 u_int8_t task_type; 884 u_int8_t reserved1; 885 u_int8_t msg_flags; 886 887 u_int8_t vp_id; 888 u_int8_t vf_id; 889 u_int16_t reserved2; 890 891 u_int16_t reserved3; 892 u_int16_t ioc_status; 893 894 u_int32_t ioc_loginfo; 895 896 u_int32_t termination_count; 897 } __packed __aligned(4); 898 899 struct mpii_msg_sas_oper_request { 900 u_int8_t operation; 901 #define MPII_SAS_OP_CLEAR_PERSISTENT (0x02) 902 #define MPII_SAS_OP_PHY_LINK_RESET (0x06) 903 #define MPII_SAS_OP_PHY_HARD_RESET (0x07) 904 #define MPII_SAS_OP_PHY_CLEAR_ERROR_LOG (0x08) 905 #define MPII_SAS_OP_SEND_PRIMITIVE (0x0a) 906 #define MPII_SAS_OP_FORCE_FULL_DISCOVERY (0x0b) 907 #define MPII_SAS_OP_TRANSMIT_PORT_SELECT (0x0c) 908 #define MPII_SAS_OP_REMOVE_DEVICE (0x0d) 909 #define MPII_SAS_OP_LOOKUP_MAPPING (0x0e) 910 #define MPII_SAS_OP_SET_IOC_PARAM (0x0f) 911 u_int8_t reserved1; 912 u_int8_t chain_offset; 913 u_int8_t function; 914 915 u_int16_t dev_handle; 916 u_int8_t ioc_param; 917 u_int8_t msg_flags; 918 919 u_int8_t vp_id; 920 u_int8_t vf_id; 921 u_int16_t reserved2; 922 923 u_int16_t reserved3; 924 u_int8_t phy_num; 925 u_int8_t prim_flags; 926 927 u_int32_t primitive; 928 929 u_int8_t lookup_method; 930 #define MPII_SAS_LOOKUP_METHOD_SAS_ADDR (0x01) 931 #define MPII_SAS_LOOKUP_METHOD_SAS_ENCL (0x02) 932 #define MPII_SAS_LOOKUP_METHOD_SAS_DEVNAME (0x03) 933 u_int8_t reserved4; 934 u_int16_t slot_num; 935 936 u_int64_t lookup_addr; 937 938 u_int32_t ioc_param_value; 939 940 u_int64_t reserved5; 941 } __packed __aligned(4); 942 943 struct mpii_msg_sas_oper_reply { 944 u_int8_t operation; 945 u_int8_t reserved1; 946 u_int8_t chain_offset; 947 u_int8_t function; 948 949 u_int16_t dev_handle; 950 u_int8_t ioc_param; 951 u_int8_t msg_flags; 952 953 u_int8_t vp_id; 954 u_int8_t vf_id; 955 u_int16_t reserved2; 956 957 u_int16_t reserved3; 958 u_int16_t ioc_status; 959 960 u_int32_t ioc_loginfo; 961 } __packed __aligned(4); 962 963 struct mpii_msg_raid_action_request { 964 u_int8_t action; 965 #define MPII_RAID_ACTION_CHANGE_VOL_WRITE_CACHE (0x17) 966 u_int8_t reserved1; 967 u_int8_t chain_offset; 968 u_int8_t function; 969 970 u_int16_t vol_dev_handle; 971 u_int8_t phys_disk_num; 972 u_int8_t msg_flags; 973 974 u_int8_t vp_id; 975 u_int8_t vf_if; 976 u_int16_t reserved2; 977 978 u_int32_t reserved3; 979 980 u_int32_t action_data; 981 #define MPII_RAID_VOL_WRITE_CACHE_MASK (0x03) 982 #define MPII_RAID_VOL_WRITE_CACHE_DISABLE (0x01) 983 #define MPII_RAID_VOL_WRITE_CACHE_ENABLE (0x02) 984 985 struct mpii_sge action_sge; 986 } __packed __aligned(4); 987 988 struct mpii_msg_raid_action_reply { 989 u_int8_t action; 990 u_int8_t reserved1; 991 u_int8_t chain_offset; 992 u_int8_t function; 993 994 u_int16_t vol_dev_handle; 995 u_int8_t phys_disk_num; 996 u_int8_t msg_flags; 997 998 u_int8_t vp_id; 999 u_int8_t vf_if; 1000 u_int16_t reserved2; 1001 1002 u_int16_t reserved3; 1003 u_int16_t ioc_status; 1004 1005 u_int32_t action_data[5]; 1006 } __packed __aligned(4); 1007 1008 struct mpii_cfg_hdr { 1009 u_int8_t page_version; 1010 u_int8_t page_length; 1011 u_int8_t page_number; 1012 u_int8_t page_type; 1013 #define MPII_CONFIG_REQ_PAGE_TYPE_ATTRIBUTE (0xf0) 1014 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 1015 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 1016 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 1017 1018 #define MPII_CONFIG_REQ_PAGE_TYPE_MASK (0x0f) 1019 #define MPII_CONFIG_REQ_PAGE_TYPE_IO_UNIT (0x00) 1020 #define MPII_CONFIG_REQ_PAGE_TYPE_IOC (0x01) 1021 #define MPII_CONFIG_REQ_PAGE_TYPE_BIOS (0x02) 1022 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_VOL (0x08) 1023 #define MPII_CONFIG_REQ_PAGE_TYPE_MANUFACTURING (0x09) 1024 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_PD (0x0a) 1025 #define MPII_CONFIG_REQ_PAGE_TYPE_EXTENDED (0x0f) 1026 } __packed __aligned(4); 1027 1028 struct mpii_ecfg_hdr { 1029 u_int8_t page_version; 1030 u_int8_t reserved1; 1031 u_int8_t page_number; 1032 u_int8_t page_type; 1033 1034 u_int16_t ext_page_length; 1035 u_int8_t ext_page_type; 1036 #define MPII_CONFIG_REQ_PAGE_TYPE_SAS_DEVICE (0x12) 1037 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_CONFIG (0x16) 1038 #define MPII_CONFIG_REQ_PAGE_TYPE_DRIVER_MAPPING (0x17) 1039 u_int8_t reserved2; 1040 } __packed __aligned(4); 1041 1042 struct mpii_msg_config_request { 1043 u_int8_t action; 1044 #define MPII_CONFIG_REQ_ACTION_PAGE_HEADER (0x00) 1045 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_CURRENT (0x01) 1046 #define MPII_CONFIG_REQ_ACTION_PAGE_WRITE_CURRENT (0x02) 1047 #define MPII_CONFIG_REQ_ACTION_PAGE_DEFAULT (0x03) 1048 #define MPII_CONFIG_REQ_ACTION_PAGE_WRITE_NVRAM (0x04) 1049 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_DEFAULT (0x05) 1050 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_NVRAM (0x06) 1051 u_int8_t sgl_flags; 1052 u_int8_t chain_offset; 1053 u_int8_t function; 1054 1055 u_int16_t ext_page_len; 1056 u_int8_t ext_page_type; 1057 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_IO_UNIT (0x10) 1058 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_EXPANDER (0x11) 1059 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_DEVICE (0x12) 1060 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_PHY (0x13) 1061 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_LOG (0x14) 1062 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 1063 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 1064 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 1065 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 1066 u_int8_t msg_flags; 1067 1068 u_int8_t vp_id; 1069 u_int8_t vf_id; 1070 u_int16_t reserved1; 1071 1072 u_int32_t reserved2[2]; 1073 1074 struct mpii_cfg_hdr config_header; 1075 1076 u_int32_t page_address; 1077 /* XXX lots of defns here */ 1078 1079 struct mpii_sge page_buffer; 1080 } __packed __aligned(4); 1081 1082 struct mpii_msg_config_reply { 1083 u_int8_t action; 1084 u_int8_t sgl_flags; 1085 u_int8_t msg_length; 1086 u_int8_t function; 1087 1088 u_int16_t ext_page_length; 1089 u_int8_t ext_page_type; 1090 u_int8_t msg_flags; 1091 1092 u_int8_t vp_id; 1093 u_int8_t vf_id; 1094 u_int16_t reserved1; 1095 1096 u_int16_t reserved2; 1097 u_int16_t ioc_status; 1098 1099 u_int32_t ioc_loginfo; 1100 1101 struct mpii_cfg_hdr config_header; 1102 } __packed __aligned(4); 1103 1104 struct mpii_cfg_manufacturing_pg0 { 1105 struct mpii_cfg_hdr config_header; 1106 1107 char chip_name[16]; 1108 char chip_revision[8]; 1109 char board_name[16]; 1110 char board_assembly[16]; 1111 char board_tracer_number[16]; 1112 } __packed __aligned(4); 1113 1114 struct mpii_cfg_ioc_pg1 { 1115 struct mpii_cfg_hdr config_header; 1116 1117 u_int32_t flags; 1118 1119 u_int32_t coalescing_timeout; 1120 #define MPII_CFG_IOC_1_REPLY_COALESCING (1<<0) 1121 1122 u_int8_t coalescing_depth; 1123 u_int8_t pci_slot_num; 1124 u_int8_t pci_bus_num; 1125 u_int8_t pci_domain_segment; 1126 1127 u_int32_t reserved1; 1128 1129 u_int32_t reserved2; 1130 } __packed __aligned(4); 1131 1132 struct mpii_cfg_ioc_pg3 { 1133 struct mpii_cfg_hdr config_header; 1134 1135 u_int8_t no_phys_disks; 1136 u_int8_t reserved[3]; 1137 1138 /* followed by a list of mpii_cfg_raid_physdisk structs */ 1139 } __packed __aligned(4); 1140 1141 struct mpii_cfg_ioc_pg8 { 1142 struct mpii_cfg_hdr config_header; 1143 1144 u_int8_t num_devs_per_enclosure; 1145 u_int8_t reserved1; 1146 u_int16_t reserved2; 1147 1148 u_int16_t max_persistent_entries; 1149 u_int16_t max_num_physical_mapped_ids; 1150 1151 u_int16_t flags; 1152 #define MPII_IOC_PG8_FLAGS_DA_START_SLOT_1 (1<<5) 1153 #define MPII_IOC_PG8_FLAGS_RESERVED_TARGETID_0 (1<<4) 1154 #define MPII_IOC_PG8_FLAGS_MAPPING_MODE_MASK (0x0000000e) 1155 #define MPII_IOC_PG8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0<<1) 1156 #define MPII_IOC_PG8_FLAGS_ENCLOSURE_SLOT_MAPPING (1<<1) 1157 #define MPII_IOC_PG8_FLAGS_DISABLE_PERSISTENT_MAPPING (1<<0) 1158 #define MPII_IOC_PG8_FLAGS_ENABLE_PERSISTENT_MAPPING (0<<0) 1159 u_int16_t reserved3; 1160 1161 u_int16_t ir_volume_mapping_flags; 1162 #define MPII_IOC_PG8_IRFLAGS_VOLUME_MAPPING_MODE_MASK (0x00000003) 1163 #define MPII_IOC_PG8_IRFLAGS_LOW_VOLUME_MAPPING (0<<0) 1164 #define MPII_IOC_PG8_IRFLAGS_HIGH_VOLUME_MAPPING (1<<0) 1165 u_int16_t reserved4; 1166 1167 u_int32_t reserved5; 1168 } __packed __aligned(4); 1169 1170 struct mpii_cfg_raid_physdisk { 1171 u_int8_t phys_disk_id; 1172 u_int8_t phys_disk_bus; 1173 u_int8_t phys_disk_ioc; 1174 u_int8_t phys_disk_num; 1175 } __packed __aligned(4); 1176 1177 struct mpii_cfg_fc_port_pg0 { 1178 struct mpii_cfg_hdr config_header; 1179 1180 u_int32_t flags; 1181 1182 u_int8_t mpii_port_nr; 1183 u_int8_t link_type; 1184 u_int8_t port_state; 1185 u_int8_t reserved1; 1186 1187 u_int32_t port_id; 1188 1189 u_int64_t wwnn; 1190 1191 u_int64_t wwpn; 1192 1193 u_int32_t supported_service_class; 1194 1195 u_int32_t supported_speeds; 1196 1197 u_int32_t current_speed; 1198 1199 u_int32_t max_frame_size; 1200 1201 u_int64_t fabric_wwnn; 1202 1203 u_int64_t fabric_wwpn; 1204 1205 u_int32_t discovered_port_count; 1206 1207 u_int32_t max_initiators; 1208 1209 u_int8_t max_aliases_supported; 1210 u_int8_t max_hard_aliases_supported; 1211 u_int8_t num_current_aliases; 1212 u_int8_t reserved2; 1213 } __packed __aligned(4); 1214 1215 struct mpii_cfg_fc_port_pg1 { 1216 struct mpii_cfg_hdr config_header; 1217 1218 u_int32_t flags; 1219 1220 u_int64_t noseepromwwnn; 1221 1222 u_int64_t noseepromwwpn; 1223 1224 u_int8_t hard_alpa; 1225 u_int8_t link_config; 1226 u_int8_t topology_config; 1227 u_int8_t alt_connector; 1228 1229 u_int8_t num_req_aliases; 1230 u_int8_t rr_tov; 1231 u_int8_t initiator_dev_to; 1232 u_int8_t initiator_lo_pend_to; 1233 } __packed __aligned(4); 1234 1235 struct mpii_cfg_fc_device_pg0 { 1236 struct mpii_cfg_hdr config_header; 1237 1238 u_int64_t wwnn; 1239 1240 u_int64_t wwpn; 1241 1242 u_int32_t port_id; 1243 1244 u_int8_t protocol; 1245 u_int8_t flags; 1246 u_int16_t bb_credit; 1247 1248 u_int16_t max_rx_frame_size; 1249 u_int8_t adisc_hard_alpa; 1250 u_int8_t port_nr; 1251 1252 u_int8_t fc_ph_low_version; 1253 u_int8_t fc_ph_high_version; 1254 u_int8_t current_target_id; 1255 u_int8_t current_bus; 1256 } __packed __aligned(4); 1257 1258 #define MPII_CFG_RAID_VOL_ADDR_HANDLE (1<<28) 1259 1260 struct mpii_cfg_raid_vol_pg0 { 1261 struct mpii_cfg_hdr config_header; 1262 1263 u_int16_t volume_handle; 1264 u_int8_t volume_state; 1265 #define MPII_CFG_RAID_VOL_0_STATE_MISSING (0x00) 1266 #define MPII_CFG_RAID_VOL_0_STATE_FAILED (0x01) 1267 #define MPII_CFG_RAID_VOL_0_STATE_INITIALIZING (0x02) 1268 #define MPII_CFG_RAID_VOL_0_STATE_ONLINE (0x03) 1269 #define MPII_CFG_RAID_VOL_0_STATE_DEGRADED (0x04) 1270 #define MPII_CFG_RAID_VOL_0_STATE_OPTIMAL (0x05) 1271 u_int8_t volume_type; 1272 #define MPII_CFG_RAID_VOL_0_TYPE_RAID0 (0x00) 1273 #define MPII_CFG_RAID_VOL_0_TYPE_RAID1E (0x01) 1274 #define MPII_CFG_RAID_VOL_0_TYPE_RAID1 (0x02) 1275 #define MPII_CFG_RAID_VOL_0_TYPE_RAID10 (0x05) 1276 #define MPII_CFG_RAID_VOL_0_TYPE_UNKNOWN (0xff) 1277 1278 u_int32_t volume_status; 1279 #define MPII_CFG_RAID_VOL_0_STATUS_SCRUB (1<<20) 1280 #define MPII_CFG_RAID_VOL_0_STATUS_RESYNC (1<<16) 1281 1282 u_int16_t volume_settings; 1283 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_MASK (0x3<<0) 1284 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_UNCHANGED (0x0<<0) 1285 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_DISABLED (0x1<<0) 1286 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_ENABLED (0x2<<0) 1287 1288 u_int8_t hot_spare_pool; 1289 u_int8_t reserved1; 1290 1291 u_int64_t max_lba; 1292 1293 u_int32_t stripe_size; 1294 1295 u_int16_t block_size; 1296 u_int16_t reserved2; 1297 1298 u_int8_t phys_disk_types; 1299 u_int8_t resync_rate; 1300 u_int16_t data_scrub_rate; 1301 1302 u_int8_t num_phys_disks; 1303 u_int16_t reserved3; 1304 u_int8_t inactive_status; 1305 #define MPII_CFG_RAID_VOL_0_INACTIVE_UNKNOWN (0x00) 1306 #define MPII_CFG_RAID_VOL_0_INACTIVE_STALE_META (0x01) 1307 #define MPII_CFG_RAID_VOL_0_INACTIVE_FOREIGN_VOL (0x02) 1308 #define MPII_CFG_RAID_VOL_0_INACTIVE_NO_RESOURCES (0x03) 1309 #define MPII_CFG_RAID_VOL_0_INACTIVE_CLONED_VOL (0x04) 1310 #define MPII_CFG_RAID_VOL_0_INACTIVE_INSUF_META (0x05) 1311 1312 /* followed by a list of mpii_cfg_raid_vol_pg0_physdisk structs */ 1313 } __packed __aligned(4); 1314 1315 struct mpii_cfg_raid_vol_pg0_physdisk { 1316 u_int8_t raid_set_num; 1317 u_int8_t phys_disk_map; 1318 u_int8_t phys_disk_num; 1319 u_int8_t reserved; 1320 } __packed __aligned(4); 1321 1322 struct mpii_cfg_raid_vol_pg1 { 1323 struct mpii_cfg_hdr config_header; 1324 1325 u_int8_t volume_id; 1326 u_int8_t volume_bus; 1327 u_int8_t volume_ioc; 1328 u_int8_t reserved1; 1329 1330 u_int8_t guid[24]; 1331 1332 u_int8_t name[32]; 1333 1334 u_int64_t wwid; 1335 1336 u_int32_t reserved2; 1337 1338 u_int32_t reserved3; 1339 } __packed __aligned(4); 1340 1341 #define MPII_CFG_RAID_PHYS_DISK_ADDR_NUMBER (1<<28) 1342 1343 struct mpii_cfg_raid_physdisk_pg0 { 1344 struct mpii_cfg_hdr config_header; 1345 1346 u_int16_t dev_handle; 1347 u_int8_t reserved1; 1348 u_int8_t phys_disk_num; 1349 1350 u_int8_t enc_id; 1351 u_int8_t enc_bus; 1352 u_int8_t hot_spare_pool; 1353 u_int8_t enc_type; 1354 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_NONE (0x0) 1355 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_SAFTE (0x1) 1356 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_SES (0x2) 1357 1358 u_int32_t reserved2; 1359 1360 u_int8_t vendor_id[8]; 1361 1362 u_int8_t product_id[16]; 1363 1364 u_int8_t product_rev[4]; 1365 1366 u_int8_t serial[32]; 1367 1368 u_int32_t reserved3; 1369 1370 u_int8_t phys_disk_state; 1371 #define MPII_CFG_RAID_PHYDISK_0_STATE_NOTCONFIGURED (0x00) 1372 #define MPII_CFG_RAID_PHYDISK_0_STATE_NOTCOMPATIBLE (0x01) 1373 #define MPII_CFG_RAID_PHYDISK_0_STATE_OFFLINE (0x02) 1374 #define MPII_CFG_RAID_PHYDISK_0_STATE_ONLINE (0x03) 1375 #define MPII_CFG_RAID_PHYDISK_0_STATE_HOTSPARE (0x04) 1376 #define MPII_CFG_RAID_PHYDISK_0_STATE_DEGRADED (0x05) 1377 #define MPII_CFG_RAID_PHYDISK_0_STATE_REBUILDING (0x06) 1378 #define MPII_CFG_RAID_PHYDISK_0_STATE_OPTIMAL (0x07) 1379 u_int8_t offline_reason; 1380 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_MISSING (0x01) 1381 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILED (0x03) 1382 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_INITIALIZING (0x04) 1383 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_REQUESTED (0x05) 1384 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILEDREQ (0x06) 1385 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_OTHER (0xff) 1386 1387 u_int8_t incompat_reason; 1388 u_int8_t phys_disk_attrs; 1389 1390 u_int32_t phys_disk_status; 1391 #define MPII_CFG_RAID_PHYDISK_0_STATUS_OUTOFSYNC (1<<0) 1392 #define MPII_CFG_RAID_PHYDISK_0_STATUS_QUIESCED (1<<1) 1393 1394 u_int64_t dev_max_lba; 1395 1396 u_int64_t host_max_lba; 1397 1398 u_int64_t coerced_max_lba; 1399 1400 u_int16_t block_size; 1401 u_int16_t reserved4; 1402 1403 u_int32_t reserved5; 1404 } __packed __aligned(4); 1405 1406 struct mpii_cfg_raid_physdisk_pg1 { 1407 struct mpii_cfg_hdr config_header; 1408 1409 u_int8_t num_phys_disk_paths; 1410 u_int8_t phys_disk_num; 1411 u_int16_t reserved1; 1412 1413 u_int32_t reserved2; 1414 1415 /* followed by mpii_cfg_raid_physdisk_path structs */ 1416 } __packed __aligned(4); 1417 1418 struct mpii_cfg_raid_physdisk_path { 1419 u_int8_t phys_disk_id; 1420 u_int8_t phys_disk_bus; 1421 u_int16_t reserved1; 1422 1423 u_int64_t wwwid; 1424 1425 u_int64_t owner_wwid; 1426 1427 u_int8_t ownder_id; 1428 u_int8_t reserved2; 1429 u_int16_t flags; 1430 #define MPII_CFG_RAID_PHYDISK_PATH_INVALID (1<<0) 1431 #define MPII_CFG_RAID_PHYDISK_PATH_BROKEN (1<<1) 1432 } __packed __aligned(4); 1433 1434 #define MPII_CFG_SAS_DEV_ADDR_NEXT (0<<28) 1435 #define MPII_CFG_SAS_DEV_ADDR_BUS (1<<28) 1436 #define MPII_CFG_SAS_DEV_ADDR_HANDLE (2<<28) 1437 1438 struct mpii_cfg_sas_dev_pg0 { 1439 struct mpii_ecfg_hdr config_header; 1440 1441 u_int16_t slot; 1442 u_int16_t enc_handle; 1443 1444 u_int64_t sas_addr; 1445 1446 u_int16_t parent_dev_handle; 1447 u_int8_t phy_num; 1448 u_int8_t access_status; 1449 1450 u_int16_t dev_handle; 1451 u_int8_t target; 1452 u_int8_t bus; 1453 1454 u_int32_t device_info; 1455 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE (0x7) 1456 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_NONE (0x0) 1457 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_END (0x1) 1458 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_EDGE_EXPANDER (0x2) 1459 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_FANOUT_EXPANDER (0x3) 1460 #define MPII_CFG_SAS_DEV_0_DEVINFO_SATA_HOST (1<<3) 1461 #define MPII_CFG_SAS_DEV_0_DEVINFO_SMP_INITIATOR (1<<4) 1462 #define MPII_CFG_SAS_DEV_0_DEVINFO_STP_INITIATOR (1<<5) 1463 #define MPII_CFG_SAS_DEV_0_DEVINFO_SSP_INITIATOR (1<<6) 1464 #define MPII_CFG_SAS_DEV_0_DEVINFO_SATA_DEVICE (1<<7) 1465 #define MPII_CFG_SAS_DEV_0_DEVINFO_SMP_TARGET (1<<8) 1466 #define MPII_CFG_SAS_DEV_0_DEVINFO_STP_TARGET (1<<9) 1467 #define MPII_CFG_SAS_DEV_0_DEVINFO_SSP_TARGET (1<<10) 1468 #define MPII_CFG_SAS_DEV_0_DEVINFO_DIRECT_ATTACHED (1<<11) 1469 #define MPII_CFG_SAS_DEV_0_DEVINFO_LSI_DEVICE (1<<12) 1470 #define MPII_CFG_SAS_DEV_0_DEVINFO_ATAPI_DEVICE (1<<13) 1471 #define MPII_CFG_SAS_DEV_0_DEVINFO_SEP_DEVICE (1<<14) 1472 1473 u_int16_t flags; 1474 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_PRESENT (1<<0) 1475 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED (1<<1) 1476 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED_PERSISTENT (1<<2) 1477 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_PORT_SELECTOR (1<<3) 1478 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_FUA (1<<4) 1479 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_NCQ (1<<5) 1480 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_SMART (1<<6) 1481 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_LBA48 (1<<7) 1482 #define MPII_CFG_SAS_DEV_0_FLAGS_UNSUPPORTED (1<<8) 1483 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_SETTINGS (1<<9) 1484 u_int8_t physical_port; 1485 u_int8_t max_port_conn; 1486 1487 u_int64_t device_name; 1488 1489 u_int8_t port_groups; 1490 u_int8_t dma_group; 1491 u_int8_t ctrl_group; 1492 u_int8_t reserved1; 1493 1494 u_int64_t reserved2; 1495 } __packed __aligned(4); 1496 1497 #define MPII_CFG_RAID_CONFIG_ACTIVE_CONFIG (2<<28) 1498 1499 struct mpii_cfg_raid_config_pg0 { 1500 struct mpii_ecfg_hdr config_header; 1501 1502 u_int8_t num_hot_spares; 1503 u_int8_t num_phys_disks; 1504 u_int8_t num_volumes; 1505 u_int8_t config_num; 1506 1507 u_int32_t flags; 1508 #define MPII_CFG_RAID_CONFIG_0_FLAGS_NATIVE (0<<0) 1509 #define MPII_CFG_RAID_CONFIG_0_FLAGS_FOREIGN (1<<0) 1510 1511 u_int32_t config_guid[6]; 1512 1513 u_int32_t reserved1; 1514 1515 u_int8_t num_elements; 1516 u_int8_t reserved2[3]; 1517 1518 /* followed by struct mpii_raid_config_element structs */ 1519 } __packed __aligned(4); 1520 1521 struct mpii_raid_config_element { 1522 u_int16_t element_flags; 1523 #define MPII_RAID_CONFIG_ELEMENT_FLAG_VOLUME (0x0) 1524 #define MPII_RAID_CONFIG_ELEMENT_FLAG_VOLUME_PHYS_DISK (0x1) 1525 #define MPII_RAID_CONFIG_ELEMENT_FLAG_HSP_PHYS_DISK (0x2) 1526 #define MPII_RAID_CONFIG_ELEMENT_ONLINE_CE_PHYS_DISK (0x3) 1527 u_int16_t vol_dev_handle; 1528 1529 u_int8_t hot_spare_pool; 1530 u_int8_t phys_disk_num; 1531 u_int16_t phys_disk_dev_handle; 1532 } __packed __aligned(4); 1533 1534 struct mpii_cfg_dpm_pg0 { 1535 struct mpii_ecfg_hdr config_header; 1536 #define MPII_DPM_ADDRESS_FORM_MASK (0xf0000000) 1537 #define MPII_DPM_ADDRESS_FORM_ENTRY_RANGE (0x00000000) 1538 #define MPII_DPM_ADDRESS_ENTRY_COUNT_MASK (0x0fff0000) 1539 #define MPII_DPM_ADDRESS_ENTRY_COUNT_SHIFT (16) 1540 #define MPII_DPM_ADDRESS_START_ENTRY_MASK (0x0000ffff) 1541 1542 /* followed by struct mpii_dpm_entry structs */ 1543 } __packed __aligned(4); 1544 1545 struct mpii_dpm_entry { 1546 u_int64_t physical_identifier; 1547 1548 u_int16_t mapping_information; 1549 u_int16_t device_index; 1550 1551 u_int32_t physical_bits_mapping; 1552 1553 u_int32_t reserved1; 1554 } __packed __aligned(4); 1555 1556 struct mpii_evt_sas_discovery { 1557 u_int8_t flags; 1558 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_MASK (1<<1) 1559 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_NO_CHANGE (0<<1) 1560 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_CHANGE (1<<1) 1561 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_IN_PROG_MASK (1<<0) 1562 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_NOT_IN_PROGRESS (1<<0) 1563 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_IN_PROGRESS (0<<0) 1564 u_int8_t reason_code; 1565 #define MPII_EVENT_SAS_DISC_REASON_CODE_STARTED (0x01) 1566 #define MPII_EVENT_SAS_DISC_REASON_CODE_COMPLETED (0x02) 1567 u_int8_t physical_port; 1568 u_int8_t reserved1; 1569 1570 u_int32_t discovery_status; 1571 } __packed __aligned(4); 1572 1573 struct mpii_evt_ir_status { 1574 u_int16_t vol_dev_handle; 1575 u_int16_t reserved1; 1576 1577 u_int8_t operation; 1578 #define MPII_EVENT_IR_RAIDOP_RESYNC (0x00) 1579 #define MPII_EVENT_IR_RAIDOP_OCE (0x01) 1580 #define MPII_EVENT_IR_RAIDOP_CONS_CHECK (0x02) 1581 #define MPII_EVENT_IR_RAIDOP_BG_INIT (0x03) 1582 #define MPII_EVENT_IR_RAIDOP_MAKE_CONS (0x04) 1583 u_int8_t percent; 1584 u_int16_t reserved2; 1585 1586 u_int32_t reserved3; 1587 }; 1588 1589 struct mpii_evt_ir_volume { 1590 u_int16_t vol_dev_handle; 1591 u_int8_t reason_code; 1592 #define MPII_EVENT_IR_VOL_RC_SETTINGS_CHANGED (0x01) 1593 #define MPII_EVENT_IR_VOL_RC_STATUS_CHANGED (0x02) 1594 #define MPII_EVENT_IR_VOL_RC_STATE_CHANGED (0x03) 1595 u_int8_t reserved1; 1596 1597 u_int32_t new_value; 1598 u_int32_t prev_value; 1599 } __packed __aligned(4); 1600 1601 struct mpii_evt_ir_physical_disk { 1602 u_int16_t reserved1; 1603 u_int8_t reason_code; 1604 #define MPII_EVENT_IR_PD_RC_SETTINGS_CHANGED (0x01) 1605 #define MPII_EVENT_IR_PD_RC_STATUS_FLAGS_CHANGED (0x02) 1606 #define MPII_EVENT_IR_PD_RC_STATUS_CHANGED (0x03) 1607 u_int8_t phys_disk_num; 1608 1609 u_int16_t phys_disk_dev_handle; 1610 u_int16_t reserved2; 1611 1612 u_int16_t slot; 1613 u_int16_t enclosure_handle; 1614 1615 u_int32_t new_value; 1616 u_int32_t previous_value; 1617 } __packed __aligned(4); 1618 1619 struct mpii_evt_sas_tcl { 1620 u_int16_t enclosure_handle; 1621 u_int16_t expander_handle; 1622 1623 u_int8_t num_phys; 1624 u_int8_t reserved1[3]; 1625 1626 u_int8_t num_entries; 1627 u_int8_t start_phy_num; 1628 u_int8_t expn_status; 1629 #define MPII_EVENT_SAS_TOPO_ES_ADDED (0x01) 1630 #define MPII_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 1631 #define MPII_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 1632 #define MPII_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 1633 u_int8_t physical_port; 1634 1635 /* followed by num_entries number of struct mpii_evt_phy_entry */ 1636 } __packed __aligned(4); 1637 1638 struct mpii_evt_phy_entry { 1639 u_int16_t dev_handle; 1640 u_int8_t link_rate; 1641 u_int8_t phy_status; 1642 #define MPII_EVENT_SAS_TOPO_PS_RC_MASK (0x0f) 1643 #define MPII_EVENT_SAS_TOPO_PS_RC_ADDED (0x01) 1644 #define MPII_EVENT_SAS_TOPO_PS_RC_MISSING (0x02) 1645 } __packed __aligned(4); 1646 1647 struct mpii_evt_ir_cfg_change_list { 1648 u_int8_t num_elements; 1649 u_int16_t reserved; 1650 u_int8_t config_num; 1651 1652 u_int32_t flags; 1653 #define MPII_EVT_IR_CFG_CHANGE_LIST_FOREIGN (0x1) 1654 1655 /* followed by num_elements struct mpii_evt_ir_cfg_elements */ 1656 } __packed __aligned(4); 1657 1658 struct mpii_evt_ir_cfg_element { 1659 u_int16_t element_flags; 1660 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_MASK (0xf) 1661 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME (0x0) 1662 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME_DISK (0x1) 1663 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_HOT_SPARE (0x2) 1664 u_int16_t vol_dev_handle; 1665 1666 u_int8_t reason_code; 1667 #define MPII_EVT_IR_CFG_ELEMENT_RC_ADDED (0x01) 1668 #define MPII_EVT_IR_CFG_ELEMENT_RC_REMOVED (0x02) 1669 #define MPII_EVT_IR_CFG_ELEMENT_RC_NO_CHANGE (0x03) 1670 #define MPII_EVT_IR_CFG_ELEMENT_RC_HIDE (0x04) 1671 #define MPII_EVT_IR_CFG_ELEMENT_RC_UNHIDE (0x05) 1672 #define MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_CREATED (0x06) 1673 #define MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_DELETED (0x07) 1674 #define MPII_EVT_IR_CFG_ELEMENT_RC_PD_CREATED (0x08) 1675 #define MPII_EVT_IR_CFG_ELEMENT_RC_PD_DELETED (0x09) 1676 u_int8_t phys_disk_num; 1677 u_int16_t phys_disk_dev_handle; 1678 } __packed __aligned(4); 1679