1 /* $OpenBSD: pccbb.c,v 1.87 2010/12/08 20:22:49 miod Exp $ */ 2 /* $NetBSD: pccbb.c,v 1.96 2004/03/28 09:49:31 nakayama Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 and 2000 6 * HAYAKAWA Koichi. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 #define CBB_DEBUG 31 #define SHOW_REGS 32 #define PCCBB_PCMCIA_POLL 33 */ 34 35 /* 36 #define CB_PCMCIA_POLL 37 #define CB_PCMCIA_POLL_ONLY 38 #define LEVEL2 39 */ 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/evcount.h> 47 #include <sys/ioctl.h> 48 #include <sys/syslog.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 52 #include <machine/intr.h> 53 #include <machine/bus.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <dev/pci/pccbbreg.h> 60 61 #include <dev/cardbus/cardslotvar.h> 62 63 #include <dev/cardbus/cardbusvar.h> 64 65 #include <dev/pcmcia/pcmciareg.h> 66 #include <dev/pcmcia/pcmciavar.h> 67 68 #include <dev/ic/i82365reg.h> 69 #include <dev/ic/i82365var.h> 70 #include <dev/pci/pccbbvar.h> 71 72 #ifndef __NetBSD_Version__ 73 struct cfdriver cbb_cd = { 74 NULL, "cbb", DV_DULL 75 }; 76 #endif 77 78 #if defined CBB_DEBUG 79 #define DPRINTF(x) printf x 80 #else 81 #define DPRINTF(x) 82 #endif 83 84 int pcicbbmatch(struct device *, void *, void *); 85 void pccbbattach(struct device *, struct device *, void *); 86 int pccbbactivate(struct device *, int); 87 int pccbbintr(void *); 88 void pccbb_shutdown(void *); 89 void pci113x_insert(void *); 90 int pccbbintr_function(struct pccbb_softc *); 91 92 int pccbb_checksockstat(struct pccbb_softc *); 93 int pccbb_detect_card(struct pccbb_softc *); 94 95 void pccbb_pcmcia_write(struct pcic_handle *, int, int); 96 u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 97 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 98 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 99 100 int cb_reset(struct pccbb_softc *); 101 int cb_detect_voltage(struct pccbb_softc *); 102 int cbbprint(void *, const char *); 103 104 int cb_chipset(u_int32_t, int *); 105 void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 106 struct pcmciabus_attach_args *); 107 #if 0 108 void pccbb_pcmcia_attach_card(struct pcic_handle *); 109 void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 110 void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 111 #endif 112 113 int pccbb_ctrl(cardbus_chipset_tag_t, int); 114 int pccbb_power(cardbus_chipset_tag_t, int); 115 int pccbb_cardenable(struct pccbb_softc * sc, int function); 116 void *pccbb_intr_establish(struct pccbb_softc *, int irq, int level, 117 int (*ih) (void *), void *sc, const char *); 118 void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 119 120 void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, int level, 121 int (*ih) (void *), void *sc, const char *); 122 void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 123 124 void pccbb_legacy_disable(struct pccbb_softc *sc); 125 void pccbb_chipinit(struct pccbb_softc *); 126 127 int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 128 struct pcmcia_mem_handle *); 129 void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 130 struct pcmcia_mem_handle *); 131 int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 132 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 133 void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 134 int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 135 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 136 void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 137 struct pcmcia_io_handle *); 138 int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 139 bus_size_t, struct pcmcia_io_handle *, int *); 140 void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 141 void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 142 struct pcmcia_function *, int, int (*)(void *), void *, char *); 143 void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 144 const char *pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t, void *); 145 void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 146 void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 147 int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 148 149 void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 150 void pccbb_pcmcia_wait_ready(struct pcic_handle *); 151 void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 152 153 /* bus-space allocation and deallocation functions */ 154 int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 155 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 156 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 157 int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 158 bus_space_handle_t, bus_size_t); 159 160 int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 161 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 162 int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 163 bus_space_handle_t, bus_size_t); 164 int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 165 bus_size_t, bus_space_handle_t, int); 166 int pccbb_winlist_delete(struct pccbb_win_chain_head *, 167 bus_space_handle_t, bus_size_t); 168 void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 169 bus_space_tag_t); 170 void pccbb_winlist_show(struct pccbb_win_chain *); 171 172 /* for config_defer */ 173 void pccbb_pci_callback(struct device *); 174 175 #if defined SHOW_REGS 176 void cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t, 177 bus_space_handle_t memh); 178 #endif 179 180 struct cfattach cbb_pci_ca = { 181 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach, NULL, 182 pccbbactivate 183 }; 184 185 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 186 pccbb_pcmcia_mem_alloc, 187 pccbb_pcmcia_mem_free, 188 pccbb_pcmcia_mem_map, 189 pccbb_pcmcia_mem_unmap, 190 pccbb_pcmcia_io_alloc, 191 pccbb_pcmcia_io_free, 192 pccbb_pcmcia_io_map, 193 pccbb_pcmcia_io_unmap, 194 pccbb_pcmcia_intr_establish, 195 pccbb_pcmcia_intr_disestablish, 196 pccbb_pcmcia_intr_string, 197 pccbb_pcmcia_socket_enable, 198 pccbb_pcmcia_socket_disable, 199 pccbb_pcmcia_card_detect 200 }; 201 202 static struct cardbus_functions pccbb_funcs = { 203 pccbb_rbus_cb_space_alloc, 204 pccbb_rbus_cb_space_free, 205 pccbb_cb_intr_establish, 206 pccbb_cb_intr_disestablish, 207 pccbb_ctrl, 208 pccbb_power, 209 }; 210 211 /* 212 * delay_ms() is wait in milliseconds. It should be used instead 213 * of delay() if you want to wait more than 1 ms. 214 */ 215 static inline void 216 delay_ms(int millis, void *param) 217 { 218 if (cold) 219 delay(millis * 1000); 220 else 221 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 222 } 223 224 int 225 pcicbbmatch(parent, match, aux) 226 struct device *parent; 227 void *match; 228 void *aux; 229 { 230 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 231 232 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 233 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 234 PCI_INTERFACE(pa->pa_class) == 0) { 235 return 1; 236 } 237 238 return 0; 239 } 240 241 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 242 | ((prod) << PCI_PRODUCT_SHIFT)) 243 244 struct yenta_chipinfo { 245 pcireg_t yc_id; /* vendor tag | product tag */ 246 int yc_chiptype; 247 int yc_flags; 248 } yc_chipsets[] = { 249 /* Texas Instruments chips */ 250 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 251 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 252 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 253 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 254 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 255 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 256 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 257 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 258 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 259 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 260 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 261 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 262 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 263 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 264 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 265 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 266 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 267 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 268 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 269 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 270 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 271 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 272 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 273 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 274 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 275 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 276 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 277 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 278 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7XX1), CB_TI12XX, 279 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 280 281 /* Ricoh chips */ 282 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X, 283 PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X, 285 PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X, 287 PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X, 289 PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X, 291 PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X, 293 PCCBB_PCMCIA_MEM_32}, 294 295 /* Toshiba products */ 296 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 297 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 299 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 301 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 303 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 304 305 /* Cirrus Logic products */ 306 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 307 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 309 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 310 311 /* older O2Micro bridges */ 312 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 313 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 315 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), /* 68[71]2 */ 317 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 319 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 321 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 322 323 /* sentinel, or Generic chip */ 324 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 325 }; 326 327 int 328 cb_chipset(pci_id, flagp) 329 u_int32_t pci_id; 330 int *flagp; 331 { 332 struct yenta_chipinfo *yc; 333 334 /* Loop over except the last default entry. */ 335 for (yc = yc_chipsets; yc < yc_chipsets + 336 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 337 if (pci_id == yc->yc_id) 338 break; 339 340 if (flagp != NULL) 341 *flagp = yc->yc_flags; 342 343 return (yc->yc_chiptype); 344 } 345 346 void 347 pccbb_shutdown(void *arg) 348 { 349 struct pccbb_softc *sc = arg; 350 pcireg_t command; 351 352 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 353 354 /* turn off power */ 355 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 356 357 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 358 0); 359 360 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 361 362 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 363 PCI_COMMAND_MASTER_ENABLE); 364 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 365 } 366 367 void 368 pccbbattach(struct device *parent, struct device *self, void *aux) 369 { 370 struct pccbb_softc *sc = (void *)self; 371 struct pci_attach_args *pa = aux; 372 pci_chipset_tag_t pc = pa->pa_pc; 373 pci_intr_handle_t ih; 374 const char *intrstr = NULL; 375 int flags; 376 377 pccbb_attach_hook(parent, self, pa); 378 379 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 380 sc->sc_id = pa->pa_id; 381 382 #ifdef CBB_DEBUG 383 printf(" (chipflags %x)", flags); 384 #endif 385 386 TAILQ_INIT(&sc->sc_memwindow); 387 TAILQ_INIT(&sc->sc_iowindow); 388 389 sc->sc_rbus_iot = rbus_pccbb_parent_io(self, pa); 390 sc->sc_rbus_memt = rbus_pccbb_parent_mem(self, pa); 391 392 /* 393 * MAP socket registers and ExCA registers on memory-space 394 */ 395 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 396 &sc->sc_base_memt, &sc->sc_base_memh, NULL, NULL, 0)) { 397 printf("can't map registers\n"); 398 return; 399 } 400 401 sc->sc_busnum = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 402 403 #if defined CBB_DEBUG 404 { 405 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 406 printf(": intrpin %s, line %d\n", 407 intrname[pa->pa_intrpin], pa->pa_intrline); 408 } 409 #endif 410 411 /* setup softc */ 412 sc->sc_pc = pc; 413 sc->sc_iot = pa->pa_iot; 414 sc->sc_memt = pa->pa_memt; 415 sc->sc_dmat = pa->pa_dmat; 416 sc->sc_tag = pa->pa_tag; 417 sc->sc_function = pa->pa_function; 418 sc->sc_intrtag = pa->pa_intrtag; 419 sc->sc_intrpin = pa->pa_intrpin; 420 421 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 422 423 /* Map and establish the interrupt. */ 424 if (pci_intr_map(pa, &ih)) { 425 printf(": couldn't map interrupt\n"); 426 return; 427 } 428 intrstr = pci_intr_string(pc, ih); 429 /* must do this after intr is mapped and established */ 430 sc->sc_intrline = pci_intr_line(pc, ih); 431 432 /* 433 * XXX pccbbintr should be called under the priority lower 434 * than any other hard interrupts. 435 */ 436 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc, 437 sc->sc_dev.dv_xname); 438 439 if (sc->sc_ih == NULL) { 440 printf(": couldn't establish interrupt"); 441 if (intrstr != NULL) { 442 printf(" at %s", intrstr); 443 } 444 printf("\n"); 445 return; 446 } 447 printf(": %s", intrstr); 448 449 /* 450 * When bus number isn't set correctly, give up using 32-bit CardBus 451 * mode. 452 */ 453 if (((sc->sc_busnum >> 8) & 0xff) == 0) { 454 printf(", CardBus support disabled"); 455 sc->sc_pcmcia_flags |= PCCBB_PCMCIA_16BITONLY; 456 } 457 458 printf("\n"); 459 460 shutdownhook_establish(pccbb_shutdown, sc); 461 462 /* Disable legacy register mapping. */ 463 pccbb_legacy_disable(sc); 464 465 timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc); 466 config_defer(self, pccbb_pci_callback); 467 } 468 469 /* 470 * void pccbb_pci_callback(struct device *self) 471 * 472 * The actual attach routine: get memory space for YENTA register 473 * space, setup YENTA register and route interrupt. 474 * 475 * This function should be deferred because this device may obtain 476 * memory space dynamically. This function must avoid obtaining 477 * memory area which has already kept for another device. Also, 478 * this function MUST be done before ISA attach process because this 479 * function kills pcic compatible port used by ISA pcic. 480 */ 481 void 482 pccbb_pci_callback(struct device *self) 483 { 484 struct pccbb_softc *sc = (void *)self; 485 pci_chipset_tag_t pc = sc->sc_pc; 486 bus_space_tag_t base_memt; 487 bus_space_handle_t base_memh; 488 u_int32_t maskreg; 489 struct cbslot_attach_args cba; 490 struct pcmciabus_attach_args paa; 491 struct cardslot_attach_args caa; 492 struct cardslot_softc *csc; 493 u_int32_t sockstat; 494 495 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 496 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 497 498 /* bus bridge initialization */ 499 pccbb_chipinit(sc); 500 501 /* clear data structure for child device interrupt handlers */ 502 sc->sc_pil = NULL; 503 sc->sc_pil_intr_enable = 1; 504 505 sockstat = bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 506 if ((sockstat & CB_SOCKET_STAT_CD) == 0) 507 sc->sc_flags |= CBB_CARDEXIST; 508 509 /* 510 * attach cardbus 511 */ 512 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 513 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 514 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 515 516 /* initialize cbslot_attach */ 517 cba.cba_busname = "cardbus"; 518 cba.cba_iot = sc->sc_iot; 519 cba.cba_memt = sc->sc_memt; 520 cba.cba_dmat = sc->sc_dmat; 521 cba.cba_bus = (busreg >> 8) & 0x0ff; 522 cba.cba_cc = (void *)sc; 523 cba.cba_pc = sc->sc_pc; 524 cba.cba_cf = &pccbb_funcs; 525 cba.cba_intrline = sc->sc_intrline; 526 527 cba.cba_rbus_iot = sc->sc_rbus_iot; 528 cba.cba_rbus_memt = sc->sc_rbus_memt; 529 530 cba.cba_cacheline = PCI_CACHELINE(bhlc); 531 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 532 533 #if defined CBB_DEBUG 534 printf("%s: cacheline 0x%x lattimer 0x%x\n", 535 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 536 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 537 busreg); 538 #endif 539 #if defined SHOW_REGS 540 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 541 sc->sc_base_memh); 542 #endif 543 } 544 545 pccbb_pcmcia_attach_setup(sc, &paa); 546 caa.caa_cb_attach = NULL; 547 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 548 caa.caa_cb_attach = &cba; 549 } 550 caa.caa_16_attach = &paa; 551 caa.caa_ph = &sc->sc_pcmcia_h; 552 553 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 554 DPRINTF(("pccbbattach: found cardslot\n")); 555 sc->sc_csc = csc; 556 } 557 558 sc->sc_ints_on = 1; 559 560 /* CSC Interrupt: Card detect interrupt on */ 561 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 562 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 563 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 564 /* reset interrupt */ 565 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 566 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 567 568 return; 569 } 570 571 void 572 pccbb_legacy_disable(struct pccbb_softc *sc) 573 { 574 pcireg_t reg; 575 576 switch (sc->sc_chipset) { 577 case CB_RX5C46X: 578 /* 579 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 580 * cannot be disabled by substituting 0 into PCI_LEGACY 581 * register. Ricoh CardBus bridges have special bits on Bridge 582 * control reg (addr 0x3e on PCI config space). 583 */ 584 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 585 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 586 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 587 break; 588 589 default: 590 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_LEGACY, 0x0); 591 break; 592 } 593 } 594 595 /* 596 * void pccbb_chipinit(struct pccbb_softc *sc) 597 * 598 * This function initialize YENTA chip registers listed below: 599 * 1) PCI command reg, 600 * 2) PCI and CardBus latency timer, 601 * 3) route PCI interrupt, 602 * 4) close all memory and io windows. 603 */ 604 void 605 pccbb_chipinit(struct pccbb_softc *sc) 606 { 607 pci_chipset_tag_t pc = sc->sc_pc; 608 pcitag_t tag = sc->sc_tag; 609 pcireg_t reg; 610 611 /* 612 * Set PCI command reg. 613 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 614 */ 615 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 616 /* I believe it is harmless. */ 617 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 618 PCI_COMMAND_MASTER_ENABLE); 619 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 620 621 /* 622 * Set CardBus latency timer. 623 */ 624 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 625 if (PCI_CB_LATENCY(reg) < 0x20) { 626 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 627 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 628 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 629 } 630 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 631 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 632 633 /* 634 * Set PCI latency timer. 635 */ 636 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 637 if (PCI_LATTIMER(reg) < 0x10) { 638 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 639 reg |= (0x10 << PCI_LATTIMER_SHIFT); 640 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 641 } 642 DPRINTF(("PCI latency timer 0x%x (%x)\n", 643 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 644 645 /* Route functional interrupts to PCI. */ 646 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 647 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 648 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 649 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 650 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 651 652 switch (sc->sc_chipset) { 653 case CB_TI113X: 654 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 655 /* This bit is shared, but may read as 0 on some chips, so set 656 it explicitly on both functions. */ 657 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 658 /* CSC intr enable */ 659 reg |= PCI113X_CBCTRL_PCI_CSC; 660 /* functional intr prohibit | prohibit ISA routing */ 661 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 662 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 663 break; 664 665 case CB_TI12XX: 666 /* 667 * Some TI 12xx (and [14][45]xx) based pci cards 668 * sometimes have issues with the MFUNC register not 669 * being initialized due to a bad EEPROM on board. 670 * Laptops that this matters on have this register 671 * properly initialized. 672 * 673 * The TI125X parts have a different register. 674 */ 675 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 676 if (reg == PCI12XX_MFUNC_DEFAULT) { 677 reg &= ~PCI12XX_MFUNC_PIN0; 678 reg |= PCI12XX_MFUNC_PIN0_INTA; 679 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 680 PCI12XX_SYSCTRL_INTRTIE) == 0) { 681 reg &= ~PCI12XX_MFUNC_PIN1; 682 reg |= PCI12XX_MFUNC_PIN1_INTB; 683 } 684 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 685 } 686 /* FALLTHROUGH */ 687 688 case CB_TI125X: 689 /* 690 * Disable zoom video. Some machines initialize this 691 * improperly and experience has shown that this helps 692 * prevent strange behavior. 693 */ 694 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 695 696 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 697 reg |= PCI12XX_SYSCTRL_VCCPROT; 698 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 699 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 700 reg |= PCI12XX_CBCTRL_CSC; 701 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 702 break; 703 704 case CB_TOPIC95B: 705 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 706 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 707 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 708 709 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 710 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 711 sc->sc_dev.dv_xname, reg)); 712 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 713 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 714 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 715 DPRINTF(("0x%x\n", reg)); 716 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 717 break; 718 719 case CB_TOPIC97: 720 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 721 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 722 sc->sc_dev.dv_xname, reg)); 723 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 724 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 725 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 726 reg |= TOPIC97_SLOT_CTRL_PCIINT; 727 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 728 DPRINTF(("0x%x\n", reg)); 729 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 730 731 /* make sure to assert LV card support bits */ 732 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 733 0x800 + 0x3e, bus_space_read_1(sc->sc_base_memt, 734 sc->sc_base_memh, 0x800 + 0x3e) | 0x03); 735 736 /* Power on the controller if the BIOS didn't */ 737 reg = pci_conf_read(pc, tag, TOPIC100_PMCSR); 738 if ((reg & TOPIC100_PMCSR_MASK) != TOPIC100_PMCSR_D0) 739 pci_conf_write(pc, tag, TOPIC100_PMCSR, 740 (reg & ~TOPIC100_PMCSR_MASK) | TOPIC100_PMCSR_D0); 741 break; 742 743 case CB_OLDO2MICRO: 744 /* 745 * older bridges have problems with both read prefetch and 746 * write bursting depending on the combination of the chipset, 747 * bridge and the cardbus card. so disable them to be on the 748 * safe side. One example is O2Micro 6812 with Atheros AR5012 749 * chipsets 750 */ 751 DPRINTF(("%s: old O2Micro bridge found\n", 752 sc->sc_dev.dv_xname, reg)); 753 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED1); 754 pci_conf_write(pc, tag, O2MICRO_RESERVED1, reg & 755 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 756 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED2); 757 pci_conf_write(pc, tag, O2MICRO_RESERVED2, reg & 758 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 759 break; 760 } 761 762 /* Close all memory and I/O windows. */ 763 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 764 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 765 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 766 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 767 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 768 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 769 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 770 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 771 772 /* reset 16-bit pcmcia bus */ 773 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 774 0x800 + PCIC_INTR, 775 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 776 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 777 778 /* turn off power */ 779 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 780 } 781 782 783 784 785 /* 786 * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 787 * struct pcmciabus_attach_args *paa) 788 * 789 * This function attaches 16-bit PCcard bus. 790 */ 791 void 792 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 793 struct pcmciabus_attach_args *paa) 794 { 795 struct pcic_handle *ph = &sc->sc_pcmcia_h; 796 rbus_tag_t rb; 797 798 /* initialize pcmcia part in pccbb_softc */ 799 ph->ph_parent = (struct device *)sc; 800 ph->sock = sc->sc_function; 801 ph->flags = 0; 802 ph->shutdown = 0; 803 ph->ih_irq = sc->sc_intrline; 804 ph->ph_bus_t = sc->sc_base_memt; 805 ph->ph_bus_h = sc->sc_base_memh; 806 ph->ph_read = pccbb_pcmcia_read; 807 ph->ph_write = pccbb_pcmcia_write; 808 sc->sc_pct = &pccbb_pcmcia_funcs; 809 810 /* 811 * We need to do a few things here: 812 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 813 * setting the IRQ numbers to 0. 814 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 815 * routing of CSC interrupts (e.g. card removal) to PCI while in 816 * PCMCIA mode. We just leave this set all the time. 817 * 3) Enable card insertion/removal interrupts in case the chip also 818 * needs that while in PCMCIA mode. 819 * 4) Clear any pending CSC interrupt. 820 */ 821 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 822 if (sc->sc_chipset == CB_TI113X) { 823 Pcic_write(ph, PCIC_CSC_INTR, 0); 824 } else { 825 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 826 Pcic_read(ph, PCIC_CSC); 827 } 828 829 /* initialize pcmcia bus attachment */ 830 paa->paa_busname = "pcmcia"; 831 paa->pct = sc->sc_pct; 832 paa->pch = ph; 833 paa->iobase = 0; /* I don't use them */ 834 paa->iosize = 0; 835 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 836 paa->iobase = rb->rb_start + rb->rb_offset; 837 paa->iosize = rb->rb_end - rb->rb_start; 838 839 return; 840 } 841 842 #if 0 843 void 844 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 845 { 846 if (ph->flags & PCIC_FLAG_CARDP) { 847 panic("pccbb_pcmcia_attach_card: already attached"); 848 } 849 850 /* call the MI attach function */ 851 pcmcia_card_attach(ph->pcmcia); 852 853 ph->flags |= PCIC_FLAG_CARDP; 854 } 855 856 void 857 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 858 { 859 if (!(ph->flags & PCIC_FLAG_CARDP)) { 860 panic("pccbb_pcmcia_detach_card: already detached"); 861 } 862 863 ph->flags &= ~PCIC_FLAG_CARDP; 864 865 /* call the MI detach function */ 866 pcmcia_card_detach(ph->pcmcia, flags); 867 } 868 #endif 869 870 int 871 pccbb_checksockstat(struct pccbb_softc *sc) 872 { 873 u_int32_t sockstate; 874 875 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 876 CB_SOCKET_STAT); 877 878 if ((sockstate & CB_SOCKET_STAT_CD) != 0) { 879 /* A card should be removed. */ 880 if (sc->sc_flags & CBB_CARDEXIST) { 881 DPRINTF(("%s: card removed, 0x%08x\n", 882 sc->sc_dev.dv_xname, sockstate)); 883 sc->sc_flags &= ~CBB_CARDEXIST; 884 if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { 885 #if 0 886 struct pcic_handle *ph = 887 &sc->sc_pcmcia_h; 888 889 pcmcia_card_deactivate(ph->pcmcia); 890 pccbb_pcmcia_socket_disable(ph); 891 pccbb_pcmcia_detach_card(ph, 892 DETACH_FORCE); 893 #endif 894 cardslot_event_throw(sc->sc_csc, 895 CARDSLOT_EVENT_REMOVAL_16); 896 } else if (sc->sc_csc->sc_status & 897 CARDSLOT_STATUS_CARD_CB) { 898 /* Cardbus intr removed */ 899 cardslot_event_throw(sc->sc_csc, 900 CARDSLOT_EVENT_REMOVAL_CB); 901 } 902 } 903 return (1); 904 } else if ((sockstate & CB_SOCKET_STAT_CD) == 0 && 905 (sc->sc_flags & CBB_CARDEXIST) == 0) { 906 timeout_add_msec(&sc->sc_ins_tmo, 100); 907 sc->sc_flags |= CBB_INSERTING; 908 return (1); 909 } 910 return (0); 911 } 912 913 /* 914 * int pccbbintr(arg) 915 * void *arg; 916 * This routine handles the interrupt from Yenta PCI-CardBus bridge 917 * itself. 918 */ 919 int 920 pccbbintr(void *arg) 921 { 922 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 923 u_int32_t sockevent; 924 struct pcic_handle *ph = &sc->sc_pcmcia_h; 925 926 if (!sc->sc_ints_on) 927 return 0; 928 929 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 930 CB_SOCKET_EVENT); 931 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, 932 CB_SOCKET_EVENT, sockevent); 933 Pcic_read(ph, PCIC_CSC); 934 935 if (sockevent & CB_SOCKET_EVENT_CD) { 936 if (pccbb_checksockstat(sc)) 937 return (1); 938 } 939 940 if (sc->sc_pil_intr_enable) 941 return pccbbintr_function(sc); 942 return (0); 943 } 944 945 /* 946 * int pccbbintr_function(struct pccbb_softc *sc) 947 * 948 * This function calls each interrupt handler registered at the 949 * bridge. The interrupt handlers are called in registered order. 950 */ 951 int 952 pccbbintr_function(struct pccbb_softc *sc) 953 { 954 int retval = 0, val; 955 struct pccbb_intrhand_list *pil; 956 int s, splchanged; 957 958 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 959 /* 960 * XXX priority change. gross. I use if-else 961 * sentences instead of switch-case sentences in order 962 * to avoid duplicate case value error. More than one 963 * IPL_XXX may use the same value. It depends on the 964 * implementation. 965 */ 966 splchanged = 1; 967 #if 0 968 if (pil->pil_level == IPL_SERIAL) { 969 s = splserial(); 970 } else if (pil->pil_level == IPL_HIGH) { 971 #endif 972 if (pil->pil_level == IPL_HIGH) { 973 s = splhigh(); 974 } else if (pil->pil_level == IPL_CLOCK) { 975 s = splclock(); 976 } else if (pil->pil_level == IPL_AUDIO) { 977 s = splaudio(); 978 } else if (pil->pil_level == IPL_VM) { 979 s = splvm(); 980 } else if (pil->pil_level == IPL_TTY) { 981 s = spltty(); 982 #if 0 983 } else if (pil->pil_level == IPL_SOFTSERIAL) { 984 s = splsoftserial(); 985 #endif 986 } else if (pil->pil_level == IPL_NET) { 987 s = splnet(); 988 } else { 989 splchanged = 0; 990 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 991 } 992 993 val = (*pil->pil_func)(pil->pil_arg); 994 if (val != 0) 995 pil->pil_count.ec_count++; 996 997 if (splchanged != 0) { 998 splx(s); 999 } 1000 1001 retval = retval == 1 ? 1 : 1002 retval == 0 ? val : val != 0 ? val : retval; 1003 } 1004 1005 return retval; 1006 } 1007 1008 void 1009 pci113x_insert(void *arg) 1010 { 1011 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1012 u_int32_t sockevent, sockstate; 1013 1014 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1015 CB_SOCKET_EVENT); 1016 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1017 CB_SOCKET_STAT); 1018 1019 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1020 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1021 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1022 sc->sc_flags |= CBB_CARDEXIST; 1023 /* call pccard interrupt handler here */ 1024 if (sockstate & CB_SOCKET_STAT_16BIT) { 1025 /* 16-bit card found */ 1026 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1027 cardslot_event_throw(sc->sc_csc, 1028 CARDSLOT_EVENT_INSERTION_16); 1029 } else if (sockstate & CB_SOCKET_STAT_CB) { 1030 /* cardbus card found */ 1031 /* cardbus_attach_card(sc->sc_csc); */ 1032 cardslot_event_throw(sc->sc_csc, 1033 CARDSLOT_EVENT_INSERTION_CB); 1034 } else { 1035 /* who are you? */ 1036 } 1037 } else { 1038 timeout_add_msec(&sc->sc_ins_tmo, 100); 1039 } 1040 } 1041 1042 #define PCCBB_PCMCIA_OFFSET 0x800 1043 u_int8_t 1044 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1045 { 1046 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1047 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1048 1049 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1050 PCCBB_PCMCIA_OFFSET + reg); 1051 } 1052 1053 void 1054 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, int val) 1055 { 1056 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1057 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1058 1059 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1060 val); 1061 } 1062 1063 /* 1064 * int pccbb_ctrl(cardbus_chipset_tag_t, int) 1065 */ 1066 int 1067 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1068 { 1069 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1070 1071 switch (command) { 1072 case CARDBUS_CD: 1073 if (2 == pccbb_detect_card(sc)) { 1074 int retval = 0; 1075 int status = cb_detect_voltage(sc); 1076 if (PCCARD_VCC_5V & status) { 1077 retval |= CARDBUS_5V_CARD; 1078 } 1079 if (PCCARD_VCC_3V & status) { 1080 retval |= CARDBUS_3V_CARD; 1081 } 1082 if (PCCARD_VCC_XV & status) { 1083 retval |= CARDBUS_XV_CARD; 1084 } 1085 if (PCCARD_VCC_YV & status) { 1086 retval |= CARDBUS_YV_CARD; 1087 } 1088 return retval; 1089 } else { 1090 return 0; 1091 } 1092 break; 1093 case CARDBUS_RESET: 1094 return cb_reset(sc); 1095 break; 1096 case CARDBUS_IO_ENABLE: /* fallthrough */ 1097 case CARDBUS_IO_DISABLE: /* fallthrough */ 1098 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1099 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1100 case CARDBUS_BM_ENABLE: /* fallthrough */ 1101 case CARDBUS_BM_DISABLE: /* fallthrough */ 1102 return pccbb_cardenable(sc, command); 1103 break; 1104 } 1105 1106 return 0; 1107 } 1108 1109 /* 1110 * int pccbb_power(cardbus_chipset_tag_t, int) 1111 * This function returns true when it succeeds and returns false when 1112 * it fails. 1113 */ 1114 int 1115 pccbb_power(cardbus_chipset_tag_t ct, int command) 1116 { 1117 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1118 1119 u_int32_t status, sock_ctrl; 1120 bus_space_tag_t memt = sc->sc_base_memt; 1121 bus_space_handle_t memh = sc->sc_base_memh; 1122 1123 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1124 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1125 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1126 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1127 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1128 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1129 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1130 "UNKNOWN", 1131 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1132 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1133 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1134 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1135 "UNKNOWN", command)); 1136 1137 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1138 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1139 1140 switch (command & CARDBUS_VCCMASK) { 1141 case CARDBUS_VCC_UC: 1142 break; 1143 case CARDBUS_VCC_5V: 1144 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1145 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1146 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1147 } else { 1148 printf("%s: BAD voltage request: no 5 V card\n", 1149 sc->sc_dev.dv_xname); 1150 } 1151 break; 1152 case CARDBUS_VCC_3V: 1153 if (CB_SOCKET_STAT_3VCARD & status) { 1154 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1155 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1156 } else { 1157 printf("%s: BAD voltage request: no 3.3 V card\n", 1158 sc->sc_dev.dv_xname); 1159 } 1160 break; 1161 case CARDBUS_VCC_0V: 1162 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1163 break; 1164 default: 1165 return 0; /* power NEVER changed */ 1166 break; 1167 } 1168 1169 switch (command & CARDBUS_VPPMASK) { 1170 case CARDBUS_VPP_UC: 1171 break; 1172 case CARDBUS_VPP_0V: 1173 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1174 break; 1175 case CARDBUS_VPP_VCC: 1176 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1177 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1178 break; 1179 case CARDBUS_VPP_12V: 1180 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1181 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1182 break; 1183 } 1184 1185 #if 0 1186 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1187 #endif 1188 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1189 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1190 1191 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1192 printf 1193 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1194 sc->sc_dev.dv_xname, sock_ctrl, status); 1195 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1196 (command & CARDBUS_VCCMASK) == 1197 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1198 CARDBUS_VCCMASK) == 1199 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1200 CARDBUS_VCCMASK) == 1201 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1202 CARDBUS_VCCMASK) == 1203 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1204 CARDBUS_VCCMASK) == 1205 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1206 CARDBUS_VCCMASK) == 1207 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1208 (command & CARDBUS_VPPMASK) == 1209 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1210 CARDBUS_VPPMASK) == 1211 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1212 CARDBUS_VPPMASK) == 1213 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1214 CARDBUS_VPPMASK) == 1215 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1216 #if 0 1217 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1218 u_int32_t force = 1219 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1220 /* Reset Bad Vcc request */ 1221 force &= ~CB_SOCKET_FORCE_BADVCC; 1222 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1223 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1224 CB_SOCKET_STAT)); 1225 return 1; 1226 } 1227 #endif 1228 return 0; 1229 } 1230 1231 /* 1232 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1233 * time is 20 ms, some PC-Card bridge requires longer duration. 1234 */ 1235 delay(300 * 1000); 1236 1237 return 1; /* power changed correctly */ 1238 } 1239 1240 #if defined CB_PCMCIA_POLL 1241 struct cb_poll_str { 1242 void *arg; 1243 int (*func)(void *); 1244 int level; 1245 pccard_chipset_tag_t ct; 1246 int count; 1247 }; 1248 1249 static struct cb_poll_str cb_poll[10]; 1250 static int cb_poll_n = 0; 1251 static struct timeout cb_poll_timeout; 1252 1253 void cb_pcmcia_poll(void *arg); 1254 1255 void 1256 cb_pcmcia_poll(void *arg) 1257 { 1258 struct cb_poll_str *poll = arg; 1259 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1260 struct pccbb_softc *sc = psc->cpc_parent; 1261 int s; 1262 u_int32_t spsr; /* socket present-state reg */ 1263 1264 timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg); 1265 timeout_add(&cb_poll_timeout, hz / 10); 1266 switch (poll->level) { 1267 case IPL_NET: 1268 s = splnet(); 1269 break; 1270 case IPL_BIO: 1271 s = splbio(); 1272 break; 1273 case IPL_TTY: /* fallthrough */ 1274 default: 1275 s = spltty(); 1276 break; 1277 } 1278 1279 spsr = 1280 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1281 CB_SOCKET_STAT); 1282 1283 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1284 if (!(spsr & 0x40)) { /* CINT low */ 1285 #else 1286 if (1) { 1287 #endif 1288 if ((*poll->func) (poll->arg) == 1) { 1289 ++poll->count; 1290 printf("intr: reported from poller, 0x%x\n", spsr); 1291 #if defined LEVEL2 1292 } else { 1293 printf("intr: miss! 0x%x\n", spsr); 1294 #endif 1295 } 1296 } 1297 splx(s); 1298 } 1299 #endif /* defined CB_PCMCIA_POLL */ 1300 1301 /* 1302 * int pccbb_detect_card(struct pccbb_softc *sc) 1303 * return value: 0 if no card exists. 1304 * 1 if 16-bit card exists. 1305 * 2 if cardbus card exists. 1306 */ 1307 int 1308 pccbb_detect_card(struct pccbb_softc *sc) 1309 { 1310 bus_space_handle_t base_memh = sc->sc_base_memh; 1311 bus_space_tag_t base_memt = sc->sc_base_memt; 1312 u_int32_t sockstat = 1313 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1314 int retval = 0; 1315 1316 /* 1317 * The SCM Microsystems TI1225-based PCI-CardBus dock card that 1318 * ships with some Lucent WaveLAN cards has only one physical slot 1319 * but OpenBSD probes two. The phantom card in the second slot can 1320 * be ignored by punting on unsupported voltages. 1321 */ 1322 if (sockstat & CB_SOCKET_STAT_XVCARD) 1323 return 0; 1324 1325 /* CD1 and CD2 asserted */ 1326 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1327 /* card must be present */ 1328 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1329 /* NOTACARD DEASSERTED */ 1330 if (CB_SOCKET_STAT_CB & sockstat) { 1331 /* CardBus mode */ 1332 retval = 2; 1333 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1334 /* 16-bit mode */ 1335 retval = 1; 1336 } 1337 } 1338 } 1339 return retval; 1340 } 1341 1342 /* 1343 * int cb_reset(struct pccbb_softc *sc) 1344 * This function resets CardBus card. 1345 */ 1346 int 1347 cb_reset(struct pccbb_softc *sc) 1348 { 1349 /* 1350 * Reset Assert at least 20 ms 1351 * Some machines request longer duration. 1352 */ 1353 int reset_duration = (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1354 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1355 1356 /* Reset bit Assert (bit 6 at 0x3E) */ 1357 bcr |= CB_BCR_RESET_ENABLE; 1358 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1359 delay_ms(reset_duration, sc); 1360 1361 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1362 /* Reset bit Deassert (bit 6 at 0x3E) */ 1363 bcr &= ~CB_BCR_RESET_ENABLE; 1364 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1365 delay_ms(reset_duration, sc); 1366 } 1367 /* No card found on the slot. Keep Reset. */ 1368 return 1; 1369 } 1370 1371 /* 1372 * int cb_detect_voltage(struct pccbb_softc *sc) 1373 * This function detect card Voltage. 1374 */ 1375 int 1376 cb_detect_voltage(struct pccbb_softc *sc) 1377 { 1378 u_int32_t psr; /* socket present-state reg */ 1379 bus_space_tag_t iot = sc->sc_base_memt; 1380 bus_space_handle_t ioh = sc->sc_base_memh; 1381 int vol = PCCARD_VCC_UKN; /* set 0 */ 1382 1383 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1384 1385 if (0x400u & psr) { 1386 vol |= PCCARD_VCC_5V; 1387 } 1388 if (0x800u & psr) { 1389 vol |= PCCARD_VCC_3V; 1390 } 1391 1392 return vol; 1393 } 1394 1395 int 1396 cbbprint(void *aux, const char *pcic) 1397 { 1398 /* 1399 struct cbslot_attach_args *cba = aux; 1400 1401 if (cba->cba_slot >= 0) { 1402 printf(" slot %d", cba->cba_slot); 1403 } 1404 */ 1405 return UNCONF; 1406 } 1407 1408 /* 1409 * int pccbb_cardenable(struct pccbb_softc *sc, int function) 1410 * This function enables and disables the card 1411 */ 1412 int 1413 pccbb_cardenable(struct pccbb_softc *sc, int function) 1414 { 1415 u_int32_t command = 1416 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1417 1418 DPRINTF(("pccbb_cardenable:")); 1419 switch (function) { 1420 case CARDBUS_IO_ENABLE: 1421 command |= PCI_COMMAND_IO_ENABLE; 1422 break; 1423 case CARDBUS_IO_DISABLE: 1424 command &= ~PCI_COMMAND_IO_ENABLE; 1425 break; 1426 case CARDBUS_MEM_ENABLE: 1427 command |= PCI_COMMAND_MEM_ENABLE; 1428 break; 1429 case CARDBUS_MEM_DISABLE: 1430 command &= ~PCI_COMMAND_MEM_ENABLE; 1431 break; 1432 case CARDBUS_BM_ENABLE: 1433 command |= PCI_COMMAND_MASTER_ENABLE; 1434 break; 1435 case CARDBUS_BM_DISABLE: 1436 command &= ~PCI_COMMAND_MASTER_ENABLE; 1437 break; 1438 default: 1439 return 0; 1440 } 1441 1442 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1443 DPRINTF((" command reg 0x%x\n", command)); 1444 return 1; 1445 } 1446 1447 /* 1448 * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1449 * int irq, 1450 * int level, 1451 * int (* func)(void *), 1452 * void *arg, 1453 * const char *name) 1454 * 1455 * This function registers an interrupt handler at the bridge, in 1456 * order not to call the interrupt handlers of child devices when 1457 * a card-deletion interrupt occurs. 1458 * 1459 * The arguments irq is not used because pccbb selects intr vector. 1460 */ 1461 void * 1462 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1463 int (*func)(void *), void *arg, const char *name) 1464 { 1465 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1466 1467 return pccbb_intr_establish(sc, irq, level, func, arg, name); 1468 } 1469 1470 1471 /* 1472 * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1473 * void *ih) 1474 * 1475 * This function removes an interrupt handler pointed by ih. 1476 */ 1477 void 1478 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1479 { 1480 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1481 1482 pccbb_intr_disestablish(sc, ih); 1483 } 1484 1485 1486 /* 1487 * void *pccbb_intr_establish(struct pccbb_softc *sc, 1488 * int irq, 1489 * int level, 1490 * int (* func)(void *), 1491 * void *arg, 1492 * const char *name) 1493 * 1494 * This function registers an interrupt handler at the bridge, in 1495 * order not to call the interrupt handlers of child devices when 1496 * a card-deletion interrupt occurs. 1497 * 1498 * The arguments irq and level are not used. 1499 */ 1500 void * 1501 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1502 int (*func)(void *), void *arg, const char *name) 1503 { 1504 struct pccbb_intrhand_list *pil, *newpil; 1505 pcireg_t reg; 1506 1507 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1508 1509 if (sc->sc_pil == NULL) { 1510 /* initialize bridge intr routing */ 1511 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1512 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1513 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1514 1515 switch (sc->sc_chipset) { 1516 case CB_TI113X: 1517 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1518 /* functional intr enabled */ 1519 reg |= PCI113X_CBCTRL_PCI_INTR; 1520 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1521 break; 1522 default: 1523 break; 1524 } 1525 } 1526 1527 /* 1528 * Allocate a room for interrupt handler structure. 1529 */ 1530 newpil = (struct pccbb_intrhand_list *) 1531 malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK); 1532 1533 newpil->pil_func = func; 1534 newpil->pil_arg = arg; 1535 newpil->pil_level = level; 1536 evcount_attach(&newpil->pil_count, name, &sc->sc_intrline); 1537 newpil->pil_next = NULL; 1538 1539 if (sc->sc_pil == NULL) { 1540 sc->sc_pil = newpil; 1541 } else { 1542 for (pil = sc->sc_pil; pil->pil_next != NULL; 1543 pil = pil->pil_next); 1544 pil->pil_next = newpil; 1545 } 1546 1547 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1548 1549 return newpil; 1550 } 1551 1552 /* 1553 * void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1554 * void *ih) 1555 * 1556 * This function removes an interrupt handler pointed by ih. 1557 */ 1558 void 1559 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1560 { 1561 struct pccbb_intrhand_list *pil, **pil_prev; 1562 pcireg_t reg; 1563 1564 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1565 1566 pil_prev = &sc->sc_pil; 1567 1568 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1569 if (pil == ih) { 1570 evcount_detach(&pil->pil_count); 1571 *pil_prev = pil->pil_next; 1572 free(pil, M_DEVBUF); 1573 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1574 break; 1575 } 1576 pil_prev = &pil->pil_next; 1577 } 1578 1579 if (sc->sc_pil == NULL) { 1580 /* No interrupt handlers */ 1581 1582 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1583 1584 /* stop routing PCI intr */ 1585 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1586 reg |= CB_BCR_INTR_IREQ_ENABLE; 1587 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1588 1589 switch (sc->sc_chipset) { 1590 case CB_TI113X: 1591 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1592 /* functional intr disabled */ 1593 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1594 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1595 break; 1596 default: 1597 break; 1598 } 1599 } 1600 } 1601 1602 #if defined SHOW_REGS 1603 void 1604 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1605 bus_space_handle_t memh) 1606 { 1607 int i; 1608 printf("PCI config regs:"); 1609 for (i = 0; i < 0x50; i += 4) { 1610 if (i % 16 == 0) { 1611 printf("\n 0x%02x:", i); 1612 } 1613 printf(" %08x", pci_conf_read(pc, tag, i)); 1614 } 1615 for (i = 0x80; i < 0xb0; i += 4) { 1616 if (i % 16 == 0) { 1617 printf("\n 0x%02x:", i); 1618 } 1619 printf(" %08x", pci_conf_read(pc, tag, i)); 1620 } 1621 1622 if (memh == 0) { 1623 printf("\n"); 1624 return; 1625 } 1626 1627 printf("\nsocket regs:"); 1628 for (i = 0; i <= 0x10; i += 0x04) { 1629 printf(" %08x", bus_space_read_4(memt, memh, i)); 1630 } 1631 printf("\nExCA regs:"); 1632 for (i = 0; i < 0x08; ++i) { 1633 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1634 } 1635 printf("\n"); 1636 return; 1637 } 1638 #endif 1639 1640 /* 1641 * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1642 * bus_addr_t start, bus_size_t size, 1643 * bus_size_t align, 1644 * struct pcmcia_io_handle *pcihp 1645 * 1646 * This function only allocates I/O region for pccard. This function 1647 * never maps the allocated region to pccard I/O area. 1648 * 1649 * XXX: The interface of this function is not very good, I believe. 1650 */ 1651 int 1652 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1653 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1654 { 1655 struct pcic_handle *ph = (struct pcic_handle *)pch; 1656 bus_addr_t ioaddr; 1657 int flags = 0; 1658 bus_space_tag_t iot; 1659 bus_space_handle_t ioh; 1660 bus_addr_t mask; 1661 rbus_tag_t rb; 1662 1663 if (align == 0) { 1664 align = size; /* XXX: funny??? */ 1665 } 1666 1667 if (start != 0) { 1668 /* XXX: assume all card decode lower 10 bits by its hardware */ 1669 mask = 0x3ff; 1670 /* enforce to use only masked address */ 1671 start &= mask; 1672 } else { 1673 /* 1674 * calculate mask: 1675 * 1. get the most significant bit of size (call it msb). 1676 * 2. compare msb with the value of size. 1677 * 3. if size is larger, shift msb left once. 1678 * 4. obtain mask value to decrement msb. 1679 */ 1680 bus_size_t size_tmp = size; 1681 int shifts = 0; 1682 1683 while (size_tmp) { 1684 ++shifts; 1685 size_tmp >>= 1; 1686 } 1687 mask = (1 << shifts); 1688 if (mask < size) { 1689 mask <<= 1; 1690 } 1691 mask--; 1692 } 1693 1694 /* 1695 * Allocate some arbitrary I/O space. 1696 */ 1697 1698 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1699 1700 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1701 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1702 return 1; 1703 } 1704 1705 pcihp->iot = iot; 1706 pcihp->ioh = ioh; 1707 pcihp->addr = ioaddr; 1708 pcihp->size = size; 1709 pcihp->flags = flags; 1710 1711 return 0; 1712 } 1713 1714 /* 1715 * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1716 * struct pcmcia_io_handle *pcihp) 1717 * 1718 * This function only frees I/O region for pccard. 1719 * 1720 * XXX: The interface of this function is not very good, I believe. 1721 */ 1722 void 1723 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1724 struct pcmcia_io_handle *pcihp) 1725 { 1726 bus_space_handle_t ioh = pcihp->ioh; 1727 bus_size_t size = pcihp->size; 1728 1729 struct pccbb_softc *sc = 1730 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1731 rbus_tag_t rb = sc->sc_rbus_iot; 1732 1733 rbus_space_free(rb, ioh, size, NULL); 1734 } 1735 1736 /* 1737 * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1738 * bus_addr_t offset, bus_size_t size, 1739 * struct pcmcia_io_handle *pcihp, 1740 * int *windowp) 1741 * 1742 * This function maps the allocated I/O region to pccard. This function 1743 * never allocates any I/O region for pccard I/O area. I don't 1744 * understand why the original authors of pcmciabus separated alloc and 1745 * map. I believe the two must be unite. 1746 * 1747 * XXX: no wait timing control? 1748 */ 1749 int 1750 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 1751 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 1752 { 1753 struct pcic_handle *ph = (struct pcic_handle *)pch; 1754 bus_addr_t ioaddr = pcihp->addr + offset; 1755 int i, win; 1756 #if defined CBB_DEBUG 1757 static char *width_names[] = { "dynamic", "io8", "io16" }; 1758 #endif 1759 1760 /* Sanity check I/O handle. */ 1761 1762 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1763 panic("pccbb_pcmcia_io_map iot is bogus"); 1764 } 1765 1766 /* XXX Sanity check offset/size. */ 1767 1768 win = -1; 1769 for (i = 0; i < PCIC_IO_WINS; i++) { 1770 if ((ph->ioalloc & (1 << i)) == 0) { 1771 win = i; 1772 ph->ioalloc |= (1 << i); 1773 break; 1774 } 1775 } 1776 1777 if (win == -1) { 1778 return 1; 1779 } 1780 1781 *windowp = win; 1782 1783 /* XXX this is pretty gross */ 1784 1785 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1786 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1787 1788 /* XXX wtf is this doing here? */ 1789 1790 #if 0 1791 printf(" port 0x%lx", (u_long) ioaddr); 1792 if (size > 1) { 1793 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1794 } 1795 #endif 1796 1797 ph->io[win].addr = ioaddr; 1798 ph->io[win].size = size; 1799 ph->io[win].width = width; 1800 1801 /* actual dirty register-value changing in the function below. */ 1802 pccbb_pcmcia_do_io_map(ph, win); 1803 1804 return 0; 1805 } 1806 1807 /* 1808 * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1809 * 1810 * This function changes register-value to map I/O region for pccard. 1811 */ 1812 void 1813 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 1814 { 1815 static u_int8_t pcic_iowidth[3] = { 1816 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1817 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1818 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1819 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1820 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1821 }; 1822 1823 #define PCIC_SIA_START_LOW 0 1824 #define PCIC_SIA_START_HIGH 1 1825 #define PCIC_SIA_STOP_LOW 2 1826 #define PCIC_SIA_STOP_HIGH 3 1827 1828 int regbase_win = 0x8 + win * 0x04; 1829 u_int8_t ioctl, enable; 1830 1831 DPRINTF( 1832 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1833 win, (long)ph->io[win].addr, (long)ph->io[win].size, 1834 ph->io[win].width * 8)); 1835 1836 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1837 ph->io[win].addr & 0xff); 1838 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1839 (ph->io[win].addr >> 8) & 0xff); 1840 1841 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1842 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1843 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1844 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1845 1846 ioctl = Pcic_read(ph, PCIC_IOCTL); 1847 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1848 switch (win) { 1849 case 0: 1850 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1851 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 1852 PCIC_IOCTL_IO0_DATASIZE_MASK); 1853 ioctl |= pcic_iowidth[ph->io[win].width]; 1854 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1855 break; 1856 case 1: 1857 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1858 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 1859 PCIC_IOCTL_IO1_DATASIZE_MASK); 1860 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1861 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1862 break; 1863 } 1864 Pcic_write(ph, PCIC_IOCTL, ioctl); 1865 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1866 #if defined CBB_DEBUG 1867 { 1868 u_int8_t start_low = 1869 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1870 u_int8_t start_high = 1871 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1872 u_int8_t stop_low = 1873 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1874 u_int8_t stop_high = 1875 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1876 printf 1877 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1878 start_low, start_high, stop_low, stop_high, ioctl, enable); 1879 } 1880 #endif 1881 } 1882 1883 /* 1884 * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1885 * 1886 * This function unmaps I/O region. No return value. 1887 */ 1888 void 1889 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 1890 { 1891 struct pcic_handle *ph = (struct pcic_handle *)pch; 1892 int reg; 1893 1894 if (win >= PCIC_IO_WINS || win < 0) { 1895 panic("pccbb_pcmcia_io_unmap: window out of range"); 1896 } 1897 1898 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1899 switch (win) { 1900 case 0: 1901 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1902 break; 1903 case 1: 1904 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1905 break; 1906 } 1907 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 1908 1909 ph->ioalloc &= ~(1 << win); 1910 } 1911 1912 /* 1913 * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1914 * 1915 * This function enables the card. All information is stored in 1916 * the first argument, pcmcia_chipset_handle_t. 1917 */ 1918 void 1919 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1920 { 1921 int i; 1922 1923 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 1924 Pcic_read(ph, PCIC_IF_STATUS))); 1925 1926 for (i = 0; i < 10000; i++) { 1927 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 1928 return; 1929 } 1930 delay(500); 1931 #ifdef CBB_DEBUG 1932 if ((i > 5000) && (i % 100 == 99)) 1933 printf("."); 1934 #endif 1935 } 1936 1937 #ifdef DIAGNOSTIC 1938 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1939 Pcic_read(ph, PCIC_IF_STATUS)); 1940 #endif 1941 } 1942 1943 /* 1944 * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 1945 * 1946 * This function enables the card. All information is stored in 1947 * the first argument, pcmcia_chipset_handle_t. 1948 */ 1949 void 1950 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 1951 { 1952 struct pcic_handle *ph = (struct pcic_handle *)pch; 1953 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 1954 int cardtype, win; 1955 u_int8_t power, intr; 1956 pcireg_t spsr; 1957 int voltage; 1958 1959 /* this bit is mostly stolen from pcic_attach_card */ 1960 1961 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 1962 1963 /* get card Vcc info */ 1964 1965 spsr = 1966 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1967 CB_SOCKET_STAT); 1968 if (spsr & CB_SOCKET_STAT_5VCARD) { 1969 DPRINTF(("5V card\n")); 1970 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 1971 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 1972 DPRINTF(("3V card\n")); 1973 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 1974 } else { 1975 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 1976 return; 1977 } 1978 1979 /* disable socket i/o: negate output enable bit */ 1980 1981 power = 0; 1982 Pcic_write(ph, PCIC_PWRCTL, power); 1983 1984 /* power down the socket to reset it, clear the card reset pin */ 1985 1986 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 1987 1988 /* 1989 * wait 200ms until power fails (Tpf). Then, wait 100ms since 1990 * we are changing Vcc (Toff). 1991 */ 1992 /* delay(300*1000); too much */ 1993 1994 /* assert reset bit */ 1995 intr = Pcic_read(ph, PCIC_INTR); 1996 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 1997 Pcic_write(ph, PCIC_INTR, intr); 1998 1999 /* Power up the socket. */ 2000 power = Pcic_read(ph, PCIC_PWRCTL); 2001 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 2002 pccbb_power((cardbus_chipset_tag_t)sc, voltage); 2003 2004 /* Now output enable */ 2005 power = Pcic_read(ph, PCIC_PWRCTL); 2006 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2007 2008 /* 2009 * hold RESET at least 10us. 2010 */ 2011 delay(10); 2012 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2013 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2014 2015 /* clear the reset flag */ 2016 2017 intr |= PCIC_INTR_RESET; 2018 Pcic_write(ph, PCIC_INTR, intr); 2019 2020 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2021 2022 delay(20000); 2023 2024 /* wait for the chip to finish initializing */ 2025 2026 pccbb_pcmcia_wait_ready(ph); 2027 2028 /* zero out the address windows */ 2029 2030 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2031 2032 /* set the card type */ 2033 2034 cardtype = pcmcia_card_gettype(ph->pcmcia); 2035 2036 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2037 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2038 Pcic_write(ph, PCIC_INTR, intr); 2039 2040 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2041 ph->ph_parent->dv_xname, ph->sock, 2042 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2043 2044 /* reinstall all the memory and io mappings */ 2045 2046 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2047 if (ph->memalloc & (1 << win)) { 2048 pccbb_pcmcia_do_mem_map(ph, win); 2049 } 2050 } 2051 2052 for (win = 0; win < PCIC_IO_WINS; ++win) { 2053 if (ph->ioalloc & (1 << win)) { 2054 pccbb_pcmcia_do_io_map(ph, win); 2055 } 2056 } 2057 } 2058 2059 /* 2060 * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2061 * 2062 * This function disables the card. All information is stored in 2063 * the first argument, pcmcia_chipset_handle_t. 2064 */ 2065 void 2066 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2067 { 2068 struct pcic_handle *ph = (struct pcic_handle *)pch; 2069 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2070 u_int8_t power, intr; 2071 2072 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2073 2074 /* reset signal asserting... */ 2075 2076 intr = Pcic_read(ph, PCIC_INTR); 2077 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2078 Pcic_write(ph, PCIC_INTR, intr); 2079 delay(2 * 1000); 2080 2081 /* power down the socket */ 2082 power = Pcic_read(ph, PCIC_PWRCTL); 2083 power &= ~PCIC_PWRCTL_OE; 2084 Pcic_write(ph, PCIC_PWRCTL, power); 2085 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2086 /* 2087 * wait 300ms until power fails (Tpf). 2088 */ 2089 delay(300 * 1000); 2090 } 2091 2092 /* 2093 * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2094 * 2095 * This function detects whether a card is in the slot or not. 2096 * If a card is inserted, return 1. Otherwise, return 0. 2097 */ 2098 int 2099 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2100 { 2101 struct pcic_handle *ph = (struct pcic_handle *)pch; 2102 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2103 2104 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2105 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2106 } 2107 2108 /* 2109 * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2110 * bus_size_t size, 2111 * struct pcmcia_mem_handle *pcmhp) 2112 * 2113 * This function only allocates memory region for pccard. This 2114 * function never maps the allocated region to pccard memory area. 2115 * 2116 * XXX: Why the argument of start address is not in? 2117 */ 2118 int 2119 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2120 struct pcmcia_mem_handle *pcmhp) 2121 { 2122 struct pcic_handle *ph = (struct pcic_handle *)pch; 2123 bus_space_handle_t memh; 2124 bus_addr_t addr; 2125 bus_size_t sizepg; 2126 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2127 rbus_tag_t rb; 2128 2129 /* out of sc->memh, allocate as many pages as necessary */ 2130 2131 /* convert size to PCIC pages */ 2132 /* 2133 * This is not enough; when the requested region is on the page 2134 * boundaries, this may calculate wrong result. 2135 */ 2136 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2137 #if 0 2138 if (sizepg > PCIC_MAX_MEM_PAGES) { 2139 return 1; 2140 } 2141 #endif 2142 2143 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2144 return 1; 2145 } 2146 2147 addr = 0; /* XXX gcc -Wuninitialized */ 2148 2149 rb = sc->sc_rbus_memt; 2150 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2151 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2152 &addr, &memh)) { 2153 return 1; 2154 } 2155 2156 DPRINTF( 2157 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2158 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2159 2160 pcmhp->memt = sc->sc_memt; 2161 pcmhp->memh = memh; 2162 pcmhp->addr = addr; 2163 pcmhp->size = size; 2164 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2165 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2166 pcmhp->mhandle = 0; 2167 /* No offset??? Funny. */ 2168 2169 return 0; 2170 } 2171 2172 /* 2173 * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2174 * struct pcmcia_mem_handle *pcmhp) 2175 * 2176 * This function release the memory space allocated by the function 2177 * pccbb_pcmcia_mem_alloc(). 2178 */ 2179 void 2180 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2181 struct pcmcia_mem_handle *pcmhp) 2182 { 2183 struct pcic_handle *ph = (struct pcic_handle *)pch; 2184 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2185 2186 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2187 } 2188 2189 /* 2190 * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2191 * 2192 * This function release the memory space allocated by the function 2193 * pccbb_pcmcia_mem_alloc(). 2194 */ 2195 void 2196 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2197 { 2198 int regbase_win; 2199 bus_addr_t phys_addr; 2200 bus_addr_t phys_end; 2201 2202 #define PCIC_SMM_START_LOW 0 2203 #define PCIC_SMM_START_HIGH 1 2204 #define PCIC_SMM_STOP_LOW 2 2205 #define PCIC_SMM_STOP_HIGH 3 2206 #define PCIC_CMA_LOW 4 2207 #define PCIC_CMA_HIGH 5 2208 2209 u_int8_t start_low, start_high = 0; 2210 u_int8_t stop_low, stop_high; 2211 u_int8_t off_low, off_high; 2212 u_int8_t mem_window; 2213 int reg; 2214 2215 regbase_win = 0x10 + win * 0x08; 2216 2217 phys_addr = ph->mem[win].addr; 2218 phys_end = phys_addr + ph->mem[win].size; 2219 2220 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2221 phys_addr, phys_end, ph->mem[win].offset)); 2222 2223 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2224 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2225 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2226 2227 /* bit 19:12 */ 2228 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2229 /* bit 23:20 and bit 7 on */ 2230 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2231 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2232 /* bit 31:24, for 32-bit address */ 2233 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2234 2235 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2236 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2237 2238 if (((struct pccbb_softc *)ph-> 2239 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2240 Pcic_write(ph, 0x40 + win, mem_window); 2241 } 2242 2243 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2244 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2245 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2246 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2247 2248 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2249 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2250 2251 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2252 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2253 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2254 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2255 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2256 2257 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2258 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2259 2260 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2261 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2262 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2263 2264 #if defined CBB_DEBUG 2265 { 2266 int r1, r2, r3, r4, r5, r6, r7 = 0; 2267 2268 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2269 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2270 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2271 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2272 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2273 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2274 if (((struct pccbb_softc *)(ph-> 2275 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2276 r7 = Pcic_read(ph, 0x40 + win); 2277 } 2278 2279 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2280 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2281 if (((struct pccbb_softc *)(ph-> 2282 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2283 DPRINTF((" %02x", r7)); 2284 } 2285 DPRINTF(("\n")); 2286 } 2287 #endif 2288 } 2289 2290 /* 2291 * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2292 * bus_addr_t card_addr, bus_size_t size, 2293 * struct pcmcia_mem_handle *pcmhp, 2294 * bus_size_t *offsetp, int *windowp) 2295 * 2296 * This function maps memory space allocated by the function 2297 * pccbb_pcmcia_mem_alloc(). 2298 */ 2299 int 2300 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2301 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2302 bus_size_t *offsetp, int *windowp) 2303 { 2304 struct pcic_handle *ph = (struct pcic_handle *)pch; 2305 bus_addr_t busaddr; 2306 long card_offset; 2307 int win; 2308 2309 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2310 if ((ph->memalloc & (1 << win)) == 0) { 2311 ph->memalloc |= (1 << win); 2312 break; 2313 } 2314 } 2315 2316 if (win == PCIC_MEM_WINS) { 2317 return 1; 2318 } 2319 2320 *windowp = win; 2321 2322 /* XXX this is pretty gross */ 2323 2324 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2325 panic("pccbb_pcmcia_mem_map memt is bogus"); 2326 } 2327 2328 busaddr = pcmhp->addr; 2329 2330 /* 2331 * compute the address offset to the pcmcia address space for the 2332 * pcic. this is intentionally signed. The masks and shifts below 2333 * will cause TRT to happen in the pcic registers. Deal with making 2334 * sure the address is aligned, and return the alignment offset. 2335 */ 2336 2337 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2338 card_addr -= *offsetp; 2339 2340 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2341 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2342 (u_long) card_addr)); 2343 2344 /* 2345 * include the offset in the size, and decrement size by one, since 2346 * the hw wants start/stop 2347 */ 2348 size += *offsetp - 1; 2349 2350 card_offset = (((long)card_addr) - ((long)busaddr)); 2351 2352 ph->mem[win].addr = busaddr; 2353 ph->mem[win].size = size; 2354 ph->mem[win].offset = card_offset; 2355 ph->mem[win].kind = kind; 2356 2357 pccbb_pcmcia_do_mem_map(ph, win); 2358 2359 return 0; 2360 } 2361 2362 /* 2363 * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2364 * int window) 2365 * 2366 * This function unmaps memory space which mapped by the function 2367 * pccbb_pcmcia_mem_map(). 2368 */ 2369 void 2370 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2371 { 2372 struct pcic_handle *ph = (struct pcic_handle *)pch; 2373 int reg; 2374 2375 if (window >= PCIC_MEM_WINS) { 2376 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2377 } 2378 2379 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2380 reg &= ~(1 << window); 2381 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2382 2383 ph->memalloc &= ~(1 << window); 2384 } 2385 2386 #if defined PCCBB_PCMCIA_POLL 2387 struct pccbb_poll_str { 2388 void *arg; 2389 int (*func)(void *); 2390 int level; 2391 struct pcic_handle *ph; 2392 int count; 2393 int num; 2394 }; 2395 2396 static struct pccbb_poll_str pccbb_poll[10]; 2397 static int pccbb_poll_n = 0; 2398 static struct timeout pccbb_poll_timeout; 2399 2400 void pccbb_pcmcia_poll(void *arg); 2401 2402 void 2403 pccbb_pcmcia_poll(void *arg) 2404 { 2405 struct pccbb_poll_str *poll = arg; 2406 struct pcic_handle *ph = poll->ph; 2407 struct pccbb_softc *sc = ph->sc; 2408 int s; 2409 u_int32_t spsr; /* socket present-state reg */ 2410 2411 timeout_set(&pccbb_poll_timeout, pccbb_pcmcia_poll, arg); 2412 timeout_add_sec(&pccbb_poll_timeout, 2); 2413 switch (poll->level) { 2414 case IPL_NET: 2415 s = splnet(); 2416 break; 2417 case IPL_BIO: 2418 s = splbio(); 2419 break; 2420 case IPL_TTY: /* fallthrough */ 2421 default: 2422 s = spltty(); 2423 break; 2424 } 2425 2426 spsr = 2427 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2428 CB_SOCKET_STAT); 2429 2430 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2431 if (!(spsr & 0x40)) /* CINT low */ 2432 #else 2433 if (1) 2434 #endif 2435 { 2436 if ((*poll->func) (poll->arg) > 0) { 2437 ++poll->count; 2438 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2439 #if defined LEVEL2 2440 } else { 2441 printf("intr: miss! 0x%x\n", spsr); 2442 #endif 2443 } 2444 } 2445 splx(s); 2446 } 2447 #endif /* defined CB_PCMCIA_POLL */ 2448 2449 /* 2450 * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2451 * struct pcmcia_function *pf, 2452 * int ipl, 2453 * int (*func)(void *), 2454 * void *arg); 2455 * 2456 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2457 */ 2458 void * 2459 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2460 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg, 2461 char *xname) 2462 { 2463 struct pcic_handle *ph = (struct pcic_handle *)pch; 2464 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2465 2466 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2467 /* what should I do? */ 2468 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2469 DPRINTF( 2470 ("%s does not provide edge nor pulse interrupt\n", 2471 sc->sc_dev.dv_xname)); 2472 return NULL; 2473 } 2474 /* 2475 * XXX Noooooo! The interrupt flag must set properly!! 2476 * dumb pcmcia driver!! 2477 */ 2478 } 2479 2480 return pccbb_intr_establish(sc, -1, ipl, func, arg, xname); 2481 } 2482 2483 /* 2484 * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2485 * void *ih) 2486 * 2487 * This function disables PC-Card interrupt. 2488 */ 2489 void 2490 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2491 { 2492 struct pcic_handle *ph = (struct pcic_handle *)pch; 2493 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2494 2495 pccbb_intr_disestablish(sc, ih); 2496 } 2497 2498 const char * 2499 pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t pch, void *ih) 2500 { 2501 if (ih == NULL) 2502 return "couldn't establish interrupt"; 2503 else 2504 return ""; /* card shares interrupt of the bridge */ 2505 } 2506 2507 /* 2508 * int 2509 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2510 * bus_addr_t addr, bus_size_t size, 2511 * bus_addr_t mask, bus_size_t align, 2512 * int flags, bus_addr_t *addrp; 2513 * bus_space_handle_t *bshp) 2514 * 2515 * This function allocates a portion of memory or io space for 2516 * clients. This function is called from CardBus card drivers. 2517 */ 2518 int 2519 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2520 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2521 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2522 { 2523 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2524 2525 DPRINTF( 2526 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2527 addr, size, mask, align)); 2528 2529 align = max(align, 4); 2530 mask = max(mask, (4 - 1)); 2531 if (rb->rb_bt == sc->sc_memt) { 2532 align = max(align, 0x1000); 2533 mask = max(mask, (0x1000 - 1)); 2534 } 2535 2536 if (rb->rb_bt == sc->sc_iot) { 2537 /* XXX: hack for avoiding ISA image */ 2538 if (mask < 0x0100) { 2539 mask = 0x3ff; 2540 addr = 0x300; 2541 } 2542 } 2543 2544 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2545 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2546 return 1; 2547 } 2548 2549 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2550 2551 return 0; 2552 } 2553 2554 /* 2555 * int 2556 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2557 * bus_space_handle_t *bshp, bus_size_t size); 2558 * 2559 * This function is called from CardBus card drivers. 2560 */ 2561 int 2562 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2563 bus_space_handle_t bsh, bus_size_t size) 2564 { 2565 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2566 bus_space_tag_t bt = rb->rb_bt; 2567 2568 pccbb_close_win(sc, bt, bsh, size); 2569 2570 if (bt == sc->sc_memt) { 2571 } else if (bt == sc->sc_iot) { 2572 } else { 2573 return 1; 2574 /* XXX: panic here? */ 2575 } 2576 2577 return rbus_space_free(rb, bsh, size, NULL); 2578 } 2579 2580 int 2581 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2582 bus_size_t size, bus_space_handle_t bsh, int flags) 2583 { 2584 struct pccbb_win_chain_head *head; 2585 bus_addr_t align; 2586 2587 head = &sc->sc_iowindow; 2588 align = 0x04; 2589 if (sc->sc_memt == bst) { 2590 head = &sc->sc_memwindow; 2591 align = 0x1000; 2592 DPRINTF(("using memory window, %x %x %x\n\n", 2593 sc->sc_iot, sc->sc_memt, bst)); 2594 } 2595 2596 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2597 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2598 sc->sc_dev.dv_xname, 2599 (head == &sc->sc_memwindow) ? "mem" : "io"); 2600 } 2601 pccbb_winset(align, sc, bst); 2602 2603 return 0; 2604 } 2605 2606 int 2607 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2608 bus_space_handle_t bsh, bus_size_t size) 2609 { 2610 struct pccbb_win_chain_head *head; 2611 bus_addr_t align; 2612 2613 head = &sc->sc_iowindow; 2614 align = 0x04; 2615 if (sc->sc_memt == bst) { 2616 head = &sc->sc_memwindow; 2617 align = 0x1000; 2618 } 2619 2620 if (pccbb_winlist_delete(head, bsh, size)) { 2621 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2622 sc->sc_dev.dv_xname, 2623 (head == &sc->sc_memwindow) ? "mem" : "io"); 2624 } 2625 pccbb_winset(align, sc, bst); 2626 2627 return 0; 2628 } 2629 2630 int 2631 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2632 bus_size_t size, bus_space_handle_t bsh, int flags) 2633 { 2634 struct pccbb_win_chain *chainp, *elem; 2635 2636 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2637 M_NOWAIT)) == NULL) 2638 return (1); /* fail */ 2639 2640 elem->wc_start = start; 2641 elem->wc_end = start + (size - 1); 2642 elem->wc_handle = bsh; 2643 elem->wc_flags = flags; 2644 2645 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2646 chainp = TAILQ_NEXT(chainp, wc_list)) { 2647 if (chainp->wc_end < start) 2648 continue; 2649 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2650 return (0); 2651 } 2652 2653 TAILQ_INSERT_TAIL(head, elem, wc_list); 2654 return (0); 2655 } 2656 2657 int 2658 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2659 bus_size_t size) 2660 { 2661 struct pccbb_win_chain *chainp; 2662 2663 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2664 chainp = TAILQ_NEXT(chainp, wc_list)) { 2665 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 2666 continue; 2667 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2668 printf("pccbb_winlist_delete: window 0x%lx size " 2669 "inconsistent: 0x%lx, 0x%lx\n", 2670 chainp->wc_start, 2671 chainp->wc_end - chainp->wc_start, 2672 size - 1); 2673 return 1; 2674 } 2675 2676 TAILQ_REMOVE(head, chainp, wc_list); 2677 free(chainp, M_DEVBUF); 2678 2679 return 0; 2680 } 2681 2682 return 1; /* fail: no candidate to remove */ 2683 } 2684 2685 void 2686 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 2687 { 2688 pci_chipset_tag_t pc; 2689 pcitag_t tag; 2690 bus_addr_t mask = ~(align - 1); 2691 struct { 2692 pcireg_t win_start; 2693 pcireg_t win_limit; 2694 int win_flags; 2695 } win[2]; 2696 struct pccbb_win_chain *chainp; 2697 int offs; 2698 2699 win[0].win_start = win[1].win_start = 0xffffffff; 2700 win[0].win_limit = win[1].win_limit = 0; 2701 win[0].win_flags = win[1].win_flags = 0; 2702 2703 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2704 offs = PCI_CB_IOBASE0; 2705 if (sc->sc_memt == bst) { 2706 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2707 offs = PCI_CB_MEMBASE0; 2708 } 2709 2710 if (chainp != NULL) { 2711 win[0].win_start = chainp->wc_start & mask; 2712 win[0].win_limit = chainp->wc_end & mask; 2713 win[0].win_flags = chainp->wc_flags; 2714 chainp = TAILQ_NEXT(chainp, wc_list); 2715 } 2716 2717 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2718 if (win[1].win_start == 0xffffffff) { 2719 /* window 1 is not used */ 2720 if ((win[0].win_flags == chainp->wc_flags) && 2721 (win[0].win_limit + align >= 2722 (chainp->wc_start & mask))) { 2723 /* concatenate */ 2724 win[0].win_limit = chainp->wc_end & mask; 2725 } else { 2726 /* make new window */ 2727 win[1].win_start = chainp->wc_start & mask; 2728 win[1].win_limit = chainp->wc_end & mask; 2729 win[1].win_flags = chainp->wc_flags; 2730 } 2731 continue; 2732 } 2733 2734 /* Both windows are engaged. */ 2735 if (win[0].win_flags == win[1].win_flags) { 2736 /* same flags */ 2737 if (win[0].win_flags == chainp->wc_flags) { 2738 if (win[1].win_start - (win[0].win_limit + 2739 align) < 2740 (chainp->wc_start & mask) - 2741 ((chainp->wc_end & mask) + align)) { 2742 /* 2743 * merge window 0 and 1, and set win1 2744 * to chainp 2745 */ 2746 win[0].win_limit = win[1].win_limit; 2747 win[1].win_start = 2748 chainp->wc_start & mask; 2749 win[1].win_limit = 2750 chainp->wc_end & mask; 2751 } else { 2752 win[1].win_limit = 2753 chainp->wc_end & mask; 2754 } 2755 } else { 2756 /* different flags */ 2757 2758 /* concatenate win0 and win1 */ 2759 win[0].win_limit = win[1].win_limit; 2760 /* allocate win[1] to new space */ 2761 win[1].win_start = chainp->wc_start & mask; 2762 win[1].win_limit = chainp->wc_end & mask; 2763 win[1].win_flags = chainp->wc_flags; 2764 } 2765 } else { 2766 /* the flags of win[0] and win[1] are different */ 2767 if (win[0].win_flags == chainp->wc_flags) { 2768 win[0].win_limit = chainp->wc_end & mask; 2769 /* 2770 * XXX this creates overlapping windows, so 2771 * what should the poor bridge do if one is 2772 * cachable, and the other is not? 2773 */ 2774 printf("%s: overlapping windows\n", 2775 sc->sc_dev.dv_xname); 2776 } else { 2777 win[1].win_limit = chainp->wc_end & mask; 2778 } 2779 } 2780 } 2781 2782 pc = sc->sc_pc; 2783 tag = sc->sc_tag; 2784 pci_conf_write(pc, tag, offs, win[0].win_start); 2785 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 2786 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 2787 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 2788 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 2789 pci_conf_read(pc, tag, offs), 2790 pci_conf_read(pc, tag, offs + 4) + align, 2791 pci_conf_read(pc, tag, offs + 8), 2792 pci_conf_read(pc, tag, offs + 12) + align)); 2793 2794 if (bst == sc->sc_memt) { 2795 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 2796 2797 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 2798 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 2799 bcr |= CB_BCR_PREFETCH_MEMWIN0; 2800 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 2801 bcr |= CB_BCR_PREFETCH_MEMWIN1; 2802 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 2803 } 2804 } 2805 2806 int 2807 pccbbactivate(struct device *self, int act) 2808 { 2809 struct pccbb_softc *sc = (struct pccbb_softc *)self; 2810 pci_chipset_tag_t pc = sc->sc_pc; 2811 pcitag_t tag = sc->sc_tag; 2812 pcireg_t csr; 2813 u_int32_t reg; 2814 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 2815 bus_space_handle_t base_memh = sc->sc_base_memh; 2816 int rv = 0; 2817 2818 switch (act) { 2819 case DVACT_QUIESCE: 2820 rv = config_activate_children(self, act); 2821 break; 2822 case DVACT_SUSPEND: 2823 rv = config_activate_children(self, act); 2824 2825 sc->sc_pil_intr_enable = 0; 2826 2827 /* Save registers that may get lost. */ 2828 sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 2829 sc->sc_bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 2830 sc->sc_int = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 2831 2832 sc->sc_sockbase = pci_conf_read(pc, tag, PCI_SOCKBASE); 2833 sc->sc_busnum = pci_conf_read(pc, tag, PCI_BUSNUM); 2834 2835 sc->sc_membase[0] = pci_conf_read(pc, tag, PCI_CB_MEMBASE0); 2836 sc->sc_memlimit[0] = pci_conf_read(pc, tag, PCI_CB_MEMLIMIT0); 2837 sc->sc_membase[1] = pci_conf_read(pc, tag, PCI_CB_MEMBASE1); 2838 sc->sc_memlimit[1] = pci_conf_read(pc, tag, PCI_CB_MEMLIMIT1); 2839 sc->sc_iobase[0] = pci_conf_read(pc, tag, PCI_CB_IOBASE0); 2840 sc->sc_iolimit[0] = pci_conf_read(pc, tag, PCI_CB_IOLIMIT0); 2841 sc->sc_iobase[1] = pci_conf_read(pc, tag, PCI_CB_IOBASE1); 2842 sc->sc_iolimit[1] = pci_conf_read(pc, tag, PCI_CB_IOLIMIT1); 2843 break; 2844 case DVACT_RESUME: 2845 /* Restore the registers saved above. */ 2846 pci_conf_write(pc, tag, PCI_BHLC_REG, sc->sc_bhlcr); 2847 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, sc->sc_int); 2848 2849 pci_conf_write(pc, tag, PCI_SOCKBASE, sc->sc_sockbase); 2850 pci_conf_write(pc, tag, PCI_BUSNUM, sc->sc_busnum); 2851 2852 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, sc->sc_membase[0]); 2853 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, sc->sc_memlimit[0]); 2854 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, sc->sc_membase[1]); 2855 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, sc->sc_memlimit[1]); 2856 pci_conf_write(pc, tag, PCI_CB_IOBASE0, sc->sc_iobase[0]); 2857 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, sc->sc_iolimit[0]); 2858 pci_conf_write(pc, tag, PCI_CB_IOBASE1, sc->sc_iobase[1]); 2859 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, sc->sc_iolimit[1]); 2860 2861 /* Disable legacy register mapping. */ 2862 pccbb_legacy_disable(sc); 2863 2864 /* 2865 * Restore command register last to avoid exposing 2866 * uninitialised windows. 2867 */ 2868 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 2869 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 2870 (csr & 0xffff0000) | (sc->sc_csr & 0x0000ffff)); 2871 2872 /* CSC Interrupt: Card detect interrupt on */ 2873 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 2874 /* Card detect intr is turned on. */ 2875 reg |= CB_SOCKET_MASK_CD; 2876 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 2877 2878 /* reset interrupt */ 2879 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 2880 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 2881 2882 /* re-check all cards */ 2883 pccbb_checksockstat(sc); 2884 2885 /* 2886 * XXX Because the cardslot stuff is so obfuscated with threads, 2887 * here we are activating children which may have been 2888 * ejected while we were asleep. This needs to be solved. 2889 */ 2890 rv = config_activate_children(self, act); 2891 2892 sc->sc_pil_intr_enable = 1; 2893 break; 2894 } 2895 return (rv); 2896 } 2897