1 /* $OpenBSD: pccbb.c,v 1.68 2009/08/28 15:54:52 kettenis Exp $ */ 2 /* $NetBSD: pccbb.c,v 1.96 2004/03/28 09:49:31 nakayama Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 and 2000 6 * HAYAKAWA Koichi. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by HAYAKAWA Koichi. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 #define CBB_DEBUG 36 #define SHOW_REGS 37 #define PCCBB_PCMCIA_POLL 38 */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/evcount.h> 52 #include <sys/ioctl.h> 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 #include <sys/proc.h> 57 58 #include <machine/intr.h> 59 #include <machine/bus.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/pccbbreg.h> 66 67 #include <dev/cardbus/cardslotvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 71 #include <dev/pcmcia/pcmciareg.h> 72 #include <dev/pcmcia/pcmciavar.h> 73 74 #include <dev/ic/i82365reg.h> 75 #include <dev/ic/i82365var.h> 76 #include <dev/pci/pccbbvar.h> 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #else 87 #define DPRINTF(x) 88 #endif 89 90 int pcicbbmatch(struct device *, void *, void *); 91 void pccbbattach(struct device *, struct device *, void *); 92 int pccbbintr(void *); 93 void pccbb_shutdown(void *); 94 void pci113x_insert(void *); 95 int pccbbintr_function(struct pccbb_softc *); 96 97 int pccbb_detect_card(struct pccbb_softc *); 98 99 void pccbb_pcmcia_write(struct pcic_handle *, int, int); 100 u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 101 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 102 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 103 104 int cb_reset(struct pccbb_softc *); 105 int cb_detect_voltage(struct pccbb_softc *); 106 int cbbprint(void *, const char *); 107 108 int cb_chipset(u_int32_t, int *); 109 void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 110 struct pcmciabus_attach_args *); 111 #if 0 112 void pccbb_pcmcia_attach_card(struct pcic_handle *); 113 void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 114 void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 115 #endif 116 117 int pccbb_ctrl(cardbus_chipset_tag_t, int); 118 int pccbb_power(cardbus_chipset_tag_t, int); 119 int pccbb_cardenable(struct pccbb_softc * sc, int function); 120 void *pccbb_intr_establish(struct pccbb_softc *, int irq, int level, 121 int (*ih) (void *), void *sc, const char *); 122 void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 123 124 void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, int level, 125 int (*ih) (void *), void *sc, const char *); 126 void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 127 128 cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int, int); 129 void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 130 cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 131 void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 132 cardbusreg_t); 133 void pccbb_chipinit(struct pccbb_softc *); 134 135 int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 136 struct pcmcia_mem_handle *); 137 void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 138 struct pcmcia_mem_handle *); 139 int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 140 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 141 void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 142 int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 143 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 144 void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 145 struct pcmcia_io_handle *); 146 int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 147 bus_size_t, struct pcmcia_io_handle *, int *); 148 void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 149 void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 150 struct pcmcia_function *, int, int (*)(void *), void *, char *); 151 void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 152 const char *pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t, void *); 153 void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 154 void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 155 int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 156 157 void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 158 void pccbb_pcmcia_wait_ready(struct pcic_handle *); 159 void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 160 void pccbb_powerhook(int, void *); 161 162 /* bus-space allocation and deallocation functions */ 163 int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 164 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 165 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 166 int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 167 bus_space_handle_t, bus_size_t); 168 169 int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 170 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 171 int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 172 bus_space_handle_t, bus_size_t); 173 int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 174 bus_size_t, bus_space_handle_t, int); 175 int pccbb_winlist_delete(struct pccbb_win_chain_head *, 176 bus_space_handle_t, bus_size_t); 177 void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 178 bus_space_tag_t); 179 void pccbb_winlist_show(struct pccbb_win_chain *); 180 181 /* for config_defer */ 182 void pccbb_pci_callback(struct device *); 183 184 #if defined SHOW_REGS 185 void cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t, 186 bus_space_handle_t memh); 187 #endif 188 189 struct cfattach cbb_pci_ca = { 190 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 191 }; 192 193 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 194 pccbb_pcmcia_mem_alloc, 195 pccbb_pcmcia_mem_free, 196 pccbb_pcmcia_mem_map, 197 pccbb_pcmcia_mem_unmap, 198 pccbb_pcmcia_io_alloc, 199 pccbb_pcmcia_io_free, 200 pccbb_pcmcia_io_map, 201 pccbb_pcmcia_io_unmap, 202 pccbb_pcmcia_intr_establish, 203 pccbb_pcmcia_intr_disestablish, 204 pccbb_pcmcia_intr_string, 205 pccbb_pcmcia_socket_enable, 206 pccbb_pcmcia_socket_disable, 207 pccbb_pcmcia_card_detect 208 }; 209 210 static struct cardbus_functions pccbb_funcs = { 211 pccbb_rbus_cb_space_alloc, 212 pccbb_rbus_cb_space_free, 213 pccbb_cb_intr_establish, 214 pccbb_cb_intr_disestablish, 215 pccbb_ctrl, 216 pccbb_power, 217 pccbb_make_tag, 218 pccbb_free_tag, 219 pccbb_conf_read, 220 pccbb_conf_write, 221 }; 222 223 /* 224 * delay_ms() is wait in milliseconds. It should be used instead 225 * of delay() if you want to wait more than 1 ms. 226 */ 227 static inline void 228 delay_ms(int millis, void *param) 229 { 230 if (cold) 231 delay(millis * 1000); 232 else 233 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 234 } 235 236 int 237 pcicbbmatch(parent, match, aux) 238 struct device *parent; 239 void *match; 240 void *aux; 241 { 242 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 243 244 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 245 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 246 PCI_INTERFACE(pa->pa_class) == 0) { 247 return 1; 248 } 249 250 return 0; 251 } 252 253 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 254 | ((prod) << PCI_PRODUCT_SHIFT)) 255 256 struct yenta_chipinfo { 257 pcireg_t yc_id; /* vendor tag | product tag */ 258 int yc_chiptype; 259 int yc_flags; 260 } yc_chipsets[] = { 261 /* Texas Instruments chips */ 262 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 263 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 264 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 265 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 266 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 267 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 268 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 269 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 270 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 271 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 272 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 273 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 274 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 275 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 276 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 277 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 278 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 279 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 280 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 281 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7XX1), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 293 /* Ricoh chips */ 294 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X, 295 PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X, 297 PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X, 299 PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X, 301 PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X, 303 PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X, 305 PCCBB_PCMCIA_MEM_32}, 306 307 /* Toshiba products */ 308 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 309 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 311 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 313 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 315 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 316 317 /* Cirrus Logic products */ 318 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 319 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 321 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 322 323 /* older O2Micro bridges */ 324 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 325 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 327 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), /* 68[71]2 */ 329 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 331 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 333 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 334 335 /* sentinel, or Generic chip */ 336 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 337 }; 338 339 int 340 cb_chipset(pci_id, flagp) 341 u_int32_t pci_id; 342 int *flagp; 343 { 344 struct yenta_chipinfo *yc; 345 346 /* Loop over except the last default entry. */ 347 for (yc = yc_chipsets; yc < yc_chipsets + 348 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 349 if (pci_id == yc->yc_id) 350 break; 351 352 if (flagp != NULL) 353 *flagp = yc->yc_flags; 354 355 return (yc->yc_chiptype); 356 } 357 358 void 359 pccbb_shutdown(void *arg) 360 { 361 struct pccbb_softc *sc = arg; 362 pcireg_t command; 363 364 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 365 366 /* turn off power */ 367 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 368 369 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 370 0); 371 372 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 373 374 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 375 PCI_COMMAND_MASTER_ENABLE); 376 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 377 } 378 379 void 380 pccbbattach(struct device *parent, struct device *self, void *aux) 381 { 382 struct pccbb_softc *sc = (void *)self; 383 struct pci_attach_args *pa = aux; 384 pci_chipset_tag_t pc = pa->pa_pc; 385 pcireg_t busreg, reg, sock_base; 386 pci_intr_handle_t ih; 387 const char *intrstr = NULL; 388 bus_addr_t sockbase; 389 int flags; 390 391 pccbb_attach_hook(parent, self, pa); 392 393 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 394 sc->sc_id = pa->pa_id; 395 396 #ifdef CBB_DEBUG 397 printf(" (chipflags %x)", flags); 398 #endif 399 400 TAILQ_INIT(&sc->sc_memwindow); 401 TAILQ_INIT(&sc->sc_iowindow); 402 403 sc->sc_rbus_iot = rbus_pccbb_parent_io(self, pa); 404 sc->sc_rbus_memt = rbus_pccbb_parent_mem(self, pa); 405 406 /* 407 * MAP socket registers and ExCA registers on memory-space 408 * When no valid address is set on socket base registers (on pci 409 * config space), get it not polite way. 410 */ 411 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 412 413 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 414 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL, 0)) { 415 printf("can't map registers\n"); 416 return; 417 } 418 419 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 420 421 #if defined CBB_DEBUG 422 { 423 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 424 printf(": intrpin %s, line %d\n", 425 intrname[pa->pa_intrpin], pa->pa_intrline); 426 } 427 #endif 428 429 /* setup softc */ 430 sc->sc_pc = pc; 431 sc->sc_iot = pa->pa_iot; 432 sc->sc_memt = pa->pa_memt; 433 sc->sc_dmat = pa->pa_dmat; 434 sc->sc_tag = pa->pa_tag; 435 sc->sc_function = pa->pa_function; 436 sc->sc_sockbase = sock_base; 437 sc->sc_busnum = busreg; 438 sc->sc_intrtag = pa->pa_intrtag; 439 sc->sc_intrpin = pa->pa_intrpin; 440 441 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 442 443 /* Map and establish the interrupt. */ 444 if (pci_intr_map(pa, &ih)) { 445 printf(": couldn't map interrupt\n"); 446 return; 447 } 448 intrstr = pci_intr_string(pc, ih); 449 /* must do this after intr is mapped and established */ 450 sc->sc_intrline = pci_intr_line(pc, ih); 451 452 /* 453 * XXX pccbbintr should be called under the priority lower 454 * than any other hard interrupts. 455 */ 456 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc, 457 sc->sc_dev.dv_xname); 458 459 if (sc->sc_ih == NULL) { 460 printf(": couldn't establish interrupt"); 461 if (intrstr != NULL) { 462 printf(" at %s", intrstr); 463 } 464 printf("\n"); 465 return; 466 } 467 printf(": %s", intrstr); 468 469 /* 470 * When bus number isn't set correctly, give up using 32-bit CardBus 471 * mode. 472 */ 473 if (((busreg >> 8) & 0xff) == 0) { 474 printf(", CardBus support disabled"); 475 sc->sc_pcmcia_flags |= PCCBB_PCMCIA_16BITONLY; 476 } 477 478 printf("\n"); 479 480 shutdownhook_establish(pccbb_shutdown, sc); 481 482 /* Disable legacy register mapping. */ 483 switch (sc->sc_chipset) { 484 case CB_RX5C46X: 485 /* 486 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 487 * cannot be disabled by substituting 0 into PCI_LEGACY 488 * register. Ricoh CardBus bridges have special bits on Bridge 489 * control reg (addr 0x3e on PCI config space). 490 */ 491 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 492 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 493 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 494 break; 495 496 default: 497 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 498 break; 499 } 500 501 timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc); 502 config_defer(self, pccbb_pci_callback); 503 } 504 505 /* 506 * void pccbb_pci_callback(struct device *self) 507 * 508 * The actual attach routine: get memory space for YENTA register 509 * space, setup YENTA register and route interrupt. 510 * 511 * This function should be deferred because this device may obtain 512 * memory space dynamically. This function must avoid obtaining 513 * memory area which has already kept for another device. Also, 514 * this function MUST be done before ISA attach process because this 515 * function kills pcic compatible port used by ISA pcic. 516 */ 517 void 518 pccbb_pci_callback(struct device *self) 519 { 520 struct pccbb_softc *sc = (void *)self; 521 pci_chipset_tag_t pc = sc->sc_pc; 522 bus_space_tag_t base_memt; 523 bus_space_handle_t base_memh; 524 u_int32_t maskreg; 525 struct cbslot_attach_args cba; 526 struct pcmciabus_attach_args paa; 527 struct cardslot_attach_args caa; 528 struct cardslot_softc *csc; 529 u_int32_t sockstat; 530 531 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 532 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 533 534 /* bus bridge initialization */ 535 pccbb_chipinit(sc); 536 537 /* clear data structure for child device interrupt handlers */ 538 sc->sc_pil = NULL; 539 sc->sc_pil_intr_enable = 1; 540 541 powerhook_establish(pccbb_powerhook, sc); 542 543 sockstat = bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 544 if ((sockstat & CB_SOCKET_STAT_CD) == 0) 545 sc->sc_flags |= CBB_CARDEXIST; 546 547 /* 548 * attach cardbus 549 */ 550 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 551 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 552 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 553 554 /* initialize cbslot_attach */ 555 cba.cba_busname = "cardbus"; 556 cba.cba_iot = sc->sc_iot; 557 cba.cba_memt = sc->sc_memt; 558 cba.cba_dmat = sc->sc_dmat; 559 cba.cba_bus = (busreg >> 8) & 0x0ff; 560 cba.cba_cc = (void *)sc; 561 cba.cba_cf = &pccbb_funcs; 562 cba.cba_intrline = sc->sc_intrline; 563 564 cba.cba_rbus_iot = sc->sc_rbus_iot; 565 cba.cba_rbus_memt = sc->sc_rbus_memt; 566 567 cba.cba_cacheline = PCI_CACHELINE(bhlc); 568 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 569 570 #if defined CBB_DEBUG 571 printf("%s: cacheline 0x%x lattimer 0x%x\n", 572 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 573 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 574 busreg); 575 #endif 576 #if defined SHOW_REGS 577 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 578 sc->sc_base_memh); 579 #endif 580 } 581 582 pccbb_pcmcia_attach_setup(sc, &paa); 583 caa.caa_cb_attach = NULL; 584 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 585 caa.caa_cb_attach = &cba; 586 } 587 caa.caa_16_attach = &paa; 588 caa.caa_ph = &sc->sc_pcmcia_h; 589 590 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 591 DPRINTF(("pccbbattach: found cardslot\n")); 592 sc->sc_csc = csc; 593 } 594 595 sc->sc_ints_on = 1; 596 597 /* CSC Interrupt: Card detect interrupt on */ 598 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 599 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 600 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 601 /* reset interrupt */ 602 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 603 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 604 605 return; 606 } 607 608 /* 609 * void pccbb_chipinit(struct pccbb_softc *sc) 610 * 611 * This function initialize YENTA chip registers listed below: 612 * 1) PCI command reg, 613 * 2) PCI and CardBus latency timer, 614 * 3) route PCI interrupt, 615 * 4) close all memory and io windows. 616 */ 617 void 618 pccbb_chipinit(struct pccbb_softc *sc) 619 { 620 pci_chipset_tag_t pc = sc->sc_pc; 621 pcitag_t tag = sc->sc_tag; 622 pcireg_t reg; 623 624 /* 625 * Set PCI command reg. 626 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 627 */ 628 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 629 /* I believe it is harmless. */ 630 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 631 PCI_COMMAND_MASTER_ENABLE); 632 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 633 634 /* 635 * Set CardBus latency timer. 636 */ 637 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 638 if (PCI_CB_LATENCY(reg) < 0x20) { 639 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 640 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 641 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 642 } 643 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 644 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 645 646 /* 647 * Set PCI latency timer. 648 */ 649 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 650 if (PCI_LATTIMER(reg) < 0x10) { 651 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 652 reg |= (0x10 << PCI_LATTIMER_SHIFT); 653 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 654 } 655 DPRINTF(("PCI latency timer 0x%x (%x)\n", 656 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 657 658 /* Route functional interrupts to PCI. */ 659 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 660 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 661 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 662 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 663 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 664 665 switch (sc->sc_chipset) { 666 case CB_TI113X: 667 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 668 /* This bit is shared, but may read as 0 on some chips, so set 669 it explicitly on both functions. */ 670 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 671 /* CSC intr enable */ 672 reg |= PCI113X_CBCTRL_PCI_CSC; 673 /* functional intr prohibit | prohibit ISA routing */ 674 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 675 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 676 break; 677 678 case CB_TI12XX: 679 /* 680 * Some TI 12xx (and [14][45]xx) based pci cards 681 * sometimes have issues with the MFUNC register not 682 * being initialized due to a bad EEPROM on board. 683 * Laptops that this matters on have this register 684 * properly initialized. 685 * 686 * The TI125X parts have a different register. 687 */ 688 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 689 if (reg == PCI12XX_MFUNC_DEFAULT) { 690 reg &= ~PCI12XX_MFUNC_PIN0; 691 reg |= PCI12XX_MFUNC_PIN0_INTA; 692 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 693 PCI12XX_SYSCTRL_INTRTIE) == 0) { 694 reg &= ~PCI12XX_MFUNC_PIN1; 695 reg |= PCI12XX_MFUNC_PIN1_INTB; 696 } 697 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 698 } 699 /* FALLTHROUGH */ 700 701 case CB_TI125X: 702 /* 703 * Disable zoom video. Some machines initialize this 704 * improperly and experience has shown that this helps 705 * prevent strange behavior. 706 */ 707 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 708 709 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 710 reg |= PCI12XX_SYSCTRL_VCCPROT; 711 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 712 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 713 reg |= PCI12XX_CBCTRL_CSC; 714 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 715 break; 716 717 case CB_TOPIC95B: 718 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 719 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 720 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 721 722 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 723 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 724 sc->sc_dev.dv_xname, reg)); 725 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 726 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 727 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 728 DPRINTF(("0x%x\n", reg)); 729 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 730 break; 731 732 case CB_TOPIC97: 733 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 734 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 735 sc->sc_dev.dv_xname, reg)); 736 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 737 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 738 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 739 reg |= TOPIC97_SLOT_CTRL_PCIINT; 740 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 741 DPRINTF(("0x%x\n", reg)); 742 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 743 744 /* make sure to assert LV card support bits */ 745 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 746 0x800 + 0x3e, bus_space_read_1(sc->sc_base_memt, 747 sc->sc_base_memh, 0x800 + 0x3e) | 0x03); 748 749 /* Power on the controller if the BIOS didn't */ 750 reg = pci_conf_read(pc, tag, TOPIC100_PMCSR); 751 if ((reg & TOPIC100_PMCSR_MASK) != TOPIC100_PMCSR_D0) 752 pci_conf_write(pc, tag, TOPIC100_PMCSR, 753 (reg & ~TOPIC100_PMCSR_MASK) | TOPIC100_PMCSR_D0); 754 break; 755 756 case CB_OLDO2MICRO: 757 /* 758 * older bridges have problems with both read prefetch and 759 * write bursting depending on the combination of the chipset, 760 * bridge and the cardbus card. so disable them to be on the 761 * safe side. One example is O2Micro 6812 with Atheros AR5012 762 * chipsets 763 */ 764 DPRINTF(("%s: old O2Micro bridge found\n", 765 sc->sc_dev.dv_xname, reg)); 766 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED1); 767 pci_conf_write(pc, tag, O2MICRO_RESERVED1, reg & 768 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 769 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED2); 770 pci_conf_write(pc, tag, O2MICRO_RESERVED2, reg & 771 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 772 break; 773 } 774 775 /* Close all memory and I/O windows. */ 776 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 777 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 778 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 779 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 780 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 781 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 782 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 783 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 784 785 /* reset 16-bit pcmcia bus */ 786 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 787 0x800 + PCIC_INTR, 788 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 789 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 790 791 /* turn off power */ 792 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 793 } 794 795 796 797 798 /* 799 * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 800 * struct pcmciabus_attach_args *paa) 801 * 802 * This function attaches 16-bit PCcard bus. 803 */ 804 void 805 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 806 struct pcmciabus_attach_args *paa) 807 { 808 struct pcic_handle *ph = &sc->sc_pcmcia_h; 809 rbus_tag_t rb; 810 811 /* initialize pcmcia part in pccbb_softc */ 812 ph->ph_parent = (struct device *)sc; 813 ph->sock = sc->sc_function; 814 ph->flags = 0; 815 ph->shutdown = 0; 816 ph->ih_irq = sc->sc_intrline; 817 ph->ph_bus_t = sc->sc_base_memt; 818 ph->ph_bus_h = sc->sc_base_memh; 819 ph->ph_read = pccbb_pcmcia_read; 820 ph->ph_write = pccbb_pcmcia_write; 821 sc->sc_pct = &pccbb_pcmcia_funcs; 822 823 /* 824 * We need to do a few things here: 825 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 826 * setting the IRQ numbers to 0. 827 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 828 * routing of CSC interrupts (e.g. card removal) to PCI while in 829 * PCMCIA mode. We just leave this set all the time. 830 * 3) Enable card insertion/removal interrupts in case the chip also 831 * needs that while in PCMCIA mode. 832 * 4) Clear any pending CSC interrupt. 833 */ 834 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 835 if (sc->sc_chipset == CB_TI113X) { 836 Pcic_write(ph, PCIC_CSC_INTR, 0); 837 } else { 838 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 839 Pcic_read(ph, PCIC_CSC); 840 } 841 842 /* initialize pcmcia bus attachment */ 843 paa->paa_busname = "pcmcia"; 844 paa->pct = sc->sc_pct; 845 paa->pch = ph; 846 paa->iobase = 0; /* I don't use them */ 847 paa->iosize = 0; 848 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 849 paa->iobase = rb->rb_start + rb->rb_offset; 850 paa->iosize = rb->rb_end - rb->rb_start; 851 852 return; 853 } 854 855 #if 0 856 void 857 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 858 { 859 if (ph->flags & PCIC_FLAG_CARDP) { 860 panic("pccbb_pcmcia_attach_card: already attached"); 861 } 862 863 /* call the MI attach function */ 864 pcmcia_card_attach(ph->pcmcia); 865 866 ph->flags |= PCIC_FLAG_CARDP; 867 } 868 869 void 870 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 871 { 872 if (!(ph->flags & PCIC_FLAG_CARDP)) { 873 panic("pccbb_pcmcia_detach_card: already detached"); 874 } 875 876 ph->flags &= ~PCIC_FLAG_CARDP; 877 878 /* call the MI detach function */ 879 pcmcia_card_detach(ph->pcmcia, flags); 880 } 881 #endif 882 883 /* 884 * int pccbbintr(arg) 885 * void *arg; 886 * This routine handles the interrupt from Yenta PCI-CardBus bridge 887 * itself. 888 */ 889 int 890 pccbbintr(void *arg) 891 { 892 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 893 u_int32_t sockevent, sockstate; 894 bus_space_tag_t memt = sc->sc_base_memt; 895 bus_space_handle_t memh = sc->sc_base_memh; 896 struct pcic_handle *ph = &sc->sc_pcmcia_h; 897 898 if (!sc->sc_ints_on) 899 return 0; 900 901 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 902 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 903 Pcic_read(ph, PCIC_CSC); 904 905 if (sockevent == 0) { 906 /* This intr is not for me: it may be for my child devices. */ 907 if (sc->sc_pil_intr_enable) { 908 return pccbbintr_function(sc); 909 } else { 910 return 0; 911 } 912 } 913 914 if (sockevent & CB_SOCKET_EVENT_CD) { 915 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 916 if ((sockstate & CB_SOCKET_STAT_CD) != 0) { 917 /* A card should be removed. */ 918 if (sc->sc_flags & CBB_CARDEXIST) { 919 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 920 sockevent)); 921 DPRINTF((" card removed, 0x%08x\n", sockstate)); 922 sc->sc_flags &= ~CBB_CARDEXIST; 923 if (sc->sc_csc->sc_status & 924 CARDSLOT_STATUS_CARD_16) { 925 #if 0 926 struct pcic_handle *ph = 927 &sc->sc_pcmcia_h; 928 929 pcmcia_card_deactivate(ph->pcmcia); 930 pccbb_pcmcia_socket_disable(ph); 931 pccbb_pcmcia_detach_card(ph, 932 DETACH_FORCE); 933 #endif 934 cardslot_event_throw(sc->sc_csc, 935 CARDSLOT_EVENT_REMOVAL_16); 936 } else if (sc->sc_csc->sc_status & 937 CARDSLOT_STATUS_CARD_CB) { 938 /* Cardbus intr removed */ 939 cardslot_event_throw(sc->sc_csc, 940 CARDSLOT_EVENT_REMOVAL_CB); 941 } 942 } 943 } else if ((sockstate & CB_SOCKET_STAT_CD) == 0 && 944 /* 945 * The pccbbintr may called from powerdown hook when 946 * the system resumed, to detect the card 947 * insertion/removal during suspension. 948 */ 949 (sc->sc_flags & CBB_CARDEXIST) == 0) { 950 timeout_add(&sc->sc_ins_tmo, hz / 10); 951 sc->sc_flags |= CBB_INSERTING; 952 } 953 return (1); 954 } 955 956 return (0); 957 } 958 959 /* 960 * int pccbbintr_function(struct pccbb_softc *sc) 961 * 962 * This function calls each interrupt handler registered at the 963 * bridge. The interrupt handlers are called in registered order. 964 */ 965 int 966 pccbbintr_function(struct pccbb_softc *sc) 967 { 968 int retval = 0, val; 969 struct pccbb_intrhand_list *pil; 970 int s, splchanged; 971 972 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 973 /* 974 * XXX priority change. gross. I use if-else 975 * sentences instead of switch-case sentences in order 976 * to avoid duplicate case value error. More than one 977 * IPL_XXX may use the same value. It depends on the 978 * implementation. 979 */ 980 splchanged = 1; 981 #if 0 982 if (pil->pil_level == IPL_SERIAL) { 983 s = splserial(); 984 } else if (pil->pil_level == IPL_HIGH) { 985 #endif 986 if (pil->pil_level == IPL_HIGH) { 987 s = splhigh(); 988 } else if (pil->pil_level == IPL_CLOCK) { 989 s = splclock(); 990 } else if (pil->pil_level == IPL_AUDIO) { 991 s = splaudio(); 992 } else if (pil->pil_level == IPL_VM) { 993 s = splvm(); 994 } else if (pil->pil_level == IPL_TTY) { 995 s = spltty(); 996 #if 0 997 } else if (pil->pil_level == IPL_SOFTSERIAL) { 998 s = splsoftserial(); 999 #endif 1000 } else if (pil->pil_level == IPL_NET) { 1001 s = splnet(); 1002 } else { 1003 splchanged = 0; 1004 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1005 } 1006 1007 val = (*pil->pil_func)(pil->pil_arg); 1008 if (val != 0) 1009 pil->pil_count.ec_count++; 1010 1011 if (splchanged != 0) { 1012 splx(s); 1013 } 1014 1015 retval = retval == 1 ? 1 : 1016 retval == 0 ? val : val != 0 ? val : retval; 1017 } 1018 1019 return retval; 1020 } 1021 1022 void 1023 pci113x_insert(void *arg) 1024 { 1025 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1026 u_int32_t sockevent, sockstate; 1027 1028 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1029 CB_SOCKET_EVENT); 1030 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1031 CB_SOCKET_STAT); 1032 1033 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1034 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1035 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1036 sc->sc_flags |= CBB_CARDEXIST; 1037 /* call pccard interrupt handler here */ 1038 if (sockstate & CB_SOCKET_STAT_16BIT) { 1039 /* 16-bit card found */ 1040 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1041 cardslot_event_throw(sc->sc_csc, 1042 CARDSLOT_EVENT_INSERTION_16); 1043 } else if (sockstate & CB_SOCKET_STAT_CB) { 1044 /* cardbus card found */ 1045 /* cardbus_attach_card(sc->sc_csc); */ 1046 cardslot_event_throw(sc->sc_csc, 1047 CARDSLOT_EVENT_INSERTION_CB); 1048 } else { 1049 /* who are you? */ 1050 } 1051 } else { 1052 timeout_add(&sc->sc_ins_tmo, hz / 10); 1053 } 1054 } 1055 1056 #define PCCBB_PCMCIA_OFFSET 0x800 1057 u_int8_t 1058 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1059 { 1060 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1061 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1062 1063 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1064 PCCBB_PCMCIA_OFFSET + reg); 1065 } 1066 1067 void 1068 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, int val) 1069 { 1070 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1071 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1072 1073 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1074 val); 1075 } 1076 1077 /* 1078 * int pccbb_ctrl(cardbus_chipset_tag_t, int) 1079 */ 1080 int 1081 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1082 { 1083 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1084 1085 switch (command) { 1086 case CARDBUS_CD: 1087 if (2 == pccbb_detect_card(sc)) { 1088 int retval = 0; 1089 int status = cb_detect_voltage(sc); 1090 if (PCCARD_VCC_5V & status) { 1091 retval |= CARDBUS_5V_CARD; 1092 } 1093 if (PCCARD_VCC_3V & status) { 1094 retval |= CARDBUS_3V_CARD; 1095 } 1096 if (PCCARD_VCC_XV & status) { 1097 retval |= CARDBUS_XV_CARD; 1098 } 1099 if (PCCARD_VCC_YV & status) { 1100 retval |= CARDBUS_YV_CARD; 1101 } 1102 return retval; 1103 } else { 1104 return 0; 1105 } 1106 break; 1107 case CARDBUS_RESET: 1108 return cb_reset(sc); 1109 break; 1110 case CARDBUS_IO_ENABLE: /* fallthrough */ 1111 case CARDBUS_IO_DISABLE: /* fallthrough */ 1112 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1113 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1114 case CARDBUS_BM_ENABLE: /* fallthrough */ 1115 case CARDBUS_BM_DISABLE: /* fallthrough */ 1116 return pccbb_cardenable(sc, command); 1117 break; 1118 } 1119 1120 return 0; 1121 } 1122 1123 /* 1124 * int pccbb_power(cardbus_chipset_tag_t, int) 1125 * This function returns true when it succeeds and returns false when 1126 * it fails. 1127 */ 1128 int 1129 pccbb_power(cardbus_chipset_tag_t ct, int command) 1130 { 1131 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1132 1133 u_int32_t status, sock_ctrl; 1134 bus_space_tag_t memt = sc->sc_base_memt; 1135 bus_space_handle_t memh = sc->sc_base_memh; 1136 1137 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1138 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1139 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1140 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1141 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1142 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1143 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1144 "UNKNOWN", 1145 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1146 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1147 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1148 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1149 "UNKNOWN", command)); 1150 1151 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1152 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1153 1154 switch (command & CARDBUS_VCCMASK) { 1155 case CARDBUS_VCC_UC: 1156 break; 1157 case CARDBUS_VCC_5V: 1158 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1159 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1160 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1161 } else { 1162 printf("%s: BAD voltage request: no 5 V card\n", 1163 sc->sc_dev.dv_xname); 1164 } 1165 break; 1166 case CARDBUS_VCC_3V: 1167 if (CB_SOCKET_STAT_3VCARD & status) { 1168 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1169 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1170 } else { 1171 printf("%s: BAD voltage request: no 3.3 V card\n", 1172 sc->sc_dev.dv_xname); 1173 } 1174 break; 1175 case CARDBUS_VCC_0V: 1176 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1177 break; 1178 default: 1179 return 0; /* power NEVER changed */ 1180 break; 1181 } 1182 1183 switch (command & CARDBUS_VPPMASK) { 1184 case CARDBUS_VPP_UC: 1185 break; 1186 case CARDBUS_VPP_0V: 1187 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1188 break; 1189 case CARDBUS_VPP_VCC: 1190 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1191 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1192 break; 1193 case CARDBUS_VPP_12V: 1194 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1195 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1196 break; 1197 } 1198 1199 #if 0 1200 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1201 #endif 1202 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1203 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1204 1205 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1206 printf 1207 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1208 sc->sc_dev.dv_xname, sock_ctrl, status); 1209 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1210 (command & CARDBUS_VCCMASK) == 1211 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1212 CARDBUS_VCCMASK) == 1213 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1214 CARDBUS_VCCMASK) == 1215 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1216 CARDBUS_VCCMASK) == 1217 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1218 CARDBUS_VCCMASK) == 1219 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1220 CARDBUS_VCCMASK) == 1221 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1222 (command & CARDBUS_VPPMASK) == 1223 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1224 CARDBUS_VPPMASK) == 1225 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1226 CARDBUS_VPPMASK) == 1227 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1228 CARDBUS_VPPMASK) == 1229 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1230 #if 0 1231 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1232 u_int32_t force = 1233 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1234 /* Reset Bad Vcc request */ 1235 force &= ~CB_SOCKET_FORCE_BADVCC; 1236 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1237 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1238 CB_SOCKET_STAT)); 1239 return 1; 1240 } 1241 #endif 1242 return 0; 1243 } 1244 1245 /* 1246 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1247 * time is 20 ms, some PC-Card bridge requires longer duration. 1248 */ 1249 delay(300 * 1000); 1250 1251 return 1; /* power changed correctly */ 1252 } 1253 1254 #if defined CB_PCMCIA_POLL 1255 struct cb_poll_str { 1256 void *arg; 1257 int (*func)(void *); 1258 int level; 1259 pccard_chipset_tag_t ct; 1260 int count; 1261 }; 1262 1263 static struct cb_poll_str cb_poll[10]; 1264 static int cb_poll_n = 0; 1265 static struct timeout cb_poll_timeout; 1266 1267 void cb_pcmcia_poll(void *arg); 1268 1269 void 1270 cb_pcmcia_poll(void *arg) 1271 { 1272 struct cb_poll_str *poll = arg; 1273 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1274 struct pccbb_softc *sc = psc->cpc_parent; 1275 int s; 1276 u_int32_t spsr; /* socket present-state reg */ 1277 1278 timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg); 1279 timeout_add(&cb_poll_timeout, hz / 10); 1280 switch (poll->level) { 1281 case IPL_NET: 1282 s = splnet(); 1283 break; 1284 case IPL_BIO: 1285 s = splbio(); 1286 break; 1287 case IPL_TTY: /* fallthrough */ 1288 default: 1289 s = spltty(); 1290 break; 1291 } 1292 1293 spsr = 1294 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1295 CB_SOCKET_STAT); 1296 1297 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1298 if (!(spsr & 0x40)) { /* CINT low */ 1299 #else 1300 if (1) { 1301 #endif 1302 if ((*poll->func) (poll->arg) == 1) { 1303 ++poll->count; 1304 printf("intr: reported from poller, 0x%x\n", spsr); 1305 #if defined LEVEL2 1306 } else { 1307 printf("intr: miss! 0x%x\n", spsr); 1308 #endif 1309 } 1310 } 1311 splx(s); 1312 } 1313 #endif /* defined CB_PCMCIA_POLL */ 1314 1315 /* 1316 * int pccbb_detect_card(struct pccbb_softc *sc) 1317 * return value: 0 if no card exists. 1318 * 1 if 16-bit card exists. 1319 * 2 if cardbus card exists. 1320 */ 1321 int 1322 pccbb_detect_card(struct pccbb_softc *sc) 1323 { 1324 bus_space_handle_t base_memh = sc->sc_base_memh; 1325 bus_space_tag_t base_memt = sc->sc_base_memt; 1326 u_int32_t sockstat = 1327 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1328 int retval = 0; 1329 1330 /* 1331 * The SCM Microsystems TI1225-based PCI-CardBus dock card that 1332 * ships with some Lucent WaveLAN cards has only one physical slot 1333 * but OpenBSD probes two. The phantom card in the second slot can 1334 * be ignored by punting on unsupported voltages. 1335 */ 1336 if (sockstat & CB_SOCKET_STAT_XVCARD) 1337 return 0; 1338 1339 /* CD1 and CD2 asserted */ 1340 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1341 /* card must be present */ 1342 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1343 /* NOTACARD DEASSERTED */ 1344 if (CB_SOCKET_STAT_CB & sockstat) { 1345 /* CardBus mode */ 1346 retval = 2; 1347 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1348 /* 16-bit mode */ 1349 retval = 1; 1350 } 1351 } 1352 } 1353 return retval; 1354 } 1355 1356 /* 1357 * int cb_reset(struct pccbb_softc *sc) 1358 * This function resets CardBus card. 1359 */ 1360 int 1361 cb_reset(struct pccbb_softc *sc) 1362 { 1363 /* 1364 * Reset Assert at least 20 ms 1365 * Some machines request longer duration. 1366 */ 1367 int reset_duration = (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1368 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1369 1370 /* Reset bit Assert (bit 6 at 0x3E) */ 1371 bcr |= CB_BCR_RESET_ENABLE; 1372 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1373 delay_ms(reset_duration, sc); 1374 1375 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1376 /* Reset bit Deassert (bit 6 at 0x3E) */ 1377 bcr &= ~CB_BCR_RESET_ENABLE; 1378 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1379 delay_ms(reset_duration, sc); 1380 } 1381 /* No card found on the slot. Keep Reset. */ 1382 return 1; 1383 } 1384 1385 /* 1386 * int cb_detect_voltage(struct pccbb_softc *sc) 1387 * This function detect card Voltage. 1388 */ 1389 int 1390 cb_detect_voltage(struct pccbb_softc *sc) 1391 { 1392 u_int32_t psr; /* socket present-state reg */ 1393 bus_space_tag_t iot = sc->sc_base_memt; 1394 bus_space_handle_t ioh = sc->sc_base_memh; 1395 int vol = PCCARD_VCC_UKN; /* set 0 */ 1396 1397 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1398 1399 if (0x400u & psr) { 1400 vol |= PCCARD_VCC_5V; 1401 } 1402 if (0x800u & psr) { 1403 vol |= PCCARD_VCC_3V; 1404 } 1405 1406 return vol; 1407 } 1408 1409 int 1410 cbbprint(void *aux, const char *pcic) 1411 { 1412 /* 1413 struct cbslot_attach_args *cba = aux; 1414 1415 if (cba->cba_slot >= 0) { 1416 printf(" slot %d", cba->cba_slot); 1417 } 1418 */ 1419 return UNCONF; 1420 } 1421 1422 /* 1423 * int pccbb_cardenable(struct pccbb_softc *sc, int function) 1424 * This function enables and disables the card 1425 */ 1426 int 1427 pccbb_cardenable(struct pccbb_softc *sc, int function) 1428 { 1429 u_int32_t command = 1430 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1431 1432 DPRINTF(("pccbb_cardenable:")); 1433 switch (function) { 1434 case CARDBUS_IO_ENABLE: 1435 command |= PCI_COMMAND_IO_ENABLE; 1436 break; 1437 case CARDBUS_IO_DISABLE: 1438 command &= ~PCI_COMMAND_IO_ENABLE; 1439 break; 1440 case CARDBUS_MEM_ENABLE: 1441 command |= PCI_COMMAND_MEM_ENABLE; 1442 break; 1443 case CARDBUS_MEM_DISABLE: 1444 command &= ~PCI_COMMAND_MEM_ENABLE; 1445 break; 1446 case CARDBUS_BM_ENABLE: 1447 command |= PCI_COMMAND_MASTER_ENABLE; 1448 break; 1449 case CARDBUS_BM_DISABLE: 1450 command &= ~PCI_COMMAND_MASTER_ENABLE; 1451 break; 1452 default: 1453 return 0; 1454 } 1455 1456 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1457 DPRINTF((" command reg 0x%x\n", command)); 1458 return 1; 1459 } 1460 1461 /* 1462 * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1463 * int irq, 1464 * int level, 1465 * int (* func)(void *), 1466 * void *arg, 1467 * const char *name) 1468 * 1469 * This function registers an interrupt handler at the bridge, in 1470 * order not to call the interrupt handlers of child devices when 1471 * a card-deletion interrupt occurs. 1472 * 1473 * The arguments irq is not used because pccbb selects intr vector. 1474 */ 1475 void * 1476 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1477 int (*func)(void *), void *arg, const char *name) 1478 { 1479 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1480 1481 return pccbb_intr_establish(sc, irq, level, func, arg, name); 1482 } 1483 1484 1485 /* 1486 * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1487 * void *ih) 1488 * 1489 * This function removes an interrupt handler pointed by ih. 1490 */ 1491 void 1492 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1493 { 1494 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1495 1496 pccbb_intr_disestablish(sc, ih); 1497 } 1498 1499 1500 /* 1501 * void *pccbb_intr_establish(struct pccbb_softc *sc, 1502 * int irq, 1503 * int level, 1504 * int (* func)(void *), 1505 * void *arg, 1506 * const char *name) 1507 * 1508 * This function registers an interrupt handler at the bridge, in 1509 * order not to call the interrupt handlers of child devices when 1510 * a card-deletion interrupt occurs. 1511 * 1512 * The arguments irq and level are not used. 1513 */ 1514 void * 1515 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1516 int (*func)(void *), void *arg, const char *name) 1517 { 1518 struct pccbb_intrhand_list *pil, *newpil; 1519 pcireg_t reg; 1520 1521 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1522 1523 if (sc->sc_pil == NULL) { 1524 /* initialize bridge intr routing */ 1525 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1526 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1527 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1528 1529 switch (sc->sc_chipset) { 1530 case CB_TI113X: 1531 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1532 /* functional intr enabled */ 1533 reg |= PCI113X_CBCTRL_PCI_INTR; 1534 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1535 break; 1536 default: 1537 break; 1538 } 1539 } 1540 1541 /* 1542 * Allocate a room for interrupt handler structure. 1543 */ 1544 newpil = (struct pccbb_intrhand_list *) 1545 malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK); 1546 1547 newpil->pil_func = func; 1548 newpil->pil_arg = arg; 1549 newpil->pil_level = level; 1550 evcount_attach(&newpil->pil_count, name, &sc->sc_intrline, 1551 &evcount_intr); 1552 newpil->pil_next = NULL; 1553 1554 if (sc->sc_pil == NULL) { 1555 sc->sc_pil = newpil; 1556 } else { 1557 for (pil = sc->sc_pil; pil->pil_next != NULL; 1558 pil = pil->pil_next); 1559 pil->pil_next = newpil; 1560 } 1561 1562 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1563 1564 return newpil; 1565 } 1566 1567 /* 1568 * void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1569 * void *ih) 1570 * 1571 * This function removes an interrupt handler pointed by ih. 1572 */ 1573 void 1574 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1575 { 1576 struct pccbb_intrhand_list *pil, **pil_prev; 1577 pcireg_t reg; 1578 1579 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1580 1581 pil_prev = &sc->sc_pil; 1582 1583 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1584 if (pil == ih) { 1585 evcount_detach(&pil->pil_count); 1586 *pil_prev = pil->pil_next; 1587 free(pil, M_DEVBUF); 1588 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1589 break; 1590 } 1591 pil_prev = &pil->pil_next; 1592 } 1593 1594 if (sc->sc_pil == NULL) { 1595 /* No interrupt handlers */ 1596 1597 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1598 1599 /* stop routing PCI intr */ 1600 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1601 reg |= CB_BCR_INTR_IREQ_ENABLE; 1602 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1603 1604 switch (sc->sc_chipset) { 1605 case CB_TI113X: 1606 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1607 /* functional intr disabled */ 1608 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1609 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1610 break; 1611 default: 1612 break; 1613 } 1614 } 1615 } 1616 1617 #if defined SHOW_REGS 1618 void 1619 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1620 bus_space_handle_t memh) 1621 { 1622 int i; 1623 printf("PCI config regs:"); 1624 for (i = 0; i < 0x50; i += 4) { 1625 if (i % 16 == 0) { 1626 printf("\n 0x%02x:", i); 1627 } 1628 printf(" %08x", pci_conf_read(pc, tag, i)); 1629 } 1630 for (i = 0x80; i < 0xb0; i += 4) { 1631 if (i % 16 == 0) { 1632 printf("\n 0x%02x:", i); 1633 } 1634 printf(" %08x", pci_conf_read(pc, tag, i)); 1635 } 1636 1637 if (memh == 0) { 1638 printf("\n"); 1639 return; 1640 } 1641 1642 printf("\nsocket regs:"); 1643 for (i = 0; i <= 0x10; i += 0x04) { 1644 printf(" %08x", bus_space_read_4(memt, memh, i)); 1645 } 1646 printf("\nExCA regs:"); 1647 for (i = 0; i < 0x08; ++i) { 1648 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1649 } 1650 printf("\n"); 1651 return; 1652 } 1653 #endif 1654 1655 /* 1656 * cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1657 * int busno, int devno, int function) 1658 * This is the function to make a tag to access config space of 1659 * a CardBus Card. It works same as pci_conf_read. 1660 */ 1661 cardbustag_t 1662 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int devno, int function) 1663 { 1664 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1665 1666 return pci_make_tag(sc->sc_pc, busno, devno, function); 1667 } 1668 1669 void 1670 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1671 { 1672 } 1673 1674 /* 1675 * cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1676 * cardbustag_t tag, int offset) 1677 * This is the function to read the config space of a CardBus Card. 1678 * It works same as pci_conf_read. 1679 */ 1680 cardbusreg_t 1681 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1682 { 1683 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1684 1685 return pci_conf_read(sc->sc_pc, tag, offset); 1686 } 1687 1688 /* 1689 * void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1690 * int offs, cardbusreg_t val) 1691 * This is the function to write the config space of a CardBus Card. 1692 * It works same as pci_conf_write. 1693 */ 1694 void 1695 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1696 cardbusreg_t val) 1697 { 1698 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1699 1700 pci_conf_write(sc->sc_pc, tag, reg, val); 1701 } 1702 1703 #if 0 1704 int 1705 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1706 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1707 int speed, int flags, 1708 bus_space_handle_t * iohp) 1709 #endif 1710 /* 1711 * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1712 * bus_addr_t start, bus_size_t size, 1713 * bus_size_t align, 1714 * struct pcmcia_io_handle *pcihp 1715 * 1716 * This function only allocates I/O region for pccard. This function 1717 * never maps the allocated region to pccard I/O area. 1718 * 1719 * XXX: The interface of this function is not very good, I believe. 1720 */ 1721 int 1722 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1723 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1724 { 1725 struct pcic_handle *ph = (struct pcic_handle *)pch; 1726 bus_addr_t ioaddr; 1727 int flags = 0; 1728 bus_space_tag_t iot; 1729 bus_space_handle_t ioh; 1730 bus_addr_t mask; 1731 rbus_tag_t rb; 1732 1733 if (align == 0) { 1734 align = size; /* XXX: funny??? */ 1735 } 1736 1737 if (start != 0) { 1738 /* XXX: assume all card decode lower 10 bits by its hardware */ 1739 mask = 0x3ff; 1740 /* enforce to use only masked address */ 1741 start &= mask; 1742 } else { 1743 /* 1744 * calculate mask: 1745 * 1. get the most significant bit of size (call it msb). 1746 * 2. compare msb with the value of size. 1747 * 3. if size is larger, shift msb left once. 1748 * 4. obtain mask value to decrement msb. 1749 */ 1750 bus_size_t size_tmp = size; 1751 int shifts = 0; 1752 1753 while (size_tmp) { 1754 ++shifts; 1755 size_tmp >>= 1; 1756 } 1757 mask = (1 << shifts); 1758 if (mask < size) { 1759 mask <<= 1; 1760 } 1761 mask--; 1762 } 1763 1764 /* 1765 * Allocate some arbitrary I/O space. 1766 */ 1767 1768 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1769 1770 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1771 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1772 return 1; 1773 } 1774 1775 pcihp->iot = iot; 1776 pcihp->ioh = ioh; 1777 pcihp->addr = ioaddr; 1778 pcihp->size = size; 1779 pcihp->flags = flags; 1780 1781 return 0; 1782 } 1783 1784 /* 1785 * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1786 * struct pcmcia_io_handle *pcihp) 1787 * 1788 * This function only frees I/O region for pccard. 1789 * 1790 * XXX: The interface of this function is not very good, I believe. 1791 */ 1792 void 1793 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1794 struct pcmcia_io_handle *pcihp) 1795 { 1796 bus_space_handle_t ioh = pcihp->ioh; 1797 bus_size_t size = pcihp->size; 1798 1799 struct pccbb_softc *sc = 1800 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1801 rbus_tag_t rb = sc->sc_rbus_iot; 1802 1803 rbus_space_free(rb, ioh, size, NULL); 1804 } 1805 1806 /* 1807 * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1808 * bus_addr_t offset, bus_size_t size, 1809 * struct pcmcia_io_handle *pcihp, 1810 * int *windowp) 1811 * 1812 * This function maps the allocated I/O region to pccard. This function 1813 * never allocates any I/O region for pccard I/O area. I don't 1814 * understand why the original authors of pcmciabus separated alloc and 1815 * map. I believe the two must be unite. 1816 * 1817 * XXX: no wait timing control? 1818 */ 1819 int 1820 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 1821 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 1822 { 1823 struct pcic_handle *ph = (struct pcic_handle *)pch; 1824 bus_addr_t ioaddr = pcihp->addr + offset; 1825 int i, win; 1826 #if defined CBB_DEBUG 1827 static char *width_names[] = { "dynamic", "io8", "io16" }; 1828 #endif 1829 1830 /* Sanity check I/O handle. */ 1831 1832 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1833 panic("pccbb_pcmcia_io_map iot is bogus"); 1834 } 1835 1836 /* XXX Sanity check offset/size. */ 1837 1838 win = -1; 1839 for (i = 0; i < PCIC_IO_WINS; i++) { 1840 if ((ph->ioalloc & (1 << i)) == 0) { 1841 win = i; 1842 ph->ioalloc |= (1 << i); 1843 break; 1844 } 1845 } 1846 1847 if (win == -1) { 1848 return 1; 1849 } 1850 1851 *windowp = win; 1852 1853 /* XXX this is pretty gross */ 1854 1855 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1856 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1857 1858 /* XXX wtf is this doing here? */ 1859 1860 #if 0 1861 printf(" port 0x%lx", (u_long) ioaddr); 1862 if (size > 1) { 1863 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1864 } 1865 #endif 1866 1867 ph->io[win].addr = ioaddr; 1868 ph->io[win].size = size; 1869 ph->io[win].width = width; 1870 1871 /* actual dirty register-value changing in the function below. */ 1872 pccbb_pcmcia_do_io_map(ph, win); 1873 1874 return 0; 1875 } 1876 1877 /* 1878 * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1879 * 1880 * This function changes register-value to map I/O region for pccard. 1881 */ 1882 void 1883 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 1884 { 1885 static u_int8_t pcic_iowidth[3] = { 1886 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1887 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1888 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1889 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1890 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1891 }; 1892 1893 #define PCIC_SIA_START_LOW 0 1894 #define PCIC_SIA_START_HIGH 1 1895 #define PCIC_SIA_STOP_LOW 2 1896 #define PCIC_SIA_STOP_HIGH 3 1897 1898 int regbase_win = 0x8 + win * 0x04; 1899 u_int8_t ioctl, enable; 1900 1901 DPRINTF( 1902 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1903 win, (long)ph->io[win].addr, (long)ph->io[win].size, 1904 ph->io[win].width * 8)); 1905 1906 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1907 ph->io[win].addr & 0xff); 1908 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1909 (ph->io[win].addr >> 8) & 0xff); 1910 1911 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1912 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1913 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1914 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1915 1916 ioctl = Pcic_read(ph, PCIC_IOCTL); 1917 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1918 switch (win) { 1919 case 0: 1920 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1921 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 1922 PCIC_IOCTL_IO0_DATASIZE_MASK); 1923 ioctl |= pcic_iowidth[ph->io[win].width]; 1924 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1925 break; 1926 case 1: 1927 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1928 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 1929 PCIC_IOCTL_IO1_DATASIZE_MASK); 1930 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1931 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1932 break; 1933 } 1934 Pcic_write(ph, PCIC_IOCTL, ioctl); 1935 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1936 #if defined CBB_DEBUG 1937 { 1938 u_int8_t start_low = 1939 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1940 u_int8_t start_high = 1941 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1942 u_int8_t stop_low = 1943 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1944 u_int8_t stop_high = 1945 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1946 printf 1947 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1948 start_low, start_high, stop_low, stop_high, ioctl, enable); 1949 } 1950 #endif 1951 } 1952 1953 /* 1954 * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1955 * 1956 * This function unmaps I/O region. No return value. 1957 */ 1958 void 1959 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 1960 { 1961 struct pcic_handle *ph = (struct pcic_handle *)pch; 1962 int reg; 1963 1964 if (win >= PCIC_IO_WINS || win < 0) { 1965 panic("pccbb_pcmcia_io_unmap: window out of range"); 1966 } 1967 1968 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1969 switch (win) { 1970 case 0: 1971 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1972 break; 1973 case 1: 1974 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1975 break; 1976 } 1977 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 1978 1979 ph->ioalloc &= ~(1 << win); 1980 } 1981 1982 /* 1983 * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1984 * 1985 * This function enables the card. All information is stored in 1986 * the first argument, pcmcia_chipset_handle_t. 1987 */ 1988 void 1989 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1990 { 1991 int i; 1992 1993 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 1994 Pcic_read(ph, PCIC_IF_STATUS))); 1995 1996 for (i = 0; i < 10000; i++) { 1997 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 1998 return; 1999 } 2000 delay(500); 2001 #ifdef CBB_DEBUG 2002 if ((i > 5000) && (i % 100 == 99)) 2003 printf("."); 2004 #endif 2005 } 2006 2007 #ifdef DIAGNOSTIC 2008 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2009 Pcic_read(ph, PCIC_IF_STATUS)); 2010 #endif 2011 } 2012 2013 /* 2014 * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2015 * 2016 * This function enables the card. All information is stored in 2017 * the first argument, pcmcia_chipset_handle_t. 2018 */ 2019 void 2020 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2021 { 2022 struct pcic_handle *ph = (struct pcic_handle *)pch; 2023 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2024 int cardtype, win; 2025 u_int8_t power, intr; 2026 pcireg_t spsr; 2027 int voltage; 2028 2029 /* this bit is mostly stolen from pcic_attach_card */ 2030 2031 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2032 2033 /* get card Vcc info */ 2034 2035 spsr = 2036 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2037 CB_SOCKET_STAT); 2038 if (spsr & CB_SOCKET_STAT_5VCARD) { 2039 DPRINTF(("5V card\n")); 2040 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2041 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2042 DPRINTF(("3V card\n")); 2043 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2044 } else { 2045 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2046 return; 2047 } 2048 2049 /* disable socket i/o: negate output enable bit */ 2050 2051 power = 0; 2052 Pcic_write(ph, PCIC_PWRCTL, power); 2053 2054 /* power down the socket to reset it, clear the card reset pin */ 2055 2056 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2057 2058 /* 2059 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2060 * we are changing Vcc (Toff). 2061 */ 2062 /* delay(300*1000); too much */ 2063 2064 /* assert reset bit */ 2065 intr = Pcic_read(ph, PCIC_INTR); 2066 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2067 Pcic_write(ph, PCIC_INTR, intr); 2068 2069 /* Power up the socket. */ 2070 power = Pcic_read(ph, PCIC_PWRCTL); 2071 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 2072 pccbb_power(sc, voltage); 2073 2074 /* Now output enable */ 2075 power = Pcic_read(ph, PCIC_PWRCTL); 2076 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2077 2078 /* 2079 * hold RESET at least 10us. 2080 */ 2081 delay(10); 2082 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2083 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2084 2085 /* clear the reset flag */ 2086 2087 intr |= PCIC_INTR_RESET; 2088 Pcic_write(ph, PCIC_INTR, intr); 2089 2090 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2091 2092 delay(20000); 2093 2094 /* wait for the chip to finish initializing */ 2095 2096 pccbb_pcmcia_wait_ready(ph); 2097 2098 /* zero out the address windows */ 2099 2100 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2101 2102 /* set the card type */ 2103 2104 cardtype = pcmcia_card_gettype(ph->pcmcia); 2105 2106 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2107 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2108 Pcic_write(ph, PCIC_INTR, intr); 2109 2110 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2111 ph->ph_parent->dv_xname, ph->sock, 2112 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2113 2114 /* reinstall all the memory and io mappings */ 2115 2116 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2117 if (ph->memalloc & (1 << win)) { 2118 pccbb_pcmcia_do_mem_map(ph, win); 2119 } 2120 } 2121 2122 for (win = 0; win < PCIC_IO_WINS; ++win) { 2123 if (ph->ioalloc & (1 << win)) { 2124 pccbb_pcmcia_do_io_map(ph, win); 2125 } 2126 } 2127 } 2128 2129 /* 2130 * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2131 * 2132 * This function disables the card. All information is stored in 2133 * the first argument, pcmcia_chipset_handle_t. 2134 */ 2135 void 2136 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2137 { 2138 struct pcic_handle *ph = (struct pcic_handle *)pch; 2139 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2140 u_int8_t power, intr; 2141 2142 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2143 2144 /* reset signal asserting... */ 2145 2146 intr = Pcic_read(ph, PCIC_INTR); 2147 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2148 Pcic_write(ph, PCIC_INTR, intr); 2149 delay(2 * 1000); 2150 2151 /* power down the socket */ 2152 power = Pcic_read(ph, PCIC_PWRCTL); 2153 power &= ~PCIC_PWRCTL_OE; 2154 Pcic_write(ph, PCIC_PWRCTL, power); 2155 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2156 /* 2157 * wait 300ms until power fails (Tpf). 2158 */ 2159 delay(300 * 1000); 2160 } 2161 2162 /* 2163 * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2164 * 2165 * This function detects whether a card is in the slot or not. 2166 * If a card is inserted, return 1. Otherwise, return 0. 2167 */ 2168 int 2169 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2170 { 2171 struct pcic_handle *ph = (struct pcic_handle *)pch; 2172 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2173 2174 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2175 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2176 } 2177 2178 #if 0 2179 int 2180 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2181 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2182 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2183 #endif 2184 /* 2185 * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2186 * bus_size_t size, 2187 * struct pcmcia_mem_handle *pcmhp) 2188 * 2189 * This function only allocates memory region for pccard. This 2190 * function never maps the allocated region to pccard memory area. 2191 * 2192 * XXX: Why the argument of start address is not in? 2193 */ 2194 int 2195 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2196 struct pcmcia_mem_handle *pcmhp) 2197 { 2198 struct pcic_handle *ph = (struct pcic_handle *)pch; 2199 bus_space_handle_t memh; 2200 bus_addr_t addr; 2201 bus_size_t sizepg; 2202 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2203 rbus_tag_t rb; 2204 2205 /* out of sc->memh, allocate as many pages as necessary */ 2206 2207 /* convert size to PCIC pages */ 2208 /* 2209 * This is not enough; when the requested region is on the page 2210 * boundaries, this may calculate wrong result. 2211 */ 2212 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2213 #if 0 2214 if (sizepg > PCIC_MAX_MEM_PAGES) { 2215 return 1; 2216 } 2217 #endif 2218 2219 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2220 return 1; 2221 } 2222 2223 addr = 0; /* XXX gcc -Wuninitialized */ 2224 2225 rb = sc->sc_rbus_memt; 2226 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2227 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2228 &addr, &memh)) { 2229 return 1; 2230 } 2231 2232 DPRINTF( 2233 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2234 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2235 2236 pcmhp->memt = sc->sc_memt; 2237 pcmhp->memh = memh; 2238 pcmhp->addr = addr; 2239 pcmhp->size = size; 2240 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2241 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2242 pcmhp->mhandle = 0; 2243 /* No offset??? Funny. */ 2244 2245 return 0; 2246 } 2247 2248 /* 2249 * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2250 * struct pcmcia_mem_handle *pcmhp) 2251 * 2252 * This function release the memory space allocated by the function 2253 * pccbb_pcmcia_mem_alloc(). 2254 */ 2255 void 2256 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2257 struct pcmcia_mem_handle *pcmhp) 2258 { 2259 struct pcic_handle *ph = (struct pcic_handle *)pch; 2260 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2261 2262 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2263 } 2264 2265 /* 2266 * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2267 * 2268 * This function release the memory space allocated by the function 2269 * pccbb_pcmcia_mem_alloc(). 2270 */ 2271 void 2272 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2273 { 2274 int regbase_win; 2275 bus_addr_t phys_addr; 2276 bus_addr_t phys_end; 2277 2278 #define PCIC_SMM_START_LOW 0 2279 #define PCIC_SMM_START_HIGH 1 2280 #define PCIC_SMM_STOP_LOW 2 2281 #define PCIC_SMM_STOP_HIGH 3 2282 #define PCIC_CMA_LOW 4 2283 #define PCIC_CMA_HIGH 5 2284 2285 u_int8_t start_low, start_high = 0; 2286 u_int8_t stop_low, stop_high; 2287 u_int8_t off_low, off_high; 2288 u_int8_t mem_window; 2289 int reg; 2290 2291 regbase_win = 0x10 + win * 0x08; 2292 2293 phys_addr = ph->mem[win].addr; 2294 phys_end = phys_addr + ph->mem[win].size; 2295 2296 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2297 phys_addr, phys_end, ph->mem[win].offset)); 2298 2299 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2300 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2301 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2302 2303 /* bit 19:12 */ 2304 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2305 /* bit 23:20 and bit 7 on */ 2306 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2307 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2308 /* bit 31:24, for 32-bit address */ 2309 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2310 2311 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2312 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2313 2314 if (((struct pccbb_softc *)ph-> 2315 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2316 Pcic_write(ph, 0x40 + win, mem_window); 2317 } 2318 2319 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2320 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2321 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2322 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2323 2324 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2325 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2326 2327 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2328 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2329 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2330 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2331 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2332 2333 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2334 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2335 2336 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2337 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2338 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2339 2340 #if defined CBB_DEBUG 2341 { 2342 int r1, r2, r3, r4, r5, r6, r7 = 0; 2343 2344 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2345 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2346 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2347 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2348 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2349 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2350 if (((struct pccbb_softc *)(ph-> 2351 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2352 r7 = Pcic_read(ph, 0x40 + win); 2353 } 2354 2355 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2356 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2357 if (((struct pccbb_softc *)(ph-> 2358 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2359 DPRINTF((" %02x", r7)); 2360 } 2361 DPRINTF(("\n")); 2362 } 2363 #endif 2364 } 2365 2366 /* 2367 * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2368 * bus_addr_t card_addr, bus_size_t size, 2369 * struct pcmcia_mem_handle *pcmhp, 2370 * bus_size_t *offsetp, int *windowp) 2371 * 2372 * This function maps memory space allocated by the function 2373 * pccbb_pcmcia_mem_alloc(). 2374 */ 2375 int 2376 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2377 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2378 bus_size_t *offsetp, int *windowp) 2379 { 2380 struct pcic_handle *ph = (struct pcic_handle *)pch; 2381 bus_addr_t busaddr; 2382 long card_offset; 2383 int win; 2384 2385 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2386 if ((ph->memalloc & (1 << win)) == 0) { 2387 ph->memalloc |= (1 << win); 2388 break; 2389 } 2390 } 2391 2392 if (win == PCIC_MEM_WINS) { 2393 return 1; 2394 } 2395 2396 *windowp = win; 2397 2398 /* XXX this is pretty gross */ 2399 2400 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2401 panic("pccbb_pcmcia_mem_map memt is bogus"); 2402 } 2403 2404 busaddr = pcmhp->addr; 2405 2406 /* 2407 * compute the address offset to the pcmcia address space for the 2408 * pcic. this is intentionally signed. The masks and shifts below 2409 * will cause TRT to happen in the pcic registers. Deal with making 2410 * sure the address is aligned, and return the alignment offset. 2411 */ 2412 2413 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2414 card_addr -= *offsetp; 2415 2416 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2417 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2418 (u_long) card_addr)); 2419 2420 /* 2421 * include the offset in the size, and decrement size by one, since 2422 * the hw wants start/stop 2423 */ 2424 size += *offsetp - 1; 2425 2426 card_offset = (((long)card_addr) - ((long)busaddr)); 2427 2428 ph->mem[win].addr = busaddr; 2429 ph->mem[win].size = size; 2430 ph->mem[win].offset = card_offset; 2431 ph->mem[win].kind = kind; 2432 2433 pccbb_pcmcia_do_mem_map(ph, win); 2434 2435 return 0; 2436 } 2437 2438 /* 2439 * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2440 * int window) 2441 * 2442 * This function unmaps memory space which mapped by the function 2443 * pccbb_pcmcia_mem_map(). 2444 */ 2445 void 2446 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2447 { 2448 struct pcic_handle *ph = (struct pcic_handle *)pch; 2449 int reg; 2450 2451 if (window >= PCIC_MEM_WINS) { 2452 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2453 } 2454 2455 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2456 reg &= ~(1 << window); 2457 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2458 2459 ph->memalloc &= ~(1 << window); 2460 } 2461 2462 #if defined PCCBB_PCMCIA_POLL 2463 struct pccbb_poll_str { 2464 void *arg; 2465 int (*func)(void *); 2466 int level; 2467 struct pcic_handle *ph; 2468 int count; 2469 int num; 2470 }; 2471 2472 static struct pccbb_poll_str pccbb_poll[10]; 2473 static int pccbb_poll_n = 0; 2474 static struct timeout pccbb_poll_timeout; 2475 2476 void pccbb_pcmcia_poll(void *arg); 2477 2478 void 2479 pccbb_pcmcia_poll(void *arg) 2480 { 2481 struct pccbb_poll_str *poll = arg; 2482 struct pcic_handle *ph = poll->ph; 2483 struct pccbb_softc *sc = ph->sc; 2484 int s; 2485 u_int32_t spsr; /* socket present-state reg */ 2486 2487 timeout_set(&pccbb_poll_timeout, pccbb_pcmcia_poll, arg); 2488 timeout_add_sec(&pccbb_poll_timeout, 2); 2489 switch (poll->level) { 2490 case IPL_NET: 2491 s = splnet(); 2492 break; 2493 case IPL_BIO: 2494 s = splbio(); 2495 break; 2496 case IPL_TTY: /* fallthrough */ 2497 default: 2498 s = spltty(); 2499 break; 2500 } 2501 2502 spsr = 2503 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2504 CB_SOCKET_STAT); 2505 2506 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2507 if (!(spsr & 0x40)) /* CINT low */ 2508 #else 2509 if (1) 2510 #endif 2511 { 2512 if ((*poll->func) (poll->arg) > 0) { 2513 ++poll->count; 2514 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2515 #if defined LEVEL2 2516 } else { 2517 printf("intr: miss! 0x%x\n", spsr); 2518 #endif 2519 } 2520 } 2521 splx(s); 2522 } 2523 #endif /* defined CB_PCMCIA_POLL */ 2524 2525 /* 2526 * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2527 * struct pcmcia_function *pf, 2528 * int ipl, 2529 * int (*func)(void *), 2530 * void *arg); 2531 * 2532 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2533 */ 2534 void * 2535 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2536 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg, 2537 char *xname) 2538 { 2539 struct pcic_handle *ph = (struct pcic_handle *)pch; 2540 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2541 2542 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2543 /* what should I do? */ 2544 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2545 DPRINTF( 2546 ("%s does not provide edge nor pulse interrupt\n", 2547 sc->sc_dev.dv_xname)); 2548 return NULL; 2549 } 2550 /* 2551 * XXX Noooooo! The interrupt flag must set properly!! 2552 * dumb pcmcia driver!! 2553 */ 2554 } 2555 2556 return pccbb_intr_establish(sc, -1, ipl, func, arg, xname); 2557 } 2558 2559 /* 2560 * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2561 * void *ih) 2562 * 2563 * This function disables PC-Card interrupt. 2564 */ 2565 void 2566 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2567 { 2568 struct pcic_handle *ph = (struct pcic_handle *)pch; 2569 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2570 2571 pccbb_intr_disestablish(sc, ih); 2572 } 2573 2574 const char * 2575 pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t pch, void *ih) 2576 { 2577 if (ih == NULL) 2578 return "couldn't establish interrupt"; 2579 else 2580 return ""; /* card shares interrupt of the bridge */ 2581 } 2582 2583 /* 2584 * int 2585 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2586 * bus_addr_t addr, bus_size_t size, 2587 * bus_addr_t mask, bus_size_t align, 2588 * int flags, bus_addr_t *addrp; 2589 * bus_space_handle_t *bshp) 2590 * 2591 * This function allocates a portion of memory or io space for 2592 * clients. This function is called from CardBus card drivers. 2593 */ 2594 int 2595 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2596 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2597 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2598 { 2599 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2600 2601 DPRINTF( 2602 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2603 addr, size, mask, align)); 2604 2605 if (align == 0) { 2606 align = size; 2607 } 2608 2609 if (rb->rb_bt == sc->sc_memt) { 2610 if (align < 16) { 2611 return 1; 2612 } 2613 } else if (rb->rb_bt == sc->sc_iot) { 2614 if (align < 4) { 2615 return 1; 2616 } 2617 /* XXX: hack for avoiding ISA image */ 2618 if (mask < 0x0100) { 2619 mask = 0x3ff; 2620 addr = 0x300; 2621 } 2622 2623 } else { 2624 DPRINTF( 2625 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2626 rb->rb_bt)); 2627 return 1; 2628 /* XXX: panic here? */ 2629 } 2630 2631 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2632 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2633 return 1; 2634 } 2635 2636 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2637 2638 return 0; 2639 } 2640 2641 /* 2642 * int 2643 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2644 * bus_space_handle_t *bshp, bus_size_t size); 2645 * 2646 * This function is called from CardBus card drivers. 2647 */ 2648 int 2649 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2650 bus_space_handle_t bsh, bus_size_t size) 2651 { 2652 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2653 bus_space_tag_t bt = rb->rb_bt; 2654 2655 pccbb_close_win(sc, bt, bsh, size); 2656 2657 if (bt == sc->sc_memt) { 2658 } else if (bt == sc->sc_iot) { 2659 } else { 2660 return 1; 2661 /* XXX: panic here? */ 2662 } 2663 2664 return rbus_space_free(rb, bsh, size, NULL); 2665 } 2666 2667 int 2668 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2669 bus_size_t size, bus_space_handle_t bsh, int flags) 2670 { 2671 struct pccbb_win_chain_head *head; 2672 bus_addr_t align; 2673 2674 head = &sc->sc_iowindow; 2675 align = 0x04; 2676 if (sc->sc_memt == bst) { 2677 head = &sc->sc_memwindow; 2678 align = 0x1000; 2679 DPRINTF(("using memory window, %x %x %x\n\n", 2680 sc->sc_iot, sc->sc_memt, bst)); 2681 } 2682 2683 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2684 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2685 sc->sc_dev.dv_xname, 2686 (head == &sc->sc_memwindow) ? "mem" : "io"); 2687 } 2688 pccbb_winset(align, sc, bst); 2689 2690 return 0; 2691 } 2692 2693 int 2694 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2695 bus_space_handle_t bsh, bus_size_t size) 2696 { 2697 struct pccbb_win_chain_head *head; 2698 bus_addr_t align; 2699 2700 head = &sc->sc_iowindow; 2701 align = 0x04; 2702 if (sc->sc_memt == bst) { 2703 head = &sc->sc_memwindow; 2704 align = 0x1000; 2705 } 2706 2707 if (pccbb_winlist_delete(head, bsh, size)) { 2708 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2709 sc->sc_dev.dv_xname, 2710 (head == &sc->sc_memwindow) ? "mem" : "io"); 2711 } 2712 pccbb_winset(align, sc, bst); 2713 2714 return 0; 2715 } 2716 2717 int 2718 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2719 bus_size_t size, bus_space_handle_t bsh, int flags) 2720 { 2721 struct pccbb_win_chain *chainp, *elem; 2722 2723 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2724 M_NOWAIT)) == NULL) 2725 return (1); /* fail */ 2726 2727 elem->wc_start = start; 2728 elem->wc_end = start + (size - 1); 2729 elem->wc_handle = bsh; 2730 elem->wc_flags = flags; 2731 2732 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2733 chainp = TAILQ_NEXT(chainp, wc_list)) { 2734 if (chainp->wc_end < start) 2735 continue; 2736 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2737 return (0); 2738 } 2739 2740 TAILQ_INSERT_TAIL(head, elem, wc_list); 2741 return (0); 2742 } 2743 2744 int 2745 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2746 bus_size_t size) 2747 { 2748 struct pccbb_win_chain *chainp; 2749 2750 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2751 chainp = TAILQ_NEXT(chainp, wc_list)) { 2752 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 2753 continue; 2754 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2755 printf("pccbb_winlist_delete: window 0x%lx size " 2756 "inconsistent: 0x%lx, 0x%lx\n", 2757 chainp->wc_start, 2758 chainp->wc_end - chainp->wc_start, 2759 size - 1); 2760 return 1; 2761 } 2762 2763 TAILQ_REMOVE(head, chainp, wc_list); 2764 free(chainp, M_DEVBUF); 2765 2766 return 0; 2767 } 2768 2769 return 1; /* fail: no candidate to remove */ 2770 } 2771 2772 void 2773 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 2774 { 2775 pci_chipset_tag_t pc; 2776 pcitag_t tag; 2777 bus_addr_t mask = ~(align - 1); 2778 struct { 2779 cardbusreg_t win_start; 2780 cardbusreg_t win_limit; 2781 int win_flags; 2782 } win[2]; 2783 struct pccbb_win_chain *chainp; 2784 int offs; 2785 2786 win[0].win_start = win[1].win_start = 0xffffffff; 2787 win[0].win_limit = win[1].win_limit = 0; 2788 win[0].win_flags = win[1].win_flags = 0; 2789 2790 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2791 offs = PCI_CB_IOBASE0; 2792 if (sc->sc_memt == bst) { 2793 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2794 offs = PCI_CB_MEMBASE0; 2795 } 2796 2797 if (chainp != NULL) { 2798 win[0].win_start = chainp->wc_start & mask; 2799 win[0].win_limit = chainp->wc_end & mask; 2800 win[0].win_flags = chainp->wc_flags; 2801 chainp = TAILQ_NEXT(chainp, wc_list); 2802 } 2803 2804 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2805 if (win[1].win_start == 0xffffffff) { 2806 /* window 1 is not used */ 2807 if ((win[0].win_flags == chainp->wc_flags) && 2808 (win[0].win_limit + align >= 2809 (chainp->wc_start & mask))) { 2810 /* concatenate */ 2811 win[0].win_limit = chainp->wc_end & mask; 2812 } else { 2813 /* make new window */ 2814 win[1].win_start = chainp->wc_start & mask; 2815 win[1].win_limit = chainp->wc_end & mask; 2816 win[1].win_flags = chainp->wc_flags; 2817 } 2818 continue; 2819 } 2820 2821 /* Both windows are engaged. */ 2822 if (win[0].win_flags == win[1].win_flags) { 2823 /* same flags */ 2824 if (win[0].win_flags == chainp->wc_flags) { 2825 if (win[1].win_start - (win[0].win_limit + 2826 align) < 2827 (chainp->wc_start & mask) - 2828 ((chainp->wc_end & mask) + align)) { 2829 /* 2830 * merge window 0 and 1, and set win1 2831 * to chainp 2832 */ 2833 win[0].win_limit = win[1].win_limit; 2834 win[1].win_start = 2835 chainp->wc_start & mask; 2836 win[1].win_limit = 2837 chainp->wc_end & mask; 2838 } else { 2839 win[1].win_limit = 2840 chainp->wc_end & mask; 2841 } 2842 } else { 2843 /* different flags */ 2844 2845 /* concatenate win0 and win1 */ 2846 win[0].win_limit = win[1].win_limit; 2847 /* allocate win[1] to new space */ 2848 win[1].win_start = chainp->wc_start & mask; 2849 win[1].win_limit = chainp->wc_end & mask; 2850 win[1].win_flags = chainp->wc_flags; 2851 } 2852 } else { 2853 /* the flags of win[0] and win[1] are different */ 2854 if (win[0].win_flags == chainp->wc_flags) { 2855 win[0].win_limit = chainp->wc_end & mask; 2856 /* 2857 * XXX this creates overlapping windows, so 2858 * what should the poor bridge do if one is 2859 * cachable, and the other is not? 2860 */ 2861 printf("%s: overlapping windows\n", 2862 sc->sc_dev.dv_xname); 2863 } else { 2864 win[1].win_limit = chainp->wc_end & mask; 2865 } 2866 } 2867 } 2868 2869 pc = sc->sc_pc; 2870 tag = sc->sc_tag; 2871 pci_conf_write(pc, tag, offs, win[0].win_start); 2872 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 2873 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 2874 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 2875 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 2876 pci_conf_read(pc, tag, offs), 2877 pci_conf_read(pc, tag, offs + 4) + align, 2878 pci_conf_read(pc, tag, offs + 8), 2879 pci_conf_read(pc, tag, offs + 12) + align)); 2880 2881 if (bst == sc->sc_memt) { 2882 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 2883 2884 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 2885 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 2886 bcr |= CB_BCR_PREFETCH_MEMWIN0; 2887 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 2888 bcr |= CB_BCR_PREFETCH_MEMWIN1; 2889 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 2890 } 2891 } 2892 2893 void 2894 pccbb_powerhook(int why, void *arg) 2895 { 2896 struct pccbb_softc *sc = arg; 2897 u_int32_t reg; 2898 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 2899 bus_space_handle_t base_memh = sc->sc_base_memh; 2900 2901 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 2902 2903 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 2904 DPRINTF(("%s: power: why %d stopping intr\n", 2905 sc->sc_dev.dv_xname, why)); 2906 if (sc->sc_pil_intr_enable) { 2907 (void)pccbbintr_function(sc); 2908 } 2909 sc->sc_pil_intr_enable = 0; 2910 2911 /* ToDo: deactivate or suspend child devices */ 2912 2913 } 2914 2915 if (why == PWR_RESUME) { 2916 if (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 2917 /* BIOS did not recover this register */ 2918 pci_conf_write(sc->sc_pc, sc->sc_tag, 2919 PCI_SOCKBASE, sc->sc_sockbase); 2920 if (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 2921 /* BIOS did not recover this register */ 2922 pci_conf_write(sc->sc_pc, sc->sc_tag, 2923 PCI_BUSNUM, sc->sc_busnum); 2924 /* CSC Interrupt: Card detect interrupt on */ 2925 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 2926 /* Card detect intr is turned on. */ 2927 reg |= CB_SOCKET_MASK_CD; 2928 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 2929 /* reset interrupt */ 2930 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 2931 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 2932 2933 /* 2934 * check for card insertion or removal during suspend period. 2935 * XXX: the code can't cope with card swap (remove then 2936 * insert). how can we detect such situation? 2937 */ 2938 (void)pccbbintr(sc); 2939 2940 sc->sc_pil_intr_enable = 1; 2941 DPRINTF(("%s: power: RESUME enabling intr\n", 2942 sc->sc_dev.dv_xname)); 2943 2944 /* ToDo: activate or wakeup child devices */ 2945 } 2946 } 2947