1 /* $OpenBSD: qle.c,v 1.38 2015/09/11 10:19:05 jmatthew Exp $ */ 2 3 /* 4 * Copyright (c) 2013, 2014 Jonathan Matthew <jmatthew@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "bio.h" 20 21 #include <sys/param.h> 22 #include <sys/systm.h> 23 #include <sys/malloc.h> 24 #include <sys/device.h> 25 #include <sys/sensors.h> 26 #include <sys/rwlock.h> 27 #include <sys/task.h> 28 29 #include <machine/atomic.h> 30 #include <machine/bus.h> 31 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 36 #ifdef __sparc64__ 37 #include <dev/ofw/openfirm.h> 38 #endif 39 40 #include <scsi/scsi_all.h> 41 #include <scsi/scsiconf.h> 42 43 #include <dev/pci/qlereg.h> 44 45 #ifdef QLE_DEBUG 46 #define DPRINTF(m, f...) do { if ((qledebug & (m)) == (m)) printf(f); } \ 47 while (0) 48 #define QLE_D_MBOX 0x01 49 #define QLE_D_INTR 0x02 50 #define QLE_D_PORT 0x04 51 #define QLE_D_IO 0x08 52 #define QLE_D_IOCB 0x10 53 int qledebug = QLE_D_PORT; 54 #else 55 #define DPRINTF(m, f...) 56 #endif 57 58 #ifndef QLE_NOFIRMWARE 59 #include <dev/microcode/isp/asm_2400.h> 60 #include <dev/microcode/isp/asm_2500.h> 61 #endif 62 63 #define QLE_PCI_MEM_BAR 0x14 64 #define QLE_PCI_IO_BAR 0x10 65 66 67 #define QLE_DEFAULT_PORT_NAME 0x400000007F000003ULL /* from isp(4) */ 68 69 #define QLE_WAIT_FOR_LOOP 10 70 71 /* rounded up range of assignable handles */ 72 #define QLE_MAX_TARGETS 2048 73 74 /* maximum number of segments allowed for in a single io */ 75 #define QLE_MAX_SEGS 32 76 77 enum qle_isp_gen { 78 QLE_GEN_ISP24XX = 1, 79 QLE_GEN_ISP25XX 80 }; 81 82 enum qle_isp_type { 83 QLE_ISP2422 = 1, 84 QLE_ISP2432, 85 QLE_ISP2512, 86 QLE_ISP2522, 87 QLE_ISP2532 88 }; 89 90 /* port database things */ 91 #define QLE_SCRATCH_SIZE 0x1000 92 93 enum qle_port_disp { 94 QLE_PORT_DISP_NEW, 95 QLE_PORT_DISP_GONE, 96 QLE_PORT_DISP_SAME, 97 QLE_PORT_DISP_CHANGED, 98 QLE_PORT_DISP_MOVED, 99 QLE_PORT_DISP_DUP 100 }; 101 102 #define QLE_LOCATION_LOOP (1 << 24) 103 #define QLE_LOCATION_FABRIC (2 << 24) 104 #define QLE_LOCATION_LOOP_ID(l) (l | QLE_LOCATION_LOOP) 105 #define QLE_LOCATION_PORT_ID(p) (p | QLE_LOCATION_FABRIC) 106 107 struct qle_fc_port { 108 TAILQ_ENTRY(qle_fc_port) ports; 109 TAILQ_ENTRY(qle_fc_port) update; 110 111 u_int64_t node_name; 112 u_int64_t port_name; 113 u_int32_t location; /* port id or loop id */ 114 115 int flags; 116 #define QLE_PORT_FLAG_IS_TARGET 1 117 #define QLE_PORT_FLAG_NEEDS_LOGIN 2 118 119 u_int32_t portid; 120 u_int16_t loopid; 121 }; 122 123 124 /* request/response queue stuff */ 125 #define QLE_QUEUE_ENTRY_SIZE 64 126 127 struct qle_ccb { 128 struct qle_softc *ccb_sc; 129 int ccb_id; 130 struct scsi_xfer *ccb_xs; 131 132 bus_dmamap_t ccb_dmamap; 133 134 struct qle_iocb_seg *ccb_segs; 135 u_int64_t ccb_seg_offset; 136 137 SIMPLEQ_ENTRY(qle_ccb) ccb_link; 138 }; 139 140 SIMPLEQ_HEAD(qle_ccb_list, qle_ccb); 141 142 struct qle_dmamem { 143 bus_dmamap_t qdm_map; 144 bus_dma_segment_t qdm_seg; 145 size_t qdm_size; 146 caddr_t qdm_kva; 147 }; 148 #define QLE_DMA_MAP(_qdm) ((_qdm)->qdm_map) 149 #define QLE_DMA_LEN(_qdm) ((_qdm)->qdm_size) 150 #define QLE_DMA_DVA(_qdm) ((u_int64_t)(_qdm)->qdm_map->dm_segs[0].ds_addr) 151 #define QLE_DMA_KVA(_qdm) ((void *)(_qdm)->qdm_kva) 152 153 struct qle_softc { 154 struct device sc_dev; 155 156 pci_chipset_tag_t sc_pc; 157 pcitag_t sc_tag; 158 159 void *sc_ih; 160 bus_space_tag_t sc_iot; 161 bus_space_handle_t sc_ioh; 162 bus_size_t sc_ios; 163 bus_dma_tag_t sc_dmat; 164 165 struct scsi_link sc_link; 166 167 struct scsibus_softc *sc_scsibus; 168 169 enum qle_isp_type sc_isp_type; 170 enum qle_isp_gen sc_isp_gen; 171 int sc_port; 172 173 bus_space_handle_t sc_mbox_ioh; 174 u_int16_t sc_mbox[QLE_MBOX_COUNT]; 175 int sc_mbox_pending; 176 struct mutex sc_mbox_mtx; 177 178 int sc_loop_up; 179 int sc_topology; 180 int sc_loop_id; 181 int sc_port_id; 182 int sc_loop_max_id; 183 u_int64_t sc_sns_port_name; 184 185 struct mutex sc_port_mtx; 186 TAILQ_HEAD(, qle_fc_port) sc_ports; 187 TAILQ_HEAD(, qle_fc_port) sc_ports_new; 188 TAILQ_HEAD(, qle_fc_port) sc_ports_gone; 189 TAILQ_HEAD(, qle_fc_port) sc_ports_found; 190 struct qle_fc_port *sc_targets[QLE_MAX_TARGETS]; 191 192 struct taskq *sc_update_taskq; 193 struct task sc_update_task; 194 int sc_update; 195 int sc_update_tasks; 196 #define QLE_UPDATE_TASK_CLEAR_ALL 0x00000001 197 #define QLE_UPDATE_TASK_SOFTRESET 0x00000002 198 #define QLE_UPDATE_TASK_UPDATE_TOPO 0x00000004 199 #define QLE_UPDATE_TASK_GET_PORT_LIST 0x00000008 200 #define QLE_UPDATE_TASK_PORT_LIST 0x00000010 201 #define QLE_UPDATE_TASK_SCAN_FABRIC 0x00000020 202 #define QLE_UPDATE_TASK_SCANNING_FABRIC 0x00000040 203 #define QLE_UPDATE_TASK_FABRIC_LOGIN 0x00000080 204 #define QLE_UPDATE_TASK_FABRIC_RELOGIN 0x00000100 205 #define QLE_UPDATE_TASK_DETACH_TARGET 0x00000200 206 #define QLE_UPDATE_TASK_ATTACH_TARGET 0x00000400 207 208 int sc_maxcmds; 209 struct qle_dmamem *sc_requests; 210 struct qle_dmamem *sc_responses; 211 struct qle_dmamem *sc_segments; 212 struct qle_dmamem *sc_pri_requests; 213 struct qle_dmamem *sc_scratch; 214 struct qle_dmamem *sc_fcp_cmnds; 215 struct qle_ccb *sc_ccbs; 216 struct qle_ccb_list sc_ccb_free; 217 struct mutex sc_ccb_mtx; 218 struct mutex sc_queue_mtx; 219 struct scsi_iopool sc_iopool; 220 u_int32_t sc_next_req_id; 221 u_int32_t sc_last_resp_id; 222 int sc_marker_required; 223 int sc_fabric_pending; 224 u_int8_t sc_fabric_response[QLE_QUEUE_ENTRY_SIZE]; 225 226 struct qle_nvram sc_nvram; 227 int sc_nvram_valid; 228 }; 229 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 230 231 int qle_intr(void *); 232 233 int qle_match(struct device *, void *, void *); 234 void qle_attach(struct device *, struct device *, void *); 235 int qle_detach(struct device *, int); 236 237 struct cfattach qle_ca = { 238 sizeof(struct qle_softc), 239 qle_match, 240 qle_attach, 241 qle_detach 242 }; 243 244 struct cfdriver qle_cd = { 245 NULL, 246 "qle", 247 DV_DULL 248 }; 249 250 void qle_scsi_cmd(struct scsi_xfer *); 251 int qle_scsi_probe(struct scsi_link *); 252 253 254 struct scsi_adapter qle_switch = { 255 qle_scsi_cmd, 256 scsi_minphys, 257 qle_scsi_probe, 258 NULL, /* scsi_free */ 259 NULL /* ioctl */ 260 }; 261 262 u_int32_t qle_read(struct qle_softc *, int); 263 void qle_write(struct qle_softc *, int, u_int32_t); 264 void qle_host_cmd(struct qle_softc *sc, u_int32_t); 265 266 int qle_mbox(struct qle_softc *, int); 267 int qle_ct_pass_through(struct qle_softc *sc, 268 u_int32_t port_handle, struct qle_dmamem *mem, 269 size_t req_size, size_t resp_size); 270 void qle_mbox_putaddr(u_int16_t *, struct qle_dmamem *); 271 u_int16_t qle_read_mbox(struct qle_softc *, int); 272 void qle_write_mbox(struct qle_softc *, int, u_int16_t); 273 274 void qle_handle_intr(struct qle_softc *, u_int16_t, u_int16_t); 275 void qle_set_ints(struct qle_softc *, int); 276 int qle_read_isr(struct qle_softc *, u_int16_t *, u_int16_t *); 277 void qle_clear_isr(struct qle_softc *, u_int16_t); 278 279 void qle_put_marker(struct qle_softc *, void *); 280 void qle_put_cmd(struct qle_softc *, void *, struct scsi_xfer *, 281 struct qle_ccb *, u_int32_t); 282 struct qle_ccb *qle_handle_resp(struct qle_softc *, u_int32_t); 283 void qle_sge(struct qle_iocb_seg *, u_int64_t, u_int32_t); 284 285 struct qle_fc_port *qle_next_fabric_port(struct qle_softc *, u_int32_t *, 286 u_int32_t *); 287 int qle_get_port_db(struct qle_softc *, u_int16_t, 288 struct qle_dmamem *); 289 int qle_get_port_name_list(struct qle_softc *sc, u_int32_t); 290 int qle_add_loop_port(struct qle_softc *, struct qle_fc_port *); 291 int qle_add_fabric_port(struct qle_softc *, struct qle_fc_port *); 292 int qle_add_logged_in_port(struct qle_softc *, u_int16_t, 293 u_int32_t); 294 int qle_classify_port(struct qle_softc *, u_int32_t, u_int64_t, 295 u_int64_t, struct qle_fc_port **); 296 int qle_get_loop_id(struct qle_softc *sc, int); 297 void qle_clear_port_lists(struct qle_softc *); 298 int qle_softreset(struct qle_softc *); 299 void qle_update_topology(struct qle_softc *); 300 int qle_update_fabric(struct qle_softc *); 301 int qle_fabric_plogx(struct qle_softc *, struct qle_fc_port *, int, 302 u_int32_t *); 303 int qle_fabric_plogi(struct qle_softc *, struct qle_fc_port *); 304 void qle_fabric_plogo(struct qle_softc *, struct qle_fc_port *); 305 306 void qle_update_start(struct qle_softc *, int); 307 void qle_update_done(struct qle_softc *, int); 308 void qle_do_update(void *); 309 int qle_async(struct qle_softc *, u_int16_t); 310 311 int qle_load_fwchunk(struct qle_softc *, 312 struct qle_dmamem *, const u_int32_t *); 313 u_int32_t qle_read_ram_word(struct qle_softc *, u_int32_t); 314 int qle_verify_firmware(struct qle_softc *, u_int32_t); 315 int qle_load_firmware_chunks(struct qle_softc *, const u_int32_t *); 316 int qle_read_nvram(struct qle_softc *); 317 318 struct qle_dmamem *qle_dmamem_alloc(struct qle_softc *, size_t); 319 void qle_dmamem_free(struct qle_softc *, struct qle_dmamem *); 320 321 int qle_alloc_ccbs(struct qle_softc *); 322 void qle_free_ccbs(struct qle_softc *); 323 void *qle_get_ccb(void *); 324 void qle_put_ccb(void *, void *); 325 326 void qle_dump_stuff(struct qle_softc *, void *, int); 327 void qle_dump_iocb(struct qle_softc *, void *); 328 void qle_dump_iocb_segs(struct qle_softc *, void *, int); 329 330 static const struct pci_matchid qle_devices[] = { 331 { PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP2422 }, 332 { PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP2432 }, 333 { PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP2512 }, 334 { PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP2522 }, 335 { PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP2532 }, 336 }; 337 338 int 339 qle_match(struct device *parent, void *match, void *aux) 340 { 341 return (pci_matchbyid(aux, qle_devices, nitems(qle_devices))); 342 } 343 344 void 345 qle_attach(struct device *parent, struct device *self, void *aux) 346 { 347 struct qle_softc *sc = (void *)self; 348 struct pci_attach_args *pa = aux; 349 pci_intr_handle_t ih; 350 const char *intrstr; 351 u_int32_t pcictl; 352 struct scsibus_attach_args saa; 353 struct qle_init_cb *icb; 354 bus_size_t mbox_base; 355 u_int32_t firmware_addr; 356 #ifndef QLE_NOFIRMWARE 357 const u_int32_t *firmware = NULL; 358 #endif 359 360 pcireg_t bars[] = { QLE_PCI_MEM_BAR, QLE_PCI_IO_BAR }; 361 pcireg_t memtype; 362 int r, i, rv; 363 364 sc->sc_pc = pa->pa_pc; 365 sc->sc_tag = pa->pa_tag; 366 sc->sc_ih = NULL; 367 sc->sc_dmat = pa->pa_dmat; 368 sc->sc_ios = 0; 369 370 for (r = 0; r < nitems(bars); r++) { 371 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, bars[r]); 372 if (pci_mapreg_map(pa, bars[r], memtype, 0, 373 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_ios, 0) == 0) 374 break; 375 376 sc->sc_ios = 0; 377 } 378 if (sc->sc_ios == 0) { 379 printf(": unable to map registers\n"); 380 return; 381 } 382 383 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 384 printf(": unable to map interrupt\n"); 385 goto unmap; 386 } 387 intrstr = pci_intr_string(sc->sc_pc, ih); 388 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_BIO, 389 qle_intr, sc, DEVNAME(sc)); 390 if (sc->sc_ih == NULL) { 391 printf(": unable to establish interrupt"); 392 if (intrstr != NULL) 393 printf(" at %s", intrstr); 394 printf("\n"); 395 goto deintr; 396 } 397 398 printf(": %s\n", intrstr); 399 400 pcictl = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 401 pcictl |= PCI_COMMAND_INVALIDATE_ENABLE | 402 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 403 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, pcictl); 404 405 pcictl = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 406 pcictl &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 407 pcictl &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 408 pcictl |= (0x80 << PCI_LATTIMER_SHIFT); 409 pcictl |= (0x10 << PCI_CACHELINE_SHIFT); 410 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, pcictl); 411 412 pcictl = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 413 pcictl &= ~1; 414 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, pcictl); 415 416 switch (PCI_PRODUCT(pa->pa_id)) { 417 case PCI_PRODUCT_QLOGIC_ISP2422: 418 sc->sc_isp_type = QLE_ISP2422; 419 sc->sc_isp_gen = QLE_GEN_ISP24XX; 420 break; 421 case PCI_PRODUCT_QLOGIC_ISP2432: 422 sc->sc_isp_type = QLE_ISP2432; 423 sc->sc_isp_gen = QLE_GEN_ISP24XX; 424 break; 425 case PCI_PRODUCT_QLOGIC_ISP2512: 426 sc->sc_isp_type = QLE_ISP2512; 427 sc->sc_isp_gen = QLE_GEN_ISP25XX; 428 break; 429 case PCI_PRODUCT_QLOGIC_ISP2522: 430 sc->sc_isp_type = QLE_ISP2522; 431 sc->sc_isp_gen = QLE_GEN_ISP25XX; 432 break; 433 case PCI_PRODUCT_QLOGIC_ISP2532: 434 sc->sc_isp_type = QLE_ISP2532; 435 sc->sc_isp_gen = QLE_GEN_ISP25XX; 436 break; 437 438 default: 439 printf("unknown pci id %x", pa->pa_id); 440 goto deintr; 441 } 442 443 /* these are the same for 24xx and 25xx but may vary later */ 444 mbox_base = QLE_MBOX_BASE_24XX; 445 firmware_addr = QLE_2400_CODE_ORG; 446 447 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, mbox_base, 448 sizeof(sc->sc_mbox), &sc->sc_mbox_ioh) != 0) { 449 printf("%s: unable to map mbox registers\n", DEVNAME(sc)); 450 goto deintr; 451 } 452 453 sc->sc_port = pa->pa_function; 454 455 TAILQ_INIT(&sc->sc_ports); 456 TAILQ_INIT(&sc->sc_ports_new); 457 TAILQ_INIT(&sc->sc_ports_gone); 458 TAILQ_INIT(&sc->sc_ports_found); 459 460 /* after reset, mbox regs 1 and 2 contain the string "ISP " */ 461 if (qle_read_mbox(sc, 1) != 0x4953 || 462 qle_read_mbox(sc, 2) != 0x5020) { 463 /* try releasing the risc processor */ 464 printf("%s: bad startup mboxes: %x %x\n", DEVNAME(sc), 465 qle_read_mbox(sc, 1), qle_read_mbox(sc, 2)); 466 qle_host_cmd(sc, QLE_HOST_CMD_RELEASE); 467 } 468 469 qle_host_cmd(sc, QLE_HOST_CMD_PAUSE); 470 if (qle_softreset(sc) != 0) { 471 printf("softreset failed\n"); 472 goto deintr; 473 } 474 475 if (qle_read_nvram(sc) == 0) 476 sc->sc_nvram_valid = 1; 477 478 #ifdef QLE_NOFIRMWARE 479 if (qle_verify_firmware(sc, firmware_addr)) { 480 printf("%s: no firmware loaded\n", DEVNAME(sc)); 481 goto deintr; 482 } 483 #else 484 switch (sc->sc_isp_gen) { 485 case QLE_GEN_ISP24XX: 486 firmware = isp_2400_risc_code; 487 break; 488 case QLE_GEN_ISP25XX: 489 firmware = isp_2500_risc_code; 490 break; 491 default: 492 printf("%s: no firmware to load?\n", DEVNAME(sc)); 493 goto deintr; 494 } 495 if (qle_load_firmware_chunks(sc, firmware)) { 496 printf("%s: firmware load failed\n", DEVNAME(sc)); 497 goto deintr; 498 } 499 #endif 500 501 /* execute firmware */ 502 sc->sc_mbox[0] = QLE_MBOX_EXEC_FIRMWARE; 503 sc->sc_mbox[1] = firmware_addr >> 16; 504 sc->sc_mbox[2] = firmware_addr & 0xffff; 505 #ifdef QLE_NOFIRMWARE 506 sc->sc_mbox[3] = 1; 507 #else 508 sc->sc_mbox[3] = 0; 509 #endif 510 sc->sc_mbox[4] = 0; 511 if (qle_mbox(sc, 0x001f)) { 512 printf("ISP couldn't exec firmware: %x\n", sc->sc_mbox[0]); 513 goto deintr; 514 } 515 516 delay(250000); /* from isp(4) */ 517 518 sc->sc_mbox[0] = QLE_MBOX_ABOUT_FIRMWARE; 519 if (qle_mbox(sc, 0x0001)) { 520 printf("ISP not talking after firmware exec: %x\n", 521 sc->sc_mbox[0]); 522 goto deintr; 523 } 524 printf("%s: firmware rev %d.%d.%d, attrs 0x%x\n", DEVNAME(sc), 525 sc->sc_mbox[1], sc->sc_mbox[2], sc->sc_mbox[3], sc->sc_mbox[6]); 526 527 sc->sc_maxcmds = 4096; 528 529 /* reserve queue slots for markers and fabric ops */ 530 sc->sc_maxcmds -= 2; 531 532 if (qle_alloc_ccbs(sc)) { 533 /* error already printed */ 534 goto deintr; 535 } 536 sc->sc_scratch = qle_dmamem_alloc(sc, QLE_SCRATCH_SIZE); 537 if (sc->sc_scratch == NULL) { 538 printf("%s: unable to allocate scratch\n", DEVNAME(sc)); 539 goto free_ccbs; 540 } 541 542 /* build init buffer thing */ 543 icb = (struct qle_init_cb *)QLE_DMA_KVA(sc->sc_scratch); 544 memset(icb, 0, sizeof(*icb)); 545 icb->icb_version = QLE_ICB_VERSION; 546 if (sc->sc_nvram_valid) { 547 icb->icb_max_frame_len = sc->sc_nvram.frame_payload_size; 548 icb->icb_exec_throttle = sc->sc_nvram.execution_throttle; 549 icb->icb_hardaddr = sc->sc_nvram.hard_address; 550 icb->icb_portname = sc->sc_nvram.port_name; 551 icb->icb_nodename = sc->sc_nvram.node_name; 552 icb->icb_login_retry = sc->sc_nvram.login_retry; 553 icb->icb_login_timeout = sc->sc_nvram.login_timeout; 554 icb->icb_fwoptions1 = sc->sc_nvram.fwoptions1; 555 icb->icb_fwoptions2 = sc->sc_nvram.fwoptions2; 556 icb->icb_fwoptions3 = sc->sc_nvram.fwoptions3; 557 } else { 558 /* defaults copied from isp(4) */ 559 htolem16(&icb->icb_max_frame_len, 1024); 560 htolem16(&icb->icb_exec_throttle, 16); 561 icb->icb_portname = htobe64(QLE_DEFAULT_PORT_NAME); 562 icb->icb_nodename = 0; 563 icb->icb_login_retry = 3; 564 565 htolem32(&icb->icb_fwoptions1, QLE_ICB_FW1_FAIRNESS | 566 QLE_ICB_FW1_HARD_ADDR | QLE_ICB_FW1_FULL_DUPLEX); 567 htolem32(&icb->icb_fwoptions2, QLE_ICB_FW2_LOOP_PTP); 568 htolem32(&icb->icb_fwoptions3, QLE_ICB_FW3_FCP_RSP_24_0 | 569 QLE_ICB_FW3_AUTONEG); 570 } 571 572 icb->icb_exchange_count = 0; 573 574 icb->icb_req_out = 0; 575 icb->icb_resp_in = 0; 576 icb->icb_pri_req_out = 0; 577 htolem16(&icb->icb_req_queue_len, sc->sc_maxcmds); 578 htolem16(&icb->icb_resp_queue_len, sc->sc_maxcmds); 579 htolem16(&icb->icb_pri_req_queue_len, 8); /* apparently the minimum */ 580 htolem32(&icb->icb_req_queue_addr_lo, 581 QLE_DMA_DVA(sc->sc_requests)); 582 htolem32(&icb->icb_req_queue_addr_hi, 583 QLE_DMA_DVA(sc->sc_requests) >> 32); 584 htolem32(&icb->icb_resp_queue_addr_lo, 585 QLE_DMA_DVA(sc->sc_responses)); 586 htolem32(&icb->icb_resp_queue_addr_hi, 587 QLE_DMA_DVA(sc->sc_responses) >> 32); 588 htolem32(&icb->icb_pri_req_queue_addr_lo, 589 QLE_DMA_DVA(sc->sc_pri_requests)); 590 htolem32(&icb->icb_pri_req_queue_addr_hi, 591 QLE_DMA_DVA(sc->sc_pri_requests) >> 32); 592 593 htolem16(&icb->icb_link_down_nos, 200); 594 icb->icb_int_delay = 0; 595 icb->icb_login_timeout = 0; 596 597 sc->sc_mbox[0] = QLE_MBOX_INIT_FIRMWARE; 598 sc->sc_mbox[4] = 0; 599 sc->sc_mbox[5] = 0; 600 qle_mbox_putaddr(sc->sc_mbox, sc->sc_scratch); 601 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(sc->sc_scratch), 0, 602 sizeof(*icb), BUS_DMASYNC_PREWRITE); 603 rv = qle_mbox(sc, 0x00fd); 604 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(sc->sc_scratch), 0, 605 sizeof(*icb), BUS_DMASYNC_POSTWRITE); 606 607 if (rv != 0) { 608 printf("%s: ISP firmware init failed: %x\n", DEVNAME(sc), 609 sc->sc_mbox[0]); 610 goto free_scratch; 611 } 612 613 /* enable some more notifications */ 614 sc->sc_mbox[0] = QLE_MBOX_SET_FIRMWARE_OPTIONS; 615 sc->sc_mbox[1] = QLE_FW_OPTION1_ASYNC_LIP_F8 | 616 QLE_FW_OPTION1_ASYNC_LIP_RESET | 617 QLE_FW_OPTION1_ASYNC_LIP_ERROR | 618 QLE_FW_OPTION1_ASYNC_LOGIN_RJT; 619 sc->sc_mbox[2] = 0; 620 sc->sc_mbox[3] = 0; 621 if (qle_mbox(sc, 0x000f)) { 622 printf("%s: setting firmware options failed: %x\n", 623 DEVNAME(sc), sc->sc_mbox[0]); 624 goto free_scratch; 625 } 626 627 sc->sc_update_taskq = taskq_create(DEVNAME(sc), 1, IPL_BIO, 0); 628 task_set(&sc->sc_update_task, qle_do_update, sc); 629 630 /* wait a bit for link to come up so we can scan and attach devices */ 631 for (i = 0; i < QLE_WAIT_FOR_LOOP * 10000; i++) { 632 u_int16_t isr, info; 633 634 delay(100); 635 636 if (qle_read_isr(sc, &isr, &info) == 0) 637 continue; 638 639 qle_handle_intr(sc, isr, info); 640 641 if (sc->sc_loop_up) 642 break; 643 } 644 645 if (sc->sc_loop_up) { 646 qle_do_update(sc); 647 } else { 648 DPRINTF(QLE_D_PORT, "%s: loop still down, giving up\n", 649 DEVNAME(sc)); 650 } 651 652 /* we should be good to go now, attach scsibus */ 653 sc->sc_link.adapter = &qle_switch; 654 sc->sc_link.adapter_softc = sc; 655 sc->sc_link.adapter_target = QLE_MAX_TARGETS; 656 sc->sc_link.adapter_buswidth = QLE_MAX_TARGETS; 657 sc->sc_link.openings = sc->sc_maxcmds; 658 sc->sc_link.pool = &sc->sc_iopool; 659 if (sc->sc_nvram_valid) { 660 sc->sc_link.port_wwn = betoh64(sc->sc_nvram.port_name); 661 sc->sc_link.node_wwn = betoh64(sc->sc_nvram.node_name); 662 } else { 663 sc->sc_link.port_wwn = QLE_DEFAULT_PORT_NAME; 664 sc->sc_link.node_wwn = 0; 665 } 666 if (sc->sc_link.node_wwn == 0) { 667 /* 668 * mask out the port number from the port name to get 669 * the node name. 670 */ 671 sc->sc_link.node_wwn = sc->sc_link.port_wwn; 672 sc->sc_link.node_wwn &= ~(0xfULL << 56); 673 } 674 675 memset(&saa, 0, sizeof(saa)); 676 saa.saa_sc_link = &sc->sc_link; 677 678 /* config_found() returns the scsibus attached to us */ 679 sc->sc_scsibus = (struct scsibus_softc *)config_found(&sc->sc_dev, 680 &saa, scsiprint); 681 682 return; 683 684 free_scratch: 685 qle_dmamem_free(sc, sc->sc_scratch); 686 free_ccbs: 687 qle_free_ccbs(sc); 688 deintr: 689 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 690 sc->sc_ih = NULL; 691 unmap: 692 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 693 sc->sc_ios = 0; 694 } 695 696 int 697 qle_detach(struct device *self, int flags) 698 { 699 struct qle_softc *sc = (struct qle_softc *)self; 700 701 if (sc->sc_ih == NULL) { 702 /* we didnt attach properly, so nothing to detach */ 703 return (0); 704 } 705 706 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 707 sc->sc_ih = NULL; 708 709 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 710 sc->sc_ios = 0; 711 712 return (0); 713 } 714 715 int 716 qle_classify_port(struct qle_softc *sc, u_int32_t location, 717 u_int64_t port_name, u_int64_t node_name, struct qle_fc_port **prev) 718 { 719 struct qle_fc_port *port, *locmatch, *wwnmatch; 720 locmatch = NULL; 721 wwnmatch = NULL; 722 723 /* make sure we don't try to add a port or location twice */ 724 TAILQ_FOREACH(port, &sc->sc_ports_new, update) { 725 if ((port->port_name == port_name && 726 port->node_name == node_name) || 727 port->location == location) { 728 *prev = port; 729 return (QLE_PORT_DISP_DUP); 730 } 731 } 732 733 /* if we're attaching, everything is new */ 734 if (sc->sc_scsibus == NULL) { 735 *prev = NULL; 736 return (QLE_PORT_DISP_NEW); 737 } 738 739 TAILQ_FOREACH(port, &sc->sc_ports, ports) { 740 if (port->location == location) 741 locmatch = port; 742 743 if (port->port_name == port_name && 744 port->node_name == node_name) 745 wwnmatch = port; 746 } 747 748 if (locmatch == NULL && wwnmatch == NULL) { 749 *prev = NULL; 750 return (QLE_PORT_DISP_NEW); 751 } else if (locmatch == wwnmatch) { 752 *prev = locmatch; 753 return (QLE_PORT_DISP_SAME); 754 } else if (wwnmatch != NULL) { 755 *prev = wwnmatch; 756 return (QLE_PORT_DISP_MOVED); 757 } else { 758 *prev = locmatch; 759 return (QLE_PORT_DISP_CHANGED); 760 } 761 } 762 763 int 764 qle_get_loop_id(struct qle_softc *sc, int start) 765 { 766 int i, last; 767 768 i = QLE_MIN_HANDLE; 769 last = QLE_MAX_HANDLE; 770 if (i < start) 771 i = start; 772 773 for (; i <= last; i++) { 774 if (sc->sc_targets[i] == NULL) 775 return (i); 776 } 777 778 return (-1); 779 } 780 781 int 782 qle_get_port_db(struct qle_softc *sc, u_int16_t loopid, struct qle_dmamem *mem) 783 { 784 sc->sc_mbox[0] = QLE_MBOX_GET_PORT_DB; 785 sc->sc_mbox[1] = loopid; 786 qle_mbox_putaddr(sc->sc_mbox, mem); 787 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(mem), 0, 788 sizeof(struct qle_get_port_db), BUS_DMASYNC_PREREAD); 789 if (qle_mbox(sc, 0x00cf)) { 790 DPRINTF(QLE_D_PORT, "%s: get port db for %d failed: %x\n", 791 DEVNAME(sc), loopid, sc->sc_mbox[0]); 792 return (1); 793 } 794 795 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(mem), 0, 796 sizeof(struct qle_get_port_db), BUS_DMASYNC_POSTREAD); 797 return (0); 798 } 799 800 int 801 qle_get_port_name_list(struct qle_softc *sc, u_int32_t match) 802 { 803 struct qle_port_name_list *l; 804 struct qle_fc_port *port; 805 int i; 806 807 sc->sc_mbox[0] = QLE_MBOX_GET_PORT_NAME_LIST; 808 sc->sc_mbox[1] = 0; 809 sc->sc_mbox[8] = QLE_DMA_LEN(sc->sc_scratch); 810 sc->sc_mbox[9] = 0; 811 qle_mbox_putaddr(sc->sc_mbox, sc->sc_scratch); 812 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(sc->sc_scratch), 0, 813 QLE_DMA_LEN(sc->sc_scratch), BUS_DMASYNC_PREREAD); 814 if (qle_mbox(sc, 0x03cf)) { 815 DPRINTF(QLE_D_PORT, "%s: get port name list failed: %x\n", 816 DEVNAME(sc), sc->sc_mbox[0]); 817 return (1); 818 } 819 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(sc->sc_scratch), 0, 820 sc->sc_mbox[1], BUS_DMASYNC_POSTREAD); 821 822 i = 0; 823 l = QLE_DMA_KVA(sc->sc_scratch); 824 mtx_enter(&sc->sc_port_mtx); 825 while (i * sizeof(*l) < sc->sc_mbox[1]) { 826 u_int16_t loopid; 827 u_int32_t loc; 828 829 loopid = lemtoh16(&l[i].loopid) & 0xfff; 830 /* skip special ports */ 831 switch (loopid) { 832 case QLE_F_PORT_HANDLE: 833 case QLE_SNS_HANDLE: 834 case QLE_FABRIC_CTRL_HANDLE: 835 case QLE_IP_BCAST_HANDLE: 836 loc = 0; 837 break; 838 default: 839 if (loopid <= sc->sc_loop_max_id) { 840 loc = QLE_LOCATION_LOOP_ID(loopid); 841 } else { 842 /* 843 * we don't have the port id here, so just 844 * indicate it's a fabric port. 845 */ 846 loc = QLE_LOCATION_FABRIC; 847 } 848 break; 849 } 850 851 if (match & loc) { 852 port = malloc(sizeof(*port), M_DEVBUF, M_ZERO | 853 M_NOWAIT); 854 if (port == NULL) { 855 printf("%s: failed to allocate port struct\n", 856 DEVNAME(sc)); 857 break; 858 } 859 port->location = loc; 860 port->loopid = loopid; 861 port->port_name = letoh64(l[i].port_name); 862 DPRINTF(QLE_D_PORT, "%s: loop id %d, port name %llx\n", 863 DEVNAME(sc), port->loopid, port->port_name); 864 TAILQ_INSERT_TAIL(&sc->sc_ports_found, port, update); 865 } 866 i++; 867 } 868 mtx_leave(&sc->sc_port_mtx); 869 870 return (0); 871 } 872 873 int 874 qle_add_loop_port(struct qle_softc *sc, struct qle_fc_port *port) 875 { 876 struct qle_get_port_db *pdb; 877 struct qle_fc_port *pport; 878 int disp; 879 880 if (qle_get_port_db(sc, port->loopid, sc->sc_scratch) != 0) { 881 return (1); 882 } 883 pdb = QLE_DMA_KVA(sc->sc_scratch); 884 885 if (lemtoh16(&pdb->prli_svc_word3) & QLE_SVC3_TARGET_ROLE) 886 port->flags |= QLE_PORT_FLAG_IS_TARGET; 887 888 port->port_name = betoh64(pdb->port_name); 889 port->node_name = betoh64(pdb->node_name); 890 port->portid = (pdb->port_id[0] << 16) | (pdb->port_id[1] << 8) | 891 pdb->port_id[2]; 892 893 mtx_enter(&sc->sc_port_mtx); 894 disp = qle_classify_port(sc, port->location, port->port_name, 895 port->node_name, &pport); 896 switch (disp) { 897 case QLE_PORT_DISP_CHANGED: 898 case QLE_PORT_DISP_MOVED: 899 case QLE_PORT_DISP_NEW: 900 TAILQ_INSERT_TAIL(&sc->sc_ports_new, port, update); 901 sc->sc_targets[port->loopid] = port; 902 break; 903 case QLE_PORT_DISP_DUP: 904 free(port, M_DEVBUF, sizeof *port); 905 break; 906 case QLE_PORT_DISP_SAME: 907 TAILQ_REMOVE(&sc->sc_ports_gone, pport, update); 908 free(port, M_DEVBUF, sizeof *port); 909 break; 910 } 911 mtx_leave(&sc->sc_port_mtx); 912 913 switch (disp) { 914 case QLE_PORT_DISP_CHANGED: 915 case QLE_PORT_DISP_MOVED: 916 case QLE_PORT_DISP_NEW: 917 DPRINTF(QLE_D_PORT, "%s: %s %d; name %llx\n", 918 DEVNAME(sc), ISSET(port->flags, QLE_PORT_FLAG_IS_TARGET) ? 919 "target" : "non-target", port->loopid, 920 betoh64(pdb->port_name)); 921 break; 922 default: 923 break; 924 } 925 return (0); 926 } 927 928 int 929 qle_add_fabric_port(struct qle_softc *sc, struct qle_fc_port *port) 930 { 931 struct qle_get_port_db *pdb; 932 933 if (qle_get_port_db(sc, port->loopid, sc->sc_scratch) != 0) { 934 free(port, M_DEVBUF, sizeof *port); 935 return (1); 936 } 937 pdb = QLE_DMA_KVA(sc->sc_scratch); 938 939 if (lemtoh16(&pdb->prli_svc_word3) & QLE_SVC3_TARGET_ROLE) 940 port->flags |= QLE_PORT_FLAG_IS_TARGET; 941 942 /* 943 * if we only know about this port because qle_get_port_name_list 944 * returned it, we don't have its port id or node name, so fill 945 * those in and update its location. 946 */ 947 if (port->location == QLE_LOCATION_FABRIC) { 948 port->node_name = betoh64(pdb->node_name); 949 port->port_name = betoh64(pdb->port_name); 950 port->portid = (pdb->port_id[0] << 16) | 951 (pdb->port_id[1] << 8) | pdb->port_id[2]; 952 port->location = QLE_LOCATION_PORT_ID(port->portid); 953 } 954 955 mtx_enter(&sc->sc_port_mtx); 956 TAILQ_INSERT_TAIL(&sc->sc_ports_new, port, update); 957 sc->sc_targets[port->loopid] = port; 958 mtx_leave(&sc->sc_port_mtx); 959 960 DPRINTF(QLE_D_PORT, "%s: %s %d; name %llx\n", 961 DEVNAME(sc), ISSET(port->flags, QLE_PORT_FLAG_IS_TARGET) ? 962 "target" : "non-target", port->loopid, port->port_name); 963 return (0); 964 } 965 966 int 967 qle_add_logged_in_port(struct qle_softc *sc, u_int16_t loopid, 968 u_int32_t portid) 969 { 970 struct qle_fc_port *port; 971 struct qle_get_port_db *pdb; 972 u_int64_t node_name, port_name; 973 int flags, ret; 974 975 ret = qle_get_port_db(sc, loopid, sc->sc_scratch); 976 mtx_enter(&sc->sc_port_mtx); 977 if (ret != 0) { 978 /* put in a fake port to prevent use of this loop id */ 979 printf("%s: loop id %d used, but can't see what's using it\n", 980 DEVNAME(sc), loopid); 981 node_name = 0; 982 port_name = 0; 983 flags = 0; 984 } else { 985 pdb = QLE_DMA_KVA(sc->sc_scratch); 986 node_name = betoh64(pdb->node_name); 987 port_name = betoh64(pdb->port_name); 988 flags = 0; 989 if (lemtoh16(&pdb->prli_svc_word3) & QLE_SVC3_TARGET_ROLE) 990 flags |= QLE_PORT_FLAG_IS_TARGET; 991 992 /* see if we've already found this port */ 993 TAILQ_FOREACH(port, &sc->sc_ports_found, update) { 994 if ((port->node_name == node_name) && 995 (port->port_name == port_name) && 996 (port->portid == portid)) { 997 mtx_leave(&sc->sc_port_mtx); 998 DPRINTF(QLE_D_PORT, "%s: already found port " 999 "%06x\n", DEVNAME(sc), portid); 1000 return (0); 1001 } 1002 } 1003 } 1004 1005 port = malloc(sizeof(*port), M_DEVBUF, M_ZERO | M_NOWAIT); 1006 if (port == NULL) { 1007 mtx_leave(&sc->sc_port_mtx); 1008 printf("%s: failed to allocate a port structure\n", 1009 DEVNAME(sc)); 1010 return (1); 1011 } 1012 port->location = QLE_LOCATION_PORT_ID(portid); 1013 port->port_name = port_name; 1014 port->node_name = node_name; 1015 port->loopid = loopid; 1016 port->portid = portid; 1017 port->flags = flags; 1018 1019 TAILQ_INSERT_TAIL(&sc->sc_ports, port, ports); 1020 sc->sc_targets[port->loopid] = port; 1021 mtx_leave(&sc->sc_port_mtx); 1022 1023 DPRINTF(QLE_D_PORT, "%s: added logged in port %06x at %d\n", 1024 DEVNAME(sc), portid, loopid); 1025 return (0); 1026 } 1027 1028 struct qle_ccb * 1029 qle_handle_resp(struct qle_softc *sc, u_int32_t id) 1030 { 1031 struct qle_ccb *ccb; 1032 struct qle_iocb_status *status; 1033 struct qle_iocb_req6 *req; 1034 struct scsi_xfer *xs; 1035 u_int32_t handle; 1036 u_int16_t completion; 1037 u_int8_t *entry; 1038 u_int8_t *data; 1039 1040 ccb = NULL; 1041 entry = QLE_DMA_KVA(sc->sc_responses) + (id * QLE_QUEUE_ENTRY_SIZE); 1042 1043 bus_dmamap_sync(sc->sc_dmat, 1044 QLE_DMA_MAP(sc->sc_responses), id * QLE_QUEUE_ENTRY_SIZE, 1045 QLE_QUEUE_ENTRY_SIZE, BUS_DMASYNC_POSTREAD); 1046 1047 qle_dump_iocb(sc, entry); 1048 switch(entry[0]) { 1049 case QLE_IOCB_STATUS: 1050 status = (struct qle_iocb_status *)entry; 1051 handle = status->handle; 1052 if (handle > sc->sc_maxcmds) { 1053 panic("bad completed command handle: %d (> %d)", 1054 handle, sc->sc_maxcmds); 1055 } 1056 1057 ccb = &sc->sc_ccbs[handle]; 1058 xs = ccb->ccb_xs; 1059 if (xs == NULL) { 1060 DPRINTF(QLE_D_IO, "%s: got status for inactive ccb %d\n", 1061 DEVNAME(sc), handle); 1062 ccb = NULL; 1063 break; 1064 } 1065 if (xs->io != ccb) { 1066 panic("completed command handle doesn't match xs " 1067 "(handle %d, ccb %p, xs->io %p)", handle, ccb, 1068 xs->io); 1069 } 1070 qle_dump_iocb(sc, status); 1071 1072 if (xs->datalen > 0) { 1073 if (ccb->ccb_dmamap->dm_nsegs > 1074 QLE_IOCB_SEGS_PER_CMD) { 1075 bus_dmamap_sync(sc->sc_dmat, 1076 QLE_DMA_MAP(sc->sc_segments), 1077 ccb->ccb_seg_offset, 1078 sizeof(*ccb->ccb_segs) * 1079 ccb->ccb_dmamap->dm_nsegs + 1, 1080 BUS_DMASYNC_POSTWRITE); 1081 } 1082 1083 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap, 0, 1084 ccb->ccb_dmamap->dm_mapsize, 1085 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1086 BUS_DMASYNC_POSTWRITE); 1087 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap); 1088 } 1089 1090 xs->status = lemtoh16(&status->scsi_status) & 0xff; 1091 xs->resid = 0; 1092 completion = lemtoh16(&status->completion); 1093 switch (completion) { 1094 case QLE_IOCB_STATUS_DATA_UNDERRUN: 1095 xs->resid = lemtoh32(&status->resid); 1096 case QLE_IOCB_STATUS_DATA_OVERRUN: 1097 case QLE_IOCB_STATUS_COMPLETE: 1098 if (lemtoh16(&status->scsi_status) & 1099 QLE_SCSI_STATUS_SENSE_VALID) { 1100 u_int32_t *pp; 1101 int sr; 1102 data = status->data + 1103 lemtoh32(&status->fcp_rsp_len); 1104 sr = MIN(lemtoh32(&status->fcp_sense_len), 1105 sizeof(xs->sense)); 1106 memcpy(&xs->sense, data, sr); 1107 xs->error = XS_SENSE; 1108 pp = (u_int32_t *)&xs->sense; 1109 for (sr = 0; sr < sizeof(xs->sense)/4; sr++) { 1110 pp[sr] = swap32(pp[sr]); 1111 } 1112 } else { 1113 xs->error = XS_NOERROR; 1114 } 1115 break; 1116 1117 case QLE_IOCB_STATUS_DMA_ERROR: 1118 DPRINTF(QLE_D_IO, "%s: dma error\n", DEVNAME(sc)); 1119 /* set resid apparently? */ 1120 break; 1121 1122 case QLE_IOCB_STATUS_RESET: 1123 DPRINTF(QLE_D_IO, "%s: reset destroyed command\n", 1124 DEVNAME(sc)); 1125 sc->sc_marker_required = 1; 1126 xs->error = XS_RESET; 1127 break; 1128 1129 case QLE_IOCB_STATUS_ABORTED: 1130 DPRINTF(QLE_D_IO, "%s: aborted\n", DEVNAME(sc)); 1131 sc->sc_marker_required = 1; 1132 xs->error = XS_DRIVER_STUFFUP; 1133 break; 1134 1135 case QLE_IOCB_STATUS_TIMEOUT: 1136 DPRINTF(QLE_D_IO, "%s: command timed out\n", 1137 DEVNAME(sc)); 1138 xs->error = XS_TIMEOUT; 1139 break; 1140 1141 case QLE_IOCB_STATUS_QUEUE_FULL: 1142 DPRINTF(QLE_D_IO, "%s: queue full\n", DEVNAME(sc)); 1143 xs->error = XS_BUSY; 1144 break; 1145 1146 case QLE_IOCB_STATUS_PORT_UNAVAIL: 1147 case QLE_IOCB_STATUS_PORT_LOGGED_OUT: 1148 case QLE_IOCB_STATUS_PORT_CHANGED: 1149 DPRINTF(QLE_D_IO, "%s: dev gone\n", DEVNAME(sc)); 1150 xs->error = XS_SELTIMEOUT; 1151 /* mark port as needing relogin? */ 1152 break; 1153 1154 default: 1155 DPRINTF(QLE_D_IO, "%s: unexpected completion status " 1156 "%x\n", DEVNAME(sc), status->completion); 1157 xs->error = XS_DRIVER_STUFFUP; 1158 break; 1159 } 1160 break; 1161 1162 case QLE_IOCB_STATUS_CONT: 1163 DPRINTF(QLE_D_IO, "%s: ignoring status continuation iocb\n", 1164 DEVNAME(sc)); 1165 break; 1166 1167 case QLE_IOCB_PLOGX: 1168 case QLE_IOCB_CT_PASSTHROUGH: 1169 if (sc->sc_fabric_pending) { 1170 qle_dump_iocb(sc, entry); 1171 memcpy(sc->sc_fabric_response, entry, 1172 QLE_QUEUE_ENTRY_SIZE); 1173 sc->sc_fabric_pending = 2; 1174 wakeup(sc->sc_scratch); 1175 } else { 1176 DPRINTF(QLE_D_IO, "%s: unexpected fabric response %x\n", 1177 DEVNAME(sc), entry[0]); 1178 } 1179 break; 1180 1181 case QLE_IOCB_MARKER: 1182 break; 1183 1184 case QLE_IOCB_CMD_TYPE_6: 1185 case QLE_IOCB_CMD_TYPE_7: 1186 DPRINTF(QLE_D_IO, "%s: request bounced back\n", DEVNAME(sc)); 1187 req = (struct qle_iocb_req6 *)entry; 1188 handle = req->req_handle; 1189 if (handle > sc->sc_maxcmds) { 1190 panic("bad bounced command handle: %d (> %d)", 1191 handle, sc->sc_maxcmds); 1192 } 1193 1194 ccb = &sc->sc_ccbs[handle]; 1195 xs = ccb->ccb_xs; 1196 xs->error = XS_DRIVER_STUFFUP; 1197 break; 1198 default: 1199 DPRINTF(QLE_D_IO, "%s: unexpected response entry type %x\n", 1200 DEVNAME(sc), entry[0]); 1201 break; 1202 } 1203 1204 return (ccb); 1205 } 1206 1207 void 1208 qle_handle_intr(struct qle_softc *sc, u_int16_t isr, u_int16_t info) 1209 { 1210 int i; 1211 u_int32_t rspin; 1212 struct qle_ccb *ccb; 1213 1214 switch (isr) { 1215 case QLE_INT_TYPE_ASYNC: 1216 qle_async(sc, info); 1217 break; 1218 1219 case QLE_INT_TYPE_IO: 1220 rspin = qle_read(sc, QLE_RESP_IN); 1221 if (rspin == sc->sc_last_resp_id) 1222 break; 1223 1224 do { 1225 ccb = qle_handle_resp(sc, sc->sc_last_resp_id); 1226 if (ccb) 1227 scsi_done(ccb->ccb_xs); 1228 1229 sc->sc_last_resp_id++; 1230 sc->sc_last_resp_id %= sc->sc_maxcmds; 1231 } while (sc->sc_last_resp_id != rspin); 1232 1233 qle_write(sc, QLE_RESP_OUT, sc->sc_last_resp_id); 1234 break; 1235 1236 case QLE_INT_TYPE_MBOX: 1237 mtx_enter(&sc->sc_mbox_mtx); 1238 if (sc->sc_mbox_pending) { 1239 for (i = 0; i < nitems(sc->sc_mbox); i++) { 1240 sc->sc_mbox[i] = qle_read_mbox(sc, i); 1241 } 1242 sc->sc_mbox_pending = 2; 1243 wakeup(sc->sc_mbox); 1244 mtx_leave(&sc->sc_mbox_mtx); 1245 } else { 1246 mtx_leave(&sc->sc_mbox_mtx); 1247 DPRINTF(QLE_D_INTR, "%s: unexpected mbox interrupt: " 1248 "%x\n", DEVNAME(sc), info); 1249 } 1250 break; 1251 1252 default: 1253 break; 1254 } 1255 1256 qle_clear_isr(sc, isr); 1257 } 1258 1259 int 1260 qle_intr(void *xsc) 1261 { 1262 struct qle_softc *sc = xsc; 1263 u_int16_t isr; 1264 u_int16_t info; 1265 1266 if (qle_read_isr(sc, &isr, &info) == 0) 1267 return (0); 1268 1269 qle_handle_intr(sc, isr, info); 1270 return (1); 1271 } 1272 1273 int 1274 qle_scsi_probe(struct scsi_link *link) 1275 { 1276 struct qle_softc *sc = link->adapter_softc; 1277 int rv = 0; 1278 1279 mtx_enter(&sc->sc_port_mtx); 1280 if (sc->sc_targets[link->target] == NULL) 1281 rv = ENXIO; 1282 else if (!ISSET(sc->sc_targets[link->target]->flags, 1283 QLE_PORT_FLAG_IS_TARGET)) 1284 rv = ENXIO; 1285 mtx_leave(&sc->sc_port_mtx); 1286 1287 return (rv); 1288 } 1289 1290 void 1291 qle_scsi_cmd(struct scsi_xfer *xs) 1292 { 1293 struct scsi_link *link = xs->sc_link; 1294 struct qle_softc *sc = link->adapter_softc; 1295 struct qle_ccb *ccb; 1296 void *iocb; 1297 struct qle_ccb_list list; 1298 u_int16_t req; 1299 u_int32_t portid; 1300 int offset, error, done; 1301 bus_dmamap_t dmap; 1302 1303 if (xs->cmdlen > 16) { 1304 DPRINTF(QLE_D_IO, "%s: cmd too big (%d)\n", DEVNAME(sc), 1305 xs->cmdlen); 1306 memset(&xs->sense, 0, sizeof(xs->sense)); 1307 xs->sense.error_code = SSD_ERRCODE_VALID | SSD_ERRCODE_CURRENT; 1308 xs->sense.flags = SKEY_ILLEGAL_REQUEST; 1309 xs->sense.add_sense_code = 0x20; 1310 xs->error = XS_SENSE; 1311 scsi_done(xs); 1312 return; 1313 } 1314 1315 portid = 0xffffffff; 1316 mtx_enter(&sc->sc_port_mtx); 1317 if (sc->sc_targets[xs->sc_link->target] != NULL) { 1318 portid = sc->sc_targets[xs->sc_link->target]->portid; 1319 } 1320 mtx_leave(&sc->sc_port_mtx); 1321 if (portid == 0xffffffff) { 1322 xs->error = XS_DRIVER_STUFFUP; 1323 scsi_done(xs); 1324 return; 1325 } 1326 1327 ccb = xs->io; 1328 dmap = ccb->ccb_dmamap; 1329 if (xs->datalen > 0) { 1330 error = bus_dmamap_load(sc->sc_dmat, dmap, xs->data, 1331 xs->datalen, NULL, (xs->flags & SCSI_NOSLEEP) ? 1332 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 1333 if (error) { 1334 xs->error = XS_DRIVER_STUFFUP; 1335 scsi_done(xs); 1336 return; 1337 } 1338 1339 bus_dmamap_sync(sc->sc_dmat, dmap, 0, 1340 dmap->dm_mapsize, 1341 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : 1342 BUS_DMASYNC_PREWRITE); 1343 } 1344 1345 mtx_enter(&sc->sc_queue_mtx); 1346 1347 /* put in a sync marker if required */ 1348 if (sc->sc_marker_required) { 1349 req = sc->sc_next_req_id++; 1350 if (sc->sc_next_req_id == sc->sc_maxcmds) 1351 sc->sc_next_req_id = 0; 1352 1353 DPRINTF(QLE_D_IO, "%s: writing marker at request %d\n", 1354 DEVNAME(sc), req); 1355 offset = (req * QLE_QUEUE_ENTRY_SIZE); 1356 iocb = QLE_DMA_KVA(sc->sc_requests) + offset; 1357 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(sc->sc_requests), 1358 offset, QLE_QUEUE_ENTRY_SIZE, BUS_DMASYNC_POSTWRITE); 1359 qle_put_marker(sc, iocb); 1360 qle_write(sc, QLE_REQ_IN, sc->sc_next_req_id); 1361 sc->sc_marker_required = 0; 1362 } 1363 1364 req = sc->sc_next_req_id++; 1365 if (sc->sc_next_req_id == sc->sc_maxcmds) 1366 sc->sc_next_req_id = 0; 1367 1368 offset = (req * QLE_QUEUE_ENTRY_SIZE); 1369 iocb = QLE_DMA_KVA(sc->sc_requests) + offset; 1370 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(sc->sc_requests), offset, 1371 QLE_QUEUE_ENTRY_SIZE, BUS_DMASYNC_POSTWRITE); 1372 1373 ccb->ccb_xs = xs; 1374 1375 qle_put_cmd(sc, iocb, xs, ccb, portid); 1376 1377 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(sc->sc_requests), offset, 1378 QLE_QUEUE_ENTRY_SIZE, BUS_DMASYNC_PREREAD); 1379 qle_write(sc, QLE_REQ_IN, sc->sc_next_req_id); 1380 1381 if (!ISSET(xs->flags, SCSI_POLL)) { 1382 mtx_leave(&sc->sc_queue_mtx); 1383 return; 1384 } 1385 1386 done = 0; 1387 SIMPLEQ_INIT(&list); 1388 do { 1389 u_int16_t isr, info; 1390 u_int32_t rspin; 1391 delay(100); 1392 1393 if (qle_read_isr(sc, &isr, &info) == 0) { 1394 continue; 1395 } 1396 1397 if (isr != QLE_INT_TYPE_IO) { 1398 qle_handle_intr(sc, isr, info); 1399 continue; 1400 } 1401 1402 rspin = qle_read(sc, QLE_RESP_IN); 1403 while (rspin != sc->sc_last_resp_id) { 1404 ccb = qle_handle_resp(sc, sc->sc_last_resp_id); 1405 1406 sc->sc_last_resp_id++; 1407 if (sc->sc_last_resp_id == sc->sc_maxcmds) 1408 sc->sc_last_resp_id = 0; 1409 1410 if (ccb != NULL) 1411 SIMPLEQ_INSERT_TAIL(&list, ccb, ccb_link); 1412 if (ccb == xs->io) 1413 done = 1; 1414 } 1415 qle_write(sc, QLE_RESP_OUT, sc->sc_last_resp_id); 1416 qle_clear_isr(sc, isr); 1417 } while (done == 0); 1418 1419 mtx_leave(&sc->sc_queue_mtx); 1420 1421 while ((ccb = SIMPLEQ_FIRST(&list)) != NULL) { 1422 SIMPLEQ_REMOVE_HEAD(&list, ccb_link); 1423 scsi_done(ccb->ccb_xs); 1424 } 1425 } 1426 1427 u_int32_t 1428 qle_read(struct qle_softc *sc, int offset) 1429 { 1430 u_int32_t v; 1431 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 1432 bus_space_barrier(sc->sc_iot, sc->sc_ioh, offset, 4, 1433 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1434 return (v); 1435 } 1436 1437 void 1438 qle_write(struct qle_softc *sc, int offset, u_int32_t value) 1439 { 1440 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 1441 bus_space_barrier(sc->sc_iot, sc->sc_ioh, offset, 4, 1442 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1443 } 1444 1445 u_int16_t 1446 qle_read_mbox(struct qle_softc *sc, int mbox) 1447 { 1448 u_int16_t v; 1449 bus_size_t offset = mbox * 2; 1450 v = bus_space_read_2(sc->sc_iot, sc->sc_mbox_ioh, offset); 1451 bus_space_barrier(sc->sc_iot, sc->sc_mbox_ioh, offset, 2, 1452 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1453 return (v); 1454 } 1455 1456 void 1457 qle_write_mbox(struct qle_softc *sc, int mbox, u_int16_t value) 1458 { 1459 bus_size_t offset = (mbox * 2); 1460 bus_space_write_2(sc->sc_iot, sc->sc_mbox_ioh, offset, value); 1461 bus_space_barrier(sc->sc_iot, sc->sc_mbox_ioh, offset, 2, 1462 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1463 } 1464 1465 void 1466 qle_host_cmd(struct qle_softc *sc, u_int32_t cmd) 1467 { 1468 qle_write(sc, QLE_HOST_CMD_CTRL, cmd << QLE_HOST_CMD_SHIFT); 1469 } 1470 1471 #define MBOX_COMMAND_TIMEOUT 400000 1472 1473 int 1474 qle_mbox(struct qle_softc *sc, int maskin) 1475 { 1476 int i; 1477 int result = 0; 1478 int rv; 1479 1480 for (i = 0; i < nitems(sc->sc_mbox); i++) { 1481 if (maskin & (1 << i)) { 1482 qle_write_mbox(sc, i, sc->sc_mbox[i]); 1483 } 1484 } 1485 qle_host_cmd(sc, QLE_HOST_CMD_SET_HOST_INT); 1486 1487 if (sc->sc_scsibus != NULL) { 1488 mtx_enter(&sc->sc_mbox_mtx); 1489 sc->sc_mbox_pending = 1; 1490 while (sc->sc_mbox_pending == 1) { 1491 msleep(sc->sc_mbox, &sc->sc_mbox_mtx, PRIBIO, 1492 "qlembox", 0); 1493 } 1494 result = sc->sc_mbox[0]; 1495 sc->sc_mbox_pending = 0; 1496 mtx_leave(&sc->sc_mbox_mtx); 1497 return (result == QLE_MBOX_COMPLETE ? 0 : result); 1498 } 1499 1500 for (i = 0; i < MBOX_COMMAND_TIMEOUT && result == 0; i++) { 1501 u_int16_t isr, info; 1502 1503 delay(100); 1504 1505 if (qle_read_isr(sc, &isr, &info) == 0) 1506 continue; 1507 1508 switch (isr) { 1509 case QLE_INT_TYPE_MBOX: 1510 result = info; 1511 break; 1512 1513 default: 1514 qle_handle_intr(sc, isr, info); 1515 break; 1516 } 1517 } 1518 1519 if (result == 0) { 1520 /* timed out; do something? */ 1521 DPRINTF(QLE_D_MBOX, "%s: mbox timed out\n", DEVNAME(sc)); 1522 rv = 1; 1523 } else { 1524 for (i = 0; i < nitems(sc->sc_mbox); i++) { 1525 sc->sc_mbox[i] = qle_read_mbox(sc, i); 1526 } 1527 rv = (result == QLE_MBOX_COMPLETE ? 0 : result); 1528 } 1529 1530 qle_clear_isr(sc, QLE_INT_TYPE_MBOX); 1531 return (rv); 1532 } 1533 1534 void 1535 qle_mbox_putaddr(u_int16_t *mbox, struct qle_dmamem *mem) 1536 { 1537 mbox[2] = (QLE_DMA_DVA(mem) >> 16) & 0xffff; 1538 mbox[3] = (QLE_DMA_DVA(mem) >> 0) & 0xffff; 1539 mbox[6] = (QLE_DMA_DVA(mem) >> 48) & 0xffff; 1540 mbox[7] = (QLE_DMA_DVA(mem) >> 32) & 0xffff; 1541 } 1542 1543 void 1544 qle_set_ints(struct qle_softc *sc, int enabled) 1545 { 1546 u_int32_t v = enabled ? QLE_INT_CTRL_ENABLE : 0; 1547 qle_write(sc, QLE_INT_CTRL, v); 1548 } 1549 1550 int 1551 qle_read_isr(struct qle_softc *sc, u_int16_t *isr, u_int16_t *info) 1552 { 1553 u_int32_t v; 1554 1555 switch (sc->sc_isp_gen) { 1556 case QLE_GEN_ISP24XX: 1557 case QLE_GEN_ISP25XX: 1558 if ((qle_read(sc, QLE_INT_STATUS) & QLE_RISC_INT_REQ) == 0) 1559 return (0); 1560 1561 v = qle_read(sc, QLE_RISC_STATUS); 1562 1563 switch (v & QLE_INT_STATUS_MASK) { 1564 case QLE_24XX_INT_ROM_MBOX: 1565 case QLE_24XX_INT_ROM_MBOX_FAIL: 1566 case QLE_24XX_INT_MBOX: 1567 case QLE_24XX_INT_MBOX_FAIL: 1568 *isr = QLE_INT_TYPE_MBOX; 1569 break; 1570 1571 case QLE_24XX_INT_ASYNC: 1572 *isr = QLE_INT_TYPE_ASYNC; 1573 break; 1574 1575 case QLE_24XX_INT_RSPQ: 1576 *isr = QLE_INT_TYPE_IO; 1577 break; 1578 1579 default: 1580 *isr = QLE_INT_TYPE_OTHER; 1581 break; 1582 } 1583 1584 *info = (v >> QLE_INT_INFO_SHIFT); 1585 return (1); 1586 1587 default: 1588 return (0); 1589 } 1590 } 1591 1592 void 1593 qle_clear_isr(struct qle_softc *sc, u_int16_t isr) 1594 { 1595 qle_host_cmd(sc, QLE_HOST_CMD_CLR_RISC_INT); 1596 } 1597 1598 void 1599 qle_update_done(struct qle_softc *sc, int task) 1600 { 1601 atomic_clearbits_int(&sc->sc_update_tasks, task); 1602 } 1603 1604 void 1605 qle_update_start(struct qle_softc *sc, int task) 1606 { 1607 atomic_setbits_int(&sc->sc_update_tasks, task); 1608 task_add(sc->sc_update_taskq, &sc->sc_update_task); 1609 } 1610 1611 void 1612 qle_clear_port_lists(struct qle_softc *sc) 1613 { 1614 struct qle_fc_port *port; 1615 while (!TAILQ_EMPTY(&sc->sc_ports_found)) { 1616 port = TAILQ_FIRST(&sc->sc_ports_found); 1617 TAILQ_REMOVE(&sc->sc_ports_found, port, update); 1618 free(port, M_DEVBUF, sizeof *port); 1619 } 1620 1621 while (!TAILQ_EMPTY(&sc->sc_ports_new)) { 1622 port = TAILQ_FIRST(&sc->sc_ports_new); 1623 TAILQ_REMOVE(&sc->sc_ports_new, port, update); 1624 free(port, M_DEVBUF, sizeof *port); 1625 } 1626 1627 while (!TAILQ_EMPTY(&sc->sc_ports_gone)) { 1628 port = TAILQ_FIRST(&sc->sc_ports_gone); 1629 TAILQ_REMOVE(&sc->sc_ports_gone, port, update); 1630 } 1631 } 1632 1633 int 1634 qle_softreset(struct qle_softc *sc) 1635 { 1636 int i; 1637 qle_set_ints(sc, 0); 1638 1639 /* set led control bits, stop dma */ 1640 qle_write(sc, QLE_GPIO_DATA, 0); 1641 qle_write(sc, QLE_CTRL_STATUS, QLE_CTRL_DMA_SHUTDOWN); 1642 while (qle_read(sc, QLE_CTRL_STATUS) & QLE_CTRL_DMA_ACTIVE) { 1643 DPRINTF(QLE_D_IO, "%s: dma still active\n", DEVNAME(sc)); 1644 delay(100); 1645 } 1646 1647 /* reset */ 1648 qle_write(sc, QLE_CTRL_STATUS, QLE_CTRL_RESET | QLE_CTRL_DMA_SHUTDOWN); 1649 delay(100); 1650 /* clear data and control dma engines? */ 1651 1652 /* wait for soft reset to clear */ 1653 for (i = 0; i < 1000; i++) { 1654 if (qle_read_mbox(sc, 0) == 0x0000) 1655 break; 1656 1657 delay(100); 1658 } 1659 1660 if (i == 1000) { 1661 printf("%s: reset mbox didn't clear\n", DEVNAME(sc)); 1662 qle_set_ints(sc, 0); 1663 return (ENXIO); 1664 } 1665 1666 for (i = 0; i < 500000; i++) { 1667 if ((qle_read(sc, QLE_CTRL_STATUS) & QLE_CTRL_RESET) == 0) 1668 break; 1669 delay(5); 1670 } 1671 if (i == 500000) { 1672 printf("%s: reset status didn't clear\n", DEVNAME(sc)); 1673 return (ENXIO); 1674 } 1675 1676 /* reset risc processor */ 1677 qle_host_cmd(sc, QLE_HOST_CMD_RESET); 1678 qle_host_cmd(sc, QLE_HOST_CMD_RELEASE); 1679 qle_host_cmd(sc, QLE_HOST_CMD_CLEAR_RESET); 1680 1681 /* wait for reset to clear */ 1682 for (i = 0; i < 1000; i++) { 1683 if (qle_read_mbox(sc, 0) == 0x0000) 1684 break; 1685 delay(100); 1686 } 1687 if (i == 1000) { 1688 printf("%s: risc not ready after reset\n", DEVNAME(sc)); 1689 return (ENXIO); 1690 } 1691 1692 /* reset queue pointers */ 1693 qle_write(sc, QLE_REQ_IN, 0); 1694 qle_write(sc, QLE_REQ_OUT, 0); 1695 qle_write(sc, QLE_RESP_IN, 0); 1696 qle_write(sc, QLE_RESP_OUT, 0); 1697 1698 qle_set_ints(sc, 1); 1699 1700 /* do a basic mailbox operation to check we're alive */ 1701 sc->sc_mbox[0] = QLE_MBOX_NOP; 1702 if (qle_mbox(sc, 0x0001)) { 1703 printf("ISP not responding after reset\n"); 1704 return (ENXIO); 1705 } 1706 1707 return (0); 1708 } 1709 1710 void 1711 qle_update_topology(struct qle_softc *sc) 1712 { 1713 sc->sc_mbox[0] = QLE_MBOX_GET_ID; 1714 if (qle_mbox(sc, 0x0001)) { 1715 DPRINTF(QLE_D_PORT, "%s: unable to get loop id\n", DEVNAME(sc)); 1716 sc->sc_topology = QLE_TOPO_N_PORT_NO_TARGET; 1717 } else { 1718 sc->sc_topology = sc->sc_mbox[6]; 1719 sc->sc_loop_id = sc->sc_mbox[1]; 1720 1721 switch (sc->sc_topology) { 1722 case QLE_TOPO_NL_PORT: 1723 case QLE_TOPO_N_PORT: 1724 DPRINTF(QLE_D_PORT, "%s: loop id %d\n", DEVNAME(sc), 1725 sc->sc_loop_id); 1726 break; 1727 1728 case QLE_TOPO_FL_PORT: 1729 case QLE_TOPO_F_PORT: 1730 sc->sc_port_id = sc->sc_mbox[2] | 1731 (sc->sc_mbox[3] << 16); 1732 DPRINTF(QLE_D_PORT, "%s: fabric port id %06x\n", 1733 DEVNAME(sc), sc->sc_port_id); 1734 break; 1735 1736 case QLE_TOPO_N_PORT_NO_TARGET: 1737 default: 1738 DPRINTF(QLE_D_PORT, "%s: not useful\n", DEVNAME(sc)); 1739 break; 1740 } 1741 1742 switch (sc->sc_topology) { 1743 case QLE_TOPO_NL_PORT: 1744 case QLE_TOPO_FL_PORT: 1745 sc->sc_loop_max_id = 126; 1746 break; 1747 1748 case QLE_TOPO_N_PORT: 1749 sc->sc_loop_max_id = 2; 1750 break; 1751 1752 default: 1753 sc->sc_loop_max_id = 0; 1754 break; 1755 } 1756 } 1757 } 1758 1759 int 1760 qle_update_fabric(struct qle_softc *sc) 1761 { 1762 /*struct qle_sns_rft_id *rft;*/ 1763 1764 switch (sc->sc_topology) { 1765 case QLE_TOPO_F_PORT: 1766 case QLE_TOPO_FL_PORT: 1767 break; 1768 1769 default: 1770 return (0); 1771 } 1772 1773 /* get the name server's port db entry */ 1774 sc->sc_mbox[0] = QLE_MBOX_GET_PORT_DB; 1775 sc->sc_mbox[1] = QLE_F_PORT_HANDLE; 1776 qle_mbox_putaddr(sc->sc_mbox, sc->sc_scratch); 1777 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(sc->sc_scratch), 0, 1778 sizeof(struct qle_get_port_db), BUS_DMASYNC_PREREAD); 1779 if (qle_mbox(sc, 0x00cf)) { 1780 DPRINTF(QLE_D_PORT, "%s: get port db for SNS failed: %x\n", 1781 DEVNAME(sc), sc->sc_mbox[0]); 1782 sc->sc_sns_port_name = 0; 1783 } else { 1784 struct qle_get_port_db *pdb; 1785 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(sc->sc_scratch), 0, 1786 sizeof(struct qle_get_port_db), BUS_DMASYNC_POSTREAD); 1787 pdb = QLE_DMA_KVA(sc->sc_scratch); 1788 DPRINTF(QLE_D_PORT, "%s: SNS port name %llx\n", DEVNAME(sc), 1789 betoh64(pdb->port_name)); 1790 sc->sc_sns_port_name = betoh64(pdb->port_name); 1791 } 1792 1793 /* 1794 * register fc4 types with the fabric 1795 * some switches do this automatically, but apparently 1796 * some don't. 1797 */ 1798 /* 1799 rft = QLE_DMA_KVA(sc->sc_scratch); 1800 memset(rft, 0, sizeof(*rft) + sizeof(struct qle_sns_req_hdr)); 1801 htolem16(&rft->subcmd, QLE_SNS_RFT_ID); 1802 htolem16(&rft->max_word, sizeof(struct qle_sns_req_hdr) / 4); 1803 htolem32(&rft->port_id, sc->sc_port_id); 1804 rft->fc4_types[0] = (1 << QLE_FC4_SCSI); 1805 if (qle_sns_req(sc, sc->sc_scratch, sizeof(*rft))) { 1806 printf("%s: RFT_ID failed\n", DEVNAME(sc)); 1807 / * we might be able to continue after this fails * / 1808 } 1809 */ 1810 1811 return (1); 1812 } 1813 1814 int 1815 qle_ct_pass_through(struct qle_softc *sc, u_int32_t port_handle, 1816 struct qle_dmamem *mem, size_t req_size, size_t resp_size) 1817 { 1818 struct qle_iocb_ct_passthrough *iocb; 1819 u_int16_t req; 1820 u_int64_t offset; 1821 int rv; 1822 1823 mtx_enter(&sc->sc_queue_mtx); 1824 1825 req = sc->sc_next_req_id++; 1826 if (sc->sc_next_req_id == sc->sc_maxcmds) 1827 sc->sc_next_req_id = 0; 1828 1829 offset = (req * QLE_QUEUE_ENTRY_SIZE); 1830 iocb = QLE_DMA_KVA(sc->sc_requests) + offset; 1831 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(sc->sc_requests), offset, 1832 QLE_QUEUE_ENTRY_SIZE, BUS_DMASYNC_POSTWRITE); 1833 1834 memset(iocb, 0, QLE_QUEUE_ENTRY_SIZE); 1835 iocb->entry_type = QLE_IOCB_CT_PASSTHROUGH; 1836 iocb->entry_count = 1; 1837 1838 iocb->req_handle = 9; 1839 htolem16(&iocb->req_nport_handle, port_handle); 1840 htolem16(&iocb->req_dsd_count, 1); 1841 htolem16(&iocb->req_resp_dsd_count, 1); 1842 htolem32(&iocb->req_cmd_byte_count, req_size); 1843 htolem32(&iocb->req_resp_byte_count, resp_size); 1844 qle_sge(&iocb->req_cmd_seg, QLE_DMA_DVA(mem), req_size); 1845 qle_sge(&iocb->req_resp_seg, QLE_DMA_DVA(mem) + req_size, resp_size); 1846 1847 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(mem), 0, QLE_DMA_LEN(mem), 1848 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1849 qle_write(sc, QLE_REQ_IN, sc->sc_next_req_id); 1850 sc->sc_fabric_pending = 1; 1851 mtx_leave(&sc->sc_queue_mtx); 1852 1853 /* maybe put a proper timeout on this */ 1854 rv = 0; 1855 while (sc->sc_fabric_pending == 1) { 1856 if (sc->sc_scsibus == NULL) { 1857 u_int16_t isr, info; 1858 1859 delay(100); 1860 if (qle_read_isr(sc, &isr, &info) != 0) 1861 qle_handle_intr(sc, isr, info); 1862 } else { 1863 tsleep(sc->sc_scratch, PRIBIO, "qle_fabric", 100); 1864 } 1865 } 1866 if (rv == 0) 1867 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(mem), 0, 1868 QLE_DMA_LEN(mem), BUS_DMASYNC_POSTREAD | 1869 BUS_DMASYNC_POSTWRITE); 1870 1871 sc->sc_fabric_pending = 0; 1872 1873 return (rv); 1874 } 1875 1876 struct qle_fc_port * 1877 qle_next_fabric_port(struct qle_softc *sc, u_int32_t *firstport, 1878 u_int32_t *lastport) 1879 { 1880 struct qle_ct_ga_nxt_req *ga; 1881 struct qle_ct_ga_nxt_resp *gar; 1882 struct qle_fc_port *fport; 1883 int result; 1884 1885 /* get the next port from the fabric nameserver */ 1886 ga = QLE_DMA_KVA(sc->sc_scratch); 1887 memset(ga, 0, sizeof(*ga) + sizeof(*gar)); 1888 ga->header.ct_revision = 0x01; 1889 ga->header.ct_gs_type = 0xfc; 1890 ga->header.ct_gs_subtype = 0x02; 1891 ga->subcmd = htobe16(QLE_SNS_GA_NXT); 1892 ga->max_word = htobe16((sizeof(*gar) - 16) / 4); 1893 ga->port_id = htobe32(*lastport); 1894 result = qle_ct_pass_through(sc, QLE_SNS_HANDLE, sc->sc_scratch, 1895 sizeof(*ga), sizeof(*gar)); 1896 if (result) { 1897 DPRINTF(QLE_D_PORT, "%s: GA_NXT %06x failed: %x\n", DEVNAME(sc), 1898 *lastport, result); 1899 *lastport = 0xffffffff; 1900 return (NULL); 1901 } 1902 1903 gar = (struct qle_ct_ga_nxt_resp *)(ga + 1); 1904 /* if the response is all zeroes, try again */ 1905 if (gar->port_type_id == 0 && gar->port_name == 0 && 1906 gar->node_name == 0) { 1907 DPRINTF(QLE_D_PORT, "%s: GA_NXT returned junk\n", DEVNAME(sc)); 1908 return (NULL); 1909 } 1910 1911 /* are we back at the start? */ 1912 *lastport = betoh32(gar->port_type_id) & 0xffffff; 1913 if (*lastport == *firstport) { 1914 *lastport = 0xffffffff; 1915 return (NULL); 1916 } 1917 if (*firstport == 0xffffffff) 1918 *firstport = *lastport; 1919 1920 DPRINTF(QLE_D_PORT, "%s: GA_NXT: port id: %06x, wwpn %llx, wwnn %llx\n", 1921 DEVNAME(sc), *lastport, betoh64(gar->port_name), 1922 betoh64(gar->node_name)); 1923 1924 /* don't try to log in to ourselves */ 1925 if (*lastport == sc->sc_port_id) { 1926 return (NULL); 1927 } 1928 1929 fport = malloc(sizeof(*fport), M_DEVBUF, M_ZERO | M_NOWAIT); 1930 if (fport == NULL) { 1931 printf("%s: failed to allocate a port struct\n", 1932 DEVNAME(sc)); 1933 *lastport = 0xffffffff; 1934 return (NULL); 1935 } 1936 fport->port_name = betoh64(gar->port_name); 1937 fport->node_name = betoh64(gar->node_name); 1938 fport->location = QLE_LOCATION_PORT_ID(*lastport); 1939 fport->portid = *lastport; 1940 return (fport); 1941 } 1942 1943 int 1944 qle_fabric_plogx(struct qle_softc *sc, struct qle_fc_port *port, int flags, 1945 u_int32_t *info) 1946 { 1947 struct qle_iocb_plogx *iocb; 1948 u_int16_t req; 1949 u_int64_t offset; 1950 int rv; 1951 1952 mtx_enter(&sc->sc_queue_mtx); 1953 1954 req = sc->sc_next_req_id++; 1955 if (sc->sc_next_req_id == sc->sc_maxcmds) 1956 sc->sc_next_req_id = 0; 1957 1958 offset = (req * QLE_QUEUE_ENTRY_SIZE); 1959 iocb = QLE_DMA_KVA(sc->sc_requests) + offset; 1960 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(sc->sc_requests), offset, 1961 QLE_QUEUE_ENTRY_SIZE, BUS_DMASYNC_POSTWRITE); 1962 1963 memset(iocb, 0, QLE_QUEUE_ENTRY_SIZE); 1964 iocb->entry_type = QLE_IOCB_PLOGX; 1965 iocb->entry_count = 1; 1966 1967 iocb->req_handle = 7; 1968 htolem16(&iocb->req_nport_handle, port->loopid); 1969 htolem16(&iocb->req_port_id_lo, port->portid); 1970 iocb->req_port_id_hi = port->portid >> 16; 1971 htolem16(&iocb->req_flags, flags); 1972 1973 DPRINTF(QLE_D_PORT, "%s: plogx loop id %d port %06x, flags %x\n", 1974 DEVNAME(sc), port->loopid, port->portid, flags); 1975 qle_dump_iocb(sc, iocb); 1976 1977 qle_write(sc, QLE_REQ_IN, sc->sc_next_req_id); 1978 sc->sc_fabric_pending = 1; 1979 mtx_leave(&sc->sc_queue_mtx); 1980 1981 /* maybe put a proper timeout on this */ 1982 rv = 0; 1983 while (sc->sc_fabric_pending == 1) { 1984 if (sc->sc_scsibus == NULL) { 1985 u_int16_t isr, info; 1986 1987 delay(100); 1988 if (qle_read_isr(sc, &isr, &info) != 0) 1989 qle_handle_intr(sc, isr, info); 1990 } else { 1991 tsleep(sc->sc_scratch, PRIBIO, "qle_fabric", 100); 1992 } 1993 } 1994 sc->sc_fabric_pending = 0; 1995 1996 iocb = (struct qle_iocb_plogx *)&sc->sc_fabric_response; 1997 rv = lemtoh16(&iocb->req_status); 1998 if (rv == QLE_PLOGX_ERROR) { 1999 rv = lemtoh32(&iocb->req_ioparms[0]); 2000 *info = lemtoh32(&iocb->req_ioparms[1]); 2001 } 2002 2003 return (rv); 2004 } 2005 2006 int 2007 qle_fabric_plogi(struct qle_softc *sc, struct qle_fc_port *port) 2008 { 2009 u_int32_t info; 2010 int err, loopid; 2011 2012 loopid = 0; 2013 retry: 2014 if (port->loopid == 0) { 2015 2016 mtx_enter(&sc->sc_port_mtx); 2017 loopid = qle_get_loop_id(sc, loopid); 2018 mtx_leave(&sc->sc_port_mtx); 2019 if (loopid == -1) { 2020 printf("%s: ran out of loop ids\n", DEVNAME(sc)); 2021 return (1); 2022 } 2023 2024 port->loopid = loopid; 2025 } 2026 2027 err = qle_fabric_plogx(sc, port, QLE_PLOGX_LOGIN, &info); 2028 switch (err) { 2029 case 0: 2030 DPRINTF(QLE_D_PORT, "%s: logged in to %06x as %d\n", 2031 DEVNAME(sc), port->portid, port->loopid); 2032 port->flags &= ~QLE_PORT_FLAG_NEEDS_LOGIN; 2033 return (0); 2034 2035 case QLE_PLOGX_ERROR_PORT_ID_USED: 2036 DPRINTF(QLE_D_PORT, "%s: already logged in to %06x as %d\n", 2037 DEVNAME(sc), port->portid, info); 2038 port->loopid = info; 2039 port->flags &= ~QLE_PORT_FLAG_NEEDS_LOGIN; 2040 return (0); 2041 2042 case QLE_PLOGX_ERROR_HANDLE_USED: 2043 if (qle_add_logged_in_port(sc, loopid, info)) { 2044 return (1); 2045 } 2046 port->loopid = 0; 2047 loopid++; 2048 goto retry; 2049 2050 default: 2051 DPRINTF(QLE_D_PORT, "%s: error %x logging in to port %06x\n", 2052 DEVNAME(sc), err, port->portid); 2053 port->loopid = 0; 2054 return (1); 2055 } 2056 } 2057 2058 void 2059 qle_fabric_plogo(struct qle_softc *sc, struct qle_fc_port *port) 2060 { 2061 int err; 2062 u_int32_t info; 2063 2064 /* 2065 * we only log out if we can't see the port any more, so we always 2066 * want to do an explicit logout and free the n-port handle. 2067 */ 2068 err = qle_fabric_plogx(sc, port, QLE_PLOGX_LOGOUT | 2069 QLE_PLOGX_LOGOUT_EXPLICIT | QLE_PLOGX_LOGOUT_FREE_HANDLE, &info); 2070 if (err == 0) { 2071 DPRINTF(QLE_D_PORT, "%s: logged out of port %06x\n", 2072 DEVNAME(sc), port->portid); 2073 } else { 2074 DPRINTF(QLE_D_PORT, "%s: failed to log out of port %06x: " 2075 "%x %x\n", DEVNAME(sc), port->portid, err, info); 2076 } 2077 } 2078 2079 void 2080 qle_do_update(void *xsc) 2081 { 2082 struct qle_softc *sc = xsc; 2083 int firstport, lastport; 2084 struct qle_fc_port *port, *fport; 2085 2086 DPRINTF(QLE_D_PORT, "%s: updating\n", DEVNAME(sc)); 2087 while (sc->sc_update_tasks != 0) { 2088 if (sc->sc_update_tasks & QLE_UPDATE_TASK_CLEAR_ALL) { 2089 TAILQ_HEAD(, qle_fc_port) detach; 2090 DPRINTF(QLE_D_PORT, "%s: detaching everything\n", 2091 DEVNAME(sc)); 2092 2093 mtx_enter(&sc->sc_port_mtx); 2094 qle_clear_port_lists(sc); 2095 TAILQ_INIT(&detach); 2096 while (!TAILQ_EMPTY(&sc->sc_ports)) { 2097 port = TAILQ_FIRST(&sc->sc_ports); 2098 TAILQ_REMOVE(&sc->sc_ports, port, ports); 2099 TAILQ_INSERT_TAIL(&detach, port, ports); 2100 } 2101 mtx_leave(&sc->sc_port_mtx); 2102 2103 while (!TAILQ_EMPTY(&detach)) { 2104 port = TAILQ_FIRST(&detach); 2105 TAILQ_REMOVE(&detach, port, ports); 2106 if (port->flags & QLE_PORT_FLAG_IS_TARGET) { 2107 scsi_detach_target(sc->sc_scsibus, 2108 port->loopid, -1); 2109 sc->sc_targets[port->loopid] = NULL; 2110 } 2111 if (port->location & QLE_LOCATION_FABRIC) 2112 qle_fabric_plogo(sc, port); 2113 2114 free(port, M_DEVBUF, sizeof *port); 2115 } 2116 2117 qle_update_done(sc, QLE_UPDATE_TASK_CLEAR_ALL); 2118 continue; 2119 } 2120 2121 if (sc->sc_update_tasks & QLE_UPDATE_TASK_SOFTRESET) { 2122 DPRINTF(QLE_D_IO, "%s: attempting softreset\n", 2123 DEVNAME(sc)); 2124 if (qle_softreset(sc) != 0) { 2125 DPRINTF(QLE_D_IO, "%s: couldn't softreset\n", 2126 DEVNAME(sc)); 2127 } 2128 qle_update_done(sc, QLE_UPDATE_TASK_SOFTRESET); 2129 continue; 2130 } 2131 2132 if (sc->sc_update_tasks & QLE_UPDATE_TASK_UPDATE_TOPO) { 2133 DPRINTF(QLE_D_PORT, "%s: updating topology\n", 2134 DEVNAME(sc)); 2135 qle_update_topology(sc); 2136 qle_update_done(sc, QLE_UPDATE_TASK_UPDATE_TOPO); 2137 continue; 2138 } 2139 2140 if (sc->sc_update_tasks & QLE_UPDATE_TASK_GET_PORT_LIST) { 2141 DPRINTF(QLE_D_PORT, "%s: getting port name list\n", 2142 DEVNAME(sc)); 2143 mtx_enter(&sc->sc_port_mtx); 2144 qle_clear_port_lists(sc); 2145 mtx_leave(&sc->sc_port_mtx); 2146 2147 qle_get_port_name_list(sc, QLE_LOCATION_LOOP | 2148 QLE_LOCATION_FABRIC); 2149 mtx_enter(&sc->sc_port_mtx); 2150 TAILQ_FOREACH(port, &sc->sc_ports, ports) { 2151 TAILQ_INSERT_TAIL(&sc->sc_ports_gone, port, 2152 update); 2153 if (port->location & QLE_LOCATION_FABRIC) { 2154 port->flags |= 2155 QLE_PORT_FLAG_NEEDS_LOGIN; 2156 } 2157 } 2158 2159 /* take care of ports that haven't changed first */ 2160 TAILQ_FOREACH(fport, &sc->sc_ports_found, update) { 2161 port = sc->sc_targets[fport->loopid]; 2162 if (port == NULL || fport->port_name != 2163 port->port_name) { 2164 /* new or changed port, handled later */ 2165 continue; 2166 } 2167 2168 /* 2169 * the port hasn't been logged out, which 2170 * means we don't need to log in again, and, 2171 * for loop ports, that the port still exists 2172 */ 2173 port->flags &= ~QLE_PORT_FLAG_NEEDS_LOGIN; 2174 if (port->location & QLE_LOCATION_LOOP) 2175 TAILQ_REMOVE(&sc->sc_ports_gone, 2176 port, update); 2177 2178 fport->location = 0; 2179 } 2180 mtx_leave(&sc->sc_port_mtx); 2181 qle_update_start(sc, QLE_UPDATE_TASK_PORT_LIST); 2182 qle_update_done(sc, QLE_UPDATE_TASK_GET_PORT_LIST); 2183 continue; 2184 } 2185 2186 if (sc->sc_update_tasks & QLE_UPDATE_TASK_PORT_LIST) { 2187 mtx_enter(&sc->sc_port_mtx); 2188 fport = TAILQ_FIRST(&sc->sc_ports_found); 2189 if (fport != NULL) { 2190 TAILQ_REMOVE(&sc->sc_ports_found, fport, 2191 update); 2192 } 2193 mtx_leave(&sc->sc_port_mtx); 2194 2195 if (fport == NULL) { 2196 DPRINTF(QLE_D_PORT, "%s: done with ports\n", 2197 DEVNAME(sc)); 2198 qle_update_done(sc, 2199 QLE_UPDATE_TASK_PORT_LIST); 2200 qle_update_start(sc, 2201 QLE_UPDATE_TASK_SCAN_FABRIC); 2202 } else if (fport->location & QLE_LOCATION_LOOP) { 2203 DPRINTF(QLE_D_PORT, "%s: loop port %04x\n", 2204 DEVNAME(sc), fport->loopid); 2205 if (qle_add_loop_port(sc, fport) != 0) 2206 free(fport, M_DEVBUF, sizeof *port); 2207 } else if (fport->location & QLE_LOCATION_FABRIC) { 2208 qle_add_fabric_port(sc, fport); 2209 } else { 2210 /* already processed */ 2211 free(fport, M_DEVBUF, sizeof *port); 2212 } 2213 continue; 2214 } 2215 2216 if (sc->sc_update_tasks & QLE_UPDATE_TASK_SCAN_FABRIC) { 2217 DPRINTF(QLE_D_PORT, "%s: starting fabric scan\n", 2218 DEVNAME(sc)); 2219 lastport = sc->sc_port_id; 2220 firstport = 0xffffffff; 2221 if (qle_update_fabric(sc)) 2222 qle_update_start(sc, 2223 QLE_UPDATE_TASK_SCANNING_FABRIC); 2224 2225 qle_update_done(sc, QLE_UPDATE_TASK_SCAN_FABRIC); 2226 continue; 2227 } 2228 2229 if (sc->sc_update_tasks & QLE_UPDATE_TASK_SCANNING_FABRIC) { 2230 fport = qle_next_fabric_port(sc, &firstport, &lastport); 2231 if (fport != NULL) { 2232 int disp; 2233 2234 mtx_enter(&sc->sc_port_mtx); 2235 disp = qle_classify_port(sc, fport->location, 2236 fport->port_name, fport->node_name, &port); 2237 switch (disp) { 2238 case QLE_PORT_DISP_CHANGED: 2239 case QLE_PORT_DISP_MOVED: 2240 /* we'll log out the old port later */ 2241 case QLE_PORT_DISP_NEW: 2242 DPRINTF(QLE_D_PORT, "%s: new port " 2243 "%06x\n", DEVNAME(sc), 2244 fport->portid); 2245 TAILQ_INSERT_TAIL(&sc->sc_ports_found, 2246 fport, update); 2247 break; 2248 case QLE_PORT_DISP_DUP: 2249 free(fport, M_DEVBUF, sizeof *port); 2250 break; 2251 case QLE_PORT_DISP_SAME: 2252 DPRINTF(QLE_D_PORT, "%s: existing port " 2253 " %06x\n", DEVNAME(sc), 2254 fport->portid); 2255 TAILQ_REMOVE(&sc->sc_ports_gone, port, 2256 update); 2257 free(fport, M_DEVBUF, sizeof *port); 2258 break; 2259 } 2260 mtx_leave(&sc->sc_port_mtx); 2261 } 2262 if (lastport == 0xffffffff) { 2263 DPRINTF(QLE_D_PORT, "%s: finished\n", 2264 DEVNAME(sc)); 2265 qle_update_done(sc, 2266 QLE_UPDATE_TASK_SCANNING_FABRIC); 2267 qle_update_start(sc, 2268 QLE_UPDATE_TASK_FABRIC_LOGIN); 2269 } 2270 continue; 2271 } 2272 2273 if (sc->sc_update_tasks & QLE_UPDATE_TASK_FABRIC_LOGIN) { 2274 mtx_enter(&sc->sc_port_mtx); 2275 port = TAILQ_FIRST(&sc->sc_ports_found); 2276 if (port != NULL) { 2277 TAILQ_REMOVE(&sc->sc_ports_found, port, update); 2278 } 2279 mtx_leave(&sc->sc_port_mtx); 2280 2281 if (port != NULL) { 2282 DPRINTF(QLE_D_PORT, "%s: found port %06x\n", 2283 DEVNAME(sc), port->portid); 2284 if (qle_fabric_plogi(sc, port) == 0) { 2285 qle_add_fabric_port(sc, port); 2286 } else { 2287 DPRINTF(QLE_D_PORT, "%s: plogi %06x " 2288 "failed\n", DEVNAME(sc), 2289 port->portid); 2290 free(port, M_DEVBUF, sizeof *port); 2291 } 2292 } else { 2293 DPRINTF(QLE_D_PORT, "%s: done with logins\n", 2294 DEVNAME(sc)); 2295 qle_update_done(sc, 2296 QLE_UPDATE_TASK_FABRIC_LOGIN); 2297 qle_update_start(sc, 2298 QLE_UPDATE_TASK_ATTACH_TARGET | 2299 QLE_UPDATE_TASK_DETACH_TARGET); 2300 } 2301 continue; 2302 } 2303 2304 if (sc->sc_update_tasks & QLE_UPDATE_TASK_FABRIC_RELOGIN) { 2305 TAILQ_FOREACH(port, &sc->sc_ports, ports) { 2306 if (port->flags & QLE_PORT_FLAG_NEEDS_LOGIN) { 2307 qle_fabric_plogi(sc, port); 2308 break; 2309 } 2310 } 2311 2312 if (port == NULL) 2313 qle_update_done(sc, 2314 QLE_UPDATE_TASK_FABRIC_RELOGIN); 2315 continue; 2316 } 2317 2318 if (sc->sc_update_tasks & QLE_UPDATE_TASK_DETACH_TARGET) { 2319 mtx_enter(&sc->sc_port_mtx); 2320 port = TAILQ_FIRST(&sc->sc_ports_gone); 2321 if (port != NULL) { 2322 sc->sc_targets[port->loopid] = NULL; 2323 TAILQ_REMOVE(&sc->sc_ports_gone, port, update); 2324 TAILQ_REMOVE(&sc->sc_ports, port, ports); 2325 } 2326 mtx_leave(&sc->sc_port_mtx); 2327 2328 if (port != NULL) { 2329 DPRINTF(QLE_D_PORT, "%s: detaching port %06x\n", 2330 DEVNAME(sc), port->portid); 2331 if (sc->sc_scsibus != NULL) 2332 scsi_detach_target(sc->sc_scsibus, 2333 port->loopid, -1); 2334 2335 if (port->location & QLE_LOCATION_FABRIC) 2336 qle_fabric_plogo(sc, port); 2337 2338 free(port, M_DEVBUF, sizeof *port); 2339 } else { 2340 DPRINTF(QLE_D_PORT, "%s: nothing to detach\n", 2341 DEVNAME(sc)); 2342 qle_update_done(sc, 2343 QLE_UPDATE_TASK_DETACH_TARGET); 2344 } 2345 continue; 2346 } 2347 2348 if (sc->sc_update_tasks & QLE_UPDATE_TASK_ATTACH_TARGET) { 2349 mtx_enter(&sc->sc_port_mtx); 2350 port = TAILQ_FIRST(&sc->sc_ports_new); 2351 if (port != NULL) { 2352 TAILQ_REMOVE(&sc->sc_ports_new, port, update); 2353 TAILQ_INSERT_TAIL(&sc->sc_ports, port, ports); 2354 } 2355 mtx_leave(&sc->sc_port_mtx); 2356 2357 if (port != NULL) { 2358 if (sc->sc_scsibus != NULL) 2359 scsi_probe_target(sc->sc_scsibus, 2360 port->loopid); 2361 } else { 2362 qle_update_done(sc, 2363 QLE_UPDATE_TASK_ATTACH_TARGET); 2364 } 2365 continue; 2366 } 2367 2368 } 2369 2370 DPRINTF(QLE_D_PORT, "%s: done updating\n", DEVNAME(sc)); 2371 } 2372 2373 int 2374 qle_async(struct qle_softc *sc, u_int16_t info) 2375 { 2376 switch (info) { 2377 case QLE_ASYNC_SYSTEM_ERROR: 2378 qle_update_start(sc, QLE_UPDATE_TASK_SOFTRESET); 2379 break; 2380 2381 case QLE_ASYNC_REQ_XFER_ERROR: 2382 qle_update_start(sc, QLE_UPDATE_TASK_SOFTRESET); 2383 break; 2384 2385 case QLE_ASYNC_RSP_XFER_ERROR: 2386 qle_update_start(sc, QLE_UPDATE_TASK_SOFTRESET); 2387 break; 2388 2389 case QLE_ASYNC_LIP_OCCURRED: 2390 DPRINTF(QLE_D_INTR, "%s: lip occurred\n", DEVNAME(sc)); 2391 break; 2392 2393 case QLE_ASYNC_LOOP_UP: 2394 DPRINTF(QLE_D_PORT, "%s: loop up\n", DEVNAME(sc)); 2395 sc->sc_loop_up = 1; 2396 sc->sc_marker_required = 1; 2397 qle_update_start(sc, QLE_UPDATE_TASK_UPDATE_TOPO | 2398 QLE_UPDATE_TASK_GET_PORT_LIST); 2399 break; 2400 2401 case QLE_ASYNC_LOOP_DOWN: 2402 DPRINTF(QLE_D_PORT, "%s: loop down\n", DEVNAME(sc)); 2403 sc->sc_loop_up = 0; 2404 qle_update_start(sc, QLE_UPDATE_TASK_CLEAR_ALL); 2405 break; 2406 2407 case QLE_ASYNC_LIP_RESET: 2408 DPRINTF(QLE_D_PORT, "%s: lip reset\n", DEVNAME(sc)); 2409 sc->sc_marker_required = 1; 2410 qle_update_start(sc, QLE_UPDATE_TASK_FABRIC_RELOGIN); 2411 break; 2412 2413 case QLE_ASYNC_PORT_DB_CHANGE: 2414 DPRINTF(QLE_D_PORT, "%s: port db changed %x\n", DEVNAME(sc), 2415 qle_read_mbox(sc, 1)); 2416 qle_update_start(sc, QLE_UPDATE_TASK_GET_PORT_LIST); 2417 break; 2418 2419 case QLE_ASYNC_CHANGE_NOTIFY: 2420 DPRINTF(QLE_D_PORT, "%s: name server change (%02x:%02x)\n", 2421 DEVNAME(sc), qle_read_mbox(sc, 1), qle_read_mbox(sc, 2)); 2422 qle_update_start(sc, QLE_UPDATE_TASK_GET_PORT_LIST); 2423 break; 2424 2425 case QLE_ASYNC_LIP_F8: 2426 DPRINTF(QLE_D_INTR, "%s: lip f8\n", DEVNAME(sc)); 2427 break; 2428 2429 case QLE_ASYNC_LOOP_INIT_ERROR: 2430 DPRINTF(QLE_D_PORT, "%s: loop initialization error: %x\n", 2431 DEVNAME(sc), qle_read_mbox(sc, 1)); 2432 break; 2433 2434 case QLE_ASYNC_POINT_TO_POINT: 2435 DPRINTF(QLE_D_PORT, "%s: connected in point-to-point mode\n", 2436 DEVNAME(sc)); 2437 break; 2438 2439 case QLE_ASYNC_ZIO_RESP_UPDATE: 2440 /* shouldn't happen, we don't do zio */ 2441 break; 2442 2443 default: 2444 DPRINTF(QLE_D_INTR, "%s: unknown async %x\n", DEVNAME(sc), info); 2445 break; 2446 } 2447 return (1); 2448 } 2449 2450 void 2451 qle_dump_stuff(struct qle_softc *sc, void *buf, int n) 2452 { 2453 #ifdef QLE_DEBUG 2454 u_int8_t *d = buf; 2455 int l; 2456 2457 if ((qledebug & QLE_D_IOCB) == 0) 2458 return; 2459 2460 printf("%s: stuff\n", DEVNAME(sc)); 2461 for (l = 0; l < n; l++) { 2462 printf(" %2.2x", d[l]); 2463 if (l % 16 == 15) 2464 printf("\n"); 2465 } 2466 if (n % 16 != 0) 2467 printf("\n"); 2468 #endif 2469 } 2470 2471 void 2472 qle_dump_iocb(struct qle_softc *sc, void *buf) 2473 { 2474 #ifdef QLE_DEBUG 2475 u_int8_t *iocb = buf; 2476 int l; 2477 int b; 2478 2479 if ((qledebug & QLE_D_IOCB) == 0) 2480 return; 2481 2482 printf("%s: iocb:\n", DEVNAME(sc)); 2483 for (l = 0; l < 4; l++) { 2484 for (b = 0; b < 16; b++) { 2485 printf(" %2.2x", iocb[(l*16)+b]); 2486 } 2487 printf("\n"); 2488 } 2489 #endif 2490 } 2491 2492 void 2493 qle_dump_iocb_segs(struct qle_softc *sc, void *segs, int n) 2494 { 2495 #ifdef QLE_DEBUG 2496 u_int8_t *buf = segs; 2497 int s, b; 2498 2499 if ((qledebug & QLE_D_IOCB) == 0) 2500 return; 2501 2502 printf("%s: iocb segs:\n", DEVNAME(sc)); 2503 for (s = 0; s < n; s++) { 2504 for (b = 0; b < sizeof(struct qle_iocb_seg); b++) { 2505 printf(" %2.2x", buf[(s*(sizeof(struct qle_iocb_seg))) 2506 + b]); 2507 } 2508 printf("\n"); 2509 } 2510 #endif 2511 } 2512 2513 void 2514 qle_put_marker(struct qle_softc *sc, void *buf) 2515 { 2516 struct qle_iocb_marker *marker = buf; 2517 2518 marker->entry_type = QLE_IOCB_MARKER; 2519 marker->entry_count = 1; 2520 marker->seqno = 0; 2521 marker->flags = 0; 2522 2523 /* could be more specific here; isp(4) isn't */ 2524 marker->target = 0; 2525 marker->modifier = QLE_IOCB_MARKER_SYNC_ALL; 2526 } 2527 2528 void 2529 qle_sge(struct qle_iocb_seg *seg, u_int64_t addr, u_int32_t len) 2530 { 2531 htolem32(&seg->seg_addr_lo, addr); 2532 htolem32(&seg->seg_addr_hi, addr >> 32); 2533 htolem32(&seg->seg_len, len); 2534 } 2535 2536 void 2537 qle_put_cmd(struct qle_softc *sc, void *buf, struct scsi_xfer *xs, 2538 struct qle_ccb *ccb, u_int32_t target_port) 2539 { 2540 bus_dmamap_t dmap = ccb->ccb_dmamap; 2541 struct qle_iocb_req6 *req = buf; 2542 struct qle_fcp_cmnd *cmnd; 2543 u_int64_t fcp_cmnd_offset; 2544 u_int32_t fcp_dl; 2545 int seg; 2546 int target = xs->sc_link->target; 2547 int lun = xs->sc_link->lun; 2548 u_int16_t flags; 2549 2550 memset(req, 0, sizeof(*req)); 2551 req->entry_type = QLE_IOCB_CMD_TYPE_6; 2552 req->entry_count = 1; 2553 2554 req->req_handle = ccb->ccb_id; 2555 htolem16(&req->req_nport_handle, target); 2556 2557 /* 2558 * timeout is in seconds. make sure it's at least 1 if a timeout 2559 * was specified in xs 2560 */ 2561 if (xs->timeout != 0) 2562 htolem16(&req->req_timeout, MAX(1, xs->timeout/1000)); 2563 2564 if (xs->datalen > 0) { 2565 flags = (xs->flags & SCSI_DATA_IN) ? 2566 QLE_IOCB_CTRL_FLAG_READ : QLE_IOCB_CTRL_FLAG_WRITE; 2567 if (dmap->dm_nsegs == 1) { 2568 qle_sge(&req->req_data_seg, dmap->dm_segs[0].ds_addr, 2569 dmap->dm_segs[0].ds_len); 2570 } else { 2571 flags |= QLE_IOCB_CTRL_FLAG_EXT_SEG; 2572 for (seg = 0; seg < dmap->dm_nsegs; seg++) { 2573 qle_sge(&ccb->ccb_segs[seg], 2574 dmap->dm_segs[seg].ds_addr, 2575 dmap->dm_segs[seg].ds_len); 2576 } 2577 qle_sge(&ccb->ccb_segs[seg++], 0, 0); 2578 2579 bus_dmamap_sync(sc->sc_dmat, 2580 QLE_DMA_MAP(sc->sc_segments), ccb->ccb_seg_offset, 2581 seg * sizeof(*ccb->ccb_segs), 2582 BUS_DMASYNC_PREWRITE); 2583 2584 qle_sge(&req->req_data_seg, 2585 QLE_DMA_DVA(sc->sc_segments) + ccb->ccb_seg_offset, 2586 seg * sizeof(struct qle_iocb_seg)); 2587 } 2588 2589 htolem16(&req->req_data_seg_count, dmap->dm_nsegs); 2590 htolem32(&req->req_data_len, xs->datalen); 2591 htolem16(&req->req_ctrl_flags, flags); 2592 } 2593 2594 htobem16(&req->req_fcp_lun[0], lun); 2595 htobem16(&req->req_fcp_lun[1], lun >> 16); 2596 htolem32(&req->req_target_id, target_port & 0xffffff); 2597 2598 fcp_cmnd_offset = ccb->ccb_id * sizeof(*cmnd); 2599 /* set up FCP_CMND */ 2600 cmnd = (struct qle_fcp_cmnd *)QLE_DMA_KVA(sc->sc_fcp_cmnds) + 2601 ccb->ccb_id; 2602 2603 memset(cmnd, 0, sizeof(*cmnd)); 2604 htobem16(&cmnd->fcp_lun[0], lun); 2605 htobem16(&cmnd->fcp_lun[1], lun >> 16); 2606 /* cmnd->fcp_task_attr = TSK_SIMPLE; */ 2607 /* cmnd->fcp_task_mgmt = 0; */ 2608 memcpy(cmnd->fcp_cdb, xs->cmd, xs->cmdlen); 2609 2610 /* FCP_DL goes after the cdb */ 2611 fcp_dl = htobe32(xs->datalen); 2612 if (xs->cmdlen > 16) { 2613 htolem16(&req->req_fcp_cmnd_len, 12 + xs->cmdlen + 4); 2614 cmnd->fcp_add_cdb_len = xs->cmdlen - 16; 2615 memcpy(cmnd->fcp_cdb + xs->cmdlen, &fcp_dl, sizeof(fcp_dl)); 2616 } else { 2617 htolem16(&req->req_fcp_cmnd_len, 12 + 16 + 4); 2618 cmnd->fcp_add_cdb_len = 0; 2619 memcpy(cmnd->fcp_cdb + 16, &fcp_dl, sizeof(fcp_dl)); 2620 } 2621 if (xs->datalen > 0) 2622 cmnd->fcp_add_cdb_len |= (xs->flags & SCSI_DATA_IN) ? 2 : 1; 2623 2624 bus_dmamap_sync(sc->sc_dmat, 2625 QLE_DMA_MAP(sc->sc_fcp_cmnds), fcp_cmnd_offset, 2626 sizeof(*cmnd), BUS_DMASYNC_PREWRITE); 2627 2628 /* link req to cmnd */ 2629 fcp_cmnd_offset += QLE_DMA_DVA(sc->sc_fcp_cmnds); 2630 htolem32(&req->req_fcp_cmnd_addr_lo, fcp_cmnd_offset); 2631 htolem32(&req->req_fcp_cmnd_addr_hi, fcp_cmnd_offset >> 32); 2632 } 2633 2634 int 2635 qle_load_fwchunk(struct qle_softc *sc, struct qle_dmamem *mem, 2636 const u_int32_t *src) 2637 { 2638 u_int32_t dest, done, total; 2639 int i; 2640 2641 dest = src[2]; 2642 done = 0; 2643 total = src[3]; 2644 2645 while (done < total) { 2646 u_int32_t *copy; 2647 u_int32_t words; 2648 2649 /* limit transfer size otherwise it just doesn't work */ 2650 words = MIN(total - done, 1 << 10); 2651 copy = QLE_DMA_KVA(mem); 2652 for (i = 0; i < words; i++) { 2653 htolem32(©[i], src[done++]); 2654 } 2655 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(mem), 0, words * 4, 2656 BUS_DMASYNC_PREWRITE); 2657 2658 sc->sc_mbox[0] = QLE_MBOX_LOAD_RISC_RAM; 2659 sc->sc_mbox[1] = dest; 2660 sc->sc_mbox[4] = words >> 16; 2661 sc->sc_mbox[5] = words & 0xffff; 2662 sc->sc_mbox[8] = dest >> 16; 2663 qle_mbox_putaddr(sc->sc_mbox, mem); 2664 if (qle_mbox(sc, 0x01ff)) { 2665 printf("firmware load failed\n"); 2666 return (1); 2667 } 2668 bus_dmamap_sync(sc->sc_dmat, QLE_DMA_MAP(mem), 0, words * 4, 2669 BUS_DMASYNC_POSTWRITE); 2670 2671 dest += words; 2672 } 2673 2674 return (qle_verify_firmware(sc, src[2])); 2675 } 2676 2677 int 2678 qle_load_firmware_chunks(struct qle_softc *sc, const u_int32_t *fw) 2679 { 2680 struct qle_dmamem *mem; 2681 int res = 0; 2682 2683 mem = qle_dmamem_alloc(sc, 65536); 2684 for (;;) { 2685 if (qle_load_fwchunk(sc, mem, fw)) { 2686 res = 1; 2687 break; 2688 } 2689 if (fw[1] == 0) 2690 break; 2691 fw += fw[3]; 2692 } 2693 2694 qle_dmamem_free(sc, mem); 2695 return (res); 2696 } 2697 2698 u_int32_t 2699 qle_read_ram_word(struct qle_softc *sc, u_int32_t addr) 2700 { 2701 sc->sc_mbox[0] = QLE_MBOX_READ_RISC_RAM; 2702 sc->sc_mbox[1] = addr & 0xffff; 2703 sc->sc_mbox[8] = addr >> 16; 2704 if (qle_mbox(sc, 0x0103)) { 2705 return (0); 2706 } 2707 return ((sc->sc_mbox[3] << 16) | sc->sc_mbox[2]); 2708 } 2709 2710 int 2711 qle_verify_firmware(struct qle_softc *sc, u_int32_t addr) 2712 { 2713 /* 2714 * QLE_MBOX_VERIFY_CSUM requires at least the firmware header 2715 * to be correct, otherwise it wanders all over ISP memory and 2716 * gets lost. Check that chunk address (addr+2) is right and 2717 * size (addr+3) is plausible first. 2718 */ 2719 if ((qle_read_ram_word(sc, addr+2) != addr) || 2720 (qle_read_ram_word(sc, addr+3) > 0xffff)) { 2721 return (1); 2722 } 2723 2724 sc->sc_mbox[0] = QLE_MBOX_VERIFY_CSUM; 2725 sc->sc_mbox[1] = addr >> 16; 2726 sc->sc_mbox[2] = addr; 2727 if (qle_mbox(sc, 0x0007)) { 2728 return (1); 2729 } 2730 return (0); 2731 } 2732 2733 int 2734 qle_read_nvram(struct qle_softc *sc) 2735 { 2736 u_int32_t data[sizeof(sc->sc_nvram) / 4]; 2737 u_int32_t csum, tmp, v; 2738 int i, base, l; 2739 2740 switch (sc->sc_isp_gen) { 2741 case QLE_GEN_ISP24XX: 2742 base = 0x7ffe0080; 2743 break; 2744 case QLE_GEN_ISP25XX: 2745 base = 0x7ff48080; 2746 break; 2747 } 2748 base += sc->sc_port * 0x100; 2749 2750 csum = 0; 2751 for (i = 0; i < nitems(data); i++) { 2752 data[i] = 0xffffffff; 2753 qle_write(sc, QLE_FLASH_NVRAM_ADDR, base + i); 2754 for (l = 0; l < 5000; l++) { 2755 delay(10); 2756 tmp = qle_read(sc, QLE_FLASH_NVRAM_ADDR); 2757 if (tmp & (1U << 31)) { 2758 v = qle_read(sc, QLE_FLASH_NVRAM_DATA); 2759 csum += v; 2760 data[i] = letoh32(v); 2761 break; 2762 } 2763 } 2764 } 2765 2766 bcopy(data, &sc->sc_nvram, sizeof(sc->sc_nvram)); 2767 /* id field should be 'ISP' */ 2768 if (sc->sc_nvram.id[0] != 'I' || sc->sc_nvram.id[1] != 'S' || 2769 sc->sc_nvram.id[2] != 'P' || csum != 0) { 2770 printf("%s: nvram corrupt\n", DEVNAME(sc)); 2771 return (1); 2772 } 2773 return (0); 2774 } 2775 2776 struct qle_dmamem * 2777 qle_dmamem_alloc(struct qle_softc *sc, size_t size) 2778 { 2779 struct qle_dmamem *m; 2780 int nsegs; 2781 2782 m = malloc(sizeof(*m), M_DEVBUF, M_NOWAIT | M_ZERO); 2783 if (m == NULL) 2784 return (NULL); 2785 2786 m->qdm_size = size; 2787 2788 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 2789 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &m->qdm_map) != 0) 2790 goto qdmfree; 2791 2792 if (bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &m->qdm_seg, 1, 2793 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0) 2794 goto destroy; 2795 2796 if (bus_dmamem_map(sc->sc_dmat, &m->qdm_seg, nsegs, size, &m->qdm_kva, 2797 BUS_DMA_NOWAIT) != 0) 2798 goto free; 2799 2800 if (bus_dmamap_load(sc->sc_dmat, m->qdm_map, m->qdm_kva, size, NULL, 2801 BUS_DMA_NOWAIT) != 0) 2802 goto unmap; 2803 2804 return (m); 2805 2806 unmap: 2807 bus_dmamem_unmap(sc->sc_dmat, m->qdm_kva, m->qdm_size); 2808 free: 2809 bus_dmamem_free(sc->sc_dmat, &m->qdm_seg, 1); 2810 destroy: 2811 bus_dmamap_destroy(sc->sc_dmat, m->qdm_map); 2812 qdmfree: 2813 free(m, M_DEVBUF, sizeof *m); 2814 2815 return (NULL); 2816 } 2817 2818 void 2819 qle_dmamem_free(struct qle_softc *sc, struct qle_dmamem *m) 2820 { 2821 bus_dmamap_unload(sc->sc_dmat, m->qdm_map); 2822 bus_dmamem_unmap(sc->sc_dmat, m->qdm_kva, m->qdm_size); 2823 bus_dmamem_free(sc->sc_dmat, &m->qdm_seg, 1); 2824 bus_dmamap_destroy(sc->sc_dmat, m->qdm_map); 2825 free(m, M_DEVBUF, sizeof *m); 2826 } 2827 2828 int 2829 qle_alloc_ccbs(struct qle_softc *sc) 2830 { 2831 struct qle_ccb *ccb; 2832 u_int8_t *cmd; 2833 int i; 2834 2835 SIMPLEQ_INIT(&sc->sc_ccb_free); 2836 mtx_init(&sc->sc_ccb_mtx, IPL_BIO); 2837 mtx_init(&sc->sc_queue_mtx, IPL_BIO); 2838 mtx_init(&sc->sc_port_mtx, IPL_BIO); 2839 mtx_init(&sc->sc_mbox_mtx, IPL_BIO); 2840 2841 sc->sc_ccbs = mallocarray(sc->sc_maxcmds, sizeof(struct qle_ccb), 2842 M_DEVBUF, M_WAITOK | M_CANFAIL | M_ZERO); 2843 if (sc->sc_ccbs == NULL) { 2844 printf("%s: unable to allocate ccbs\n", DEVNAME(sc)); 2845 return (1); 2846 } 2847 2848 sc->sc_requests = qle_dmamem_alloc(sc, sc->sc_maxcmds * 2849 QLE_QUEUE_ENTRY_SIZE); 2850 if (sc->sc_requests == NULL) { 2851 printf("%s: unable to allocate ccb dmamem\n", DEVNAME(sc)); 2852 goto free_ccbs; 2853 } 2854 sc->sc_responses = qle_dmamem_alloc(sc, sc->sc_maxcmds * 2855 QLE_QUEUE_ENTRY_SIZE); 2856 if (sc->sc_responses == NULL) { 2857 printf("%s: unable to allocate rcb dmamem\n", DEVNAME(sc)); 2858 goto free_req; 2859 } 2860 sc->sc_pri_requests = qle_dmamem_alloc(sc, 8 * QLE_QUEUE_ENTRY_SIZE); 2861 if (sc->sc_pri_requests == NULL) { 2862 printf("%s: unable to allocate pri ccb dmamem\n", DEVNAME(sc)); 2863 goto free_pri; 2864 } 2865 sc->sc_segments = qle_dmamem_alloc(sc, sc->sc_maxcmds * QLE_MAX_SEGS * 2866 sizeof(struct qle_iocb_seg)); 2867 if (sc->sc_segments == NULL) { 2868 printf("%s: unable to allocate iocb segments\n", DEVNAME(sc)); 2869 goto free_res; 2870 } 2871 2872 sc->sc_fcp_cmnds = qle_dmamem_alloc(sc, sc->sc_maxcmds * 2873 sizeof(struct qle_fcp_cmnd)); 2874 if (sc->sc_fcp_cmnds == NULL) { 2875 printf("%s: unable to allocate FCP_CMNDs\n", DEVNAME(sc)); 2876 goto free_seg; 2877 } 2878 2879 cmd = QLE_DMA_KVA(sc->sc_requests); 2880 memset(cmd, 0, QLE_QUEUE_ENTRY_SIZE * sc->sc_maxcmds); 2881 for (i = 0; i < sc->sc_maxcmds; i++) { 2882 ccb = &sc->sc_ccbs[i]; 2883 2884 if (bus_dmamap_create(sc->sc_dmat, MAXPHYS, 2885 QLE_MAX_SEGS-1, MAXPHYS, 0, 2886 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2887 &ccb->ccb_dmamap) != 0) { 2888 printf("%s: unable to create dma map\n", DEVNAME(sc)); 2889 goto free_maps; 2890 } 2891 2892 ccb->ccb_sc = sc; 2893 ccb->ccb_id = i; 2894 2895 ccb->ccb_seg_offset = i * QLE_MAX_SEGS * 2896 sizeof(struct qle_iocb_seg); 2897 ccb->ccb_segs = QLE_DMA_KVA(sc->sc_segments) + 2898 ccb->ccb_seg_offset; 2899 2900 qle_put_ccb(sc, ccb); 2901 } 2902 2903 scsi_iopool_init(&sc->sc_iopool, sc, qle_get_ccb, qle_put_ccb); 2904 return (0); 2905 2906 free_maps: 2907 while ((ccb = qle_get_ccb(sc)) != NULL) 2908 bus_dmamap_destroy(sc->sc_dmat, ccb->ccb_dmamap); 2909 2910 qle_dmamem_free(sc, sc->sc_fcp_cmnds); 2911 free_seg: 2912 qle_dmamem_free(sc, sc->sc_segments); 2913 free_pri: 2914 qle_dmamem_free(sc, sc->sc_pri_requests); 2915 free_res: 2916 qle_dmamem_free(sc, sc->sc_responses); 2917 free_req: 2918 qle_dmamem_free(sc, sc->sc_requests); 2919 free_ccbs: 2920 free(sc->sc_ccbs, M_DEVBUF, 0); 2921 2922 return (1); 2923 } 2924 2925 void 2926 qle_free_ccbs(struct qle_softc *sc) 2927 { 2928 struct qle_ccb *ccb; 2929 2930 scsi_iopool_destroy(&sc->sc_iopool); 2931 while ((ccb = qle_get_ccb(sc)) != NULL) 2932 bus_dmamap_destroy(sc->sc_dmat, ccb->ccb_dmamap); 2933 qle_dmamem_free(sc, sc->sc_segments); 2934 qle_dmamem_free(sc, sc->sc_responses); 2935 qle_dmamem_free(sc, sc->sc_requests); 2936 free(sc->sc_ccbs, M_DEVBUF, 0); 2937 } 2938 2939 void * 2940 qle_get_ccb(void *xsc) 2941 { 2942 struct qle_softc *sc = xsc; 2943 struct qle_ccb *ccb; 2944 2945 mtx_enter(&sc->sc_ccb_mtx); 2946 ccb = SIMPLEQ_FIRST(&sc->sc_ccb_free); 2947 if (ccb != NULL) { 2948 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_free, ccb_link); 2949 } 2950 mtx_leave(&sc->sc_ccb_mtx); 2951 return (ccb); 2952 } 2953 2954 void 2955 qle_put_ccb(void *xsc, void *io) 2956 { 2957 struct qle_softc *sc = xsc; 2958 struct qle_ccb *ccb = io; 2959 2960 ccb->ccb_xs = NULL; 2961 mtx_enter(&sc->sc_ccb_mtx); 2962 SIMPLEQ_INSERT_HEAD(&sc->sc_ccb_free, ccb, ccb_link); 2963 mtx_leave(&sc->sc_ccb_mtx); 2964 } 2965