1 /* $OpenBSD: tgavar.h,v 1.4 2001/03/18 04:37:21 nate Exp $ */ 2 /* $NetBSD: tgavar.h,v 1.8 2000/04/02 19:01:11 nathanw Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #include <dev/ic/ramdac.h> 32 #include <dev/pci/tgareg.h> 33 #include <dev/wscons/wsconsio.h> 34 #include <dev/wscons/wscons_raster.h> 35 #include <dev/wscons/wsdisplayvar.h> 36 #include <dev/rasops/rasops.h> 37 38 struct tga_devconfig; 39 struct fbcmap; 40 struct fbcursor; 41 struct fbcurpos; 42 43 struct tga_conf { 44 char *tgac_name; /* name for this board type */ 45 46 struct ramdac_funcs *(*ramdac_funcs) __P((void)); 47 48 int tgac_phys_depth; /* physical frame buffer depth */ 49 vsize_t tgac_cspace_size; /* core space size */ 50 vsize_t tgac_vvbr_units; /* what '1' in the VVBR means */ 51 52 int tgac_ndbuf; /* number of display buffers */ 53 vaddr_t tgac_dbuf[2]; /* display buffer offsets/addresses */ 54 vsize_t tgac_dbufsz[2]; /* display buffer sizes */ 55 56 int tgac_nbbuf; /* number of display buffers */ 57 vaddr_t tgac_bbuf[2]; /* back buffer offsets/addresses */ 58 vsize_t tgac_bbufsz[2]; /* back buffer sizes */ 59 }; 60 61 struct tga_devconfig { 62 bus_space_tag_t dc_memt; 63 bus_space_handle_t dc_memh; 64 65 pcitag_t dc_pcitag; /* PCI tag */ 66 bus_addr_t dc_pcipaddr; /* PCI phys addr. */ 67 68 bus_space_handle_t dc_regs; /* registers; XXX: need aliases */ 69 70 int dc_tga_type; /* the device type; see below */ 71 int dc_tga2; /* True if it is a TGA2 */ 72 const struct tga_conf *dc_tgaconf; /* device buffer configuration */ 73 74 struct ramdac_funcs 75 *dc_ramdac_funcs; /* The RAMDAC functions */ 76 struct ramdac_cookie 77 *dc_ramdac_cookie; /* the RAMDAC type; see above */ 78 79 vaddr_t dc_vaddr; /* memory space virtual base address */ 80 paddr_t dc_paddr; /* memory space physical base address */ 81 82 int dc_wid; /* width of frame buffer */ 83 int dc_ht; /* height of frame buffer */ 84 int dc_rowbytes; /* bytes in a FB scan line */ 85 86 vaddr_t dc_videobase; /* base of flat frame buffer */ 87 88 struct rasops_info dc_rinfo; /* raster display data */ 89 90 int dc_blanked; /* currently had video disabled */ 91 void *dc_ramdac_private; /* RAMDAC private storage */ 92 93 void (*dc_ramdac_intr) __P((void *)); 94 int dc_intrenabled; /* can we depend on interrupts yet? */ 95 }; 96 97 struct tga_softc { 98 struct device sc_dev; 99 100 struct tga_devconfig *sc_dc; /* device configuration */ 101 void *sc_intr; /* interrupt handler info */ 102 /* XXX should record intr fns/arg */ 103 104 int nscreens; 105 }; 106 107 #define TGA_TYPE_T8_01 0 /* 8bpp, 1MB */ 108 #define TGA_TYPE_T8_02 1 /* 8bpp, 2MB */ 109 #define TGA_TYPE_T8_22 2 /* 8bpp, 4MB */ 110 #define TGA_TYPE_T8_44 3 /* 8bpp, 8MB */ 111 #define TGA_TYPE_T32_04 4 /* 32bpp, 4MB */ 112 #define TGA_TYPE_T32_08 5 /* 32bpp, 8MB */ 113 #define TGA_TYPE_T32_88 6 /* 32bpp, 16MB */ 114 #define TGA_TYPE_UNKNOWN 7 /* unknown */ 115 116 #define DEVICE_IS_TGA(class, id) \ 117 (((PCI_VENDOR(id) == PCI_VENDOR_DEC && \ 118 PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21030) || \ 119 PCI_PRODUCT(id) == PCI_PRODUCT_DEC_PBXGB) ? 10 : 0) 120 121 int tga_cnattach __P((bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t, 122 int, int, int)); 123 124 int tga_identify __P((struct tga_devconfig *)); 125 const struct tga_conf *tga_getconf __P((int)); 126 127 int tga_builtin_set_cursor __P((struct tga_devconfig *, 128 struct wsdisplay_cursor *)); 129 int tga_builtin_get_cursor __P((struct tga_devconfig *, 130 struct wsdisplay_cursor *)); 131 int tga_builtin_set_curpos __P((struct tga_devconfig *, 132 struct wsdisplay_curpos *)); 133 int tga_builtin_get_curpos __P((struct tga_devconfig *, 134 struct wsdisplay_curpos *)); 135 int tga_builtin_get_curmax __P((struct tga_devconfig *, 136 struct wsdisplay_curpos *)); 137 138 /* Read a TGA register */ 139 #define TGARREG(dc,reg) (bus_space_read_4((dc)->dc_memt, (dc)->dc_regs, \ 140 (reg) << 2)) 141 142 /* Write a TGA register */ 143 #define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \ 144 (reg) << 2, (val)) 145 146 /* Write a TGA register at an alternate aliased location */ 147 #define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \ 148 (dc)->dc_memt, (dc)->dc_regs, \ 149 ((alias) * TGA_CREGS_ALIAS) + ((reg) << 2), \ 150 (val)) 151 152 /* Insert a write barrier */ 153 #define TGAREGWB(dc,reg, nregs) bus_space_barrier( \ 154 (dc)->dc_memt, (dc)->dc_regs, \ 155 ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_WRITE) 156 157 /* Insert a read barrier */ 158 #define TGAREGRB(dc,reg, nregs) bus_space_barrier( \ 159 (dc)->dc_memt, (dc)->dc_regs, \ 160 ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_READ) 161 162 /* Insert a read/write barrier */ 163 #define TGAREGRWB(dc,reg, nregs) bus_space_barrier( \ 164 (dc)->dc_memt, (dc)->dc_regs, \ 165 ((reg) << 2), 4 * (nregs), \ 166 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 167