1 /* $OpenBSD: be.c,v 1.20 2008/06/26 05:42:18 ray Exp $ */ 2 /* $NetBSD: be.c,v 1.26 2001/03/20 15:39:20 pk Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58 #include "bpfilter.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/timeout.h> 63 #include <sys/kernel.h> 64 #include <sys/errno.h> 65 #include <sys/ioctl.h> 66 #include <sys/mbuf.h> 67 #include <sys/socket.h> 68 #include <sys/syslog.h> 69 #include <sys/device.h> 70 #include <sys/malloc.h> 71 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_types.h> 75 #include <net/netisr.h> 76 #include <net/if_media.h> 77 78 #ifdef INET 79 #include <netinet/in.h> 80 #include <netinet/in_systm.h> 81 #include <netinet/in_var.h> 82 #include <netinet/ip.h> 83 #include <netinet/if_ether.h> 84 #endif 85 86 #if NBPFILTER > 0 87 #include <net/bpf.h> 88 #endif 89 90 #include <machine/bus.h> 91 #include <machine/intr.h> 92 #include <machine/autoconf.h> 93 94 #include <dev/sbus/sbusvar.h> 95 96 #include <dev/mii/mii.h> 97 #include <dev/mii/miivar.h> 98 99 #include <dev/sbus/qecreg.h> 100 #include <dev/sbus/qecvar.h> 101 #include <dev/sbus/bereg.h> 102 103 struct be_softc { 104 struct device sc_dev; 105 bus_space_tag_t sc_bustag; /* bus & dma tags */ 106 bus_dma_tag_t sc_dmatag; 107 bus_dmamap_t sc_dmamap; 108 struct arpcom sc_arpcom; 109 /*struct ifmedia sc_ifmedia; -* interface media */ 110 struct mii_data sc_mii; /* MII media control */ 111 #define sc_media sc_mii.mii_media/* shorthand */ 112 int sc_phys[2]; /* MII instance -> phy */ 113 114 struct timeout sc_tick_ch; 115 116 /* 117 * Some `mii_softc' items we need to emulate MII operation 118 * for our internal transceiver. 119 */ 120 int sc_mii_inst; /* instance of internal phy */ 121 int sc_mii_active; /* currently active medium */ 122 int sc_mii_ticks; /* tick counter */ 123 int sc_mii_flags; /* phy status flags */ 124 #define MIIF_HAVELINK 0x04000000 125 int sc_intphy_curspeed; /* Established link speed */ 126 127 struct qec_softc *sc_qec; /* QEC parent */ 128 129 bus_space_handle_t sc_qr; /* QEC registers */ 130 bus_space_handle_t sc_br; /* BE registers */ 131 bus_space_handle_t sc_cr; /* channel registers */ 132 bus_space_handle_t sc_tr; /* transceiver registers */ 133 134 u_int sc_rev; 135 136 int sc_channel; /* channel number */ 137 int sc_burst; 138 139 struct qec_ring sc_rb; /* Packet Ring Buffer */ 140 }; 141 142 int bematch(struct device *, void *, void *); 143 void beattach(struct device *, struct device *, void *); 144 145 void beinit(struct be_softc *); 146 void bestart(struct ifnet *); 147 void bestop(struct be_softc *); 148 void bewatchdog(struct ifnet *); 149 int beioctl(struct ifnet *, u_long, caddr_t); 150 void bereset(struct be_softc *); 151 152 int beintr(void *); 153 int berint(struct be_softc *); 154 int betint(struct be_softc *); 155 int beqint(struct be_softc *, u_int32_t); 156 int beeint(struct be_softc *, u_int32_t); 157 158 static void be_read(struct be_softc *, int, int); 159 static int be_put(struct be_softc *, int, struct mbuf *); 160 static struct mbuf *be_get(struct be_softc *, int, int); 161 162 void be_pal_gate(struct be_softc *, int); 163 164 /* ifmedia callbacks */ 165 void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 166 int be_ifmedia_upd(struct ifnet *); 167 168 void be_mcreset(struct be_softc *); 169 170 /* MII methods & callbacks */ 171 static int be_mii_readreg(struct device *, int, int); 172 static void be_mii_writereg(struct device *, int, int, int); 173 static void be_mii_statchg(struct device *); 174 175 /* MII helpers */ 176 static void be_mii_sync(struct be_softc *); 177 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int); 178 static int be_mii_reset(struct be_softc *, int); 179 static int be_tcvr_read_bit(struct be_softc *, int); 180 static void be_tcvr_write_bit(struct be_softc *, int, int); 181 182 void be_tick(void *); 183 void be_intphy_auto(struct be_softc *); 184 void be_intphy_status(struct be_softc *); 185 int be_intphy_service(struct be_softc *, struct mii_data *, int); 186 187 188 struct cfattach be_ca = { 189 sizeof(struct be_softc), bematch, beattach 190 }; 191 192 struct cfdriver be_cd = { 193 NULL, "be", DV_IFNET 194 }; 195 196 int 197 bematch(struct device *parent, void *vcf, void *aux) 198 { 199 struct cfdata *cf = vcf; 200 struct sbus_attach_args *sa = aux; 201 202 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 203 } 204 205 void 206 beattach(struct device *parent, struct device *self, void *aux) 207 { 208 struct sbus_attach_args *sa = aux; 209 struct qec_softc *qec = (struct qec_softc *)parent; 210 struct be_softc *sc = (struct be_softc *)self; 211 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 212 struct mii_data *mii = &sc->sc_mii; 213 struct mii_softc *child; 214 int node = sa->sa_node; 215 bus_dma_tag_t dmatag = sa->sa_dmatag; 216 bus_dma_segment_t seg; 217 bus_size_t size; 218 int instance; 219 int rseg, error; 220 u_int32_t v; 221 extern void myetheraddr(u_char *); 222 223 /* Pass on the bus tags */ 224 sc->sc_bustag = sa->sa_bustag; 225 sc->sc_dmatag = sa->sa_dmatag; 226 227 if (sa->sa_nreg < 3) { 228 printf("%s: only %d register sets\n", 229 self->dv_xname, sa->sa_nreg); 230 return; 231 } 232 233 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 234 (bus_addr_t)sa->sa_reg[0].sbr_offset, 235 (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) { 236 printf("beattach: cannot map registers\n"); 237 return; 238 } 239 240 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot, 241 (bus_addr_t)sa->sa_reg[1].sbr_offset, 242 (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_br) != 0) { 243 printf("beattach: cannot map registers\n"); 244 return; 245 } 246 247 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[2].sbr_slot, 248 (bus_addr_t)sa->sa_reg[2].sbr_offset, 249 (bus_size_t)sa->sa_reg[2].sbr_size, 0, 0, &sc->sc_tr) != 0) { 250 printf("beattach: cannot map registers\n"); 251 return; 252 } 253 254 sc->sc_qec = qec; 255 sc->sc_qr = qec->sc_regs; 256 257 sc->sc_rev = getpropint(node, "board-version", -1); 258 printf(" rev %x", sc->sc_rev); 259 260 bestop(sc); 261 262 sc->sc_channel = getpropint(node, "channel#", -1); 263 if (sc->sc_channel == -1) 264 sc->sc_channel = 0; 265 266 sc->sc_burst = getpropint(node, "burst-sizes", -1); 267 if (sc->sc_burst == -1) 268 sc->sc_burst = qec->sc_burst; 269 270 /* Clamp at parent's burst sizes */ 271 sc->sc_burst &= qec->sc_burst; 272 273 /* Establish interrupt handler */ 274 if (sa->sa_nintr == 0 || bus_intr_establish(sa->sa_bustag, sa->sa_pri, 275 IPL_NET, 0, beintr, sc, self->dv_xname) == NULL) { 276 printf(": no interrupt established\n"); 277 return; 278 } 279 280 myetheraddr(sc->sc_arpcom.ac_enaddr); 281 printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 282 283 /* 284 * Allocate descriptor ring and buffers. 285 */ 286 287 /* for now, allocate as many bufs as there are ring descriptors */ 288 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 289 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 290 291 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 292 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 293 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 294 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 295 296 /* Get a DMA handle */ 297 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 298 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 299 printf("%s: DMA map create error %d\n", self->dv_xname, error); 300 return; 301 } 302 303 /* Allocate DMA buffer */ 304 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 305 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 306 printf("%s: DMA buffer alloc error %d\n", 307 self->dv_xname, error); 308 return; 309 } 310 311 /* Map DMA memory in CPU addressable space */ 312 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 313 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 314 printf("%s: DMA buffer map error %d\n", 315 self->dv_xname, error); 316 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 317 return; 318 } 319 320 /* Load the buffer */ 321 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 322 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 323 printf("%s: DMA buffer map load error %d\n", 324 self->dv_xname, error); 325 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 326 bus_dmamem_free(dmatag, &seg, rseg); 327 return; 328 } 329 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 330 331 /* 332 * Initialize our media structures and MII info. 333 */ 334 mii->mii_ifp = ifp; 335 mii->mii_readreg = be_mii_readreg; 336 mii->mii_writereg = be_mii_writereg; 337 mii->mii_statchg = be_mii_statchg; 338 339 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 340 341 timeout_set(&sc->sc_tick_ch, be_tick, sc); 342 343 /* 344 * Initialize transceiver and determine which PHY connection to use. 345 */ 346 be_mii_sync(sc); 347 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 348 349 instance = 0; 350 351 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 352 353 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 354 MII_OFFSET_ANY, 0); 355 356 child = LIST_FIRST(&mii->mii_phys); 357 if (child == NULL) { 358 /* No PHY attached */ 359 ifmedia_add(&sc->sc_media, 360 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 361 0, NULL); 362 ifmedia_set(&sc->sc_media, 363 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 364 } else { 365 /* 366 * Note: we support just one PHY on the external 367 * MII connector. 368 */ 369 #ifdef DIAGNOSTIC 370 if (LIST_NEXT(child, mii_list) != NULL) { 371 printf("%s: spurious MII device %s attached\n", 372 sc->sc_dev.dv_xname, 373 child->mii_dev.dv_xname); 374 } 375 #endif 376 if (child->mii_phy != BE_PHY_EXTERNAL || 377 child->mii_inst > 0) { 378 printf("%s: cannot accommodate MII device %s" 379 " at phy %d, instance %d\n", 380 sc->sc_dev.dv_xname, 381 child->mii_dev.dv_xname, 382 child->mii_phy, child->mii_inst); 383 } else { 384 sc->sc_phys[instance] = child->mii_phy; 385 } 386 387 /* 388 * XXX - we can really do the following ONLY if the 389 * phy indeed has the auto negotiation capability!! 390 */ 391 ifmedia_set(&sc->sc_media, 392 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 393 394 /* Mark our current media setting */ 395 be_pal_gate(sc, BE_PHY_EXTERNAL); 396 instance++; 397 } 398 399 } 400 401 if ((v & MGMT_PAL_INT_MDIO) != 0) { 402 /* 403 * The be internal phy looks vaguely like MII hardware, 404 * but not enough to be able to use the MII device 405 * layer. Hence, we have to take care of media selection 406 * ourselves. 407 */ 408 409 sc->sc_mii_inst = instance; 410 sc->sc_phys[instance] = BE_PHY_INTERNAL; 411 412 /* Use `ifm_data' to store BMCR bits */ 413 ifmedia_add(&sc->sc_media, 414 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 0, NULL); 415 ifmedia_add(&sc->sc_media, 416 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 417 BMCR_S100, NULL); 418 ifmedia_add(&sc->sc_media, 419 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 0, NULL); 420 421 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 422 self->dv_xname); 423 424 be_mii_reset(sc, BE_PHY_INTERNAL); 425 /* Only set default medium here if there's no external PHY */ 426 if (instance == 0) { 427 be_pal_gate(sc, BE_PHY_INTERNAL); 428 ifmedia_set(&sc->sc_media, 429 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 430 } else 431 be_mii_writereg((void *)sc, 432 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 433 } 434 435 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 436 ifp->if_softc = sc; 437 ifp->if_start = bestart; 438 ifp->if_ioctl = beioctl; 439 ifp->if_watchdog = bewatchdog; 440 ifp->if_flags = 441 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 442 IFQ_SET_READY(&ifp->if_snd); 443 444 /* Attach the interface. */ 445 if_attach(ifp); 446 ether_ifattach(ifp); 447 } 448 449 450 /* 451 * Routine to copy from mbuf chain to transmit buffer in 452 * network buffer memory. 453 */ 454 static __inline__ int 455 be_put(struct be_softc *sc, int idx, struct mbuf *m) 456 { 457 struct mbuf *n; 458 int len, tlen = 0, boff = 0; 459 caddr_t bp; 460 461 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 462 463 for (; m; m = n) { 464 len = m->m_len; 465 if (len == 0) { 466 MFREE(m, n); 467 continue; 468 } 469 bcopy(mtod(m, caddr_t), bp+boff, len); 470 boff += len; 471 tlen += len; 472 MFREE(m, n); 473 } 474 return (tlen); 475 } 476 477 /* 478 * Pull data off an interface. 479 * Len is the length of data, with local net header stripped. 480 * We copy the data into mbufs. When full cluster sized units are present, 481 * we copy into clusters. 482 */ 483 static __inline__ struct mbuf * 484 be_get(struct be_softc *sc, int idx, int totlen) 485 { 486 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 487 struct mbuf *m; 488 struct mbuf *top, **mp; 489 int len, pad, boff = 0; 490 caddr_t bp; 491 492 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 493 494 MGETHDR(m, M_DONTWAIT, MT_DATA); 495 if (m == NULL) 496 return (NULL); 497 m->m_pkthdr.rcvif = ifp; 498 m->m_pkthdr.len = totlen; 499 500 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 501 m->m_data += pad; 502 len = MHLEN - pad; 503 top = NULL; 504 mp = ⊤ 505 506 while (totlen > 0) { 507 if (top) { 508 MGET(m, M_DONTWAIT, MT_DATA); 509 if (m == NULL) { 510 m_freem(top); 511 return (NULL); 512 } 513 len = MLEN; 514 } 515 if (top && totlen >= MINCLSIZE) { 516 MCLGET(m, M_DONTWAIT); 517 if (m->m_flags & M_EXT) 518 len = MCLBYTES; 519 } 520 m->m_len = len = min(totlen, len); 521 bcopy(bp + boff, mtod(m, caddr_t), len); 522 boff += len; 523 totlen -= len; 524 *mp = m; 525 mp = &m->m_next; 526 } 527 528 return (top); 529 } 530 531 /* 532 * Pass a packet to the higher levels. 533 */ 534 static __inline__ void 535 be_read(struct be_softc *sc, int idx, int len) 536 { 537 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 538 struct mbuf *m; 539 540 if (len <= sizeof(struct ether_header) || 541 len > ETHERMTU + sizeof(struct ether_header)) { 542 543 printf("%s: invalid packet size %d; dropping\n", 544 ifp->if_xname, len); 545 546 ifp->if_ierrors++; 547 return; 548 } 549 550 /* 551 * Pull packet off interface. 552 */ 553 m = be_get(sc, idx, len); 554 if (m == NULL) { 555 ifp->if_ierrors++; 556 return; 557 } 558 ifp->if_ipackets++; 559 560 #if NBPFILTER > 0 561 /* 562 * Check if there's a BPF listener on this interface. 563 * If so, hand off the raw packet to BPF. 564 */ 565 if (ifp->if_bpf) 566 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 567 #endif 568 /* Pass the packet up. */ 569 ether_input_mbuf(ifp, m); 570 } 571 572 /* 573 * Start output on interface. 574 * We make two assumptions here: 575 * 1) that the current priority is set to splnet _before_ this code 576 * is called *and* is returned to the appropriate priority after 577 * return 578 * 2) that the IFF_OACTIVE flag is checked before this code is called 579 * (i.e. that the output part of the interface is idle) 580 */ 581 void 582 bestart(struct ifnet *ifp) 583 { 584 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 585 struct qec_xd *txd = sc->sc_rb.rb_txd; 586 struct mbuf *m; 587 unsigned int bix, len; 588 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 589 590 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 591 return; 592 593 bix = sc->sc_rb.rb_tdhead; 594 595 for (;;) { 596 IFQ_DEQUEUE(&ifp->if_snd, m); 597 if (m == 0) 598 break; 599 600 #if NBPFILTER > 0 601 /* 602 * If BPF is listening on this interface, let it see the 603 * packet before we commit it to the wire. 604 */ 605 if (ifp->if_bpf) 606 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 607 #endif 608 609 /* 610 * Copy the mbuf chain into the transmit buffer. 611 */ 612 len = be_put(sc, bix, m); 613 614 /* 615 * Initialize transmit registers and start transmission 616 */ 617 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 618 (len & QEC_XD_LENGTH); 619 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 620 BE_CR_CTRL_TWAKEUP); 621 622 if (++bix == QEC_XD_RING_MAXSIZE) 623 bix = 0; 624 625 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 626 ifp->if_flags |= IFF_OACTIVE; 627 break; 628 } 629 } 630 631 sc->sc_rb.rb_tdhead = bix; 632 } 633 634 void 635 bestop(struct be_softc *sc) 636 { 637 int n; 638 bus_space_tag_t t = sc->sc_bustag; 639 bus_space_handle_t br = sc->sc_br; 640 641 timeout_del(&sc->sc_tick_ch); 642 643 /* Down the MII. */ 644 mii_down(&sc->sc_mii); 645 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 646 647 /* Stop the transmitter */ 648 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 649 for (n = 32; n > 0; n--) { 650 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 651 break; 652 DELAY(20); 653 } 654 655 /* Stop the receiver */ 656 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 657 for (n = 32; n > 0; n--) { 658 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 659 break; 660 DELAY(20); 661 } 662 } 663 664 /* 665 * Reset interface. 666 */ 667 void 668 bereset(struct be_softc *sc) 669 { 670 int s; 671 672 s = splnet(); 673 bestop(sc); 674 if ((sc->sc_arpcom.ac_if.if_flags & IFF_UP) != 0) 675 beinit(sc); 676 splx(s); 677 } 678 679 void 680 bewatchdog(struct ifnet *ifp) 681 { 682 struct be_softc *sc = ifp->if_softc; 683 684 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 685 ++sc->sc_arpcom.ac_if.if_oerrors; 686 bereset(sc); 687 } 688 689 int 690 beintr(void *v) 691 { 692 struct be_softc *sc = (struct be_softc *)v; 693 bus_space_tag_t t = sc->sc_bustag; 694 u_int32_t whyq, whyb, whyc; 695 int r = 0; 696 697 /* Read QEC status, channel status and BE status */ 698 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 699 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 700 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 701 702 if (whyq & QEC_STAT_BM) 703 r |= beeint(sc, whyb); 704 705 if (whyq & QEC_STAT_ER) 706 r |= beqint(sc, whyc); 707 708 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 709 r |= betint(sc); 710 711 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 712 r |= berint(sc); 713 714 return (r); 715 } 716 717 /* 718 * QEC Interrupt. 719 */ 720 int 721 beqint(struct be_softc *sc, u_int32_t why) 722 { 723 int r = 0, rst = 0; 724 725 if (why & BE_CR_STAT_TXIRQ) 726 r |= 1; 727 if (why & BE_CR_STAT_RXIRQ) 728 r |= 1; 729 730 if (why & BE_CR_STAT_BERROR) { 731 r |= 1; 732 rst = 1; 733 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 734 } 735 736 if (why & BE_CR_STAT_TXDERR) { 737 r |= 1; 738 rst = 1; 739 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 740 } 741 742 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 743 r |= 1; 744 rst = 1; 745 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 746 if (why & BE_CR_STAT_TXLERR) 747 printf("Late "); 748 if (why & BE_CR_STAT_TXPERR) 749 printf("Parity "); 750 if (why & BE_CR_STAT_TXSERR) 751 printf("Generic "); 752 printf(")\n"); 753 } 754 755 if (why & BE_CR_STAT_RXDROP) { 756 r |= 1; 757 rst = 1; 758 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 759 } 760 761 if (why & BE_CR_STAT_RXSMALL) { 762 r |= 1; 763 rst = 1; 764 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 765 } 766 767 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 768 r |= 1; 769 rst = 1; 770 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 771 if (why & BE_CR_STAT_RXLERR) 772 printf("Late "); 773 if (why & BE_CR_STAT_RXPERR) 774 printf("Parity "); 775 if (why & BE_CR_STAT_RXSERR) 776 printf("Generic "); 777 printf(")\n"); 778 } 779 780 if (!r) { 781 rst = 1; 782 printf("%s: unexpected error interrupt %08x\n", 783 sc->sc_dev.dv_xname, why); 784 } 785 786 if (rst) { 787 printf("%s: resetting\n", sc->sc_dev.dv_xname); 788 bereset(sc); 789 } 790 791 return (r); 792 } 793 794 /* 795 * Error interrupt. 796 */ 797 int 798 beeint(struct be_softc *sc, u_int32_t why) 799 { 800 int r = 0, rst = 0; 801 802 if (why & BE_BR_STAT_RFIFOVF) { 803 r |= 1; 804 rst = 1; 805 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 806 } 807 if (why & BE_BR_STAT_TFIFO_UND) { 808 r |= 1; 809 rst = 1; 810 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 811 } 812 if (why & BE_BR_STAT_MAXPKTERR) { 813 r |= 1; 814 rst = 1; 815 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 816 } 817 818 if (!r) { 819 rst = 1; 820 printf("%s: unexpected error interrupt %08x\n", 821 sc->sc_dev.dv_xname, why); 822 } 823 824 if (rst) { 825 printf("%s: resetting\n", sc->sc_dev.dv_xname); 826 bereset(sc); 827 } 828 829 return (r); 830 } 831 832 /* 833 * Transmit interrupt. 834 */ 835 int 836 betint(struct be_softc *sc) 837 { 838 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 839 bus_space_tag_t t = sc->sc_bustag; 840 bus_space_handle_t br = sc->sc_br; 841 unsigned int bix, txflags; 842 843 /* 844 * Unload collision counters 845 */ 846 ifp->if_collisions += 847 bus_space_read_4(t, br, BE_BRI_NCCNT) + 848 bus_space_read_4(t, br, BE_BRI_FCCNT) + 849 bus_space_read_4(t, br, BE_BRI_EXCNT) + 850 bus_space_read_4(t, br, BE_BRI_LTCNT); 851 852 /* 853 * the clear the hardware counters 854 */ 855 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 856 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 857 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 858 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 859 860 bix = sc->sc_rb.rb_tdtail; 861 862 for (;;) { 863 if (sc->sc_rb.rb_td_nbusy <= 0) 864 break; 865 866 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 867 868 if (txflags & QEC_XD_OWN) 869 break; 870 871 ifp->if_flags &= ~IFF_OACTIVE; 872 ifp->if_opackets++; 873 874 if (++bix == QEC_XD_RING_MAXSIZE) 875 bix = 0; 876 877 --sc->sc_rb.rb_td_nbusy; 878 } 879 880 sc->sc_rb.rb_tdtail = bix; 881 882 bestart(ifp); 883 884 if (sc->sc_rb.rb_td_nbusy == 0) 885 ifp->if_timer = 0; 886 887 return (1); 888 } 889 890 /* 891 * Receive interrupt. 892 */ 893 int 894 berint(struct be_softc *sc) 895 { 896 struct qec_xd *xd = sc->sc_rb.rb_rxd; 897 unsigned int bix, len; 898 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 899 900 bix = sc->sc_rb.rb_rdtail; 901 902 /* 903 * Process all buffers with valid data. 904 */ 905 for (;;) { 906 len = xd[bix].xd_flags; 907 if (len & QEC_XD_OWN) 908 break; 909 910 len &= QEC_XD_LENGTH; 911 be_read(sc, bix, len); 912 913 /* ... */ 914 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 915 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 916 917 if (++bix == QEC_XD_RING_MAXSIZE) 918 bix = 0; 919 } 920 921 sc->sc_rb.rb_rdtail = bix; 922 923 return (1); 924 } 925 926 int 927 beioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 928 { 929 struct be_softc *sc = ifp->if_softc; 930 struct ifaddr *ifa = (struct ifaddr *)data; 931 struct ifreq *ifr = (struct ifreq *)data; 932 int s, error = 0; 933 934 s = splnet(); 935 936 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) { 937 splx(s); 938 return (error); 939 } 940 941 switch (cmd) { 942 case SIOCSIFADDR: 943 ifp->if_flags |= IFF_UP; 944 switch (ifa->ifa_addr->sa_family) { 945 #ifdef INET 946 case AF_INET: 947 beinit(sc); 948 arp_ifinit(&sc->sc_arpcom, ifa); 949 break; 950 #endif /* INET */ 951 default: 952 beinit(sc); 953 break; 954 } 955 break; 956 957 case SIOCSIFFLAGS: 958 if ((ifp->if_flags & IFF_UP) == 0 && 959 (ifp->if_flags & IFF_RUNNING) != 0) { 960 /* 961 * If interface is marked down and it is running, then 962 * stop it. 963 */ 964 bestop(sc); 965 ifp->if_flags &= ~IFF_RUNNING; 966 } else if ((ifp->if_flags & IFF_UP) != 0 && 967 (ifp->if_flags & IFF_RUNNING) == 0) { 968 /* 969 * If interface is marked up and it is stopped, then 970 * start it. 971 */ 972 beinit(sc); 973 } else { 974 /* 975 * Reset the interface to pick up changes in any other 976 * flags that affect hardware registers. 977 */ 978 bestop(sc); 979 beinit(sc); 980 } 981 #ifdef BEDEBUG 982 if (ifp->if_flags & IFF_DEBUG) 983 sc->sc_debug = 1; 984 else 985 sc->sc_debug = 0; 986 #endif 987 break; 988 989 case SIOCADDMULTI: 990 case SIOCDELMULTI: 991 error = (cmd == SIOCADDMULTI) ? 992 ether_addmulti(ifr, &sc->sc_arpcom): 993 ether_delmulti(ifr, &sc->sc_arpcom); 994 995 if (error == ENETRESET) { 996 /* 997 * Multicast list has changed; set the hardware filter 998 * accordingly. 999 */ 1000 if (ifp->if_flags & IFF_RUNNING) 1001 be_mcreset(sc); 1002 error = 0; 1003 } 1004 break; 1005 case SIOCGIFMEDIA: 1006 case SIOCSIFMEDIA: 1007 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1008 break; 1009 default: 1010 error = EINVAL; 1011 break; 1012 } 1013 splx(s); 1014 return (error); 1015 } 1016 1017 1018 void 1019 beinit(struct be_softc *sc) 1020 { 1021 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1022 bus_space_tag_t t = sc->sc_bustag; 1023 bus_space_handle_t br = sc->sc_br; 1024 bus_space_handle_t cr = sc->sc_cr; 1025 struct qec_softc *qec = sc->sc_qec; 1026 u_int32_t v; 1027 u_int32_t qecaddr; 1028 u_int8_t *ea; 1029 int s; 1030 1031 s = splnet(); 1032 1033 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1034 1035 bestop(sc); 1036 1037 ea = sc->sc_arpcom.ac_enaddr; 1038 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1039 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1040 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1041 1042 /* Clear hash table */ 1043 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1044 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1045 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1046 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1047 1048 /* Re-initialize RX configuration */ 1049 v = BE_BR_RXCFG_FIFO; 1050 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1051 1052 be_mcreset(sc); 1053 1054 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1055 1056 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1057 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1058 1059 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1060 1061 /* 1062 * Turn off counter expiration interrupts as well as 1063 * 'gotframe' and 'sentframe' 1064 */ 1065 bus_space_write_4(t, br, BE_BRI_IMASK, 1066 BE_BR_IMASK_GOTFRAME | 1067 BE_BR_IMASK_RCNTEXP | 1068 BE_BR_IMASK_ACNTEXP | 1069 BE_BR_IMASK_CCNTEXP | 1070 BE_BR_IMASK_LCNTEXP | 1071 BE_BR_IMASK_CVCNTEXP | 1072 BE_BR_IMASK_SENTFRAME | 1073 BE_BR_IMASK_NCNTEXP | 1074 BE_BR_IMASK_ECNTEXP | 1075 BE_BR_IMASK_LCCNTEXP | 1076 BE_BR_IMASK_FCNTEXP | 1077 BE_BR_IMASK_DTIMEXP); 1078 1079 /* Channel registers: */ 1080 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1081 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1082 1083 qecaddr = sc->sc_channel * qec->sc_msize; 1084 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1085 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1086 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1087 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1088 1089 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1090 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1091 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1092 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1093 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1094 1095 /* Enable transmitter */ 1096 bus_space_write_4(t, br, BE_BRI_TXCFG, 1097 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1098 1099 /* Enable receiver */ 1100 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1101 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1102 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1103 1104 ifp->if_flags |= IFF_RUNNING; 1105 ifp->if_flags &= ~IFF_OACTIVE; 1106 1107 be_ifmedia_upd(ifp); 1108 timeout_add(&sc->sc_tick_ch, hz); 1109 splx(s); 1110 } 1111 1112 void 1113 be_mcreset(struct be_softc *sc) 1114 { 1115 struct arpcom *ac = &sc->sc_arpcom; 1116 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1117 bus_space_tag_t t = sc->sc_bustag; 1118 bus_space_handle_t br = sc->sc_br; 1119 u_int32_t crc; 1120 u_int16_t hash[4]; 1121 u_int8_t octet; 1122 u_int32_t v; 1123 int i, j; 1124 struct ether_multi *enm; 1125 struct ether_multistep step; 1126 1127 if (ifp->if_flags & IFF_PROMISC) { 1128 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1129 v |= BE_BR_RXCFG_PMISC; 1130 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1131 return; 1132 } 1133 1134 if (ifp->if_flags & IFF_ALLMULTI) { 1135 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1136 goto chipit; 1137 } 1138 1139 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1140 1141 ETHER_FIRST_MULTI(step, ac, enm); 1142 while (enm != NULL) { 1143 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1144 /* 1145 * We must listen to a range of multicast 1146 * addresses. For now, just accept all 1147 * multicasts, rather than trying to set only 1148 * those filter bits needed to match the range. 1149 * (At this time, the only use of address 1150 * ranges is for IP multicast routing, for 1151 * which the range is big enough to require 1152 * all bits set.) 1153 */ 1154 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1155 ifp->if_flags |= IFF_ALLMULTI; 1156 goto chipit; 1157 } 1158 1159 crc = 0xffffffff; 1160 1161 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1162 octet = enm->enm_addrlo[i]; 1163 1164 for (j = 0; j < 8; j++) { 1165 if ((crc & 1) ^ (octet & 1)) { 1166 crc >>= 1; 1167 crc ^= MC_POLY_LE; 1168 } 1169 else 1170 crc >>= 1; 1171 octet >>= 1; 1172 } 1173 } 1174 1175 crc >>= 26; 1176 hash[crc >> 4] |= 1 << (crc & 0xf); 1177 ETHER_NEXT_MULTI(step, enm); 1178 } 1179 1180 ifp->if_flags &= ~IFF_ALLMULTI; 1181 1182 chipit: 1183 /* Enable the hash filter */ 1184 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1185 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1186 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1187 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1188 1189 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1190 v &= ~BE_BR_RXCFG_PMISC; 1191 v |= BE_BR_RXCFG_HENABLE; 1192 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1193 } 1194 1195 /* 1196 * Set the tcvr to an idle state 1197 */ 1198 void 1199 be_mii_sync(struct be_softc *sc) 1200 { 1201 bus_space_tag_t t = sc->sc_bustag; 1202 bus_space_handle_t tr = sc->sc_tr; 1203 int n = 32; 1204 1205 while (n--) { 1206 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1207 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1208 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1209 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1210 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1211 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1212 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1213 } 1214 } 1215 1216 void 1217 be_pal_gate(struct be_softc *sc, int phy) 1218 { 1219 bus_space_tag_t t = sc->sc_bustag; 1220 bus_space_handle_t tr = sc->sc_tr; 1221 u_int32_t v; 1222 1223 be_mii_sync(sc); 1224 1225 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1226 if (phy == BE_PHY_INTERNAL) 1227 v &= ~TCVR_PAL_SERIAL; 1228 1229 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1230 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1231 } 1232 1233 static int 1234 be_tcvr_read_bit(struct be_softc *sc, int phy) 1235 { 1236 bus_space_tag_t t = sc->sc_bustag; 1237 bus_space_handle_t tr = sc->sc_tr; 1238 int ret; 1239 1240 if (phy == BE_PHY_INTERNAL) { 1241 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1242 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1243 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1244 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1245 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1246 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1247 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1248 } else { 1249 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1250 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1251 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1252 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1253 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1254 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1255 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1256 } 1257 1258 return (ret); 1259 } 1260 1261 static void 1262 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1263 { 1264 bus_space_tag_t t = sc->sc_bustag; 1265 bus_space_handle_t tr = sc->sc_tr; 1266 u_int32_t v; 1267 1268 if (phy == BE_PHY_INTERNAL) { 1269 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1270 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1271 } else { 1272 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1273 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1274 } 1275 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1276 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1277 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1278 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1279 } 1280 1281 static void 1282 be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits) 1283 { 1284 int i; 1285 1286 for (i = 1 << (nbits - 1); i != 0; i >>= 1) 1287 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1288 } 1289 1290 static int 1291 be_mii_readreg(struct device *self, int phy, int reg) 1292 { 1293 struct be_softc *sc = (struct be_softc *)self; 1294 int val = 0, i; 1295 1296 /* 1297 * Read the PHY register by manually driving the MII control lines. 1298 */ 1299 be_mii_sync(sc); 1300 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1301 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1302 be_mii_sendbits(sc, phy, phy, 5); 1303 be_mii_sendbits(sc, phy, reg, 5); 1304 1305 (void) be_tcvr_read_bit(sc, phy); 1306 (void) be_tcvr_read_bit(sc, phy); 1307 1308 for (i = 15; i >= 0; i--) 1309 val |= (be_tcvr_read_bit(sc, phy) << i); 1310 1311 (void) be_tcvr_read_bit(sc, phy); 1312 (void) be_tcvr_read_bit(sc, phy); 1313 (void) be_tcvr_read_bit(sc, phy); 1314 1315 return (val); 1316 } 1317 1318 void 1319 be_mii_writereg(struct device *self, int phy, int reg, int val) 1320 { 1321 struct be_softc *sc = (struct be_softc *)self; 1322 int i; 1323 1324 /* 1325 * Write the PHY register by manually driving the MII control lines. 1326 */ 1327 be_mii_sync(sc); 1328 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1329 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1330 be_mii_sendbits(sc, phy, phy, 5); 1331 be_mii_sendbits(sc, phy, reg, 5); 1332 1333 be_tcvr_write_bit(sc, phy, 1); 1334 be_tcvr_write_bit(sc, phy, 0); 1335 1336 for (i = 15; i >= 0; i--) 1337 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1338 } 1339 1340 int 1341 be_mii_reset(struct be_softc *sc, int phy) 1342 { 1343 int n; 1344 1345 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1346 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1347 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1348 1349 for (n = 16; n >= 0; n--) { 1350 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1351 if ((bmcr & BMCR_RESET) == 0) 1352 break; 1353 DELAY(20); 1354 } 1355 if (n == 0) { 1356 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1357 return (EIO); 1358 } 1359 1360 return (0); 1361 } 1362 1363 void 1364 be_tick(void *arg) 1365 { 1366 struct be_softc *sc = arg; 1367 int s = splnet(); 1368 1369 mii_tick(&sc->sc_mii); 1370 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1371 1372 timeout_add(&sc->sc_tick_ch, hz); 1373 splx(s); 1374 } 1375 1376 void 1377 be_mii_statchg(struct device *self) 1378 { 1379 struct be_softc *sc = (struct be_softc *)self; 1380 bus_space_tag_t t = sc->sc_bustag; 1381 bus_space_handle_t br = sc->sc_br; 1382 u_int instance; 1383 u_int32_t v; 1384 1385 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1386 #ifdef DIAGNOSTIC 1387 if (instance > 1) 1388 panic("be_mii_statchg: instance %d out of range", instance); 1389 #endif 1390 1391 /* Update duplex mode in TX configuration */ 1392 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1393 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1394 v |= BE_BR_TXCFG_FULLDPLX; 1395 else 1396 v &= ~BE_BR_TXCFG_FULLDPLX; 1397 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1398 1399 /* Change to appropriate gate in transceiver PAL */ 1400 be_pal_gate(sc, sc->sc_phys[instance]); 1401 } 1402 1403 /* 1404 * Get current media settings. 1405 */ 1406 void 1407 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1408 { 1409 struct be_softc *sc = ifp->if_softc; 1410 1411 mii_pollstat(&sc->sc_mii); 1412 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1413 1414 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1415 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1416 return; 1417 } 1418 1419 /* 1420 * Set media options. 1421 */ 1422 int 1423 be_ifmedia_upd(struct ifnet *ifp) 1424 { 1425 struct be_softc *sc = ifp->if_softc; 1426 int error; 1427 1428 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1429 return (error); 1430 1431 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1432 } 1433 1434 /* 1435 * Service routine for our pseudo-MII internal transceiver. 1436 */ 1437 int 1438 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1439 { 1440 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1441 int bmcr, bmsr; 1442 int error; 1443 1444 switch (cmd) { 1445 case MII_POLLSTAT: 1446 /* 1447 * If we're not polling our PHY instance, just return. 1448 */ 1449 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1450 return (0); 1451 1452 break; 1453 1454 case MII_MEDIACHG: 1455 1456 /* 1457 * If the media indicates a different PHY instance, 1458 * isolate ourselves. 1459 */ 1460 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1461 bmcr = be_mii_readreg((void *)sc, 1462 BE_PHY_INTERNAL, MII_BMCR); 1463 be_mii_writereg((void *)sc, 1464 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1465 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1466 sc->sc_intphy_curspeed = 0; 1467 return (0); 1468 } 1469 1470 1471 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1472 return (error); 1473 1474 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1475 1476 /* 1477 * Select the new mode and take out of isolation 1478 */ 1479 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1480 bmcr |= BMCR_S100; 1481 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1482 bmcr &= ~BMCR_S100; 1483 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1484 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1485 bmcr &= ~BMCR_S100; 1486 bmcr |= sc->sc_intphy_curspeed; 1487 } else { 1488 /* Keep isolated until link is up */ 1489 bmcr |= BMCR_ISO; 1490 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1491 } 1492 } 1493 1494 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1495 bmcr |= BMCR_FDX; 1496 else 1497 bmcr &= ~BMCR_FDX; 1498 1499 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1500 break; 1501 1502 case MII_TICK: 1503 /* 1504 * If we're not currently selected, just return. 1505 */ 1506 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1507 return (0); 1508 1509 /* Only used for automatic media selection */ 1510 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1511 return (0); 1512 1513 /* Is the interface even up? */ 1514 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1515 return (0); 1516 1517 /* 1518 * Check link status; if we don't have a link, try another 1519 * speed. We can't detect duplex mode, so half-duplex is 1520 * what we have to settle for. 1521 */ 1522 1523 /* Read twice in case the register is latched */ 1524 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1525 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1526 1527 if ((bmsr & BMSR_LINK) != 0) { 1528 /* We have a carrier */ 1529 bmcr = be_mii_readreg((void *)sc, 1530 BE_PHY_INTERNAL, MII_BMCR); 1531 1532 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1533 bmcr = be_mii_readreg((void *)sc, 1534 BE_PHY_INTERNAL, MII_BMCR); 1535 1536 sc->sc_mii_flags |= MIIF_HAVELINK; 1537 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1538 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1539 1540 bmcr &= ~BMCR_ISO; 1541 be_mii_writereg((void *)sc, 1542 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1543 1544 printf("%s: link up at %s Mbps\n", 1545 sc->sc_dev.dv_xname, 1546 (bmcr & BMCR_S100) ? "100" : "10"); 1547 } 1548 return (0); 1549 } 1550 1551 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1552 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1553 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1554 sc->sc_intphy_curspeed = 0; 1555 printf("%s: link down\n", sc->sc_dev.dv_xname); 1556 } 1557 1558 /* Only retry autonegotiation every 5 seconds. */ 1559 if (++sc->sc_mii_ticks < 5) 1560 return(0); 1561 1562 sc->sc_mii_ticks = 0; 1563 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1564 /* Just flip the fast speed bit */ 1565 bmcr ^= BMCR_S100; 1566 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1567 1568 break; 1569 1570 case MII_DOWN: 1571 /* Isolate this phy */ 1572 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1573 be_mii_writereg((void *)sc, 1574 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1575 return (0); 1576 } 1577 1578 /* Update the media status. */ 1579 be_intphy_status(sc); 1580 1581 /* Callback if something changed. */ 1582 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1583 (*mii->mii_statchg)((struct device *)sc); 1584 sc->sc_mii_active = mii->mii_media_active; 1585 } 1586 return (0); 1587 } 1588 1589 /* 1590 * Determine status of internal transceiver 1591 */ 1592 void 1593 be_intphy_status(struct be_softc *sc) 1594 { 1595 struct mii_data *mii = &sc->sc_mii; 1596 int media_active, media_status; 1597 int bmcr, bmsr; 1598 1599 media_status = IFM_AVALID; 1600 media_active = 0; 1601 1602 /* 1603 * Internal transceiver; do the work here. 1604 */ 1605 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1606 1607 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1608 case (BMCR_S100 | BMCR_FDX): 1609 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1610 break; 1611 case BMCR_S100: 1612 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1613 break; 1614 case BMCR_FDX: 1615 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1616 break; 1617 case 0: 1618 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1619 break; 1620 } 1621 1622 /* Read twice in case the register is latched */ 1623 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1624 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1625 if (bmsr & BMSR_LINK) 1626 media_status |= IFM_ACTIVE; 1627 1628 mii->mii_media_status = media_status; 1629 mii->mii_media_active = media_active; 1630 } 1631