1 /* $OpenBSD: cgthree.c,v 1.45 2013/10/20 20:07:30 miod Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Jason L. Wright (jason@thought.net) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Effort sponsored in part by the Defense Advanced Research Projects 29 * Agency (DARPA) and Air Force Research Laboratory, Air Force 30 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 31 * 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/errno.h> 38 #include <sys/device.h> 39 #include <sys/ioctl.h> 40 #include <sys/malloc.h> 41 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 #include <machine/autoconf.h> 45 #include <machine/openfirm.h> 46 47 #include <dev/sbus/sbusvar.h> 48 #include <dev/wscons/wsconsio.h> 49 #include <dev/wscons/wsdisplayvar.h> 50 #include <dev/rasops/rasops.h> 51 #include <machine/fbvar.h> 52 53 #include <dev/ic/bt458reg.h> 54 55 #define CGTHREE_CTRL_OFFSET 0x400000 56 #define CGTHREE_CTRL_SIZE (sizeof(u_int32_t) * 8) 57 #define CGTHREE_VID_OFFSET 0x800000 58 #define CGTHREE_VID_SIZE (1024 * 1024) 59 60 union bt_cmap { 61 u_int8_t cm_map[256][3]; /* 256 r/b/g entries */ 62 u_int32_t cm_chip[256 * 3 / 4]; /* the way the chip is loaded */ 63 }; 64 65 #define BT_ADDR 0x00 /* map address register */ 66 #define BT_CMAP 0x04 /* colormap data register */ 67 #define BT_CTRL 0x08 /* control register */ 68 #define BT_OMAP 0x0c /* overlay (cursor) map register */ 69 #define CG3_FBC_CTRL 0x10 /* control */ 70 #define CG3_FBC_STAT 0x11 /* status */ 71 #define CG3_FBC_START 0x12 /* cursor start */ 72 #define CG3_FBC_END 0x13 /* cursor end */ 73 #define CG3_FBC_VCTRL 0x14 /* 12 bytes of timing goo */ 74 75 #define BT_WRITE(sc, reg, val) \ 76 bus_space_write_4((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val)) 77 #define BT_READ(sc, reg) \ 78 bus_space_read_4((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg)) 79 #define BT_BARRIER(sc,reg,flags) \ 80 bus_space_barrier((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), \ 81 sizeof(u_int32_t), (flags)) 82 83 #define BT_D4M3(x) ((((x) >> 2) << 1) + ((x) >> 2)) /* (x / 4) * 3 */ 84 #define BT_D4M4(x) ((x) & ~3) /* (x / 4) * 4 */ 85 86 #define FBC_CTRL_IENAB 0x80 /* interrupt enable */ 87 #define FBC_CTRL_VENAB 0x40 /* video enable */ 88 #define FBC_CTRL_TIME 0x20 /* timing enable */ 89 #define FBC_CTRL_CURS 0x10 /* cursor compare enable */ 90 #define FBC_CTRL_XTAL 0x0c /* xtal select (0,1,2,test): */ 91 #define FBC_CTRL_XTAL_0 0x00 /* 0 */ 92 #define FBC_CTRL_XTAL_1 0x04 /* 0 */ 93 #define FBC_CTRL_XTAL_2 0x08 /* 0 */ 94 #define FBC_CTRL_XTAL_TEST 0x0c /* 0 */ 95 #define FBC_CTRL_DIV 0x03 /* divisor (1,2,3,4): */ 96 #define FBC_CTRL_DIV_1 0x00 /* / 1 */ 97 #define FBC_CTRL_DIV_2 0x01 /* / 2 */ 98 #define FBC_CTRL_DIV_3 0x02 /* / 3 */ 99 #define FBC_CTRL_DIV_4 0x03 /* / 4 */ 100 101 #define FBC_STAT_INTR 0x80 /* interrupt pending */ 102 #define FBC_STAT_RES 0x70 /* monitor sense: */ 103 #define FBC_STAT_RES_1024 0x10 /* 1024x768 */ 104 #define FBC_STAT_RES_1280 0x40 /* 1280x1024 */ 105 #define FBC_STAT_RES_1152 0x30 /* 1152x900 */ 106 #define FBC_STAT_RES_1152A 0x40 /* 1152x900x76, A */ 107 #define FBC_STAT_RES_1600 0x50 /* 1600x1200 */ 108 #define FBC_STAT_RES_1152B 0x60 /* 1152x900x86, B */ 109 #define FBC_STAT_ID 0x0f /* id mask: */ 110 #define FBC_STAT_ID_COLOR 0x01 /* color */ 111 #define FBC_STAT_ID_MONO 0x02 /* monochrome */ 112 #define FBC_STAT_ID_MONOECL 0x03 /* monochrome, ecl */ 113 114 #define FBC_READ(sc, reg) \ 115 bus_space_read_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg)) 116 #define FBC_WRITE(sc, reg, val) \ 117 bus_space_write_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val)) 118 119 struct cgthree_softc { 120 struct sunfb sc_sunfb; 121 bus_space_tag_t sc_bustag; 122 bus_addr_t sc_paddr; 123 bus_space_handle_t sc_ctrl_regs; 124 bus_space_handle_t sc_vid_regs; 125 int sc_nscreens; 126 union bt_cmap sc_cmap; 127 u_int sc_mode; 128 }; 129 130 int cgthree_ioctl(void *, u_long, caddr_t, int, struct proc *); 131 paddr_t cgthree_mmap(void *, off_t, int); 132 int cgthree_is_console(int); 133 void cgthree_loadcmap(struct cgthree_softc *, u_int, u_int); 134 int cg3_bt_putcmap(union bt_cmap *, struct wsdisplay_cmap *); 135 int cg3_bt_getcmap(union bt_cmap *, struct wsdisplay_cmap *); 136 void cgthree_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); 137 void cgthree_burner(void *, u_int, u_int); 138 void cgthree_reset(struct cgthree_softc *); 139 140 struct wsdisplay_accessops cgthree_accessops = { 141 .ioctl = cgthree_ioctl, 142 .mmap = cgthree_mmap, 143 .burn_screen = cgthree_burner 144 }; 145 146 int cgthreematch(struct device *, void *, void *); 147 void cgthreeattach(struct device *, struct device *, void *); 148 149 struct cfattach cgthree_ca = { 150 sizeof (struct cgthree_softc), cgthreematch, cgthreeattach 151 }; 152 153 struct cfdriver cgthree_cd = { 154 NULL, "cgthree", DV_DULL 155 }; 156 157 #define CG3_TYPE_DEFAULT 0 158 #define CG3_TYPE_76HZ 1 159 #define CG3_TYPE_SMALL 2 160 161 struct cg3_videoctrl { 162 u_int8_t sense; 163 u_int8_t vctrl[12]; 164 u_int8_t ctrl; 165 } cg3_videoctrl[] = { 166 { /* cpd-1790 */ 167 FBC_STAT_RES_1152 | FBC_STAT_ID_COLOR, 168 { 0xbb, 0x2b, 0x04, 0x14, 0xae, 0x03, 169 0xa8, 0x24, 0x01, 0x05, 0xff, 0x01 }, 170 FBC_CTRL_XTAL_0 | FBC_CTRL_DIV_1 171 }, 172 { /* gdm-20e20 */ 173 FBC_STAT_RES_1152A | FBC_STAT_ID_COLOR, 174 { 0xb7, 0x27, 0x03, 0x0f, 0xae, 0x03, 175 0xae, 0x2a, 0x01, 0x09, 0xff, 0x01 }, 176 FBC_CTRL_XTAL_1 | FBC_CTRL_DIV_1 177 }, 178 { /* defaults, should be last */ 179 0xff, 180 { 0xbb, 0x2b, 0x03, 0x0b, 0xb3, 0x03, 181 0xaf, 0x2b, 0x02, 0x0a, 0xff, 0x01 }, 182 0, 183 }, 184 }; 185 186 int 187 cgthreematch(struct device *parent, void *vcf, void *aux) 188 { 189 struct cfdata *cf = vcf; 190 struct sbus_attach_args *sa = aux; 191 192 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 193 } 194 195 void 196 cgthreeattach(struct device *parent, struct device *self, void *aux) 197 { 198 struct cgthree_softc *sc = (struct cgthree_softc *)self; 199 struct sbus_attach_args *sa = aux; 200 int node, console; 201 const char *nam; 202 203 node = sa->sa_node; 204 sc->sc_bustag = sa->sa_bustag; 205 sc->sc_paddr = sbus_bus_addr(sa->sa_bustag, sa->sa_slot, sa->sa_offset); 206 207 fb_setsize(&sc->sc_sunfb, 8, 1152, 900, node, 0); 208 209 if (sa->sa_nreg != 1) { 210 printf(": expected %d registers, got %d\n", 1, sa->sa_nreg); 211 goto fail; 212 } 213 214 /* 215 * Map just CTRL and video RAM. 216 */ 217 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 218 sa->sa_reg[0].sbr_offset + CGTHREE_CTRL_OFFSET, 219 CGTHREE_CTRL_SIZE, 0, 0, &sc->sc_ctrl_regs) != 0) { 220 printf(": cannot map ctrl registers\n"); 221 goto fail_ctrl; 222 } 223 224 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 225 sa->sa_reg[0].sbr_offset + CGTHREE_VID_OFFSET, 226 sc->sc_sunfb.sf_fbsize, BUS_SPACE_MAP_LINEAR, 227 0, &sc->sc_vid_regs) != 0) { 228 printf(": cannot map vid registers\n"); 229 goto fail_vid; 230 } 231 232 nam = getpropstring(node, "model"); 233 if (*nam == '\0') 234 nam = sa->sa_name; 235 printf(": %s", nam); 236 237 console = cgthree_is_console(node); 238 239 cgthree_reset(sc); 240 cgthree_burner(sc, 1, 0); 241 242 sc->sc_sunfb.sf_ro.ri_bits = (void *)bus_space_vaddr(sc->sc_bustag, 243 sc->sc_vid_regs); 244 sc->sc_sunfb.sf_ro.ri_hw = sc; 245 246 printf(", %dx%d\n", sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height); 247 248 fbwscons_init(&sc->sc_sunfb, 0, console); 249 fbwscons_setcolormap(&sc->sc_sunfb, cgthree_setcolor); 250 251 if (console) 252 fbwscons_console_init(&sc->sc_sunfb, -1); 253 254 fbwscons_attach(&sc->sc_sunfb, &cgthree_accessops, console); 255 256 return; 257 258 fail_vid: 259 bus_space_unmap(sa->sa_bustag, sc->sc_ctrl_regs, CGTHREE_CTRL_SIZE); 260 fail_ctrl: 261 fail: 262 ; 263 } 264 265 int 266 cgthree_ioctl(void *v, u_long cmd, caddr_t data, int flags, struct proc *p) 267 { 268 struct cgthree_softc *sc = v; 269 struct wsdisplay_fbinfo *wdf; 270 struct wsdisplay_cmap *cm; 271 int error; 272 273 switch (cmd) { 274 case WSDISPLAYIO_GTYPE: 275 *(u_int *)data = WSDISPLAY_TYPE_SUNCG3; 276 break; 277 case WSDISPLAYIO_SMODE: 278 sc->sc_mode = *(u_int *)data; 279 break; 280 case WSDISPLAYIO_GINFO: 281 wdf = (void *)data; 282 wdf->height = sc->sc_sunfb.sf_height; 283 wdf->width = sc->sc_sunfb.sf_width; 284 wdf->depth = sc->sc_sunfb.sf_depth; 285 wdf->cmsize = 256; 286 break; 287 case WSDISPLAYIO_LINEBYTES: 288 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 289 break; 290 291 case WSDISPLAYIO_GETCMAP: 292 cm = (struct wsdisplay_cmap *)data; 293 error = cg3_bt_getcmap(&sc->sc_cmap, cm); 294 if (error) 295 return (error); 296 break; 297 298 case WSDISPLAYIO_PUTCMAP: 299 cm = (struct wsdisplay_cmap *)data; 300 error = cg3_bt_putcmap(&sc->sc_cmap, cm); 301 if (error) 302 return (error); 303 cgthree_loadcmap(sc, cm->index, cm->count); 304 break; 305 306 case WSDISPLAYIO_SVIDEO: 307 case WSDISPLAYIO_GVIDEO: 308 break; 309 310 case WSDISPLAYIO_GCURPOS: 311 case WSDISPLAYIO_SCURPOS: 312 case WSDISPLAYIO_GCURMAX: 313 case WSDISPLAYIO_GCURSOR: 314 case WSDISPLAYIO_SCURSOR: 315 default: 316 return -1; /* not supported yet */ 317 } 318 319 return (0); 320 } 321 322 #define START (128 * 1024 + 128 * 1024) 323 #define NOOVERLAY (0x04000000) 324 325 paddr_t 326 cgthree_mmap(void *v, off_t offset, int prot) 327 { 328 struct cgthree_softc *sc = v; 329 330 if (offset & PGOFSET || offset < 0) 331 return (-1); 332 333 switch (sc->sc_mode) { 334 case WSDISPLAYIO_MODE_MAPPED: 335 if (offset >= NOOVERLAY) 336 offset -= NOOVERLAY; 337 else if (offset >= START) 338 offset -= START; 339 else 340 offset = 0; 341 if (offset >= sc->sc_sunfb.sf_fbsize) 342 return (-1); 343 return (bus_space_mmap(sc->sc_bustag, sc->sc_paddr, 344 CGTHREE_VID_OFFSET + offset, prot, BUS_SPACE_MAP_LINEAR)); 345 case WSDISPLAYIO_MODE_DUMBFB: 346 if (offset < sc->sc_sunfb.sf_fbsize) 347 return (bus_space_mmap(sc->sc_bustag, sc->sc_paddr, 348 CGTHREE_VID_OFFSET + offset, prot, 349 BUS_SPACE_MAP_LINEAR)); 350 break; 351 } 352 return (-1); 353 } 354 355 int 356 cgthree_is_console(int node) 357 { 358 extern int fbnode; 359 360 return (fbnode == node); 361 } 362 363 void 364 cgthree_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) 365 { 366 struct cgthree_softc *sc = v; 367 union bt_cmap *bcm = &sc->sc_cmap; 368 369 bcm->cm_map[index][0] = r; 370 bcm->cm_map[index][1] = g; 371 bcm->cm_map[index][2] = b; 372 cgthree_loadcmap(sc, index, 1); 373 } 374 375 void 376 cgthree_loadcmap(struct cgthree_softc *sc, u_int start, u_int ncolors) 377 { 378 u_int cstart; 379 int count; 380 381 cstart = BT_D4M3(start); 382 count = BT_D4M3(start + ncolors - 1) - BT_D4M3(start) + 3; 383 BT_WRITE(sc, BT_ADDR, BT_D4M4(start)); 384 while (--count >= 0) { 385 BT_WRITE(sc, BT_CMAP, sc->sc_cmap.cm_chip[cstart]); 386 cstart++; 387 } 388 } 389 390 int 391 cg3_bt_getcmap(union bt_cmap *bcm, struct wsdisplay_cmap *rcm) 392 { 393 u_int index = rcm->index, count = rcm->count, i; 394 int error; 395 396 if (index >= 256 || count > 256 - index) 397 return (EINVAL); 398 for (i = 0; i < count; i++) { 399 if ((error = copyout(&bcm->cm_map[index + i][0], 400 &rcm->red[i], 1)) != 0) 401 return (error); 402 if ((error = copyout(&bcm->cm_map[index + i][1], 403 &rcm->green[i], 1)) != 0) 404 return (error); 405 if ((error = copyout(&bcm->cm_map[index + i][2], 406 &rcm->blue[i], 1)) != 0) 407 return (error); 408 } 409 return (0); 410 } 411 412 int 413 cg3_bt_putcmap(union bt_cmap *bcm, struct wsdisplay_cmap *rcm) 414 { 415 u_int index = rcm->index, count = rcm->count, i; 416 int error; 417 418 if (index >= 256 || count > 256 - index) 419 return (EINVAL); 420 for (i = 0; i < count; i++) { 421 if ((error = copyin(&rcm->red[i], 422 &bcm->cm_map[index + i][0], 1)) != 0) 423 return (error); 424 if ((error = copyin(&rcm->green[i], 425 &bcm->cm_map[index + i][1], 1)) != 0) 426 return (error); 427 if ((error = copyin(&rcm->blue[i], 428 &bcm->cm_map[index + i][2], 1)) != 0) 429 return (error); 430 } 431 return (0); 432 } 433 434 void 435 cgthree_reset(struct cgthree_softc *sc) 436 { 437 int i, j; 438 u_int8_t sts, ctrl; 439 440 sts = FBC_READ(sc, CG3_FBC_STAT); 441 ctrl = FBC_READ(sc, CG3_FBC_CTRL); 442 443 if (ctrl & FBC_CTRL_TIME) { 444 /* already initialized */ 445 return; 446 } 447 448 for (i = 0; i < nitems(cg3_videoctrl); i++) { 449 if (cg3_videoctrl[i].sense == 0xff || 450 (cg3_videoctrl[i].sense == 451 (sts & (FBC_STAT_RES | FBC_STAT_ID)))) { 452 for (j = 0; j < 12; j++) 453 FBC_WRITE(sc, CG3_FBC_VCTRL + j, 454 cg3_videoctrl[i].vctrl[j]); 455 ctrl &= ~(FBC_CTRL_XTAL | FBC_CTRL_DIV); 456 ctrl |= cg3_videoctrl[i].ctrl | 457 FBC_CTRL_TIME; 458 FBC_WRITE(sc, CG3_FBC_CTRL, ctrl); 459 break; 460 } 461 } 462 463 /* enable all the bit planes */ 464 BT_WRITE(sc, BT_ADDR, BT_RMR); 465 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); 466 BT_WRITE(sc, BT_CTRL, 0xff); 467 BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE); 468 469 /* no plane should blink */ 470 BT_WRITE(sc, BT_ADDR, BT_BMR); 471 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); 472 BT_WRITE(sc, BT_CTRL, 0x00); 473 BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE); 474 475 /* 476 * enable the RAMDAC, disable blink, disable overlay 0 and 1, 477 * use 4:1 multiplexor. 478 */ 479 BT_WRITE(sc, BT_ADDR, BT_CR); 480 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); 481 BT_WRITE(sc, BT_CTRL, 482 (BTCR_MPLX_4 | BTCR_RAMENA | BTCR_BLINK_6464)); 483 BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE); 484 485 /* disable the D/A read pins */ 486 BT_WRITE(sc, BT_ADDR, BT_CTR); 487 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); 488 BT_WRITE(sc, BT_CTRL, 0x00); 489 BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE); 490 } 491 492 void 493 cgthree_burner(void *vsc, u_int on, u_int flags) 494 { 495 struct cgthree_softc *sc = vsc; 496 int s; 497 u_int8_t fbc; 498 499 s = splhigh(); 500 fbc = FBC_READ(sc, CG3_FBC_CTRL); 501 if (on) 502 fbc |= FBC_CTRL_VENAB | FBC_CTRL_TIME; 503 else { 504 fbc &= ~FBC_CTRL_VENAB; 505 if (flags & WSDISPLAY_BURN_VBLANK) 506 fbc &= ~FBC_CTRL_TIME; 507 } 508 FBC_WRITE(sc, CG3_FBC_CTRL, fbc); 509 splx(s); 510 } 511