1 /* $OpenBSD: spifreg.h,v 1.5 2003/06/02 18:32:41 jason Exp $ */ 2 3 /* 4 * Copyright (c) 1999-2002 Jason L. Wright (jason@thought.net) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Effort sponsored in part by the Defense Advanced Research Projects 29 * Agency (DARPA) and Air Force Research Laboratory, Air Force 30 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 31 * 32 */ 33 34 #define PPC_IN_PDATA 0x000 /* input data */ 35 #define PPC_IN_PSTAT 0x001 /* input status */ 36 #define PPC_IN_CTRL 0x002 /* input control */ 37 #define PPC_IN_PWEIRD 0x003 /* input weird */ 38 #define PPC_OUT_PDATA 0x000 /* output data */ 39 #define PPC_OUT_PSTAT 0x001 /* output status */ 40 #define PPC_OUT_PCTRL 0x002 /* output control */ 41 #define PPC_OUT_PWEIRD 0x003 /* output weird */ 42 #define PPC_IACK_PDATA 0x1fc /* iack data */ 43 #define PPC_IACK_PSTAT 0x1fd /* iack status */ 44 #define PPC_IACK_PCTRL 0x1fe /* iack control */ 45 #define PPC_IACK_PWEIRD 0x1ff /* iack weird */ 46 47 /* Parallel Status: read only */ 48 #define PPC_PSTAT_ERROR 0x08 /* error */ 49 #define PPC_PSTAT_SELECT 0x10 /* select */ 50 #define PPC_PSTAT_PAPER 0x20 /* paper out */ 51 #define PPC_PSTAT_ACK 0x40 /* ack */ 52 #define PPC_PSTAT_BUSY 0x80 /* busy */ 53 54 /* Parallel Control: read/write */ 55 #define PPC_CTRL_STROBE 0x01 /* strobe, 1=drop strobe */ 56 #define PPC_CTRL_AFX 0x02 /* auto form-feed */ 57 #define PPC_CTRL_INIT 0x04 /* init, 1=enable printer */ 58 #define PPC_CTRL_SLCT 0x08 /* SLC, 1=select printer */ 59 #define PPC_CTRL_IRQE 0x10 /* IRQ, 1=enable intrs */ 60 #define PPC_CTRL_OUTPUT 0x20 /* direction: 1=ppc out */ 61 62 /* 63 * The 'stc' is a Cirrus Logic CL-CD180 (either revision B or revision C) 64 */ 65 #define STC_CCR 0x01 /* channel command */ 66 #define STC_SRER 0x02 /* service request enable */ 67 #define STC_COR1 0x03 /* channel option 1 */ 68 #define STC_COR2 0x04 /* channel option 2 */ 69 #define STC_COR3 0x05 /* channel option 3 */ 70 #define STC_CCSR 0x06 /* channel control status */ 71 #define STC_RDCR 0x07 /* rx data count */ 72 #define STC_SCHR1 0x09 /* special character 1 */ 73 #define STC_SCHR2 0x0a /* special character 2 */ 74 #define STC_SCHR3 0x0b /* special character 3 */ 75 #define STC_SCHR4 0x0c /* special character 4 */ 76 #define STC_MCOR1 0x10 /* modem change option 1 */ 77 #define STC_MCOR2 0x11 /* modem change option 2 */ 78 #define STC_MCR 0x12 /* modem change */ 79 #define STC_RTPR 0x18 /* rx timeout period */ 80 #define STC_MSVR 0x28 /* modem signal value */ 81 #define STC_MSVRTS 0x29 /* modem signal value rts */ 82 #define STC_MSVDTR 0x2a /* modem signal value dtr */ 83 #define STC_RBPRH 0x31 /* rx bit rate period high */ 84 #define STC_RBPRL 0x32 /* rx bit rate period low */ 85 #define STC_RBR 0x33 /* rx bit */ 86 #define STC_TBPRH 0x39 /* tx bit rate period high */ 87 #define STC_TBPRL 0x3a /* tx bit rate period low */ 88 #define STC_GSVR 0x40 /* global service vector */ 89 #define STC_GSCR1 0x41 /* global service channel 1 */ 90 #define STC_GSCR2 0x42 /* global service channel 2 */ 91 #define STC_GSCR3 0x43 /* global service channel 3 */ 92 #define STC_MSMR 0x61 /* modem service match */ 93 #define STC_TSMR 0x62 /* tx service match */ 94 #define STC_RSMR 0x63 /* rx service match */ 95 #define STC_CAR 0x64 /* channel access */ 96 #define STC_SRSR 0x65 /* service request status */ 97 #define STC_SRCR 0x66 /* service request config */ 98 #define STC_GFRCR 0x6b /* global firmware rev code */ 99 #define STC_PPRH 0x70 /* prescalar period high */ 100 #define STC_PPRL 0x71 /* prescalar period low */ 101 #define STC_MRAR 0x75 /* modem request ack */ 102 #define STC_TRAR 0x76 /* tx request ack */ 103 #define STC_RRAR 0x77 /* rx request ack */ 104 #define STC_RDR 0x78 /* rx data */ 105 #define STC_RCSR 0x7a /* rx character status */ 106 #define STC_TDR 0x7b /* tx data */ 107 #define STC_EOSRR 0x7f /* end of service */ 108 109 #define STC_REGMAPSIZE 0x80 110 111 /* Global Firmware Revision Code Register (rw) */ 112 #define CD180_GFRCR_REV_B 0x81 /* CL-CD180B */ 113 #define CD180_GFRCR_REV_C 0x82 /* CL-CD180C */ 114 115 /* Service Request Configuration Register (rw) (CD180C or higher) */ 116 #define CD180_SRCR_PKGTYP 0x80 /* pkg type,0=PLCC,1=PQFP */ 117 #define CD180_SRCR_REGACKEN 0x40 /* register ack enable */ 118 #define CD180_SRCR_DAISYEN 0x20 /* daisy chain enable */ 119 #define CD180_SRCR_GLOBPRI 0x10 /* global priority */ 120 #define CD180_SRCR_UNFAIR 0x08 /* use unfair interrupts */ 121 #define CD180_SRCR_AUTOPRI 0x02 /* automatic priority */ 122 #define CD180_SRCR_PRISEL 0x01 /* select rx/tx as high pri */ 123 124 /* Prescalar Period Register High (rw) */ 125 #define CD180_PPRH 0xf0 /* high byte */ 126 #define CD180_PPRL 0x00 /* low byte */ 127 128 /* Global Service Vector Register (rw) */ 129 /* Modem Request Acknowledgement Register (ro) (and IACK equivalent) */ 130 /* Receive Request Acknowledgement Register (ro) (and IACK equivalent) */ 131 /* Transmit Request Acknowledgement Register (ro) (and IACK equivalent) */ 132 #define CD180_GSVR_USERMASK 0xf8 /* user defined bits */ 133 #define CD180_GSVR_IMASK 0x07 /* interrupt type mask */ 134 #define CD180_GSVR_NOREQUEST 0x00 /* no request pending */ 135 #define CD180_GSVR_STATCHG 0x01 /* modem signal change */ 136 #define CD180_GSVR_TXDATA 0x02 /* tx service request */ 137 #define CD180_GSVR_RXGOOD 0x03 /* rx service request */ 138 #define CD180_GSVR_reserved1 0x04 /* reserved */ 139 #define CD180_GSVR_reserved2 0x05 /* reserved */ 140 #define CD180_GSVR_reserved3 0x06 /* reserved */ 141 #define CD180_GSVR_RXEXCEPTION 0x07 /* rx exception request */ 142 143 /* Service Request Status Register (ro) (CD180C and higher) */ 144 #define CD180_SRSR_MREQINT 0x01 /* modem request internal */ 145 #define CD180_SRSR_MREQEXT 0x02 /* modem request external */ 146 #define CD180_SRSR_TREQINT 0x04 /* tx request internal */ 147 #define CD180_SRSR_TREQEXT 0x08 /* tx request external */ 148 #define CD180_SRSR_RREQINT 0x10 /* rx request internal */ 149 #define CD180_SRSR_RREQEXT 0x20 /* rx request external */ 150 #define CD180_SRSR_ILV_MASK 0xc0 /* internal service context */ 151 #define CD180_SRSR_ILV_NONE 0x00 /* not in service context */ 152 #define CD180_SRSR_ILV_RX 0xc0 /* in rx service context */ 153 #define CD180_SRSR_ILV_TX 0x80 /* in tx service context */ 154 #define CD180_SRSR_ILV_MODEM 0x40 /* in modem service context */ 155 156 /* Global Service Channel Register 1,2,3 (rw) */ 157 #define CD180_GSCR_CHANNEL(gscr) (((gscr) >> 2) & 7) 158 159 /* Receive Data Count Register (ro) */ 160 #define CD180_RDCR_MASK 0x0f /* mask for fifo length */ 161 162 /* Receive Character Status Register (ro) */ 163 #define CD180_RCSR_TO 0x80 /* time out */ 164 #define CD180_RCSR_SCD2 0x40 /* special char detect 2 */ 165 #define CD180_RCSR_SCD1 0x20 /* special char detect 1 */ 166 #define CD180_RCSR_SCD0 0x10 /* special char detect 0 */ 167 #define CD180_RCSR_BE 0x08 /* break exception */ 168 #define CD180_RCSR_PE 0x04 /* parity exception */ 169 #define CD180_RCSR_FE 0x02 /* framing exception */ 170 #define CD180_RCSR_OE 0x01 /* overrun exception */ 171 172 /* Service Request Enable Register (rw) */ 173 #define CD180_SRER_DSR 0x80 /* DSR service request */ 174 #define CD180_SRER_CD 0x40 /* CD service request */ 175 #define CD180_SRER_CTS 0x20 /* CTS service request */ 176 #define CD180_SRER_RXD 0x10 /* RXD service request */ 177 #define CD180_SRER_RXSCD 0x08 /* RX special char request */ 178 #define CD180_SRER_TXD 0x04 /* TX ready service request */ 179 #define CD180_SRER_TXE 0x02 /* TX empty service request */ 180 #define CD180_SRER_NNDT 0x01 /* No new data timeout req */ 181 182 /* Channel Command Register (rw) */ 183 /* Reset Channel Command */ 184 #define CD180_CCR_CMD_RESET 0x80 /* chip/channel reset */ 185 #define CD180_CCR_RESETALL 0x01 /* global reset */ 186 #define CD180_CCR_RESETCHAN 0x00 /* current channel reset */ 187 /* Channel Option Register Command */ 188 #define CD180_CCR_CMD_COR 0x40 /* channel opt reg changed */ 189 #define CD180_CCR_CORCHG1 0x02 /* cor1 has changed */ 190 #define CD180_CCR_CORCHG2 0x04 /* cor2 has changed */ 191 #define CD180_CCR_CORCHG3 0x08 /* cor3 has changed */ 192 /* Send Special Character Command */ 193 #define CD180_CCR_CMD_SPC 0x20 /* send special chars changed */ 194 #define CD180_CCR_SSPC0 0x01 /* send special char 0 change */ 195 #define CD180_CCR_SSPC1 0x02 /* send special char 1 change */ 196 #define CD180_CCR_SSPC2 0x04 /* send special char 2 change */ 197 /* Channel Control Command */ 198 #define CD180_CCR_CMD_CHAN 0x10 /* channel control command */ 199 #define CD180_CCR_CHAN_TXEN 0x08 /* enable channel tx */ 200 #define CD180_CCR_CHAN_TXDIS 0x04 /* disable channel tx */ 201 #define CD180_CCR_CHAN_RXEN 0x02 /* enable channel rx */ 202 #define CD180_CCR_CHAN_RXDIS 0x01 /* disable channel rx */ 203 204 /* Channel Option Register 1 (rw) */ 205 #define CD180_COR1_EVENPAR 0x00 /* even parity */ 206 #define CD180_COR1_ODDPAR 0x80 /* odd parity */ 207 #define CD180_COR1_PARMODE_NO 0x00 /* no parity */ 208 #define CD180_COR1_PARMODE_FORCE 0x20 /* force (odd=1, even=0) */ 209 #define CD180_COR1_PARMODE_NORMAL 0x40 /* normal parity mode */ 210 #define CD180_COR1_PARMODE_NA 0x60 /* notused */ 211 #define CD180_COR1_IGNPAR 0x10 /* ignore parity */ 212 #define CD180_COR1_STOP1 0x00 /* 1 stop bit */ 213 #define CD180_COR1_STOP15 0x04 /* 1.5 stop bits */ 214 #define CD180_COR1_STOP2 0x08 /* 2 stop bits */ 215 #define CD180_COR1_STOP25 0x0c /* 2.5 stop bits */ 216 #define CD180_COR1_CS5 0x00 /* 5 bit characters */ 217 #define CD180_COR1_CS6 0x01 /* 6 bit characters */ 218 #define CD180_COR1_CS7 0x02 /* 7 bit characters */ 219 #define CD180_COR1_CS8 0x03 /* 8 bit characters */ 220 221 /* Channel Option Register 2 (rw) */ 222 #define CD180_COR2_IXM 0x80 /* implied xon mode */ 223 #define CD180_COR2_TXIBE 0x40 /* tx in-band flow control */ 224 #define CD180_COR2_ETC 0x20 /* embedded tx command enbl */ 225 #define CD180_COR2_LLM 0x10 /* local loopback mode */ 226 #define CD180_COR2_RLM 0x08 /* remote loopback mode */ 227 #define CD180_COR2_RTSAO 0x04 /* RTS automatic output enbl */ 228 #define CD180_COR2_CTSAE 0x02 /* CTS automatic enable */ 229 #define CD180_COR2_DSRAE 0x01 /* DSR automatic enable */ 230 231 /* Channel Option Register 3 (rw) */ 232 #define CD180_COR3_XON2 0x80 /* XON char in spc1&3 */ 233 #define CD180_COR3_XON1 0x00 /* XON char in spc1 */ 234 #define CD180_COR3_XOFF2 0x40 /* XOFF char in spc2&4 */ 235 #define CD180_COR3_XOFF1 0x00 /* XOFF char in spc2 */ 236 #define CD180_COR3_FCT 0x20 /* flow control transparency */ 237 #define CD180_COR3_SCDE 0x10 /* special char recognition */ 238 #define CD180_COR3_RXFIFO_MASK 0x0f /* rx fifo threshold */ 239 240 /* Channel Control Status Register (ro) */ 241 #define CD180_CCSR_RXEN 0x80 /* rx is enabled */ 242 #define CD180_CCSR_RXFLOFF 0x40 /* rx flow-off */ 243 #define CD180_CCSR_RXFLON 0x20 /* rx flow-on */ 244 #define CD180_CCSR_TXEN 0x08 /* tx is enabled */ 245 #define CD180_CCSR_TXFLOFF 0x04 /* tx flow-off */ 246 #define CD180_CCSR_TXFLON 0x02 /* tx flow-on */ 247 248 /* Receiver Bit Register (ro) */ 249 #define CD180_RBR_RXD 0x40 /* state of RxD pin */ 250 #define CD180_RBR_STARTHUNT 0x20 /* looking for start bit */ 251 252 /* Modem Change Register (rw) */ 253 #define CD180_MCR_DSR 0x80 /* DSR changed */ 254 #define CD180_MCR_CD 0x40 /* CD changed */ 255 #define CD180_MCR_CTS 0x20 /* CTS changed */ 256 257 /* Modem Change Option Register 1 (rw) */ 258 #define CD180_MCOR1_DSRZD 0x80 /* catch 0->1 DSR changes */ 259 #define CD180_MCOR1_CDZD 0x40 /* catch 0->1 CD changes */ 260 #define CD180_MCOR1_CTSZD 0x40 /* catch 0->1 CTS changes */ 261 #define CD180_MCOR1_DTRTHRESH 0x0f /* DTR threshold mask */ 262 263 /* Modem Change Option Register 2 (rw) */ 264 #define CD180_MCOR2_DSROD 0x80 /* catch 1->0 DSR changes */ 265 #define CD180_MCOR2_CDOD 0x40 /* catch 1->0 CD changes */ 266 #define CD180_MCOR2_CTSOD 0x20 /* catch 1->0 CTS changes */ 267 268 /* Modem Signal Value Register (rw) */ 269 #define CD180_MSVR_DSR 0x80 /* DSR input state */ 270 #define CD180_MSVR_CD 0x40 /* CD input state */ 271 #define CD180_MSVR_CTS 0x20 /* CTS input state */ 272 #define CD180_MSVR_DTR 0x02 /* DTR output state */ 273 #define CD180_MSVR_RTS 0x01 /* RTS output state */ 274 275 /* Modem Signal Value Register - Request To Send (w) (CD180C and higher) */ 276 #define CD180_MSVRTS_RTS 0x01 /* RTS signal value */ 277 278 /* Modem Signal Value Register - Data Terminal Ready (w) (CD180C and higher) */ 279 #define CD180_MSVDTR_DTR 0x02 /* DTR signal value */ 280 281 /* 282 * The register map for the SUNW,spif looks something like: 283 * Offset: Function: 284 * 0000 - 03ff Boot ROM 285 * 0400 - 0407 dtr latches (one per port) 286 * 0409 - 07ff unused 287 * 0800 - 087f CD180 registers (normal mapping) 288 * 0880 - 0bff unused 289 * 0c00 - 0c7f CD180 registers (*iack mapping) 290 * 0c80 - 0dff unused 291 * 0e00 - 1fff PPC registers 292 * 293 * One note about the DTR latches: The values stored there are reversed. 294 * By writing a 1 to the latch, DTR is lowered, and by writing a 0, DTR 295 * is raised. The latches cannot be read, and no other value can be written 296 * there or the system will crash due to "excessive bus loading (see 297 * SBus loading and capacitance spec)" 298 * 299 * The *iack registers are read/written with the IACK bit set. When 300 * the interrupt routine starts, it reads the MRAR, TRAR, and RRAR registers 301 * from this mapping. This signals an interrupt acknowledgement cycle. 302 * (NOTE: these are not really the MRAR, TRAR, and RRAR... They are copies 303 * of the GSVR, I just mapped them to the same location as the mrar, trar, 304 * and rrar because it seemed appropriate). 305 */ 306 #define DTR_REG_OFFSET 0x400 /* DTR latches */ 307 #define DTR_REG_LEN 0x8 308 #define STC_REG_OFFSET 0x800 /* normal cd180 access */ 309 #define STC_REG_LEN 0x80 310 #define ISTC_REG_OFFSET 0xc00 /* IACK cd180 access */ 311 #define ISTC_REG_LEN STC_REG_LEN 312 #define PPC_REG_OFFSET 0xe00 /* PPC registers */ 313 #define PPC_REG_LEN 0x200 314 315 /* 316 * The mapping of minor device number -> card and port is done as 317 * follows by default: 318 * 319 * +---+---+---+---+---+---+---+---+ 320 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 321 * +---+---+---+---+---+---+---+---+ 322 * | | | | | | | | 323 * | | | | | +---+---+---> port number 324 * | | | | | 325 * | | | | +---------------> unused 326 * | | | | 327 * | | | +-------------------> dialout (on tty ports) 328 * | | | 329 * | | +-----------------------> unused 330 * | | 331 * +---+---------------------------> card number 332 * 333 */ 334 #define SPIF_MAX_CARDS 4 335 #define SPIF_MAX_TTY 8 336 #define SPIF_MAX_BPP 1 337 338 /* 339 * device selectors 340 */ 341 #define SPIF_CARD(x) ((minor(x) >> 6) & 0x03) 342 #define SPIF_PORT(x) (minor(x) & 0x07) 343 #define STTY_DIALOUT(x) (minor(x) & 0x10) 344 345 #define STTY_RX_FIFO_THRESHOLD 4 346 #define STTY_RX_DTR_THRESHOLD 7 347 #define CD180_TX_FIFO_SIZE 8 /* 8 chars of fifo */ 348 349 /* 350 * These are the offsets of the MRAR, TRAR, and RRAR in *IACK space. 351 * The high bit must be set as per specs for the MSMR, TSMR, and RSMR. 352 */ 353 #define SPIF_MSMR (0x80 | STC_MRAR) /* offset of MRAR | 0x80 */ 354 #define SPIF_TSMR (0x80 | STC_TRAR) /* offset of TRAR | 0x80 */ 355 #define SPIF_RSMR (0x80 | STC_RRAR) /* offset of RRAR | 0x80 */ 356 357 /* 358 * "verosc" node tells which oscillator we have. 359 */ 360 #define SPIF_OSC9 1 /* 9.8304 MHz */ 361 #define SPIF_OSC10 2 /* 10MHz */ 362 363 /* 364 * There are two interrupts, serial gets interrupt[0], and parallel 365 * gets interrupt[1] 366 */ 367 #define SERIAL_INTR 0 368 #define PARALLEL_INTR 1 369 370 /* 371 * spif tty flags 372 */ 373 #define STTYF_CDCHG 0x01 /* carrier changed */ 374 #define STTYF_RING_OVERFLOW 0x02 /* ring buffer overflowed */ 375 #define STTYF_DONE 0x04 /* done... flush buffers */ 376 #define STTYF_SET_BREAK 0x08 /* set break signal */ 377 #define STTYF_CLR_BREAK 0x10 /* clear break signal */ 378 #define STTYF_STOP 0x20 /* stopped */ 379 380 #define STTY_RBUF_SIZE (2 * 512) 381