1 /* $OpenBSD: sdhc.c,v 1.69 2020/08/14 14:49:04 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * SD Host Controller driver based on the SD Host Controller Standard 21 * Simplified Specification Version 1.00 (www.sdcard.com). 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/malloc.h> 28 #include <sys/proc.h> 29 #include <sys/systm.h> 30 #include <sys/time.h> 31 32 #include <dev/sdmmc/sdhcreg.h> 33 #include <dev/sdmmc/sdhcvar.h> 34 #include <dev/sdmmc/sdmmcchip.h> 35 #include <dev/sdmmc/sdmmcreg.h> 36 #include <dev/sdmmc/sdmmcvar.h> 37 #include <dev/sdmmc/sdmmc_ioreg.h> 38 39 /* Timeouts in seconds */ 40 #define SDHC_COMMAND_TIMEOUT 1 41 #define SDHC_BUFFER_TIMEOUT 1 42 #define SDHC_TRANSFER_TIMEOUT 1 43 #define SDHC_DMA_TIMEOUT 3 44 45 struct sdhc_host { 46 struct sdhc_softc *sc; /* host controller device */ 47 struct device *sdmmc; /* generic SD/MMC device */ 48 bus_space_tag_t iot; /* host register set tag */ 49 bus_space_handle_t ioh; /* host register set handle */ 50 u_int16_t version; /* specification version */ 51 u_int clkbase; /* base clock frequency in KHz */ 52 int maxblklen; /* maximum block length */ 53 int flags; /* flags for this host */ 54 u_int32_t ocr; /* OCR value from capabilities */ 55 u_int8_t regs[14]; /* host controller state */ 56 u_int16_t intr_status; /* soft interrupt status */ 57 u_int16_t intr_error_status; /* soft error status */ 58 59 bus_dmamap_t adma_map; 60 bus_dma_segment_t adma_segs[1]; 61 caddr_t adma2; 62 63 uint16_t block_size; 64 uint16_t block_count; 65 uint16_t transfer_mode; 66 }; 67 68 /* flag values */ 69 #define SHF_USE_DMA 0x0001 70 #define SHF_USE_DMA64 0x0002 71 #define SHF_USE_32BIT_ACCESS 0x0004 72 73 #define HREAD1(hp, reg) \ 74 (sdhc_read_1((hp), (reg))) 75 #define HREAD2(hp, reg) \ 76 (sdhc_read_2((hp), (reg))) 77 #define HREAD4(hp, reg) \ 78 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 79 #define HWRITE1(hp, reg, val) \ 80 sdhc_write_1((hp), (reg), (val)) 81 #define HWRITE2(hp, reg, val) \ 82 sdhc_write_2((hp), (reg), (val)) 83 #define HWRITE4(hp, reg, val) \ 84 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 85 #define HCLR1(hp, reg, bits) \ 86 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 87 #define HCLR2(hp, reg, bits) \ 88 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 89 #define HSET1(hp, reg, bits) \ 90 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 91 #define HSET2(hp, reg, bits) \ 92 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 93 94 int sdhc_host_reset(sdmmc_chipset_handle_t); 95 u_int32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 96 int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 97 int sdhc_card_detect(sdmmc_chipset_handle_t); 98 int sdhc_bus_power(sdmmc_chipset_handle_t, u_int32_t); 99 int sdhc_bus_clock(sdmmc_chipset_handle_t, int, int); 100 int sdhc_bus_width(sdmmc_chipset_handle_t, int); 101 void sdhc_card_intr_mask(sdmmc_chipset_handle_t, int); 102 void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 103 int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 104 void sdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 105 int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 106 int sdhc_wait_state(struct sdhc_host *, u_int32_t, u_int32_t); 107 int sdhc_soft_reset(struct sdhc_host *, int); 108 int sdhc_wait_intr_cold(struct sdhc_host *, int, int); 109 int sdhc_wait_intr(struct sdhc_host *, int, int); 110 void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 111 void sdhc_read_data(struct sdhc_host *, u_char *, int); 112 void sdhc_write_data(struct sdhc_host *, u_char *, int); 113 int sdhc_hibernate_init(sdmmc_chipset_handle_t, void *); 114 115 #ifdef SDHC_DEBUG 116 int sdhcdebug = 0; 117 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 118 void sdhc_dump_regs(struct sdhc_host *); 119 #else 120 #define DPRINTF(n,s) do {} while(0) 121 #endif 122 123 struct sdmmc_chip_functions sdhc_functions = { 124 .host_reset = sdhc_host_reset, 125 .host_ocr = sdhc_host_ocr, 126 .host_maxblklen = sdhc_host_maxblklen, 127 .card_detect = sdhc_card_detect, 128 .bus_power = sdhc_bus_power, 129 .bus_clock = sdhc_bus_clock, 130 .bus_width = sdhc_bus_width, 131 .exec_command = sdhc_exec_command, 132 .card_intr_mask = sdhc_card_intr_mask, 133 .card_intr_ack = sdhc_card_intr_ack, 134 .signal_voltage = sdhc_signal_voltage, 135 .hibernate_init = sdhc_hibernate_init, 136 }; 137 138 struct cfdriver sdhc_cd = { 139 NULL, "sdhc", DV_DULL 140 }; 141 142 /* 143 * Some controllers live on a bus that only allows 32-bit 144 * transactions. In that case we use a RMW cycle for 8-bit and 16-bit 145 * register writes. However that doesn't work for the Transfer Mode 146 * register as this register lives in the same 32-bit word as the 147 * Command register and writing the Command register triggers SD 148 * command generation. We avoid this issue by using a shadow variable 149 * for the Transfer Mode register that we write out when we write the 150 * Command register. 151 * 152 * The Arasan controller controller integrated on the Broadcom SoCs 153 * used in the Raspberry Pi has an interesting bug where writing the 154 * same 32-bit register twice doesn't work. This means that we lose 155 * writes to the Block Sine and/or Block Count register. We work 156 * around that issue by using shadow variables as well. 157 */ 158 159 uint8_t 160 sdhc_read_1(struct sdhc_host *hp, bus_size_t offset) 161 { 162 uint32_t reg; 163 164 if (hp->flags & SHF_USE_32BIT_ACCESS) { 165 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3); 166 return (reg >> ((offset & 3) * 8)) & 0xff; 167 } 168 169 return bus_space_read_1(hp->iot, hp->ioh, offset); 170 } 171 172 uint16_t 173 sdhc_read_2(struct sdhc_host *hp, bus_size_t offset) 174 { 175 uint32_t reg; 176 177 if (hp->flags & SHF_USE_32BIT_ACCESS) { 178 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2); 179 return (reg >> ((offset & 2) * 8)) & 0xffff; 180 } 181 182 return bus_space_read_2(hp->iot, hp->ioh, offset); 183 } 184 185 void 186 sdhc_write_1(struct sdhc_host *hp, bus_size_t offset, uint8_t value) 187 { 188 uint32_t reg; 189 190 if (hp->flags & SHF_USE_32BIT_ACCESS) { 191 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3); 192 reg &= ~(0xff << ((offset & 3) * 8)); 193 reg |= (value << ((offset & 3) * 8)); 194 bus_space_write_4(hp->iot, hp->ioh, offset & ~3, reg); 195 return; 196 } 197 198 bus_space_write_1(hp->iot, hp->ioh, offset, value); 199 } 200 201 void 202 sdhc_write_2(struct sdhc_host *hp, bus_size_t offset, uint16_t value) 203 { 204 uint32_t reg; 205 206 if (hp->flags & SHF_USE_32BIT_ACCESS) { 207 switch (offset) { 208 case SDHC_BLOCK_SIZE: 209 hp->block_size = value; 210 return; 211 case SDHC_BLOCK_COUNT: 212 hp->block_count = value; 213 return; 214 case SDHC_TRANSFER_MODE: 215 hp->transfer_mode = value; 216 return; 217 case SDHC_COMMAND: 218 bus_space_write_4(hp->iot, hp->ioh, SDHC_BLOCK_SIZE, 219 (hp->block_count << 16) | hp->block_size); 220 bus_space_write_4(hp->iot, hp->ioh, SDHC_TRANSFER_MODE, 221 (value << 16) | hp->transfer_mode); 222 return; 223 } 224 225 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2); 226 reg &= ~(0xffff << ((offset & 2) * 8)); 227 reg |= (value << ((offset & 2) * 8)); 228 bus_space_write_4(hp->iot, hp->ioh, offset & ~2, reg); 229 return; 230 } 231 232 bus_space_write_2(hp->iot, hp->ioh, offset, value); 233 } 234 235 /* 236 * Called by attachment driver. For each SD card slot there is one SD 237 * host controller standard register set. (1.3) 238 */ 239 int 240 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 241 bus_space_handle_t ioh, bus_size_t iosize, int usedma, u_int32_t caps) 242 { 243 struct sdmmcbus_attach_args saa; 244 struct sdhc_host *hp; 245 int error = 1; 246 int max_clock; 247 248 /* Allocate one more host structure. */ 249 sc->sc_nhosts++; 250 hp = malloc(sizeof(*hp), M_DEVBUF, M_WAITOK | M_ZERO); 251 sc->sc_host[sc->sc_nhosts - 1] = hp; 252 253 if (ISSET(sc->sc_flags, SDHC_F_32BIT_ACCESS)) 254 SET(hp->flags, SHF_USE_32BIT_ACCESS); 255 256 /* Fill in the new host structure. */ 257 hp->sc = sc; 258 hp->iot = iot; 259 hp->ioh = ioh; 260 261 /* Store specification version. */ 262 hp->version = HREAD2(hp, SDHC_HOST_CTL_VERSION); 263 264 /* 265 * Reset the host controller and enable interrupts. 266 */ 267 (void)sdhc_host_reset(hp); 268 269 /* Determine host capabilities. */ 270 if (caps == 0) 271 caps = HREAD4(hp, SDHC_CAPABILITIES); 272 273 /* Use DMA if the host system and the controller support it. */ 274 if (usedma && ISSET(caps, SDHC_ADMA2_SUPP)) { 275 SET(hp->flags, SHF_USE_DMA); 276 if (ISSET(caps, SDHC_64BIT_DMA_SUPP)) 277 SET(hp->flags, SHF_USE_DMA64); 278 } 279 280 /* 281 * Determine the base clock frequency. (2.2.24) 282 */ 283 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 284 /* SDHC 3.0 supports 10-255 MHz. */ 285 max_clock = 255000; 286 if (SDHC_BASE_FREQ_KHZ_V3(caps) != 0) 287 hp->clkbase = SDHC_BASE_FREQ_KHZ_V3(caps); 288 } else { 289 /* SDHC 1.0/2.0 supports only 10-63 MHz. */ 290 max_clock = 63000; 291 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 292 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 293 } 294 if (hp->clkbase == 0) { 295 /* Make sure we can clock down to 400 kHz. */ 296 max_clock = 400 * SDHC_SDCLK_DIV_MAX_V3; 297 hp->clkbase = sc->sc_clkbase; 298 } 299 if (hp->clkbase == 0) { 300 /* The attachment driver must tell us. */ 301 printf("%s: base clock frequency unknown\n", 302 sc->sc_dev.dv_xname); 303 goto err; 304 } else if (hp->clkbase < 10000 || hp->clkbase > max_clock) { 305 printf("%s: base clock frequency out of range: %u MHz\n", 306 sc->sc_dev.dv_xname, hp->clkbase / 1000); 307 goto err; 308 } 309 310 printf("%s: SDHC %d.0, %d MHz base clock\n", DEVNAME(sc), 311 SDHC_SPEC_VERSION(hp->version) + 1, hp->clkbase / 1000); 312 313 /* 314 * XXX Set the data timeout counter value according to 315 * capabilities. (2.2.15) 316 */ 317 318 /* 319 * Determine SD bus voltage levels supported by the controller. 320 */ 321 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 322 SET(hp->ocr, MMC_OCR_1_65V_1_95V); 323 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 324 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 325 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 326 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 327 328 /* 329 * Determine the maximum block length supported by the host 330 * controller. (2.2.24) 331 */ 332 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 333 case SDHC_MAX_BLK_LEN_512: 334 hp->maxblklen = 512; 335 break; 336 case SDHC_MAX_BLK_LEN_1024: 337 hp->maxblklen = 1024; 338 break; 339 case SDHC_MAX_BLK_LEN_2048: 340 hp->maxblklen = 2048; 341 break; 342 default: 343 hp->maxblklen = 1; 344 break; 345 } 346 347 if (ISSET(hp->flags, SHF_USE_DMA)) { 348 int rseg; 349 350 /* Allocate ADMA2 descriptor memory */ 351 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 352 PAGE_SIZE, hp->adma_segs, 1, &rseg, 353 BUS_DMA_WAITOK | BUS_DMA_ZERO); 354 if (error) 355 goto adma_done; 356 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 357 PAGE_SIZE, &hp->adma2, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 358 if (error) { 359 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 360 goto adma_done; 361 } 362 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 363 0, BUS_DMA_WAITOK, &hp->adma_map); 364 if (error) { 365 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 366 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 367 goto adma_done; 368 } 369 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 370 hp->adma2, PAGE_SIZE, NULL, 371 BUS_DMA_WAITOK | BUS_DMA_WRITE); 372 if (error) { 373 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 374 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 375 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 376 goto adma_done; 377 } 378 379 adma_done: 380 if (error) { 381 printf("%s: can't allocate DMA descriptor table\n", 382 DEVNAME(hp->sc)); 383 CLR(hp->flags, SHF_USE_DMA); 384 } 385 } 386 387 /* 388 * Attach the generic SD/MMC bus driver. (The bus driver must 389 * not invoke any chipset functions before it is attached.) 390 */ 391 bzero(&saa, sizeof(saa)); 392 saa.saa_busname = "sdmmc"; 393 saa.sct = &sdhc_functions; 394 saa.sch = hp; 395 saa.caps = SMC_CAPS_4BIT_MODE; 396 saa.dmat = sc->sc_dmat; 397 if (ISSET(hp->flags, SHF_USE_DMA)) 398 saa.caps |= SMC_CAPS_DMA; 399 400 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 401 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 402 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 403 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 404 405 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 406 uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 407 408 if (ISSET(caps, SDHC_8BIT_MODE_SUPP)) 409 saa.caps |= SMC_CAPS_8BIT_MODE; 410 411 if (ISSET(caps2, SDHC_DDR50_SUPP)) 412 saa.caps |= SMC_CAPS_MMC_DDR52; 413 } 414 415 if (ISSET(sc->sc_flags, SDHC_F_NODDR50)) 416 saa.caps &= ~SMC_CAPS_MMC_DDR52; 417 418 if (ISSET(sc->sc_flags, SDHC_F_NONREMOVABLE)) 419 saa.caps |= SMC_CAPS_NONREMOVABLE; 420 421 hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 422 if (hp->sdmmc == NULL) { 423 error = 0; 424 goto err; 425 } 426 427 return 0; 428 429 err: 430 free(hp, M_DEVBUF, sizeof *hp); 431 sc->sc_host[sc->sc_nhosts - 1] = NULL; 432 sc->sc_nhosts--; 433 return (error); 434 } 435 436 int 437 sdhc_activate(struct device *self, int act) 438 { 439 struct sdhc_softc *sc = (struct sdhc_softc *)self; 440 struct sdhc_host *hp; 441 int n, i, rv = 0; 442 443 switch (act) { 444 case DVACT_SUSPEND: 445 rv = config_activate_children(self, act); 446 447 /* Save the host controller state. */ 448 for (n = 0; n < sc->sc_nhosts; n++) { 449 hp = sc->sc_host[n]; 450 for (i = 0; i < sizeof hp->regs; i++) 451 hp->regs[i] = HREAD1(hp, i); 452 } 453 break; 454 case DVACT_RESUME: 455 /* Restore the host controller state. */ 456 for (n = 0; n < sc->sc_nhosts; n++) { 457 hp = sc->sc_host[n]; 458 (void)sdhc_host_reset(hp); 459 for (i = 0; i < sizeof hp->regs; i++) 460 HWRITE1(hp, i, hp->regs[i]); 461 } 462 rv = config_activate_children(self, act); 463 break; 464 case DVACT_POWERDOWN: 465 rv = config_activate_children(self, act); 466 sdhc_shutdown(self); 467 break; 468 default: 469 rv = config_activate_children(self, act); 470 break; 471 } 472 return (rv); 473 } 474 475 /* 476 * Shutdown hook established by or called from attachment driver. 477 */ 478 void 479 sdhc_shutdown(void *arg) 480 { 481 struct sdhc_softc *sc = arg; 482 struct sdhc_host *hp; 483 int i; 484 485 /* XXX chip locks up if we don't disable it before reboot. */ 486 for (i = 0; i < sc->sc_nhosts; i++) { 487 hp = sc->sc_host[i]; 488 (void)sdhc_host_reset(hp); 489 } 490 } 491 492 /* 493 * Reset the host controller. Called during initialization, when 494 * cards are removed, upon resume, and during error recovery. 495 */ 496 int 497 sdhc_host_reset(sdmmc_chipset_handle_t sch) 498 { 499 struct sdhc_host *hp = sch; 500 u_int16_t imask; 501 int error; 502 int s; 503 504 s = splsdmmc(); 505 506 /* Disable all interrupts. */ 507 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 508 509 /* 510 * Reset the entire host controller and wait up to 100ms for 511 * the controller to clear the reset bit. 512 */ 513 if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL)) != 0) { 514 splx(s); 515 return (error); 516 } 517 518 /* Set data timeout counter value to max for now. */ 519 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 520 521 /* Enable interrupts. */ 522 imask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 523 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 524 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 525 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 526 527 HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask); 528 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 529 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask); 530 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 531 532 splx(s); 533 return 0; 534 } 535 536 u_int32_t 537 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 538 { 539 struct sdhc_host *hp = sch; 540 return hp->ocr; 541 } 542 543 int 544 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 545 { 546 struct sdhc_host *hp = sch; 547 return hp->maxblklen; 548 } 549 550 /* 551 * Return non-zero if the card is currently inserted. 552 */ 553 int 554 sdhc_card_detect(sdmmc_chipset_handle_t sch) 555 { 556 struct sdhc_host *hp = sch; 557 558 if (hp->sc->sc_card_detect) 559 return hp->sc->sc_card_detect(hp->sc); 560 561 return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED) ? 562 1 : 0; 563 } 564 565 /* 566 * Set or change SD bus voltage and enable or disable SD bus power. 567 * Return zero on success. 568 */ 569 int 570 sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 571 { 572 struct sdhc_host *hp = sch; 573 u_int8_t vdd; 574 int s; 575 576 s = splsdmmc(); 577 578 /* 579 * Disable bus power before voltage change. 580 */ 581 if (!(hp->sc->sc_flags & SDHC_F_NOPWR0)) 582 HWRITE1(hp, SDHC_POWER_CTL, 0); 583 584 /* If power is disabled, reset the host and return now. */ 585 if (ocr == 0) { 586 splx(s); 587 (void)sdhc_host_reset(hp); 588 return 0; 589 } 590 591 /* 592 * Select the maximum voltage according to capabilities. 593 */ 594 ocr &= hp->ocr; 595 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 596 vdd = SDHC_VOLTAGE_3_3V; 597 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 598 vdd = SDHC_VOLTAGE_3_0V; 599 else if (ISSET(ocr, MMC_OCR_1_65V_1_95V)) 600 vdd = SDHC_VOLTAGE_1_8V; 601 else { 602 /* Unsupported voltage level requested. */ 603 splx(s); 604 return EINVAL; 605 } 606 607 /* 608 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 609 * voltage ramp until power rises. 610 */ 611 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) | 612 SDHC_BUS_POWER); 613 sdmmc_delay(10000); 614 615 /* 616 * The host system may not power the bus due to battery low, 617 * etc. In that case, the host controller should clear the 618 * bus power bit. 619 */ 620 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 621 splx(s); 622 return ENXIO; 623 } 624 625 splx(s); 626 return 0; 627 } 628 629 /* 630 * Return the smallest possible base clock frequency divisor value 631 * for the CLOCK_CTL register to produce `freq' (KHz). 632 */ 633 static int 634 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 635 { 636 int max_div = SDHC_SDCLK_DIV_MAX; 637 int div; 638 639 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) 640 max_div = SDHC_SDCLK_DIV_MAX_V3; 641 642 for (div = 1; div <= max_div; div *= 2) 643 if ((hp->clkbase / div) <= freq) 644 return (div / 2); 645 /* No divisor found. */ 646 return -1; 647 } 648 649 /* 650 * Set or change SDCLK frequency or disable the SD clock. 651 * Return zero on success. 652 */ 653 int 654 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 655 { 656 struct sdhc_host *hp = sch; 657 int s; 658 int div; 659 int sdclk; 660 int timo; 661 int error = 0; 662 663 s = splsdmmc(); 664 665 if (hp->sc->sc_bus_clock_pre) 666 hp->sc->sc_bus_clock_pre(hp->sc, freq, timing); 667 668 #ifdef DIAGNOSTIC 669 /* Must not stop the clock if commands are in progress. */ 670 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK) && 671 sdhc_card_detect(hp)) 672 printf("sdhc_sdclk_frequency_select: command in progress\n"); 673 #endif 674 675 /* 676 * Stop SD clock before changing the frequency. 677 */ 678 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 679 if (freq == SDMMC_SDCLK_OFF) 680 goto ret; 681 682 if (timing == SDMMC_TIMING_LEGACY) 683 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 684 else 685 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 686 687 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 688 switch (timing) { 689 case SDMMC_TIMING_MMC_DDR52: 690 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 691 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_DDR50); 692 break; 693 } 694 } 695 696 /* 697 * Set the minimum base clock frequency divisor. 698 */ 699 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 700 /* Invalid base clock frequency or `freq' value. */ 701 error = EINVAL; 702 goto ret; 703 } 704 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) 705 sdclk = SDHC_SDCLK_DIV_V3(div); 706 else 707 sdclk = SDHC_SDCLK_DIV(div); 708 HWRITE2(hp, SDHC_CLOCK_CTL, sdclk); 709 710 /* 711 * Start internal clock. Wait 10ms for stabilization. 712 */ 713 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 714 for (timo = 1000; timo > 0; timo--) { 715 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 716 break; 717 sdmmc_delay(10); 718 } 719 if (timo == 0) { 720 error = ETIMEDOUT; 721 goto ret; 722 } 723 724 /* 725 * Enable SD clock. 726 */ 727 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 728 729 if (hp->sc->sc_bus_clock_post) 730 hp->sc->sc_bus_clock_post(hp->sc, freq, timing); 731 732 ret: 733 splx(s); 734 return error; 735 } 736 737 int 738 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 739 { 740 struct sdhc_host *hp = (struct sdhc_host *)sch; 741 int reg; 742 int s; 743 744 if (width != 1 && width != 4 && width != 8) 745 return EINVAL; 746 747 s = splsdmmc(); 748 749 reg = HREAD1(hp, SDHC_HOST_CTL); 750 reg &= ~SDHC_4BIT_MODE; 751 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 752 reg &= ~SDHC_8BIT_MODE; 753 } 754 if (width == 4) { 755 reg |= SDHC_4BIT_MODE; 756 } else if (width == 8) { 757 KASSERT(SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3); 758 reg |= SDHC_8BIT_MODE; 759 } 760 HWRITE1(hp, SDHC_HOST_CTL, reg); 761 762 splx(s); 763 764 return 0; 765 } 766 767 void 768 sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 769 { 770 struct sdhc_host *hp = sch; 771 772 if (enable) { 773 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 774 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 775 } else { 776 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 777 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 778 } 779 } 780 781 void 782 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 783 { 784 struct sdhc_host *hp = sch; 785 786 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 787 } 788 789 int 790 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 791 { 792 struct sdhc_host *hp = sch; 793 794 if (hp->sc->sc_signal_voltage) 795 return hp->sc->sc_signal_voltage(hp->sc, signal_voltage); 796 797 if (SDHC_SPEC_VERSION(hp->version) < SDHC_SPEC_V3) 798 return EINVAL; 799 800 switch (signal_voltage) { 801 case SDMMC_SIGNAL_VOLTAGE_180: 802 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 803 break; 804 case SDMMC_SIGNAL_VOLTAGE_330: 805 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 806 break; 807 default: 808 return EINVAL; 809 } 810 811 /* Regulator output shall be stable within 5 ms. */ 812 sdmmc_delay(5000); 813 814 /* Host controller clears this bit if 1.8V signalling fails. */ 815 if (signal_voltage == SDMMC_SIGNAL_VOLTAGE_180 && 816 !ISSET(HREAD2(hp, SDHC_HOST_CTL2), SDHC_1_8V_SIGNAL_EN)) 817 return EIO; 818 819 return 0; 820 } 821 822 int 823 sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value) 824 { 825 u_int32_t state; 826 int timeout; 827 828 for (timeout = 10; timeout > 0; timeout--) { 829 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) 830 == value) 831 return 0; 832 sdmmc_delay(10000); 833 } 834 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(hp->sc), 835 value, state, SDHC_PRESENT_STATE_BITS)); 836 return ETIMEDOUT; 837 } 838 839 void 840 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 841 { 842 struct sdhc_host *hp = sch; 843 int error; 844 845 /* 846 * Start the MMC command, or mark `cmd' as failed and return. 847 */ 848 error = sdhc_start_command(hp, cmd); 849 if (error != 0) { 850 cmd->c_error = error; 851 SET(cmd->c_flags, SCF_ITSDONE); 852 return; 853 } 854 855 /* 856 * Wait until the command phase is done, or until the command 857 * is marked done for any other reason. 858 */ 859 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, 860 SDHC_COMMAND_TIMEOUT)) { 861 cmd->c_error = ETIMEDOUT; 862 SET(cmd->c_flags, SCF_ITSDONE); 863 return; 864 } 865 866 /* 867 * The host controller removes bits [0:7] from the response 868 * data (CRC) and we pass the data up unchanged to the bus 869 * driver (without padding). 870 */ 871 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 872 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 873 u_char *p = (u_char *)cmd->c_resp; 874 int i; 875 876 for (i = 0; i < 15; i++) 877 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 878 } else 879 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 880 } 881 882 /* 883 * If the command has data to transfer in any direction, 884 * execute the transfer now. 885 */ 886 if (cmd->c_error == 0 && cmd->c_data != NULL) 887 sdhc_transfer_data(hp, cmd); 888 889 /* Turn off the LED. */ 890 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 891 892 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n", 893 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 894 SET(cmd->c_flags, SCF_ITSDONE); 895 } 896 897 int 898 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 899 { 900 struct sdhc_adma2_descriptor32 *desc32 = (void *)hp->adma2; 901 struct sdhc_adma2_descriptor64 *desc64 = (void *)hp->adma2; 902 struct sdhc_softc *sc = hp->sc; 903 u_int16_t blksize = 0; 904 u_int16_t blkcount = 0; 905 u_int16_t mode; 906 u_int16_t command; 907 int error; 908 int seg; 909 int s; 910 911 DPRINTF(1,("%s: start cmd %u arg=%#x data=%p dlen=%d flags=%#x\n", 912 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, cmd->c_data, 913 cmd->c_datalen, cmd->c_flags)); 914 915 /* 916 * The maximum block length for commands should be the minimum 917 * of the host buffer size and the card buffer size. (1.7.2) 918 */ 919 920 /* Fragment the data into proper blocks. */ 921 if (cmd->c_datalen > 0) { 922 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 923 blkcount = cmd->c_datalen / blksize; 924 if (cmd->c_datalen % blksize > 0) { 925 /* XXX: Split this command. (1.7.4) */ 926 printf("%s: data not a multiple of %d bytes\n", 927 DEVNAME(hp->sc), blksize); 928 return EINVAL; 929 } 930 } 931 932 /* Check limit imposed by 9-bit block count. (1.7.2) */ 933 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 934 printf("%s: too much data\n", DEVNAME(hp->sc)); 935 return EINVAL; 936 } 937 938 /* Prepare transfer mode register value. (2.2.5) */ 939 mode = 0; 940 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 941 mode |= SDHC_READ_MODE; 942 if (blkcount > 0) { 943 mode |= SDHC_BLOCK_COUNT_ENABLE; 944 if (blkcount > 1) { 945 mode |= SDHC_MULTI_BLOCK_MODE; 946 if (cmd->c_opcode != SD_IO_RW_EXTENDED) 947 mode |= SDHC_AUTO_CMD12_ENABLE; 948 } 949 } 950 if (cmd->c_dmamap && cmd->c_datalen > 0 && 951 ISSET(hp->flags, SHF_USE_DMA)) 952 mode |= SDHC_DMA_ENABLE; 953 954 /* 955 * Prepare command register value. (2.2.6) 956 */ 957 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << 958 SDHC_COMMAND_INDEX_SHIFT; 959 960 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 961 command |= SDHC_CRC_CHECK_ENABLE; 962 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 963 command |= SDHC_INDEX_CHECK_ENABLE; 964 if (cmd->c_data != NULL) 965 command |= SDHC_DATA_PRESENT_SELECT; 966 967 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 968 command |= SDHC_NO_RESPONSE; 969 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 970 command |= SDHC_RESP_LEN_136; 971 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 972 command |= SDHC_RESP_LEN_48_CHK_BUSY; 973 else 974 command |= SDHC_RESP_LEN_48; 975 976 /* Wait until command and data inhibit bits are clear. (1.5) */ 977 if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0)) != 0) 978 return error; 979 980 s = splsdmmc(); 981 982 /* Alert the user not to remove the card. */ 983 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 984 985 /* Set DMA start address if SHF_USE_DMA is set. */ 986 if (cmd->c_dmamap && ISSET(hp->flags, SHF_USE_DMA)) { 987 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 988 bus_addr_t paddr = 989 cmd->c_dmamap->dm_segs[seg].ds_addr; 990 uint16_t len = 991 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 992 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 993 uint16_t attr; 994 995 attr = SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 996 if (seg == cmd->c_dmamap->dm_nsegs - 1) 997 attr |= SDHC_ADMA2_END; 998 999 if (ISSET(hp->flags, SHF_USE_DMA64)) { 1000 desc64[seg].attribute = htole16(attr); 1001 desc64[seg].length = htole16(len); 1002 desc64[seg].address_lo = 1003 htole32((uint64_t)paddr & 0xffffffff); 1004 desc64[seg].address_hi = 1005 htole32((uint64_t)paddr >> 32); 1006 } else { 1007 desc32[seg].attribute = htole16(attr); 1008 desc32[seg].length = htole16(len); 1009 desc32[seg].address = htole32(paddr); 1010 } 1011 } 1012 1013 if (ISSET(hp->flags, SHF_USE_DMA64)) 1014 desc64[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1015 else 1016 desc32[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1017 1018 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1019 BUS_DMASYNC_PREWRITE); 1020 1021 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1022 if (ISSET(hp->flags, SHF_USE_DMA64)) 1023 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA64); 1024 else 1025 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA32); 1026 1027 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, 1028 hp->adma_map->dm_segs[0].ds_addr); 1029 } else 1030 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1031 1032 DPRINTF(1,("%s: cmd=%#x mode=%#x blksize=%d blkcount=%d\n", 1033 DEVNAME(hp->sc), command, mode, blksize, blkcount)); 1034 1035 /* 1036 * Start a CPU data transfer. Writing to the high order byte 1037 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1038 */ 1039 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1040 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1041 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1042 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1043 HWRITE2(hp, SDHC_COMMAND, command); 1044 1045 splx(s); 1046 return 0; 1047 } 1048 1049 void 1050 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1051 { 1052 struct sdhc_softc *sc = hp->sc; 1053 u_char *datap = cmd->c_data; 1054 int i, datalen; 1055 int mask; 1056 int error; 1057 1058 if (cmd->c_dmamap) { 1059 int status; 1060 1061 error = 0; 1062 for (;;) { 1063 status = sdhc_wait_intr(hp, 1064 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1065 SDHC_DMA_TIMEOUT); 1066 if (status & SDHC_TRANSFER_COMPLETE) 1067 break; 1068 if (!status) { 1069 error = ETIMEDOUT; 1070 break; 1071 } 1072 } 1073 1074 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1075 BUS_DMASYNC_POSTWRITE); 1076 goto done; 1077 } 1078 1079 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 1080 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 1081 error = 0; 1082 datalen = cmd->c_datalen; 1083 1084 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(hp->sc), 1085 MMC_R1(cmd->c_resp), datalen)); 1086 1087 #ifdef SDHC_DEBUG 1088 /* XXX I forgot why I wanted to know when this happens :-( */ 1089 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1090 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) 1091 printf("%s: CMD52/53 error response flags %#x\n", 1092 DEVNAME(hp->sc), MMC_R1(cmd->c_resp) & 0xff00); 1093 #endif 1094 1095 while (datalen > 0) { 1096 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY| 1097 SDHC_BUFFER_WRITE_READY, SDHC_BUFFER_TIMEOUT)) { 1098 error = ETIMEDOUT; 1099 break; 1100 } 1101 1102 if ((error = sdhc_wait_state(hp, mask, mask)) != 0) 1103 break; 1104 1105 i = MIN(datalen, cmd->c_blklen); 1106 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1107 sdhc_read_data(hp, datap, i); 1108 else 1109 sdhc_write_data(hp, datap, i); 1110 1111 datap += i; 1112 datalen -= i; 1113 } 1114 1115 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1116 SDHC_TRANSFER_TIMEOUT)) 1117 error = ETIMEDOUT; 1118 1119 done: 1120 if (error != 0) 1121 cmd->c_error = error; 1122 SET(cmd->c_flags, SCF_ITSDONE); 1123 1124 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1125 DEVNAME(hp->sc), cmd->c_error)); 1126 } 1127 1128 void 1129 sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen) 1130 { 1131 while (datalen > 3) { 1132 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA); 1133 datap += 4; 1134 datalen -= 4; 1135 } 1136 if (datalen > 0) { 1137 u_int32_t rv = HREAD4(hp, SDHC_DATA); 1138 do { 1139 *datap++ = rv & 0xff; 1140 rv = rv >> 8; 1141 } while (--datalen > 0); 1142 } 1143 } 1144 1145 void 1146 sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen) 1147 { 1148 while (datalen > 3) { 1149 DPRINTF(3,("%08x\n", *(u_int32_t *)datap)); 1150 HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap)); 1151 datap += 4; 1152 datalen -= 4; 1153 } 1154 if (datalen > 0) { 1155 u_int32_t rv = *datap++; 1156 if (datalen > 1) 1157 rv |= *datap++ << 8; 1158 if (datalen > 2) 1159 rv |= *datap++ << 16; 1160 DPRINTF(3,("rv %08x\n", rv)); 1161 HWRITE4(hp, SDHC_DATA, rv); 1162 } 1163 } 1164 1165 /* Prepare for another command. */ 1166 int 1167 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1168 { 1169 int timo; 1170 1171 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask)); 1172 1173 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1174 for (timo = 10; timo > 0; timo--) { 1175 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1176 break; 1177 sdmmc_delay(10000); 1178 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1179 } 1180 if (timo == 0) { 1181 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(hp->sc), 1182 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1183 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1184 return (ETIMEDOUT); 1185 } 1186 1187 return (0); 1188 } 1189 1190 int 1191 sdhc_wait_intr_cold(struct sdhc_host *hp, int mask, int secs) 1192 { 1193 int status, usecs; 1194 1195 mask |= SDHC_ERROR_INTERRUPT; 1196 usecs = secs * 1000000; 1197 status = hp->intr_status; 1198 while ((status & mask) == 0) { 1199 1200 status = HREAD2(hp, SDHC_NINTR_STATUS); 1201 if (ISSET(status, SDHC_NINTR_STATUS_MASK)) { 1202 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1203 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1204 uint16_t error; 1205 error = HREAD2(hp, SDHC_EINTR_STATUS); 1206 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1207 hp->intr_status |= status; 1208 1209 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1210 SDHC_DATA_TIMEOUT_ERROR)) 1211 break; 1212 } 1213 1214 if (ISSET(status, SDHC_BUFFER_READ_READY | 1215 SDHC_BUFFER_WRITE_READY | SDHC_COMMAND_COMPLETE | 1216 SDHC_TRANSFER_COMPLETE)) { 1217 hp->intr_status |= status; 1218 break; 1219 } 1220 1221 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1222 HSET2(hp, SDHC_NINTR_STATUS_EN, 1223 SDHC_CARD_INTERRUPT); 1224 } 1225 1226 continue; 1227 } 1228 1229 delay(1); 1230 if (usecs-- == 0) { 1231 status |= SDHC_ERROR_INTERRUPT; 1232 break; 1233 } 1234 } 1235 1236 hp->intr_status &= ~(status & mask); 1237 return (status & mask); 1238 } 1239 1240 int 1241 sdhc_wait_intr(struct sdhc_host *hp, int mask, int secs) 1242 { 1243 int status; 1244 int s; 1245 1246 if (cold) 1247 return (sdhc_wait_intr_cold(hp, mask, secs)); 1248 1249 mask |= SDHC_ERROR_INTERRUPT; 1250 1251 s = splsdmmc(); 1252 status = hp->intr_status & mask; 1253 while (status == 0) { 1254 if (tsleep_nsec(&hp->intr_status, PWAIT, "hcintr", 1255 SEC_TO_NSEC(secs)) == EWOULDBLOCK) { 1256 status |= SDHC_ERROR_INTERRUPT; 1257 break; 1258 } 1259 status = hp->intr_status & mask; 1260 } 1261 hp->intr_status &= ~status; 1262 1263 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status, 1264 hp->intr_error_status)); 1265 1266 /* Command timeout has higher priority than command complete. */ 1267 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1268 hp->intr_error_status = 0; 1269 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1270 status = 0; 1271 } 1272 1273 splx(s); 1274 return status; 1275 } 1276 1277 /* 1278 * Established by attachment driver at interrupt priority IPL_SDMMC. 1279 */ 1280 int 1281 sdhc_intr(void *arg) 1282 { 1283 struct sdhc_softc *sc = arg; 1284 int host; 1285 int done = 0; 1286 1287 /* We got an interrupt, but we don't know from which slot. */ 1288 for (host = 0; host < sc->sc_nhosts; host++) { 1289 struct sdhc_host *hp = sc->sc_host[host]; 1290 u_int16_t status; 1291 1292 if (hp == NULL) 1293 continue; 1294 1295 /* Find out which interrupts are pending. */ 1296 status = HREAD2(hp, SDHC_NINTR_STATUS); 1297 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1298 continue; /* no interrupt for us */ 1299 1300 /* Acknowledge the interrupts we are about to handle. */ 1301 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1302 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(hp->sc), 1303 status, SDHC_NINTR_STATUS_BITS)); 1304 1305 /* Claim this interrupt. */ 1306 done = 1; 1307 1308 /* 1309 * Service error interrupts. 1310 */ 1311 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1312 u_int16_t error; 1313 1314 /* Acknowledge error interrupts. */ 1315 error = HREAD2(hp, SDHC_EINTR_STATUS); 1316 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1317 DPRINTF(2,("%s: error interrupt, status=%b\n", 1318 DEVNAME(hp->sc), error, SDHC_EINTR_STATUS_BITS)); 1319 1320 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1321 SDHC_DATA_TIMEOUT_ERROR)) { 1322 hp->intr_error_status |= error; 1323 hp->intr_status |= status; 1324 wakeup(&hp->intr_status); 1325 } 1326 } 1327 1328 /* 1329 * Wake up the sdmmc event thread to scan for cards. 1330 */ 1331 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1332 sdmmc_needs_discover(hp->sdmmc); 1333 1334 /* 1335 * Wake up the blocking process to service command 1336 * related interrupt(s). 1337 */ 1338 if (ISSET(status, SDHC_BUFFER_READ_READY| 1339 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 1340 SDHC_TRANSFER_COMPLETE)) { 1341 hp->intr_status |= status; 1342 wakeup(&hp->intr_status); 1343 } 1344 1345 /* 1346 * Service SD card interrupts. 1347 */ 1348 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1349 DPRINTF(0,("%s: card interrupt\n", DEVNAME(hp->sc))); 1350 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1351 sdmmc_card_intr(hp->sdmmc); 1352 } 1353 } 1354 return done; 1355 } 1356 1357 void 1358 sdhc_needs_discover(struct sdhc_softc *sc) 1359 { 1360 int host; 1361 1362 for (host = 0; host < sc->sc_nhosts; host++) 1363 sdmmc_needs_discover(sc->sc_host[host]->sdmmc); 1364 } 1365 1366 #ifdef SDHC_DEBUG 1367 void 1368 sdhc_dump_regs(struct sdhc_host *hp) 1369 { 1370 printf("0x%02x PRESENT_STATE: %b\n", SDHC_PRESENT_STATE, 1371 HREAD4(hp, SDHC_PRESENT_STATE), SDHC_PRESENT_STATE_BITS); 1372 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1373 HREAD1(hp, SDHC_POWER_CTL)); 1374 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1375 HREAD2(hp, SDHC_NINTR_STATUS)); 1376 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1377 HREAD2(hp, SDHC_EINTR_STATUS)); 1378 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1379 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1380 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1381 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1382 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1383 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1384 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1385 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1386 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1387 HREAD4(hp, SDHC_CAPABILITIES)); 1388 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1389 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1390 } 1391 #endif 1392 1393 int 1394 sdhc_hibernate_init(sdmmc_chipset_handle_t sch, void *fake_softc) 1395 { 1396 struct sdhc_host *hp, *fhp; 1397 fhp = fake_softc; 1398 hp = sch; 1399 *fhp = *hp; 1400 1401 return (0); 1402 } 1403