1 /* $OpenBSD: sdhc.c,v 1.62 2019/04/02 07:08:40 stsp Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * SD Host Controller driver based on the SD Host Controller Standard 21 * Simplified Specification Version 1.00 (www.sdcard.com). 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/malloc.h> 28 #include <sys/proc.h> 29 #include <sys/systm.h> 30 31 #include <dev/sdmmc/sdhcreg.h> 32 #include <dev/sdmmc/sdhcvar.h> 33 #include <dev/sdmmc/sdmmcchip.h> 34 #include <dev/sdmmc/sdmmcreg.h> 35 #include <dev/sdmmc/sdmmcvar.h> 36 #include <dev/sdmmc/sdmmc_ioreg.h> 37 38 #define SDHC_COMMAND_TIMEOUT hz 39 #define SDHC_BUFFER_TIMEOUT hz 40 #define SDHC_TRANSFER_TIMEOUT hz 41 #define SDHC_DMA_TIMEOUT (hz*3) 42 43 struct sdhc_host { 44 struct sdhc_softc *sc; /* host controller device */ 45 struct device *sdmmc; /* generic SD/MMC device */ 46 bus_space_tag_t iot; /* host register set tag */ 47 bus_space_handle_t ioh; /* host register set handle */ 48 u_int16_t version; /* specification version */ 49 u_int clkbase; /* base clock frequency in KHz */ 50 int maxblklen; /* maximum block length */ 51 int flags; /* flags for this host */ 52 u_int32_t ocr; /* OCR value from capabilities */ 53 u_int8_t regs[14]; /* host controller state */ 54 u_int16_t intr_status; /* soft interrupt status */ 55 u_int16_t intr_error_status; /* soft error status */ 56 57 bus_dmamap_t adma_map; 58 bus_dma_segment_t adma_segs[1]; 59 caddr_t adma2; 60 }; 61 62 /* flag values */ 63 #define SHF_USE_DMA 0x0001 64 #define SHF_USE_DMA64 0x0002 65 66 #define HREAD1(hp, reg) \ 67 (bus_space_read_1((hp)->iot, (hp)->ioh, (reg))) 68 #define HREAD2(hp, reg) \ 69 (bus_space_read_2((hp)->iot, (hp)->ioh, (reg))) 70 #define HREAD4(hp, reg) \ 71 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 72 #define HWRITE1(hp, reg, val) \ 73 bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val)) 74 #define HWRITE2(hp, reg, val) \ 75 bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val)) 76 #define HWRITE4(hp, reg, val) \ 77 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 78 #define HCLR1(hp, reg, bits) \ 79 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 80 #define HCLR2(hp, reg, bits) \ 81 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 82 #define HSET1(hp, reg, bits) \ 83 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 84 #define HSET2(hp, reg, bits) \ 85 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 86 87 int sdhc_host_reset(sdmmc_chipset_handle_t); 88 u_int32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 89 int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 90 int sdhc_card_detect(sdmmc_chipset_handle_t); 91 int sdhc_bus_power(sdmmc_chipset_handle_t, u_int32_t); 92 int sdhc_bus_clock(sdmmc_chipset_handle_t, int, int); 93 int sdhc_bus_width(sdmmc_chipset_handle_t, int); 94 void sdhc_card_intr_mask(sdmmc_chipset_handle_t, int); 95 void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 96 int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 97 void sdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 98 int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 99 int sdhc_wait_state(struct sdhc_host *, u_int32_t, u_int32_t); 100 int sdhc_soft_reset(struct sdhc_host *, int); 101 int sdhc_wait_intr_cold(struct sdhc_host *, int, int); 102 int sdhc_wait_intr(struct sdhc_host *, int, int); 103 void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 104 void sdhc_read_data(struct sdhc_host *, u_char *, int); 105 void sdhc_write_data(struct sdhc_host *, u_char *, int); 106 int sdhc_hibernate_init(sdmmc_chipset_handle_t, void *); 107 108 #ifdef SDHC_DEBUG 109 int sdhcdebug = 0; 110 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 111 void sdhc_dump_regs(struct sdhc_host *); 112 #else 113 #define DPRINTF(n,s) do {} while(0) 114 #endif 115 116 struct sdmmc_chip_functions sdhc_functions = { 117 /* host controller reset */ 118 sdhc_host_reset, 119 /* host controller capabilities */ 120 sdhc_host_ocr, 121 sdhc_host_maxblklen, 122 /* card detection */ 123 sdhc_card_detect, 124 /* bus power and clock frequency */ 125 sdhc_bus_power, 126 sdhc_bus_clock, 127 sdhc_bus_width, 128 /* command execution */ 129 sdhc_exec_command, 130 /* card interrupt */ 131 sdhc_card_intr_mask, 132 sdhc_card_intr_ack, 133 /* UHS functions */ 134 sdhc_signal_voltage, 135 /* hibernate */ 136 sdhc_hibernate_init, 137 }; 138 139 struct cfdriver sdhc_cd = { 140 NULL, "sdhc", DV_DULL 141 }; 142 143 /* 144 * Called by attachment driver. For each SD card slot there is one SD 145 * host controller standard register set. (1.3) 146 */ 147 int 148 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 149 bus_space_handle_t ioh, bus_size_t iosize, int usedma, u_int32_t caps) 150 { 151 struct sdmmcbus_attach_args saa; 152 struct sdhc_host *hp; 153 int error = 1; 154 int max_clock; 155 #ifdef SDHC_DEBUG 156 u_int16_t version; 157 158 version = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 159 printf("%s: SD Host Specification/Vendor Version ", 160 sc->sc_dev.dv_xname); 161 switch(SDHC_SPEC_VERSION(version)) { 162 case 0x00: 163 printf("1.0/%u\n", SDHC_VENDOR_VERSION(version)); 164 break; 165 default: 166 printf(">1.0/%u\n", SDHC_VENDOR_VERSION(version)); 167 break; 168 } 169 #endif 170 171 /* Allocate one more host structure. */ 172 sc->sc_nhosts++; 173 hp = malloc(sizeof(*hp), M_DEVBUF, M_WAITOK | M_ZERO); 174 sc->sc_host[sc->sc_nhosts - 1] = hp; 175 176 /* Fill in the new host structure. */ 177 hp->sc = sc; 178 hp->iot = iot; 179 hp->ioh = ioh; 180 181 /* Store specification version. */ 182 hp->version = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 183 184 /* 185 * Reset the host controller and enable interrupts. 186 */ 187 (void)sdhc_host_reset(hp); 188 189 /* Determine host capabilities. */ 190 if (caps == 0) 191 caps = HREAD4(hp, SDHC_CAPABILITIES); 192 193 /* Use DMA if the host system and the controller support it. */ 194 if (usedma && ISSET(caps, SDHC_ADMA2_SUPP)) { 195 SET(hp->flags, SHF_USE_DMA); 196 if (ISSET(caps, SDHC_64BIT_DMA_SUPP)) 197 SET(hp->flags, SHF_USE_DMA64); 198 } 199 200 /* 201 * Determine the base clock frequency. (2.2.24) 202 */ 203 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 204 /* SDHC 3.0 supports 10-255 MHz. */ 205 max_clock = 255000; 206 if (SDHC_BASE_FREQ_KHZ_V3(caps) != 0) 207 hp->clkbase = SDHC_BASE_FREQ_KHZ_V3(caps); 208 } else { 209 /* SDHC 1.0/2.0 supports only 10-63 MHz. */ 210 max_clock = 63000; 211 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 212 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 213 } 214 if (hp->clkbase == 0) { 215 /* Make sure we can clock down to 400 kHz. */ 216 max_clock = 400 * SDHC_SDCLK_DIV_MAX_V3; 217 hp->clkbase = sc->sc_clkbase; 218 } 219 if (hp->clkbase == 0) { 220 /* The attachment driver must tell us. */ 221 printf("%s: base clock frequency unknown\n", 222 sc->sc_dev.dv_xname); 223 goto err; 224 } else if (hp->clkbase < 10000 || hp->clkbase > max_clock) { 225 printf("%s: base clock frequency out of range: %u MHz\n", 226 sc->sc_dev.dv_xname, hp->clkbase / 1000); 227 goto err; 228 } 229 230 printf("%s: SDHC %d.0, %d MHz base clock\n", DEVNAME(sc), 231 SDHC_SPEC_VERSION(hp->version) + 1, hp->clkbase / 1000); 232 233 /* 234 * XXX Set the data timeout counter value according to 235 * capabilities. (2.2.15) 236 */ 237 238 /* 239 * Determine SD bus voltage levels supported by the controller. 240 */ 241 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 242 SET(hp->ocr, MMC_OCR_1_65V_1_95V); 243 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 244 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 245 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 246 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 247 248 /* 249 * Determine the maximum block length supported by the host 250 * controller. (2.2.24) 251 */ 252 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 253 case SDHC_MAX_BLK_LEN_512: 254 hp->maxblklen = 512; 255 break; 256 case SDHC_MAX_BLK_LEN_1024: 257 hp->maxblklen = 1024; 258 break; 259 case SDHC_MAX_BLK_LEN_2048: 260 hp->maxblklen = 2048; 261 break; 262 default: 263 hp->maxblklen = 1; 264 break; 265 } 266 267 if (ISSET(hp->flags, SHF_USE_DMA)) { 268 int rseg; 269 270 /* Allocate ADMA2 descriptor memory */ 271 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 272 PAGE_SIZE, hp->adma_segs, 1, &rseg, 273 BUS_DMA_WAITOK | BUS_DMA_ZERO); 274 if (error) 275 goto adma_done; 276 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 277 PAGE_SIZE, &hp->adma2, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 278 if (error) { 279 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 280 goto adma_done; 281 } 282 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 283 0, BUS_DMA_WAITOK, &hp->adma_map); 284 if (error) { 285 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 286 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 287 goto adma_done; 288 } 289 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 290 hp->adma2, PAGE_SIZE, NULL, 291 BUS_DMA_WAITOK | BUS_DMA_WRITE); 292 if (error) { 293 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 294 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 295 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg); 296 goto adma_done; 297 } 298 299 adma_done: 300 if (error) { 301 printf("%s: can't allocate DMA descriptor table\n", 302 DEVNAME(hp->sc)); 303 CLR(hp->flags, SHF_USE_DMA); 304 } 305 } 306 307 /* 308 * Attach the generic SD/MMC bus driver. (The bus driver must 309 * not invoke any chipset functions before it is attached.) 310 */ 311 bzero(&saa, sizeof(saa)); 312 saa.saa_busname = "sdmmc"; 313 saa.sct = &sdhc_functions; 314 saa.sch = hp; 315 saa.caps = SMC_CAPS_4BIT_MODE; 316 saa.dmat = sc->sc_dmat; 317 if (ISSET(hp->flags, SHF_USE_DMA)) 318 saa.caps |= SMC_CAPS_DMA; 319 320 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 321 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 322 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 323 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 324 325 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 326 uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 327 328 if (ISSET(caps, SDHC_8BIT_MODE_SUPP)) 329 saa.caps |= SMC_CAPS_8BIT_MODE; 330 331 if (ISSET(caps2, SDHC_DDR50_SUPP)) 332 saa.caps |= SMC_CAPS_MMC_DDR52; 333 } 334 335 if (ISSET(sc->sc_flags, SDHC_F_NODDR50)) 336 saa.caps &= ~SMC_CAPS_MMC_DDR52; 337 338 if (ISSET(sc->sc_flags, SDHC_F_NONREMOVABLE)) 339 saa.caps |= SMC_CAPS_NONREMOVABLE; 340 341 hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 342 if (hp->sdmmc == NULL) { 343 error = 0; 344 goto err; 345 } 346 347 return 0; 348 349 err: 350 free(hp, M_DEVBUF, sizeof *hp); 351 sc->sc_host[sc->sc_nhosts - 1] = NULL; 352 sc->sc_nhosts--; 353 return (error); 354 } 355 356 int 357 sdhc_activate(struct device *self, int act) 358 { 359 struct sdhc_softc *sc = (struct sdhc_softc *)self; 360 struct sdhc_host *hp; 361 int n, i, rv = 0; 362 363 switch (act) { 364 case DVACT_SUSPEND: 365 rv = config_activate_children(self, act); 366 367 /* Save the host controller state. */ 368 for (n = 0; n < sc->sc_nhosts; n++) { 369 hp = sc->sc_host[n]; 370 for (i = 0; i < sizeof hp->regs; i++) 371 hp->regs[i] = HREAD1(hp, i); 372 } 373 break; 374 case DVACT_RESUME: 375 /* Restore the host controller state. */ 376 for (n = 0; n < sc->sc_nhosts; n++) { 377 hp = sc->sc_host[n]; 378 (void)sdhc_host_reset(hp); 379 for (i = 0; i < sizeof hp->regs; i++) 380 HWRITE1(hp, i, hp->regs[i]); 381 } 382 rv = config_activate_children(self, act); 383 break; 384 case DVACT_POWERDOWN: 385 rv = config_activate_children(self, act); 386 sdhc_shutdown(self); 387 break; 388 default: 389 rv = config_activate_children(self, act); 390 break; 391 } 392 return (rv); 393 } 394 395 /* 396 * Shutdown hook established by or called from attachment driver. 397 */ 398 void 399 sdhc_shutdown(void *arg) 400 { 401 struct sdhc_softc *sc = arg; 402 struct sdhc_host *hp; 403 int i; 404 405 /* XXX chip locks up if we don't disable it before reboot. */ 406 for (i = 0; i < sc->sc_nhosts; i++) { 407 hp = sc->sc_host[i]; 408 (void)sdhc_host_reset(hp); 409 } 410 } 411 412 /* 413 * Reset the host controller. Called during initialization, when 414 * cards are removed, upon resume, and during error recovery. 415 */ 416 int 417 sdhc_host_reset(sdmmc_chipset_handle_t sch) 418 { 419 struct sdhc_host *hp = sch; 420 u_int16_t imask; 421 int error; 422 int s; 423 424 s = splsdmmc(); 425 426 /* Disable all interrupts. */ 427 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 428 429 /* 430 * Reset the entire host controller and wait up to 100ms for 431 * the controller to clear the reset bit. 432 */ 433 if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL)) != 0) { 434 splx(s); 435 return (error); 436 } 437 438 /* Set data timeout counter value to max for now. */ 439 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 440 441 /* Enable interrupts. */ 442 imask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 443 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 444 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 445 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 446 447 HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask); 448 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 449 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask); 450 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 451 452 splx(s); 453 return 0; 454 } 455 456 u_int32_t 457 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 458 { 459 struct sdhc_host *hp = sch; 460 return hp->ocr; 461 } 462 463 int 464 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 465 { 466 struct sdhc_host *hp = sch; 467 return hp->maxblklen; 468 } 469 470 /* 471 * Return non-zero if the card is currently inserted. 472 */ 473 int 474 sdhc_card_detect(sdmmc_chipset_handle_t sch) 475 { 476 struct sdhc_host *hp = sch; 477 478 if (hp->sc->sc_card_detect) 479 return hp->sc->sc_card_detect(hp->sc); 480 481 return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED) ? 482 1 : 0; 483 } 484 485 /* 486 * Set or change SD bus voltage and enable or disable SD bus power. 487 * Return zero on success. 488 */ 489 int 490 sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 491 { 492 struct sdhc_host *hp = sch; 493 u_int8_t vdd; 494 int s; 495 496 s = splsdmmc(); 497 498 /* 499 * Disable bus power before voltage change. 500 */ 501 if (!(hp->sc->sc_flags & SDHC_F_NOPWR0)) 502 HWRITE1(hp, SDHC_POWER_CTL, 0); 503 504 /* If power is disabled, reset the host and return now. */ 505 if (ocr == 0) { 506 splx(s); 507 (void)sdhc_host_reset(hp); 508 return 0; 509 } 510 511 /* 512 * Select the maximum voltage according to capabilities. 513 */ 514 ocr &= hp->ocr; 515 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 516 vdd = SDHC_VOLTAGE_3_3V; 517 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 518 vdd = SDHC_VOLTAGE_3_0V; 519 else if (ISSET(ocr, MMC_OCR_1_65V_1_95V)) 520 vdd = SDHC_VOLTAGE_1_8V; 521 else { 522 /* Unsupported voltage level requested. */ 523 splx(s); 524 return EINVAL; 525 } 526 527 /* 528 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 529 * voltage ramp until power rises. 530 */ 531 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) | 532 SDHC_BUS_POWER); 533 sdmmc_delay(10000); 534 535 /* 536 * The host system may not power the bus due to battery low, 537 * etc. In that case, the host controller should clear the 538 * bus power bit. 539 */ 540 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 541 splx(s); 542 return ENXIO; 543 } 544 545 splx(s); 546 return 0; 547 } 548 549 /* 550 * Return the smallest possible base clock frequency divisor value 551 * for the CLOCK_CTL register to produce `freq' (KHz). 552 */ 553 static int 554 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 555 { 556 int max_div = SDHC_SDCLK_DIV_MAX;; 557 int div; 558 559 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) 560 max_div = SDHC_SDCLK_DIV_MAX_V3;; 561 562 for (div = 1; div <= max_div; div *= 2) 563 if ((hp->clkbase / div) <= freq) 564 return (div / 2); 565 /* No divisor found. */ 566 return -1; 567 } 568 569 /* 570 * Set or change SDCLK frequency or disable the SD clock. 571 * Return zero on success. 572 */ 573 int 574 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 575 { 576 struct sdhc_host *hp = sch; 577 int s; 578 int div; 579 int sdclk; 580 int timo; 581 int error = 0; 582 583 s = splsdmmc(); 584 585 #ifdef DIAGNOSTIC 586 /* Must not stop the clock if commands are in progress. */ 587 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK) && 588 sdhc_card_detect(hp)) 589 printf("sdhc_sdclk_frequency_select: command in progress\n"); 590 #endif 591 592 /* 593 * Stop SD clock before changing the frequency. 594 */ 595 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 596 if (freq == SDMMC_SDCLK_OFF) 597 goto ret; 598 599 if (timing == SDMMC_TIMING_LEGACY) 600 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 601 else 602 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 603 604 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 605 switch (timing) { 606 case SDMMC_TIMING_MMC_DDR52: 607 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 608 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_DDR50); 609 break; 610 } 611 } 612 613 /* 614 * Set the minimum base clock frequency divisor. 615 */ 616 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 617 /* Invalid base clock frequency or `freq' value. */ 618 error = EINVAL; 619 goto ret; 620 } 621 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) 622 sdclk = SDHC_SDCLK_DIV_V3(div); 623 else 624 sdclk = SDHC_SDCLK_DIV(div); 625 HWRITE2(hp, SDHC_CLOCK_CTL, sdclk); 626 627 /* 628 * Start internal clock. Wait 10ms for stabilization. 629 */ 630 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 631 for (timo = 1000; timo > 0; timo--) { 632 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 633 break; 634 sdmmc_delay(10); 635 } 636 if (timo == 0) { 637 error = ETIMEDOUT; 638 goto ret; 639 } 640 641 /* 642 * Enable SD clock. 643 */ 644 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 645 646 ret: 647 splx(s); 648 return error; 649 } 650 651 int 652 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 653 { 654 struct sdhc_host *hp = (struct sdhc_host *)sch; 655 int reg; 656 int s; 657 658 if (width != 1 && width != 4 && width != 8) 659 return EINVAL; 660 661 s = splsdmmc(); 662 663 reg = HREAD1(hp, SDHC_HOST_CTL); 664 reg &= ~SDHC_4BIT_MODE; 665 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) { 666 reg &= ~SDHC_8BIT_MODE; 667 } 668 if (width == 4) { 669 reg |= SDHC_4BIT_MODE; 670 } else if (width == 8) { 671 KASSERT(SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3); 672 reg |= SDHC_8BIT_MODE; 673 } 674 HWRITE1(hp, SDHC_HOST_CTL, reg); 675 676 splx(s); 677 678 return 0; 679 } 680 681 void 682 sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 683 { 684 struct sdhc_host *hp = sch; 685 686 if (enable) { 687 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 688 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 689 } else { 690 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 691 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 692 } 693 } 694 695 void 696 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 697 { 698 struct sdhc_host *hp = sch; 699 700 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 701 } 702 703 int 704 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 705 { 706 struct sdhc_host *hp = sch; 707 708 if (hp->sc->sc_signal_voltage) 709 return hp->sc->sc_signal_voltage(hp->sc, signal_voltage); 710 711 if (SDHC_SPEC_VERSION(hp->version) < SDHC_SPEC_V3) 712 return EINVAL; 713 714 switch (signal_voltage) { 715 case SDMMC_SIGNAL_VOLTAGE_180: 716 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 717 break; 718 case SDMMC_SIGNAL_VOLTAGE_330: 719 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 720 break; 721 default: 722 return EINVAL; 723 } 724 725 /* Regulator output shall be stable within 5 ms. */ 726 sdmmc_delay(5000); 727 728 /* Host controller clears this bit if 1.8V signalling fails. */ 729 if (signal_voltage == SDMMC_SIGNAL_VOLTAGE_180 && 730 !ISSET(HREAD4(hp, SDHC_HOST_CTL2), SDHC_1_8V_SIGNAL_EN)) 731 return EIO; 732 733 return 0; 734 } 735 736 int 737 sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value) 738 { 739 u_int32_t state; 740 int timeout; 741 742 for (timeout = 10; timeout > 0; timeout--) { 743 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) 744 == value) 745 return 0; 746 sdmmc_delay(10000); 747 } 748 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(hp->sc), 749 value, state, SDHC_PRESENT_STATE_BITS)); 750 return ETIMEDOUT; 751 } 752 753 void 754 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 755 { 756 struct sdhc_host *hp = sch; 757 int error; 758 759 /* 760 * Start the MMC command, or mark `cmd' as failed and return. 761 */ 762 error = sdhc_start_command(hp, cmd); 763 if (error != 0) { 764 cmd->c_error = error; 765 SET(cmd->c_flags, SCF_ITSDONE); 766 return; 767 } 768 769 /* 770 * Wait until the command phase is done, or until the command 771 * is marked done for any other reason. 772 */ 773 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, 774 SDHC_COMMAND_TIMEOUT)) { 775 cmd->c_error = ETIMEDOUT; 776 SET(cmd->c_flags, SCF_ITSDONE); 777 return; 778 } 779 780 /* 781 * The host controller removes bits [0:7] from the response 782 * data (CRC) and we pass the data up unchanged to the bus 783 * driver (without padding). 784 */ 785 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 786 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 787 u_char *p = (u_char *)cmd->c_resp; 788 int i; 789 790 for (i = 0; i < 15; i++) 791 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 792 } else 793 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 794 } 795 796 /* 797 * If the command has data to transfer in any direction, 798 * execute the transfer now. 799 */ 800 if (cmd->c_error == 0 && cmd->c_data != NULL) 801 sdhc_transfer_data(hp, cmd); 802 803 /* Turn off the LED. */ 804 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 805 806 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n", 807 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 808 SET(cmd->c_flags, SCF_ITSDONE); 809 } 810 811 int 812 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 813 { 814 struct sdhc_adma2_descriptor32 *desc32 = (void *)hp->adma2; 815 struct sdhc_adma2_descriptor64 *desc64 = (void *)hp->adma2; 816 struct sdhc_softc *sc = hp->sc; 817 u_int16_t blksize = 0; 818 u_int16_t blkcount = 0; 819 u_int16_t mode; 820 u_int16_t command; 821 int error; 822 int seg; 823 int s; 824 825 DPRINTF(1,("%s: start cmd %u arg=%#x data=%p dlen=%d flags=%#x " 826 "proc=\"%s\"\n", DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, 827 cmd->c_data, cmd->c_datalen, cmd->c_flags, curproc ? 828 curproc->p_p->ps_comm : "")); 829 830 /* 831 * The maximum block length for commands should be the minimum 832 * of the host buffer size and the card buffer size. (1.7.2) 833 */ 834 835 /* Fragment the data into proper blocks. */ 836 if (cmd->c_datalen > 0) { 837 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 838 blkcount = cmd->c_datalen / blksize; 839 if (cmd->c_datalen % blksize > 0) { 840 /* XXX: Split this command. (1.7.4) */ 841 printf("%s: data not a multiple of %d bytes\n", 842 DEVNAME(hp->sc), blksize); 843 return EINVAL; 844 } 845 } 846 847 /* Check limit imposed by 9-bit block count. (1.7.2) */ 848 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 849 printf("%s: too much data\n", DEVNAME(hp->sc)); 850 return EINVAL; 851 } 852 853 /* Prepare transfer mode register value. (2.2.5) */ 854 mode = 0; 855 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 856 mode |= SDHC_READ_MODE; 857 if (blkcount > 0) { 858 mode |= SDHC_BLOCK_COUNT_ENABLE; 859 if (blkcount > 1) { 860 mode |= SDHC_MULTI_BLOCK_MODE; 861 if (cmd->c_opcode != SD_IO_RW_EXTENDED) 862 mode |= SDHC_AUTO_CMD12_ENABLE; 863 } 864 } 865 if (cmd->c_dmamap && cmd->c_datalen > 0 && 866 ISSET(hp->flags, SHF_USE_DMA)) 867 mode |= SDHC_DMA_ENABLE; 868 869 /* 870 * Prepare command register value. (2.2.6) 871 */ 872 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << 873 SDHC_COMMAND_INDEX_SHIFT; 874 875 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 876 command |= SDHC_CRC_CHECK_ENABLE; 877 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 878 command |= SDHC_INDEX_CHECK_ENABLE; 879 if (cmd->c_data != NULL) 880 command |= SDHC_DATA_PRESENT_SELECT; 881 882 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 883 command |= SDHC_NO_RESPONSE; 884 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 885 command |= SDHC_RESP_LEN_136; 886 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 887 command |= SDHC_RESP_LEN_48_CHK_BUSY; 888 else 889 command |= SDHC_RESP_LEN_48; 890 891 /* Wait until command and data inhibit bits are clear. (1.5) */ 892 if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0)) != 0) 893 return error; 894 895 s = splsdmmc(); 896 897 /* Alert the user not to remove the card. */ 898 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 899 900 /* Set DMA start address if SHF_USE_DMA is set. */ 901 if (cmd->c_dmamap && ISSET(hp->flags, SHF_USE_DMA)) { 902 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 903 bus_addr_t paddr = 904 cmd->c_dmamap->dm_segs[seg].ds_addr; 905 uint16_t len = 906 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 907 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 908 uint16_t attr; 909 910 attr = SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 911 if (seg == cmd->c_dmamap->dm_nsegs - 1) 912 attr |= SDHC_ADMA2_END; 913 914 if (ISSET(hp->flags, SHF_USE_DMA64)) { 915 desc64[seg].attribute = htole16(attr); 916 desc64[seg].length = htole16(len); 917 desc64[seg].address_lo = 918 htole32((uint64_t)paddr & 0xffffffff); 919 desc64[seg].address_hi = 920 htole32((uint64_t)paddr >> 32); 921 } else { 922 desc32[seg].attribute = htole16(attr); 923 desc32[seg].length = htole16(len); 924 desc32[seg].address = htole32(paddr); 925 } 926 } 927 928 if (ISSET(hp->flags, SHF_USE_DMA64)) 929 desc64[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 930 else 931 desc32[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 932 933 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 934 BUS_DMASYNC_PREWRITE); 935 936 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 937 if (ISSET(hp->flags, SHF_USE_DMA64)) 938 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA64); 939 else 940 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA32); 941 942 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, 943 hp->adma_map->dm_segs[0].ds_addr); 944 } else 945 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 946 947 DPRINTF(1,("%s: cmd=%#x mode=%#x blksize=%d blkcount=%d\n", 948 DEVNAME(hp->sc), command, mode, blksize, blkcount)); 949 950 /* 951 * Start a CPU data transfer. Writing to the high order byte 952 * of the SDHC_COMMAND register triggers the SD command. (1.5) 953 */ 954 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 955 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 956 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 957 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 958 HWRITE2(hp, SDHC_COMMAND, command); 959 960 splx(s); 961 return 0; 962 } 963 964 void 965 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 966 { 967 struct sdhc_softc *sc = hp->sc; 968 u_char *datap = cmd->c_data; 969 int i, datalen; 970 int mask; 971 int error; 972 973 if (cmd->c_dmamap) { 974 int status; 975 976 error = 0; 977 for (;;) { 978 status = sdhc_wait_intr(hp, 979 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 980 SDHC_DMA_TIMEOUT); 981 if (status & SDHC_TRANSFER_COMPLETE) 982 break; 983 if (!status) { 984 error = ETIMEDOUT; 985 break; 986 } 987 } 988 989 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 990 BUS_DMASYNC_POSTWRITE); 991 goto done; 992 } 993 994 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 995 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 996 error = 0; 997 datalen = cmd->c_datalen; 998 999 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(hp->sc), 1000 MMC_R1(cmd->c_resp), datalen)); 1001 1002 #ifdef SDHC_DEBUG 1003 /* XXX I forgot why I wanted to know when this happens :-( */ 1004 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1005 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) 1006 printf("%s: CMD52/53 error response flags %#x\n", 1007 DEVNAME(hp->sc), MMC_R1(cmd->c_resp) & 0xff00); 1008 #endif 1009 1010 while (datalen > 0) { 1011 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY| 1012 SDHC_BUFFER_WRITE_READY, SDHC_BUFFER_TIMEOUT)) { 1013 error = ETIMEDOUT; 1014 break; 1015 } 1016 1017 if ((error = sdhc_wait_state(hp, mask, mask)) != 0) 1018 break; 1019 1020 i = MIN(datalen, cmd->c_blklen); 1021 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1022 sdhc_read_data(hp, datap, i); 1023 else 1024 sdhc_write_data(hp, datap, i); 1025 1026 datap += i; 1027 datalen -= i; 1028 } 1029 1030 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1031 SDHC_TRANSFER_TIMEOUT)) 1032 error = ETIMEDOUT; 1033 1034 done: 1035 if (error != 0) 1036 cmd->c_error = error; 1037 SET(cmd->c_flags, SCF_ITSDONE); 1038 1039 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1040 DEVNAME(hp->sc), cmd->c_error)); 1041 } 1042 1043 void 1044 sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen) 1045 { 1046 while (datalen > 3) { 1047 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA); 1048 datap += 4; 1049 datalen -= 4; 1050 } 1051 if (datalen > 0) { 1052 u_int32_t rv = HREAD4(hp, SDHC_DATA); 1053 do { 1054 *datap++ = rv & 0xff; 1055 rv = rv >> 8; 1056 } while (--datalen > 0); 1057 } 1058 } 1059 1060 void 1061 sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen) 1062 { 1063 while (datalen > 3) { 1064 DPRINTF(3,("%08x\n", *(u_int32_t *)datap)); 1065 HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap)); 1066 datap += 4; 1067 datalen -= 4; 1068 } 1069 if (datalen > 0) { 1070 u_int32_t rv = *datap++; 1071 if (datalen > 1) 1072 rv |= *datap++ << 8; 1073 if (datalen > 2) 1074 rv |= *datap++ << 16; 1075 DPRINTF(3,("rv %08x\n", rv)); 1076 HWRITE4(hp, SDHC_DATA, rv); 1077 } 1078 } 1079 1080 /* Prepare for another command. */ 1081 int 1082 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1083 { 1084 int timo; 1085 1086 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask)); 1087 1088 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1089 for (timo = 10; timo > 0; timo--) { 1090 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1091 break; 1092 sdmmc_delay(10000); 1093 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1094 } 1095 if (timo == 0) { 1096 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(hp->sc), 1097 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1098 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1099 return (ETIMEDOUT); 1100 } 1101 1102 return (0); 1103 } 1104 1105 int 1106 sdhc_wait_intr_cold(struct sdhc_host *hp, int mask, int timo) 1107 { 1108 int status; 1109 1110 mask |= SDHC_ERROR_INTERRUPT; 1111 timo = timo * tick; 1112 status = hp->intr_status; 1113 while ((status & mask) == 0) { 1114 1115 status = HREAD2(hp, SDHC_NINTR_STATUS); 1116 if (ISSET(status, SDHC_NINTR_STATUS_MASK)) { 1117 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1118 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1119 uint16_t error; 1120 error = HREAD2(hp, SDHC_EINTR_STATUS); 1121 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1122 hp->intr_status |= status; 1123 1124 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1125 SDHC_DATA_TIMEOUT_ERROR)) 1126 break; 1127 } 1128 1129 if (ISSET(status, SDHC_BUFFER_READ_READY | 1130 SDHC_BUFFER_WRITE_READY | SDHC_COMMAND_COMPLETE | 1131 SDHC_TRANSFER_COMPLETE)) { 1132 hp->intr_status |= status; 1133 break; 1134 } 1135 1136 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1137 HSET2(hp, SDHC_NINTR_STATUS_EN, 1138 SDHC_CARD_INTERRUPT); 1139 } 1140 1141 continue; 1142 } 1143 1144 delay(1); 1145 if (timo-- == 0) { 1146 status |= SDHC_ERROR_INTERRUPT; 1147 break; 1148 } 1149 } 1150 1151 hp->intr_status &= ~(status & mask); 1152 return (status & mask); 1153 } 1154 1155 int 1156 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1157 { 1158 int status; 1159 int s; 1160 1161 if (cold) 1162 return (sdhc_wait_intr_cold(hp, mask, timo)); 1163 1164 mask |= SDHC_ERROR_INTERRUPT; 1165 1166 s = splsdmmc(); 1167 status = hp->intr_status & mask; 1168 while (status == 0) { 1169 if (tsleep(&hp->intr_status, PWAIT, "hcintr", timo) 1170 == EWOULDBLOCK) { 1171 status |= SDHC_ERROR_INTERRUPT; 1172 break; 1173 } 1174 status = hp->intr_status & mask; 1175 } 1176 hp->intr_status &= ~status; 1177 1178 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status, 1179 hp->intr_error_status)); 1180 1181 /* Command timeout has higher priority than command complete. */ 1182 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1183 hp->intr_error_status = 0; 1184 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1185 status = 0; 1186 } 1187 1188 splx(s); 1189 return status; 1190 } 1191 1192 /* 1193 * Established by attachment driver at interrupt priority IPL_SDMMC. 1194 */ 1195 int 1196 sdhc_intr(void *arg) 1197 { 1198 struct sdhc_softc *sc = arg; 1199 int host; 1200 int done = 0; 1201 1202 /* We got an interrupt, but we don't know from which slot. */ 1203 for (host = 0; host < sc->sc_nhosts; host++) { 1204 struct sdhc_host *hp = sc->sc_host[host]; 1205 u_int16_t status; 1206 1207 if (hp == NULL) 1208 continue; 1209 1210 /* Find out which interrupts are pending. */ 1211 status = HREAD2(hp, SDHC_NINTR_STATUS); 1212 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1213 continue; /* no interrupt for us */ 1214 1215 /* Acknowledge the interrupts we are about to handle. */ 1216 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1217 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(hp->sc), 1218 status, SDHC_NINTR_STATUS_BITS)); 1219 1220 /* Claim this interrupt. */ 1221 done = 1; 1222 1223 /* 1224 * Service error interrupts. 1225 */ 1226 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1227 u_int16_t error; 1228 1229 /* Acknowledge error interrupts. */ 1230 error = HREAD2(hp, SDHC_EINTR_STATUS); 1231 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1232 DPRINTF(2,("%s: error interrupt, status=%b\n", 1233 DEVNAME(hp->sc), error, SDHC_EINTR_STATUS_BITS)); 1234 1235 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1236 SDHC_DATA_TIMEOUT_ERROR)) { 1237 hp->intr_error_status |= error; 1238 hp->intr_status |= status; 1239 wakeup(&hp->intr_status); 1240 } 1241 } 1242 1243 /* 1244 * Wake up the sdmmc event thread to scan for cards. 1245 */ 1246 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1247 sdmmc_needs_discover(hp->sdmmc); 1248 1249 /* 1250 * Wake up the blocking process to service command 1251 * related interrupt(s). 1252 */ 1253 if (ISSET(status, SDHC_BUFFER_READ_READY| 1254 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 1255 SDHC_TRANSFER_COMPLETE)) { 1256 hp->intr_status |= status; 1257 wakeup(&hp->intr_status); 1258 } 1259 1260 /* 1261 * Service SD card interrupts. 1262 */ 1263 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1264 DPRINTF(0,("%s: card interrupt\n", DEVNAME(hp->sc))); 1265 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1266 sdmmc_card_intr(hp->sdmmc); 1267 } 1268 } 1269 return done; 1270 } 1271 1272 void 1273 sdhc_needs_discover(struct sdhc_softc *sc) 1274 { 1275 int host; 1276 1277 for (host = 0; host < sc->sc_nhosts; host++) 1278 sdmmc_needs_discover(sc->sc_host[host]->sdmmc); 1279 } 1280 1281 #ifdef SDHC_DEBUG 1282 void 1283 sdhc_dump_regs(struct sdhc_host *hp) 1284 { 1285 printf("0x%02x PRESENT_STATE: %b\n", SDHC_PRESENT_STATE, 1286 HREAD4(hp, SDHC_PRESENT_STATE), SDHC_PRESENT_STATE_BITS); 1287 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1288 HREAD1(hp, SDHC_POWER_CTL)); 1289 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1290 HREAD2(hp, SDHC_NINTR_STATUS)); 1291 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1292 HREAD2(hp, SDHC_EINTR_STATUS)); 1293 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1294 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1295 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1296 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1297 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1298 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1299 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1300 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1301 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1302 HREAD4(hp, SDHC_CAPABILITIES)); 1303 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1304 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1305 } 1306 #endif 1307 1308 int 1309 sdhc_hibernate_init(sdmmc_chipset_handle_t sch, void *fake_softc) 1310 { 1311 struct sdhc_host *hp, *fhp; 1312 fhp = fake_softc; 1313 hp = sch; 1314 *fhp = *hp; 1315 1316 return (0); 1317 } 1318