1 /* $OpenBSD: sdmmcreg.h,v 1.8 2016/01/10 14:11:43 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _SDMMCREG_H_ 20 #define _SDMMCREG_H_ 21 22 /* MMC commands */ /* response type */ 23 #define MMC_GO_IDLE_STATE 0 /* R0 */ 24 #define MMC_SEND_OP_COND 1 /* R3 */ 25 #define MMC_ALL_SEND_CID 2 /* R2 */ 26 #define MMC_SET_RELATIVE_ADDR 3 /* R1 */ 27 #define MMC_SWITCH 6 /* R1B */ 28 #define MMC_SELECT_CARD 7 /* R1 */ 29 #define MMC_SEND_EXT_CSD 8 /* R1 */ 30 #define MMC_SEND_CSD 9 /* R2 */ 31 #define MMC_STOP_TRANSMISSION 12 /* R1B */ 32 #define MMC_SEND_STATUS 13 /* R1 */ 33 #define MMC_SET_BLOCKLEN 16 /* R1 */ 34 #define MMC_READ_BLOCK_SINGLE 17 /* R1 */ 35 #define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */ 36 #define MMC_SET_BLOCK_COUNT 23 /* R1 */ 37 #define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */ 38 #define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */ 39 #define MMC_APP_CMD 55 /* R1 */ 40 41 /* SD commands */ /* response type */ 42 #define SD_SEND_RELATIVE_ADDR 3 /* R6 */ 43 #define SD_SEND_IF_COND 8 /* R7 */ 44 45 /* SD application commands */ /* response type */ 46 #define SD_APP_SET_BUS_WIDTH 6 /* R1 */ 47 #define SD_APP_OP_COND 41 /* R3 */ 48 49 /* OCR bits */ 50 #define MMC_OCR_MEM_READY (1<<31) /* memory power-up status bit */ 51 #define MMC_OCR_ACCESS_MODE_MASK 0x60000000 /* bits 30:29 */ 52 #define MMC_OCR_SECTOR_MODE (1<<30) 53 #define MMC_OCR_BYTE_MODE (1<<29) 54 #define MMC_OCR_3_5V_3_6V (1<<23) 55 #define MMC_OCR_3_4V_3_5V (1<<22) 56 #define MMC_OCR_3_3V_3_4V (1<<21) 57 #define MMC_OCR_3_2V_3_3V (1<<20) 58 #define MMC_OCR_3_1V_3_2V (1<<19) 59 #define MMC_OCR_3_0V_3_1V (1<<18) 60 #define MMC_OCR_2_9V_3_0V (1<<17) 61 #define MMC_OCR_2_8V_2_9V (1<<16) 62 #define MMC_OCR_2_7V_2_8V (1<<15) 63 #define MMC_OCR_2_6V_2_7V (1<<14) 64 #define MMC_OCR_2_5V_2_6V (1<<13) 65 #define MMC_OCR_2_4V_2_5V (1<<12) 66 #define MMC_OCR_2_3V_2_4V (1<<11) 67 #define MMC_OCR_2_2V_2_3V (1<<10) 68 #define MMC_OCR_2_1V_2_2V (1<<9) 69 #define MMC_OCR_2_0V_2_1V (1<<8) 70 #define MMC_OCR_1_65V_1_95V (1<<7) 71 72 #define SD_OCR_SDHC_CAP (1<<30) 73 #define SD_OCR_VOL_MASK 0xFF8000 /* bits 23:15 */ 74 75 /* R1 response type bits */ 76 #define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */ 77 #define MMC_R1_APP_CMD (1<<5) /* app. commands supported */ 78 79 /* 48-bit response decoding (32 bits w/o CRC) */ 80 #define MMC_R1(resp) ((resp)[0]) 81 #define MMC_R3(resp) ((resp)[0]) 82 #define SD_R6(resp) ((resp)[0]) 83 84 /* RCA argument and response */ 85 #define MMC_ARG_RCA(rca) ((rca) << 16) 86 #define SD_R6_RCA(resp) (SD_R6((resp)) >> 16) 87 88 /* bus width argument */ 89 #define SD_ARG_BUS_WIDTH_1 0 90 #define SD_ARG_BUS_WIDTH_4 2 91 92 /* EXT_CSD fields */ 93 #define EXT_CSD_BUS_WIDTH 183 /* WO */ 94 #define EXT_CSD_HS_TIMING 185 /* R/W */ 95 #define EXT_CSD_REV 192 /* RO */ 96 #define EXT_CSD_STRUCTURE 194 /* RO */ 97 #define EXT_CSD_CARD_TYPE 196 /* RO */ 98 #define EXT_CSD_SEC_COUNT 212 /* RO */ 99 100 /* EXT_CSD field definitions */ 101 #define EXT_CSD_CMD_SET_NORMAL (1U << 0) 102 #define EXT_CSD_CMD_SET_SECURE (1U << 1) 103 #define EXT_CSD_CMD_SET_CPSECURE (1U << 2) 104 105 /* EXT_CSD_BUS_WIDTH */ 106 #define EXT_CSD_BUS_WIDTH_1 0 107 #define EXT_CSD_BUS_WIDTH_4 1 108 #define EXT_CSD_BUS_WIDTH_8 2 109 110 /* EXT_CSD_CARD_TYPE */ 111 /* The only currently valid values for this field are 0x01, 0x03, 0x07, 112 * 0x0B and 0x0F. */ 113 #define EXT_CSD_CARD_TYPE_F_26M (1 << 0) 114 #define EXT_CSD_CARD_TYPE_F_52M (1 << 1) 115 #define EXT_CSD_CARD_TYPE_F_52M_1_8V (1 << 2) 116 #define EXT_CSD_CARD_TYPE_F_52M_1_2V (1 << 3) 117 #define EXT_CSD_CARD_TYPE_26M 0x01 118 #define EXT_CSD_CARD_TYPE_52M 0x03 119 #define EXT_CSD_CARD_TYPE_52M_V18 0x07 120 #define EXT_CSD_CARD_TYPE_52M_V12 0x0b 121 #define EXT_CSD_CARD_TYPE_52M_V12_18 0x0f 122 123 /* MMC_SWITCH access mode */ 124 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 125 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */ 126 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */ 127 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ 128 129 /* MMC R2 response (CSD) */ 130 #define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) 131 #define MMC_CSD_CSDVER_1_0 1 132 #define MMC_CSD_CSDVER_2_0 2 133 #define MMC_CSD_CSDVER_EXT_CSD 3 134 #define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4) 135 #define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */ 136 #define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */ 137 #define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */ 138 #define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */ 139 #define MMC_CSD_MMCVER_4_0 4 /* MMC 4 */ 140 #define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) 141 #define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) 142 #define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \ 143 (MMC_CSD_C_SIZE_MULT((resp))+2)) 144 #define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) 145 146 /* MMC v1 R2 response (CID) */ 147 #define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24) 148 #define MMC_CID_PNM_V1_CPY(resp, pnm) \ 149 do { \ 150 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 151 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 152 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 153 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 154 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 155 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ 156 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \ 157 (pnm)[7] = '\0'; \ 158 } while (0) 159 #define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8) 160 #define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24) 161 #define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8) 162 163 /* MMC v2 R2 response (CID) */ 164 #define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8) 165 #define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16) 166 #define MMC_CID_PNM_V2_CPY(resp, pnm) \ 167 do { \ 168 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 169 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 170 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 171 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 172 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 173 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ 174 (pnm)[6] = '\0'; \ 175 } while (0) 176 #define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32) 177 178 /* SD R2 response (CSD) */ 179 #define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) 180 #define SD_CSD_CSDVER_1_0 0 181 #define SD_CSD_CSDVER_2_0 1 182 #define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8) 183 #define SD_CSD_TAAC_1_5_MSEC 0x26 184 #define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8) 185 #define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8) 186 #define SD_CSD_SPEED_25_MHZ 0x32 187 #define SD_CSD_SPEED_50_MHZ 0x5a 188 #define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12) 189 #define SD_CSD_CCC_ALL 0x5f5 190 #define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) 191 #define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1) 192 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1) 193 #define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1) 194 #define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1) 195 #define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) 196 #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \ 197 (SD_CSD_C_SIZE_MULT((resp))+2)) 198 #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22) 199 #define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10) 200 #define SD_CSD_V2_BL_LEN 0x9 /* 512 */ 201 #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3) 202 #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3) 203 #define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3) 204 #define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3) 205 #define SD_CSD_VDD_RW_CURR_100mA 0x7 206 #define SD_CSD_VDD_RW_CURR_80mA 0x6 207 #define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) 208 #define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1) 209 #define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */ 210 #define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */ 211 #define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1) 212 #define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3) 213 #define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4) 214 #define SD_CSD_RW_BL_LEN_2G 0xa 215 #define SD_CSD_RW_BL_LEN_1G 0x9 216 #define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1) 217 #define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1) 218 #define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1) 219 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1) 220 #define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1) 221 #define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2) 222 223 /* SD R2 response (CID) */ 224 #define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8) 225 #define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16) 226 #define SD_CID_PNM_CPY(resp, pnm) \ 227 do { \ 228 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 229 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 230 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 231 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 232 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 233 (pnm)[5] = '\0'; \ 234 } while (0) 235 #define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8) 236 #define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32) 237 #define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12) 238 239 /* Might be slow, but it should work on big and little endian systems. */ 240 #define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len)) 241 static __inline int 242 __bitfield(u_int32_t *src, int start, int len) 243 { 244 u_int8_t *sp; 245 u_int32_t dst, mask; 246 int shift, bs, bc; 247 248 if (start < 0 || len < 0 || len > 32) 249 return 0; 250 251 dst = 0; 252 mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX; 253 shift = 0; 254 255 while (len > 0) { 256 sp = (u_int8_t *)src + start / 8; 257 bs = start % 8; 258 bc = 8 - bs; 259 if (bc > len) 260 bc = len; 261 dst |= (*sp++ >> bs) << shift; 262 shift += bc; 263 start += bc; 264 len -= bc; 265 } 266 267 dst &= mask; 268 return (int)dst; 269 } 270 271 #endif 272