1 /* $OpenBSD: asc_tcds.c,v 1.8 2014/01/18 22:33:59 dlg Exp $ */ 2 /* $NetBSD: asc_tcds.c,v 1.5 2001/11/15 09:48:19 lukem Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/device.h> 61 #include <sys/buf.h> 62 63 #include <scsi/scsi_all.h> 64 #include <scsi/scsiconf.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 #include <dev/tc/ascvar.h> 69 70 #include <machine/bus.h> 71 72 #include <dev/tc/tcvar.h> 73 #include <dev/tc/tcdsreg.h> 74 #include <dev/tc/tcdsvar.h> 75 76 struct asc_tcds_softc { 77 struct asc_softc asc; 78 79 struct tcds_slotconfig *sc_tcds; 80 }; 81 82 int asc_tcds_match (struct device *, void *, void *); 83 void asc_tcds_attach(struct device *, struct device *, void *); 84 85 /* Linkup to the rest of the kernel */ 86 struct cfattach asc_tcds_ca = { 87 sizeof(struct asc_tcds_softc), asc_tcds_match, asc_tcds_attach 88 }; 89 90 /* 91 * Functions and the switch for the MI code. 92 */ 93 int tcds_dma_isintr(struct ncr53c9x_softc *); 94 void tcds_dma_reset(struct ncr53c9x_softc *); 95 int tcds_dma_intr(struct ncr53c9x_softc *); 96 int tcds_dma_setup(struct ncr53c9x_softc *, caddr_t *, 97 size_t *, int, size_t *); 98 void tcds_dma_go(struct ncr53c9x_softc *); 99 void tcds_dma_stop(struct ncr53c9x_softc *); 100 int tcds_dma_isactive(struct ncr53c9x_softc *); 101 void tcds_clear_latched_intr(struct ncr53c9x_softc *); 102 103 struct ncr53c9x_glue asc_tcds_glue = { 104 asc_read_reg, 105 asc_write_reg, 106 tcds_dma_isintr, 107 tcds_dma_reset, 108 tcds_dma_intr, 109 tcds_dma_setup, 110 tcds_dma_go, 111 tcds_dma_stop, 112 tcds_dma_isactive, 113 tcds_clear_latched_intr, 114 }; 115 116 int 117 asc_tcds_match(parent, cf, aux) 118 struct device *parent; 119 void *cf, *aux; 120 { 121 122 /* We always exist. */ 123 return 1; 124 } 125 126 #define DMAMAX(a) (NBPG - ((a) & (NBPG - 1))) 127 128 /* 129 * Attach this instance, and then all the sub-devices 130 */ 131 void 132 asc_tcds_attach(parent, self, aux) 133 struct device *parent, *self; 134 void *aux; 135 { 136 struct tcdsdev_attach_args *tcdsdev = aux; 137 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)self; 138 struct ncr53c9x_softc *sc = &asc->asc.sc_ncr53c9x; 139 int error; 140 141 /* 142 * Set up glue for MI code early; we use some of it here. 143 */ 144 sc->sc_glue = &asc_tcds_glue; 145 146 asc->asc.sc_bst = tcdsdev->tcdsda_bst; 147 asc->asc.sc_bsh = tcdsdev->tcdsda_bsh; 148 asc->sc_tcds = tcdsdev->tcdsda_sc; 149 150 /* 151 * The TCDS ASIC cannot DMA across 8k boundaries, and this 152 * driver is written such that each DMA segment gets a new 153 * call to tcds_dma_setup(). Thus, the DMA map only needs 154 * to support 8k transfers. 155 */ 156 asc->asc.sc_dmat = tcdsdev->tcdsda_dmat; 157 if ((error = bus_dmamap_create(asc->asc.sc_dmat, NBPG, 1, NBPG, 158 NBPG, BUS_DMA_NOWAIT, &asc->asc.sc_dmamap)) < 0) { 159 printf("failed to create dma map, error = %d\n", error); 160 } 161 162 sc->sc_id = tcdsdev->tcdsda_id; 163 sc->sc_freq = tcdsdev->tcdsda_freq; 164 165 /* gimme MHz */ 166 sc->sc_freq /= 1000000; 167 168 tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc, 169 self->dv_xname); 170 171 /* 172 * XXX More of this should be in ncr53c9x_attach(), but 173 * XXX should we really poke around the chip that much in 174 * XXX the MI code? Think about this more... 175 */ 176 177 /* 178 * Set up static configuration info. 179 */ 180 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 181 sc->sc_cfg2 = NCRCFG2_SCSI2; 182 sc->sc_cfg3 = NCRCFG3_CDB; 183 if (sc->sc_freq > 25) 184 sc->sc_cfg3 |= NCRF9XCFG3_FCLK; 185 sc->sc_rev = tcdsdev->tcdsda_variant; 186 if (tcdsdev->tcdsda_fast) { 187 sc->sc_features |= NCR_F_FASTSCSI; 188 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 189 } 190 191 /* 192 * XXX minsync and maxxfer _should_ be set up in MI code, 193 * XXX but it appears to have some dependency on what sort 194 * XXX of DMA we're hooked up to, etc. 195 */ 196 197 /* 198 * This is the value used to start sync negotiations 199 * Note that the NCR register "SYNCTP" is programmed 200 * in "clocks per byte", and has a minimum value of 4. 201 * The SCSI period used in negotiation is one-fourth 202 * of the time (in nanoseconds) needed to transfer one byte. 203 * Since the chip's clock is given in MHz, we have the following 204 * formula: 4 * period = (1000 / freq) * 4 205 */ 206 sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4; 207 208 sc->sc_maxxfer = 64 * 1024; 209 210 /* Do the common parts of attachment. */ 211 ncr53c9x_attach(sc); 212 } 213 214 void 215 tcds_dma_reset(sc) 216 struct ncr53c9x_softc *sc; 217 { 218 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 219 220 /* TCDS SCSI disable/reset/enable. */ 221 tcds_scsi_reset(asc->sc_tcds); /* XXX */ 222 223 if (asc->asc.sc_flags & ASC_MAPLOADED) 224 bus_dmamap_unload(asc->asc.sc_dmat, asc->asc.sc_dmamap); 225 asc->asc.sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 226 } 227 228 /* 229 * start a dma transfer or keep it going 230 */ 231 int 232 tcds_dma_setup(sc, addr, len, ispullup, dmasize) 233 struct ncr53c9x_softc *sc; 234 caddr_t *addr; 235 size_t *len, *dmasize; 236 int ispullup; /* DMA into main memory */ 237 { 238 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 239 struct tcds_slotconfig *tcds = asc->sc_tcds; 240 size_t size; 241 u_int32_t dic; 242 243 NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot, 244 (int)*asc->asc.sc_dmalen, *asc->asc.sc_dmaaddr, 245 (ispullup) ? "IN" : "OUT")); 246 247 /* 248 * the rules say we cannot transfer more than the limit 249 * of this DMA chip (64k) and we cannot cross a 8k boundary. 250 */ 251 size = min(*dmasize, DMAMAX((size_t)*addr)); 252 asc->asc.sc_dmaaddr = addr; 253 asc->asc.sc_dmalen = len; 254 asc->asc.sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 255 *dmasize = asc->asc.sc_dmasize = size; 256 257 NCR_DMA(("dma_start: dmasize = %d\n", (int)size)); 258 259 if (size == 0) 260 return 0; 261 262 if (bus_dmamap_load(asc->asc.sc_dmat, asc->asc.sc_dmamap, *addr, size, 263 NULL, BUS_DMA_NOWAIT | (ispullup ? BUS_DMA_READ : BUS_DMA_WRITE))) { 264 /* 265 * XXX Should return an error, here, but the upper-layer 266 * XXX doesn't check the return value! 267 */ 268 panic("tcds_dma_setup: dmamap load failed"); 269 } 270 271 /* synchronize dmamap contents with memory image */ 272 bus_dmamap_sync(asc->asc.sc_dmat, asc->asc.sc_dmamap, 0, size, 273 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 274 275 /* load address, set/clear unaligned transfer and read/write bits. */ 276 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda, 277 asc->asc.sc_dmamap->dm_segs[0].ds_addr >> 2); 278 dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic); 279 dic &= ~TCDS_DIC_ADDRMASK; 280 dic |= asc->asc.sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK; 281 if (ispullup) 282 dic |= TCDS_DIC_WRITE; 283 else 284 dic &= ~TCDS_DIC_WRITE; 285 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic); 286 287 asc->asc.sc_flags |= ASC_MAPLOADED; 288 return 0; 289 } 290 291 void 292 tcds_dma_go(sc) 293 struct ncr53c9x_softc *sc; 294 { 295 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 296 297 /* mark unit as DMA-active */ 298 asc->asc.sc_flags |= ASC_DMAACTIVE; 299 300 /* start DMA */ 301 tcds_dma_enable(asc->sc_tcds, 1); 302 } 303 304 void 305 tcds_dma_stop(sc) 306 struct ncr53c9x_softc *sc; 307 { 308 #if 0 309 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 310 #endif 311 312 /* 313 * XXX STOP DMA HERE! 314 */ 315 } 316 317 /* 318 * Pseudo (chained) interrupt from the asc driver to kick the 319 * current running DMA transfer. Called from ncr53c9x_intr() 320 * for now. 321 * 322 * return 1 if it was a DMA continue. 323 */ 324 int 325 tcds_dma_intr(sc) 326 struct ncr53c9x_softc *sc; 327 { 328 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 329 struct tcds_slotconfig *tcds = asc->sc_tcds; 330 int trans, resid; 331 u_int32_t tcl, tcm; 332 u_int32_t dud, dudmask, *addr; 333 bus_addr_t pa; 334 335 NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot)); 336 337 if (tcds_scsi_iserr(tcds)) 338 return 0; 339 340 /* This is an "assertion" :) */ 341 if ((asc->asc.sc_flags & ASC_DMAACTIVE) == 0) 342 panic("tcds_dma_intr: DMA wasn't active"); 343 344 /* DMA has stopped */ 345 tcds_dma_enable(tcds, 0); 346 asc->asc.sc_flags &= ~ASC_DMAACTIVE; 347 348 if (asc->asc.sc_dmasize == 0) { 349 /* A "Transfer Pad" operation completed */ 350 tcl = NCR_READ_REG(sc, NCR_TCL); 351 tcm = NCR_READ_REG(sc, NCR_TCM); 352 NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 353 tcl | (tcm << 8), tcl, tcm)); 354 return 0; 355 } 356 357 resid = 0; 358 if ((asc->asc.sc_flags & ASC_ISPULLUP) == 0 && 359 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 360 NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid)); 361 DELAY(1); 362 } 363 364 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 365 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 366 367 trans = asc->asc.sc_dmasize - resid; 368 if (trans < 0) { /* transferred < 0 ? */ 369 printf("tcds_dma %d: xfer (%d) > req (%d)\n", 370 tcds->sc_slot, trans, (int)asc->asc.sc_dmasize); 371 trans = asc->asc.sc_dmasize; 372 } 373 374 NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 375 tcl, tcm, trans, resid)); 376 377 *asc->asc.sc_dmalen -= trans; 378 *asc->asc.sc_dmaaddr += trans; 379 380 bus_dmamap_sync(asc->asc.sc_dmat, asc->asc.sc_dmamap, 381 0, asc->asc.sc_dmamap->dm_mapsize, 382 (asc->asc.sc_flags & ASC_ISPULLUP) 383 ? BUS_DMASYNC_POSTREAD 384 : BUS_DMASYNC_POSTWRITE); 385 386 /* 387 * Clean up unaligned DMAs into main memory. 388 */ 389 if (asc->asc.sc_flags & ASC_ISPULLUP) { 390 /* Handle unaligned starting address, length. */ 391 dud = bus_space_read_4(tcds->sc_bst, 392 tcds->sc_bsh, tcds->sc_dud0); 393 if ((dud & TCDS_DUD0_VALIDBITS) != 0) { 394 addr = (u_int32_t *) 395 ((paddr_t)*asc->asc.sc_dmaaddr & ~0x3); 396 dudmask = 0; 397 if (dud & TCDS_DUD0_VALID00) 398 panic("tcds_dma: dud0 byte 0 valid"); 399 if (dud & TCDS_DUD0_VALID01) 400 dudmask |= TCDS_DUD_BYTE01; 401 if (dud & TCDS_DUD0_VALID10) 402 dudmask |= TCDS_DUD_BYTE10; 403 #ifdef DIAGNOSTIC 404 if (dud & TCDS_DUD0_VALID11) 405 dudmask |= TCDS_DUD_BYTE11; 406 #endif 407 NCR_DMA(("dud0 at %p dudmask 0x%x\n", 408 addr, dudmask)); 409 *addr = (*addr & ~dudmask) | (dud & dudmask); 410 } 411 dud = bus_space_read_4(tcds->sc_bst, 412 tcds->sc_bsh, tcds->sc_dud1); 413 if ((dud & TCDS_DUD1_VALIDBITS) != 0) { 414 pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, 415 tcds->sc_sda) << 2; 416 dudmask = 0; 417 if (dud & TCDS_DUD1_VALID00) 418 dudmask |= TCDS_DUD_BYTE00; 419 if (dud & TCDS_DUD1_VALID01) 420 dudmask |= TCDS_DUD_BYTE01; 421 if (dud & TCDS_DUD1_VALID10) 422 dudmask |= TCDS_DUD_BYTE10; 423 #ifdef DIAGNOSTIC 424 if (dud & TCDS_DUD1_VALID11) 425 panic("tcds_dma: dud1 byte 3 valid"); 426 #endif 427 NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n", 428 pa, dudmask)); 429 /* XXX Fix TC_PHYS_TO_UNCACHED() */ 430 #if defined(__alpha__) 431 addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG(pa); 432 #elif defined(__mips__) 433 addr = (u_int32_t *)MIPS_PHYS_TO_KSEG1(pa); 434 #else 435 #error TURBOchannel only exists on DECs, folks... 436 #endif 437 *addr = (*addr & ~dudmask) | (dud & dudmask); 438 } 439 /* XXX deal with saved residual byte? */ 440 } 441 442 bus_dmamap_unload(asc->asc.sc_dmat, asc->asc.sc_dmamap); 443 asc->asc.sc_flags &= ~ASC_MAPLOADED; 444 445 return 0; 446 } 447 448 /* 449 * Glue functions. 450 */ 451 int 452 tcds_dma_isintr(sc) 453 struct ncr53c9x_softc *sc; 454 { 455 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 456 int x; 457 458 x = tcds_scsi_isintr(asc->sc_tcds, 1); 459 460 /* XXX */ 461 return x; 462 } 463 464 int 465 tcds_dma_isactive(sc) 466 struct ncr53c9x_softc *sc; 467 { 468 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 469 470 return !!(asc->asc.sc_flags & ASC_DMAACTIVE); 471 } 472 473 void 474 tcds_clear_latched_intr(sc) 475 struct ncr53c9x_softc *sc; 476 { 477 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 478 479 /* Clear the TCDS interrupt bit. */ 480 (void)tcds_scsi_isintr(asc->sc_tcds, 1); 481 } 482