1 /* $OpenBSD: asc_tcds.c,v 1.7 2010/06/28 18:31:02 krw Exp $ */ 2 /* $NetBSD: asc_tcds.c,v 1.5 2001/11/15 09:48:19 lukem Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/device.h> 61 #include <sys/buf.h> 62 63 #include <scsi/scsi_all.h> 64 #include <scsi/scsiconf.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 #include <dev/tc/ascvar.h> 69 70 #include <machine/bus.h> 71 72 #include <dev/tc/tcvar.h> 73 #include <dev/tc/tcdsreg.h> 74 #include <dev/tc/tcdsvar.h> 75 76 struct asc_tcds_softc { 77 struct asc_softc asc; 78 79 struct tcds_slotconfig *sc_tcds; 80 }; 81 82 int asc_tcds_match (struct device *, void *, void *); 83 void asc_tcds_attach(struct device *, struct device *, void *); 84 85 /* Linkup to the rest of the kernel */ 86 struct cfattach asc_tcds_ca = { 87 sizeof(struct asc_tcds_softc), asc_tcds_match, asc_tcds_attach 88 }; 89 90 /* 91 * Functions and the switch for the MI code. 92 */ 93 int tcds_dma_isintr(struct ncr53c9x_softc *); 94 void tcds_dma_reset(struct ncr53c9x_softc *); 95 int tcds_dma_intr(struct ncr53c9x_softc *); 96 int tcds_dma_setup(struct ncr53c9x_softc *, caddr_t *, 97 size_t *, int, size_t *); 98 void tcds_dma_go(struct ncr53c9x_softc *); 99 void tcds_dma_stop(struct ncr53c9x_softc *); 100 int tcds_dma_isactive(struct ncr53c9x_softc *); 101 void tcds_clear_latched_intr(struct ncr53c9x_softc *); 102 103 struct ncr53c9x_glue asc_tcds_glue = { 104 asc_read_reg, 105 asc_write_reg, 106 tcds_dma_isintr, 107 tcds_dma_reset, 108 tcds_dma_intr, 109 tcds_dma_setup, 110 tcds_dma_go, 111 tcds_dma_stop, 112 tcds_dma_isactive, 113 tcds_clear_latched_intr, 114 }; 115 116 extern struct scsi_adapter asc_switch; 117 118 int 119 asc_tcds_match(parent, cf, aux) 120 struct device *parent; 121 void *cf, *aux; 122 { 123 124 /* We always exist. */ 125 return 1; 126 } 127 128 #define DMAMAX(a) (NBPG - ((a) & (NBPG - 1))) 129 130 /* 131 * Attach this instance, and then all the sub-devices 132 */ 133 void 134 asc_tcds_attach(parent, self, aux) 135 struct device *parent, *self; 136 void *aux; 137 { 138 struct tcdsdev_attach_args *tcdsdev = aux; 139 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)self; 140 struct ncr53c9x_softc *sc = &asc->asc.sc_ncr53c9x; 141 int error; 142 143 /* 144 * Set up glue for MI code early; we use some of it here. 145 */ 146 sc->sc_glue = &asc_tcds_glue; 147 148 asc->asc.sc_bst = tcdsdev->tcdsda_bst; 149 asc->asc.sc_bsh = tcdsdev->tcdsda_bsh; 150 asc->sc_tcds = tcdsdev->tcdsda_sc; 151 152 /* 153 * The TCDS ASIC cannot DMA across 8k boundaries, and this 154 * driver is written such that each DMA segment gets a new 155 * call to tcds_dma_setup(). Thus, the DMA map only needs 156 * to support 8k transfers. 157 */ 158 asc->asc.sc_dmat = tcdsdev->tcdsda_dmat; 159 if ((error = bus_dmamap_create(asc->asc.sc_dmat, NBPG, 1, NBPG, 160 NBPG, BUS_DMA_NOWAIT, &asc->asc.sc_dmamap)) < 0) { 161 printf("failed to create dma map, error = %d\n", error); 162 } 163 164 sc->sc_id = tcdsdev->tcdsda_id; 165 sc->sc_freq = tcdsdev->tcdsda_freq; 166 167 /* gimme MHz */ 168 sc->sc_freq /= 1000000; 169 170 tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc, 171 self->dv_xname); 172 173 /* 174 * XXX More of this should be in ncr53c9x_attach(), but 175 * XXX should we really poke around the chip that much in 176 * XXX the MI code? Think about this more... 177 */ 178 179 /* 180 * Set up static configuration info. 181 */ 182 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 183 sc->sc_cfg2 = NCRCFG2_SCSI2; 184 sc->sc_cfg3 = NCRCFG3_CDB; 185 if (sc->sc_freq > 25) 186 sc->sc_cfg3 |= NCRF9XCFG3_FCLK; 187 sc->sc_rev = tcdsdev->tcdsda_variant; 188 if (tcdsdev->tcdsda_fast) { 189 sc->sc_features |= NCR_F_FASTSCSI; 190 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 191 } 192 193 /* 194 * XXX minsync and maxxfer _should_ be set up in MI code, 195 * XXX but it appears to have some dependency on what sort 196 * XXX of DMA we're hooked up to, etc. 197 */ 198 199 /* 200 * This is the value used to start sync negotiations 201 * Note that the NCR register "SYNCTP" is programmed 202 * in "clocks per byte", and has a minimum value of 4. 203 * The SCSI period used in negotiation is one-fourth 204 * of the time (in nanoseconds) needed to transfer one byte. 205 * Since the chip's clock is given in MHz, we have the following 206 * formula: 4 * period = (1000 / freq) * 4 207 */ 208 sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4; 209 210 sc->sc_maxxfer = 64 * 1024; 211 212 /* Do the common parts of attachment. */ 213 ncr53c9x_attach(sc, &asc_switch); 214 } 215 216 void 217 tcds_dma_reset(sc) 218 struct ncr53c9x_softc *sc; 219 { 220 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 221 222 /* TCDS SCSI disable/reset/enable. */ 223 tcds_scsi_reset(asc->sc_tcds); /* XXX */ 224 225 if (asc->asc.sc_flags & ASC_MAPLOADED) 226 bus_dmamap_unload(asc->asc.sc_dmat, asc->asc.sc_dmamap); 227 asc->asc.sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 228 } 229 230 /* 231 * start a dma transfer or keep it going 232 */ 233 int 234 tcds_dma_setup(sc, addr, len, ispullup, dmasize) 235 struct ncr53c9x_softc *sc; 236 caddr_t *addr; 237 size_t *len, *dmasize; 238 int ispullup; /* DMA into main memory */ 239 { 240 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 241 struct tcds_slotconfig *tcds = asc->sc_tcds; 242 size_t size; 243 u_int32_t dic; 244 245 NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot, 246 (int)*asc->asc.sc_dmalen, *asc->asc.sc_dmaaddr, 247 (ispullup) ? "IN" : "OUT")); 248 249 /* 250 * the rules say we cannot transfer more than the limit 251 * of this DMA chip (64k) and we cannot cross a 8k boundary. 252 */ 253 size = min(*dmasize, DMAMAX((size_t)*addr)); 254 asc->asc.sc_dmaaddr = addr; 255 asc->asc.sc_dmalen = len; 256 asc->asc.sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 257 *dmasize = asc->asc.sc_dmasize = size; 258 259 NCR_DMA(("dma_start: dmasize = %d\n", (int)size)); 260 261 if (size == 0) 262 return 0; 263 264 if (bus_dmamap_load(asc->asc.sc_dmat, asc->asc.sc_dmamap, *addr, size, 265 NULL, BUS_DMA_NOWAIT | (ispullup ? BUS_DMA_READ : BUS_DMA_WRITE))) { 266 /* 267 * XXX Should return an error, here, but the upper-layer 268 * XXX doesn't check the return value! 269 */ 270 panic("tcds_dma_setup: dmamap load failed"); 271 } 272 273 /* synchronize dmamap contents with memory image */ 274 bus_dmamap_sync(asc->asc.sc_dmat, asc->asc.sc_dmamap, 0, size, 275 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 276 277 /* load address, set/clear unaligned transfer and read/write bits. */ 278 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda, 279 asc->asc.sc_dmamap->dm_segs[0].ds_addr >> 2); 280 dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic); 281 dic &= ~TCDS_DIC_ADDRMASK; 282 dic |= asc->asc.sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK; 283 if (ispullup) 284 dic |= TCDS_DIC_WRITE; 285 else 286 dic &= ~TCDS_DIC_WRITE; 287 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic); 288 289 asc->asc.sc_flags |= ASC_MAPLOADED; 290 return 0; 291 } 292 293 void 294 tcds_dma_go(sc) 295 struct ncr53c9x_softc *sc; 296 { 297 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 298 299 /* mark unit as DMA-active */ 300 asc->asc.sc_flags |= ASC_DMAACTIVE; 301 302 /* start DMA */ 303 tcds_dma_enable(asc->sc_tcds, 1); 304 } 305 306 void 307 tcds_dma_stop(sc) 308 struct ncr53c9x_softc *sc; 309 { 310 #if 0 311 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 312 #endif 313 314 /* 315 * XXX STOP DMA HERE! 316 */ 317 } 318 319 /* 320 * Pseudo (chained) interrupt from the asc driver to kick the 321 * current running DMA transfer. Called from ncr53c9x_intr() 322 * for now. 323 * 324 * return 1 if it was a DMA continue. 325 */ 326 int 327 tcds_dma_intr(sc) 328 struct ncr53c9x_softc *sc; 329 { 330 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 331 struct tcds_slotconfig *tcds = asc->sc_tcds; 332 int trans, resid; 333 u_int32_t tcl, tcm; 334 u_int32_t dud, dudmask, *addr; 335 bus_addr_t pa; 336 337 NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot)); 338 339 if (tcds_scsi_iserr(tcds)) 340 return 0; 341 342 /* This is an "assertion" :) */ 343 if ((asc->asc.sc_flags & ASC_DMAACTIVE) == 0) 344 panic("tcds_dma_intr: DMA wasn't active"); 345 346 /* DMA has stopped */ 347 tcds_dma_enable(tcds, 0); 348 asc->asc.sc_flags &= ~ASC_DMAACTIVE; 349 350 if (asc->asc.sc_dmasize == 0) { 351 /* A "Transfer Pad" operation completed */ 352 tcl = NCR_READ_REG(sc, NCR_TCL); 353 tcm = NCR_READ_REG(sc, NCR_TCM); 354 NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 355 tcl | (tcm << 8), tcl, tcm)); 356 return 0; 357 } 358 359 resid = 0; 360 if ((asc->asc.sc_flags & ASC_ISPULLUP) == 0 && 361 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 362 NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid)); 363 DELAY(1); 364 } 365 366 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 367 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 368 369 trans = asc->asc.sc_dmasize - resid; 370 if (trans < 0) { /* transferred < 0 ? */ 371 printf("tcds_dma %d: xfer (%d) > req (%d)\n", 372 tcds->sc_slot, trans, (int)asc->asc.sc_dmasize); 373 trans = asc->asc.sc_dmasize; 374 } 375 376 NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 377 tcl, tcm, trans, resid)); 378 379 *asc->asc.sc_dmalen -= trans; 380 *asc->asc.sc_dmaaddr += trans; 381 382 bus_dmamap_sync(asc->asc.sc_dmat, asc->asc.sc_dmamap, 383 0, asc->asc.sc_dmamap->dm_mapsize, 384 (asc->asc.sc_flags & ASC_ISPULLUP) 385 ? BUS_DMASYNC_POSTREAD 386 : BUS_DMASYNC_POSTWRITE); 387 388 /* 389 * Clean up unaligned DMAs into main memory. 390 */ 391 if (asc->asc.sc_flags & ASC_ISPULLUP) { 392 /* Handle unaligned starting address, length. */ 393 dud = bus_space_read_4(tcds->sc_bst, 394 tcds->sc_bsh, tcds->sc_dud0); 395 if ((dud & TCDS_DUD0_VALIDBITS) != 0) { 396 addr = (u_int32_t *) 397 ((paddr_t)*asc->asc.sc_dmaaddr & ~0x3); 398 dudmask = 0; 399 if (dud & TCDS_DUD0_VALID00) 400 panic("tcds_dma: dud0 byte 0 valid"); 401 if (dud & TCDS_DUD0_VALID01) 402 dudmask |= TCDS_DUD_BYTE01; 403 if (dud & TCDS_DUD0_VALID10) 404 dudmask |= TCDS_DUD_BYTE10; 405 #ifdef DIAGNOSTIC 406 if (dud & TCDS_DUD0_VALID11) 407 dudmask |= TCDS_DUD_BYTE11; 408 #endif 409 NCR_DMA(("dud0 at %p dudmask 0x%x\n", 410 addr, dudmask)); 411 *addr = (*addr & ~dudmask) | (dud & dudmask); 412 } 413 dud = bus_space_read_4(tcds->sc_bst, 414 tcds->sc_bsh, tcds->sc_dud1); 415 if ((dud & TCDS_DUD1_VALIDBITS) != 0) { 416 pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, 417 tcds->sc_sda) << 2; 418 dudmask = 0; 419 if (dud & TCDS_DUD1_VALID00) 420 dudmask |= TCDS_DUD_BYTE00; 421 if (dud & TCDS_DUD1_VALID01) 422 dudmask |= TCDS_DUD_BYTE01; 423 if (dud & TCDS_DUD1_VALID10) 424 dudmask |= TCDS_DUD_BYTE10; 425 #ifdef DIAGNOSTIC 426 if (dud & TCDS_DUD1_VALID11) 427 panic("tcds_dma: dud1 byte 3 valid"); 428 #endif 429 NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n", 430 pa, dudmask)); 431 /* XXX Fix TC_PHYS_TO_UNCACHED() */ 432 #if defined(__alpha__) 433 addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG(pa); 434 #elif defined(__mips__) 435 addr = (u_int32_t *)MIPS_PHYS_TO_KSEG1(pa); 436 #else 437 #error TURBOchannel only exists on DECs, folks... 438 #endif 439 *addr = (*addr & ~dudmask) | (dud & dudmask); 440 } 441 /* XXX deal with saved residual byte? */ 442 } 443 444 bus_dmamap_unload(asc->asc.sc_dmat, asc->asc.sc_dmamap); 445 asc->asc.sc_flags &= ~ASC_MAPLOADED; 446 447 return 0; 448 } 449 450 /* 451 * Glue functions. 452 */ 453 int 454 tcds_dma_isintr(sc) 455 struct ncr53c9x_softc *sc; 456 { 457 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 458 int x; 459 460 x = tcds_scsi_isintr(asc->sc_tcds, 1); 461 462 /* XXX */ 463 return x; 464 } 465 466 int 467 tcds_dma_isactive(sc) 468 struct ncr53c9x_softc *sc; 469 { 470 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 471 472 return !!(asc->asc.sc_flags & ASC_DMAACTIVE); 473 } 474 475 void 476 tcds_clear_latched_intr(sc) 477 struct ncr53c9x_softc *sc; 478 { 479 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 480 481 /* Clear the TCDS interrupt bit. */ 482 (void)tcds_scsi_isintr(asc->sc_tcds, 1); 483 } 484