1 /* $OpenBSD: dwc2_core.h,v 1.9 2015/06/28 11:48:18 jmatthew Exp $ */ 2 /* $NetBSD: dwc2_core.h,v 1.5 2014/04/03 06:34:58 skrll Exp $ */ 3 4 /* 5 * core.h - DesignWare HS OTG Controller common declarations 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef __DWC2_CORE_H__ 41 #define __DWC2_CORE_H__ 42 43 #include <sys/stdint.h> 44 #include <sys/task.h> 45 #include <sys/pool.h> 46 #include <sys/queue.h> 47 #include <sys/device.h> 48 49 #include <machine/intr.h> 50 #include <machine/bus.h> 51 52 #include <dev/usb/dwc2/dwc2_hw.h> 53 54 /* Maximum number of Endpoints/HostChannels */ 55 #define MAX_EPS_CHANNELS 16 56 57 struct dwc2_hsotg; 58 struct dwc2_host_chan; 59 60 /* Device States */ 61 enum dwc2_lx_state { 62 DWC2_L0, /* On state */ 63 DWC2_L1, /* LPM sleep state */ 64 DWC2_L2, /* USB suspend state */ 65 DWC2_L3, /* Off state */ 66 }; 67 68 /** 69 * struct dwc2_core_params - Parameters for configuring the core 70 * 71 * @otg_cap: Specifies the OTG capabilities. 72 * 0 - HNP and SRP capable 73 * 1 - SRP Only capable 74 * 2 - No HNP/SRP capable (always available) 75 * Defaults to best available option (0, 1, then 2) 76 * @otg_ver: OTG version supported 77 * 0 - 1.3 (default) 78 * 1 - 2.0 79 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 80 * the data FIFOs. The driver will automatically detect the 81 * value for this parameter if none is specified. 82 * 0 - Slave (always available) 83 * 1 - DMA (default, if available) 84 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 85 * address DMA mode or descriptor DMA mode for accessing 86 * the data FIFOs. The driver will automatically detect the 87 * value for this if none is specified. 88 * 0 - Address DMA 89 * 1 - Descriptor DMA (default, if available) 90 * @speed: Specifies the maximum speed of operation in host and 91 * device mode. The actual speed depends on the speed of 92 * the attached device and the value of phy_type. 93 * 0 - High Speed 94 * (default when phy_type is UTMI+ or ULPI) 95 * 1 - Full Speed 96 * (default when phy_type is Full Speed) 97 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 98 * 1 - Allow dynamic FIFO sizing (default, if available) 99 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 100 * are enabled 101 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 102 * dynamic FIFO sizing is enabled 103 * 16 to 32768 104 * Actual maximum value is autodetected and also 105 * the default. 106 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 107 * in host mode when dynamic FIFO sizing is enabled 108 * 16 to 32768 109 * Actual maximum value is autodetected and also 110 * the default. 111 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 112 * host mode when dynamic FIFO sizing is enabled 113 * 16 to 32768 114 * Actual maximum value is autodetected and also 115 * the default. 116 * @max_transfer_size: The maximum transfer size supported, in bytes 117 * 2047 to 65,535 118 * Actual maximum value is autodetected and also 119 * the default. 120 * @max_packet_count: The maximum number of packets in a transfer 121 * 15 to 511 122 * Actual maximum value is autodetected and also 123 * the default. 124 * @host_channels: The number of host channel registers to use 125 * 1 to 16 126 * Actual maximum value is autodetected and also 127 * the default. 128 * @phy_type: Specifies the type of PHY interface to use. By default, 129 * the driver will automatically detect the phy_type. 130 * 0 - Full Speed Phy 131 * 1 - UTMI+ Phy 132 * 2 - ULPI Phy 133 * Defaults to best available option (2, 1, then 0) 134 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 135 * is applicable for a phy_type of UTMI+ or ULPI. (For a 136 * ULPI phy_type, this parameter indicates the data width 137 * between the MAC and the ULPI Wrapper.) Also, this 138 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 139 * parameter was set to "8 and 16 bits", meaning that the 140 * core has been configured to work at either data path 141 * width. 142 * 8 or 16 (default 16 if available) 143 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 144 * data rate. This parameter is only applicable if phy_type 145 * is ULPI. 146 * 0 - single data rate ULPI interface with 8 bit wide 147 * data bus (default) 148 * 1 - double data rate ULPI interface with 4 bit wide 149 * data bus 150 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 151 * external supply to drive the VBus 152 * 0 - Internal supply (default) 153 * 1 - External supply 154 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 155 * speed PHY. This parameter is only applicable if phy_type 156 * is FS. 157 * 0 - No (default) 158 * 1 - Yes 159 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 160 * 0 - No (default) 161 * 1 - Yes 162 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 163 * when attached to a Full Speed or Low Speed device in 164 * host mode. 165 * 0 - Don't support low power mode (default) 166 * 1 - Support low power mode 167 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 168 * when connected to a Low Speed device in host 169 * mode. This parameter is applicable only if 170 * host_support_fs_ls_low_power is enabled. 171 * 0 - 48 MHz 172 * (default when phy_type is UTMI+ or ULPI) 173 * 1 - 6 MHz 174 * (default when phy_type is Full Speed) 175 * @ts_dline: Enable Term Select Dline pulsing 176 * 0 - No (default) 177 * 1 - Yes 178 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 179 * 0 - No (default for core < 2.92a) 180 * 1 - Yes (default for core >= 2.92a) 181 * @ahbcfg: This field allows the default value of the GAHBCFG 182 * register to be overridden 183 * -1 - GAHBCFG value will be set to 0x06 184 * (INCR4, default) 185 * all others - GAHBCFG value will be overridden with 186 * this value 187 * Not all bits can be controlled like this, the 188 * bits defined by GAHBCFG_CTRL_MASK are controlled 189 * by the driver and are ignored in this 190 * configuration value. 191 * @uframe_sched: True to enable the microframe scheduler 192 * 193 * The following parameters may be specified when starting the module. These 194 * parameters define how the DWC_otg controller should be configured. A 195 * value of -1 (or any other out of range value) for any parameter means 196 * to read the value from hardware (if possible) or use the builtin 197 * default described above. 198 */ 199 struct dwc2_core_params { 200 /* 201 * Don't add any non-int members here, this will break 202 * dwc2_set_all_params! 203 */ 204 int otg_cap; 205 int otg_ver; 206 int dma_enable; 207 int dma_desc_enable; 208 int speed; 209 int enable_dynamic_fifo; 210 int en_multiple_tx_fifo; 211 int host_rx_fifo_size; 212 int host_nperio_tx_fifo_size; 213 int host_perio_tx_fifo_size; 214 int max_transfer_size; 215 int max_packet_count; 216 int host_channels; 217 int phy_type; 218 int phy_utmi_width; 219 int phy_ulpi_ddr; 220 int phy_ulpi_ext_vbus; 221 int i2c_enable; 222 int ulpi_fs_ls; 223 int host_support_fs_ls_low_power; 224 int host_ls_low_power_phy_clk; 225 int ts_dline; 226 int reload_ctl; 227 int ahbcfg; 228 int uframe_sched; 229 }; 230 231 /** 232 * struct dwc2_hw_params - Autodetected parameters. 233 * 234 * These parameters are the various parameters read from hardware 235 * registers during initialization. They typically contain the best 236 * supported or maximum value that can be configured in the 237 * corresponding dwc2_core_params value. 238 * 239 * The values that are not in dwc2_core_params are documented below. 240 * 241 * @op_mode Mode of Operation 242 * 0 - HNP- and SRP-Capable OTG (Host & Device) 243 * 1 - SRP-Capable OTG (Host & Device) 244 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 245 * 3 - SRP-Capable Device 246 * 4 - Non-OTG Device 247 * 5 - SRP-Capable Host 248 * 6 - Non-OTG Host 249 * @arch Architecture 250 * 0 - Slave only 251 * 1 - External DMA 252 * 2 - Internal DMA 253 * @power_optimized Are power optimizations enabled? 254 * @num_dev_ep Number of device endpoints available 255 * @num_dev_perio_in_ep Number of device periodic IN endpoints 256 * avaialable 257 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 258 * Depth 259 * 0 to 30 260 * @host_perio_tx_q_depth 261 * Host Mode Periodic Request Queue Depth 262 * 2, 4 or 8 263 * @nperio_tx_q_depth 264 * Non-Periodic Request Queue Depth 265 * 2, 4 or 8 266 * @hs_phy_type High-speed PHY interface type 267 * 0 - High-speed interface not supported 268 * 1 - UTMI+ 269 * 2 - ULPI 270 * 3 - UTMI+ and ULPI 271 * @fs_phy_type Full-speed PHY interface type 272 * 0 - Full speed interface not supported 273 * 1 - Dedicated full speed interface 274 * 2 - FS pins shared with UTMI+ pins 275 * 3 - FS pins shared with ULPI pins 276 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 277 * @utmi_phy_data_width UTMI+ PHY data width 278 * 0 - 8 bits 279 * 1 - 16 bits 280 * 2 - 8 or 16 bits 281 * @snpsid: Value from SNPSID register 282 */ 283 struct dwc2_hw_params { 284 unsigned op_mode:3; 285 unsigned arch:2; 286 unsigned dma_desc_enable:1; 287 unsigned enable_dynamic_fifo:1; 288 unsigned en_multiple_tx_fifo:1; 289 unsigned host_rx_fifo_size:16; 290 unsigned host_nperio_tx_fifo_size:16; 291 unsigned host_perio_tx_fifo_size:16; 292 unsigned nperio_tx_q_depth:3; 293 unsigned host_perio_tx_q_depth:3; 294 unsigned dev_token_q_depth:5; 295 unsigned max_transfer_size:26; 296 unsigned max_packet_count:11; 297 unsigned host_channels:5; 298 unsigned hs_phy_type:2; 299 unsigned fs_phy_type:2; 300 unsigned i2c_enable:1; 301 unsigned num_dev_ep:4; 302 unsigned num_dev_perio_in_ep:4; 303 unsigned total_fifo_size:16; 304 unsigned power_optimized:1; 305 unsigned utmi_phy_data_width:2; 306 u32 snpsid; 307 }; 308 309 struct dwc2_core_dma_config { 310 int (*set_dma_addr)(void *, dma_addr_t, int); 311 void *set_dma_addr_data; 312 }; 313 314 TAILQ_HEAD(dwc2_qh_list, dwc2_qh); 315 316 /** 317 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 318 * and periodic schedules 319 * 320 * @dev: The struct device pointer 321 * @regs: Pointer to controller regs 322 * @core_params: Parameters that define how the core should be configured 323 * @hw_params: Parameters that were autodetected from the 324 * hardware registers 325 * @op_state: The operational State, during transitions (a_host=> 326 * a_peripheral and b_device=>b_host) this may not match 327 * the core, but allows the software to determine 328 * transitions 329 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 330 * transfer are in process of being queued 331 * @srp_success: Stores status of SRP request in the case of a FS PHY 332 * with an I2C interface 333 * @wq_otg: Workqueue object used for handling of some interrupts 334 * @wf_otg: Work object for handling Connector ID Status Change 335 * interrupt 336 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 337 * @lx_state: Lx state of connected device 338 * @flags: Flags for handling root port state changes 339 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 340 * Transfers associated with these QHs are not currently 341 * assigned to a host channel. 342 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 343 * Transfers associated with these QHs are currently 344 * assigned to a host channel. 345 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 346 * non-periodic schedule 347 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 348 * list of QHs for periodic transfers that are _not_ 349 * scheduled for the next frame. Each QH in the list has an 350 * interval counter that determines when it needs to be 351 * scheduled for execution. This scheduling mechanism 352 * allows only a simple calculation for periodic bandwidth 353 * used (i.e. must assume that all periodic transfers may 354 * need to execute in the same frame). However, it greatly 355 * simplifies scheduling and should be sufficient for the 356 * vast majority of OTG hosts, which need to connect to a 357 * small number of peripherals at one time. Items move from 358 * this list to periodic_sched_ready when the QH interval 359 * counter is 0 at SOF. 360 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 361 * the next frame, but have not yet been assigned to host 362 * channels. Items move from this list to 363 * periodic_sched_assigned as host channels become 364 * available during the current frame. 365 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 366 * frame that are assigned to host channels. Items move 367 * from this list to periodic_sched_queued as the 368 * transactions for the QH are queued to the DWC_otg 369 * controller. 370 * @periodic_sched_queued: List of periodic QHs that have been queued for 371 * execution. Items move from this list to either 372 * periodic_sched_inactive or periodic_sched_ready when the 373 * channel associated with the transfer is released. If the 374 * interval for the QH is 1, the item moves to 375 * periodic_sched_ready because it must be rescheduled for 376 * the next frame. Otherwise, the item moves to 377 * periodic_sched_inactive. 378 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 379 * This value is in microseconds per (micro)frame. The 380 * assumption is that all periodic transfers may occur in 381 * the same (micro)frame. 382 * @frame_usecs: Internal variable used by the microframe scheduler 383 * @frame_number: Frame number read from the core at SOF. The value ranges 384 * from 0 to HFNUM_MAX_FRNUM. 385 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 386 * SOF enable/disable. 387 * @free_hc_list: Free host channels in the controller. This is a list of 388 * struct dwc2_host_chan items. 389 * @periodic_channels: Number of host channels assigned to periodic transfers. 390 * Currently assuming that there is a dedicated host 391 * channel for each periodic transaction and at least one 392 * host channel is available for non-periodic transactions. 393 * @non_periodic_channels: Number of host channels assigned to non-periodic 394 * transfers 395 * @available_host_channels Number of host channels available for the microframe 396 * scheduler to use 397 * @hc_ptr_array: Array of pointers to the host channel descriptors. 398 * Allows accessing a host channel descriptor given the 399 * host channel number. This is useful in interrupt 400 * handlers. 401 * @status_buf: Buffer used for data received during the status phase of 402 * a control transfer. 403 * @status_buf_dma: DMA address for status_buf 404 * @start_work: Delayed work for handling host A-cable connection 405 * @reset_work: Delayed work for handling a port reset 406 * @lock: Spinlock that protects all the driver data structures 407 * @priv: Stores a pointer to the struct usb_hcd 408 * @otg_port: OTG port number 409 * @frame_list: Frame list 410 * @frame_list_dma: Frame list DMA address 411 */ 412 struct dwc2_hsotg { 413 struct device *dev; 414 struct dwc2_softc *hsotg_sc; 415 /** Params detected from hardware */ 416 struct dwc2_hw_params hw_params; 417 /** Params to actually use */ 418 struct dwc2_core_params *core_params; 419 struct dwc2_core_dma_config *core_dma_config; 420 enum usb_otg_state op_state; 421 422 unsigned int queuing_high_bandwidth:1; 423 unsigned int srp_success:1; 424 425 struct taskq *wq_otg; 426 struct task wf_otg; 427 struct timeout wkp_timer; 428 enum dwc2_lx_state lx_state; 429 430 union dwc2_hcd_internal_flags { 431 u32 d32; 432 struct { 433 unsigned port_connect_status_change:1; 434 unsigned port_connect_status:1; 435 unsigned port_reset_change:1; 436 unsigned port_enable_change:1; 437 unsigned port_suspend_change:1; 438 unsigned port_over_current_change:1; 439 unsigned port_l1_change:1; 440 unsigned reserved:26; 441 } b; 442 } flags; 443 444 struct dwc2_qh_list non_periodic_sched_inactive; 445 struct dwc2_qh_list non_periodic_sched_active; 446 struct dwc2_qh *non_periodic_qh_ptr; 447 struct dwc2_qh_list periodic_sched_inactive; 448 struct dwc2_qh_list periodic_sched_ready; 449 struct dwc2_qh_list periodic_sched_assigned; 450 struct dwc2_qh_list periodic_sched_queued; 451 u16 periodic_usecs; 452 u16 frame_usecs[8]; 453 u16 frame_number; 454 u16 periodic_qh_count; 455 456 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 457 #define FRAME_NUM_ARRAY_SIZE 1000 458 u16 last_frame_num; 459 u16 *frame_num_array; 460 u16 *last_frame_num_array; 461 int frame_num_idx; 462 int dumped_frame_num_array; 463 #endif 464 465 LIST_HEAD(, dwc2_host_chan) free_hc_list; 466 int periodic_channels; 467 int non_periodic_channels; 468 int available_host_channels; 469 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 470 struct usb_dma status_buf_usbdma; 471 u8 *status_buf; 472 dma_addr_t status_buf_dma; 473 #define DWC2_HCD_STATUS_BUF_SIZE 64 474 475 struct delayed_work start_work; 476 struct delayed_work reset_work; 477 spinlock_t lock; 478 void *priv; 479 u8 otg_port; 480 struct usb_dma frame_list_usbdma; 481 u32 *frame_list; 482 dma_addr_t frame_list_dma; 483 484 /* DWC OTG HW Release versions */ 485 #define DWC2_CORE_REV_2_71a 0x4f54271a 486 #define DWC2_CORE_REV_2_90a 0x4f54290a 487 #define DWC2_CORE_REV_2_92a 0x4f54292a 488 #define DWC2_CORE_REV_2_94a 0x4f54294a 489 #define DWC2_CORE_REV_3_00a 0x4f54300a 490 491 #ifdef DEBUG 492 u32 frrem_samples; 493 u64 frrem_accum; 494 495 u32 hfnum_7_samples_a; 496 u64 hfnum_7_frrem_accum_a; 497 u32 hfnum_0_samples_a; 498 u64 hfnum_0_frrem_accum_a; 499 u32 hfnum_other_samples_a; 500 u64 hfnum_other_frrem_accum_a; 501 502 u32 hfnum_7_samples_b; 503 u64 hfnum_7_frrem_accum_b; 504 u32 hfnum_0_samples_b; 505 u64 hfnum_0_frrem_accum_b; 506 u32 hfnum_other_samples_b; 507 u64 hfnum_other_frrem_accum_b; 508 #endif 509 }; 510 511 /* Reasons for halting a host channel */ 512 enum dwc2_halt_status { 513 DWC2_HC_XFER_NO_HALT_STATUS, 514 DWC2_HC_XFER_COMPLETE, 515 DWC2_HC_XFER_URB_COMPLETE, 516 DWC2_HC_XFER_ACK, 517 DWC2_HC_XFER_NAK, 518 DWC2_HC_XFER_NYET, 519 DWC2_HC_XFER_STALL, 520 DWC2_HC_XFER_XACT_ERR, 521 DWC2_HC_XFER_FRAME_OVERRUN, 522 DWC2_HC_XFER_BABBLE_ERR, 523 DWC2_HC_XFER_DATA_TOGGLE_ERR, 524 DWC2_HC_XFER_AHB_ERR, 525 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 526 DWC2_HC_XFER_URB_DEQUEUE, 527 }; 528 529 /* 530 * The following functions support initialization of the core driver component 531 * and the DWC_otg controller 532 */ 533 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 534 535 /* 536 * Host core Functions. 537 * The following functions support managing the DWC_otg controller in host 538 * mode. 539 */ 540 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 541 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 542 enum dwc2_halt_status halt_status); 543 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 544 struct dwc2_host_chan *chan); 545 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 546 struct dwc2_host_chan *chan); 547 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 548 struct dwc2_host_chan *chan); 549 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 550 struct dwc2_host_chan *chan); 551 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 552 struct dwc2_host_chan *chan); 553 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 554 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 555 556 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 557 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 558 559 /* 560 * Common core Functions. 561 * The following functions support managing the DWC_otg controller in either 562 * device or host mode. 563 */ 564 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 565 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 566 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 567 568 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy); 569 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 570 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 571 572 /* This function should be called on every hardware interrupt. */ 573 extern irqreturn_t dwc2_handle_common_intr(void *dev); 574 575 /* OTG Core Parameters */ 576 577 /* 578 * Specifies the OTG capabilities. The driver will automatically 579 * detect the value for this parameter if none is specified. 580 * 0 - HNP and SRP capable (default) 581 * 1 - SRP Only capable 582 * 2 - No HNP/SRP capable 583 */ 584 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 585 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 586 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 587 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 588 589 /* 590 * Specifies whether to use slave or DMA mode for accessing the data 591 * FIFOs. The driver will automatically detect the value for this 592 * parameter if none is specified. 593 * 0 - Slave 594 * 1 - DMA (default, if available) 595 */ 596 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 597 598 /* 599 * When DMA mode is enabled specifies whether to use 600 * address DMA or DMA Descritor mode for accessing the data 601 * FIFOs in device mode. The driver will automatically detect 602 * the value for this parameter if none is specified. 603 * 0 - address DMA 604 * 1 - DMA Descriptor(default, if available) 605 */ 606 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 607 608 /* 609 * Specifies the maximum speed of operation in host and device mode. 610 * The actual speed depends on the speed of the attached device and 611 * the value of phy_type. The actual speed depends on the speed of the 612 * attached device. 613 * 0 - High Speed (default) 614 * 1 - Full Speed 615 */ 616 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 617 #define DWC2_SPEED_PARAM_HIGH 0 618 #define DWC2_SPEED_PARAM_FULL 1 619 620 /* 621 * Specifies whether low power mode is supported when attached 622 * to a Full Speed or Low Speed device in host mode. 623 * 624 * 0 - Don't support low power mode (default) 625 * 1 - Support low power mode 626 */ 627 extern void dwc2_set_param_host_support_fs_ls_low_power( 628 struct dwc2_hsotg *hsotg, int val); 629 630 /* 631 * Specifies the PHY clock rate in low power mode when connected to a 632 * Low Speed device in host mode. This parameter is applicable only if 633 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 634 * then defaults to 6 MHZ otherwise 48 MHZ. 635 * 636 * 0 - 48 MHz 637 * 1 - 6 MHz 638 */ 639 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 640 int val); 641 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 642 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 643 644 /* 645 * 0 - Use cC FIFO size parameters 646 * 1 - Allow dynamic FIFO sizing (default) 647 */ 648 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 649 int val); 650 651 /* 652 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 653 * FIFO sizing is enabled. 654 * 16 to 32768 (default 1024) 655 */ 656 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 657 658 /* 659 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 660 * when Dynamic FIFO sizing is enabled in the core. 661 * 16 to 32768 (default 256) 662 */ 663 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 664 int val); 665 666 /* 667 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 668 * FIFO sizing is enabled. 669 * 16 to 32768 (default 256) 670 */ 671 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 672 int val); 673 674 /* 675 * The maximum transfer size supported in bytes. 676 * 2047 to 65,535 (default 65,535) 677 */ 678 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 679 680 /* 681 * The maximum number of packets in a transfer. 682 * 15 to 511 (default 511) 683 */ 684 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 685 686 /* 687 * The number of host channel registers to use. 688 * 1 to 16 (default 11) 689 * Note: The FPGA configuration supports a maximum of 11 host channels. 690 */ 691 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 692 693 /* 694 * Specifies the type of PHY interface to use. By default, the driver 695 * will automatically detect the phy_type. 696 * 697 * 0 - Full Speed PHY 698 * 1 - UTMI+ (default) 699 * 2 - ULPI 700 */ 701 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 702 #define DWC2_PHY_TYPE_PARAM_FS 0 703 #define DWC2_PHY_TYPE_PARAM_UTMI 1 704 #define DWC2_PHY_TYPE_PARAM_ULPI 2 705 706 /* 707 * Specifies the UTMI+ Data Width. This parameter is 708 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 709 * PHY_TYPE, this parameter indicates the data width between 710 * the MAC and the ULPI Wrapper.) Also, this parameter is 711 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 712 * to "8 and 16 bits", meaning that the core has been 713 * configured to work at either data path width. 714 * 715 * 8 or 16 bits (default 16) 716 */ 717 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 718 719 /* 720 * Specifies whether the ULPI operates at double or single 721 * data rate. This parameter is only applicable if PHY_TYPE is 722 * ULPI. 723 * 724 * 0 - single data rate ULPI interface with 8 bit wide data 725 * bus (default) 726 * 1 - double data rate ULPI interface with 4 bit wide data 727 * bus 728 */ 729 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 730 731 /* 732 * Specifies whether to use the internal or external supply to 733 * drive the vbus with a ULPI phy. 734 */ 735 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 736 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 737 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 738 739 /* 740 * Specifies whether to use the I2Cinterface for full speed PHY. This 741 * parameter is only applicable if PHY_TYPE is FS. 742 * 0 - No (default) 743 * 1 - Yes 744 */ 745 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 746 747 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 748 749 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 750 751 /* 752 * Specifies whether dedicated transmit FIFOs are 753 * enabled for non periodic IN endpoints in device mode 754 * 0 - No 755 * 1 - Yes 756 */ 757 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 758 int val); 759 760 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 761 762 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 763 764 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 765 766 /* 767 * Dump core registers and SPRAM 768 */ 769 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 770 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 771 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 772 773 /* 774 * Return OTG version - either 1.3 or 2.0 775 */ 776 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 777 778 #endif /* __DWC2_CORE_H__ */ 779