1 /* $OpenBSD: dwc2_hcd.h,v 1.16 2022/09/04 08:42:40 mglocker Exp $ */ 2 /* $NetBSD: dwc2_hcd.h,v 1.9 2014/09/03 10:00:08 skrll Exp $ */ 3 4 /* 5 * hcd.h - DesignWare HS OTG Controller host-mode declarations 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 #ifndef __DWC2_HCD_H__ 40 #define __DWC2_HCD_H__ 41 42 /* 43 * This file contains the structures, constants, and interfaces for the 44 * Host Contoller Driver (HCD) 45 * 46 * The Host Controller Driver (HCD) is responsible for translating requests 47 * from the USB Driver into the appropriate actions on the DWC_otg controller. 48 * It isolates the USBD from the specifics of the controller by providing an 49 * API to the USBD. 50 */ 51 52 struct dwc2_qh; 53 54 /** 55 * struct dwc2_host_chan - Software host channel descriptor 56 * 57 * @hc_num: Host channel number, used for register address lookup 58 * @dev_addr: Address of the device 59 * @ep_num: Endpoint of the device 60 * @ep_is_in: Endpoint direction 61 * @speed: Device speed. One of the following values: 62 * - USB_SPEED_LOW 63 * - USB_SPEED_FULL 64 * - USB_SPEED_HIGH 65 * @ep_type: Endpoint type. One of the following values: 66 * - USB_ENDPOINT_XFER_CONTROL: 0 67 * - USB_ENDPOINT_XFER_ISOC: 1 68 * - USB_ENDPOINT_XFER_BULK: 2 69 * - USB_ENDPOINT_XFER_INTR: 3 70 * @max_packet: Max packet size in bytes 71 * @data_pid_start: PID for initial transaction. 72 * 0: DATA0 73 * 1: DATA2 74 * 2: DATA1 75 * 3: MDATA (non-Control EP), 76 * SETUP (Control EP) 77 * @multi_count: Number of additional periodic transactions per 78 * (micro)frame 79 * @xfer_buf: Pointer to current transfer buffer position 80 * @xfer_dma: DMA address of xfer_buf 81 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not 82 * DWORD aligned 83 * @xfer_len: Total number of bytes to transfer 84 * @xfer_count: Number of bytes transferred so far 85 * @start_pkt_count: Packet count at start of transfer 86 * @xfer_started: True if the transfer has been started 87 * @do_ping: True if a PING request should be issued on this channel 88 * @error_state: True if the error count for this transaction is non-zero 89 * @halt_on_queue: True if this channel should be halted the next time a 90 * request is queued for the channel. This is necessary in 91 * slave mode if no request queue space is available when 92 * an attempt is made to halt the channel. 93 * @halt_pending: True if the host channel has been halted, but the core 94 * is not finished flushing queued requests 95 * @do_split: Enable split for the channel 96 * @complete_split: Enable complete split 97 * @hub_addr: Address of high speed hub for the split 98 * @hub_port: Port of the low/full speed device for the split 99 * @xact_pos: Split transaction position. One of the following values: 100 * - DWC2_HCSPLT_XACTPOS_MID 101 * - DWC2_HCSPLT_XACTPOS_BEGIN 102 * - DWC2_HCSPLT_XACTPOS_END 103 * - DWC2_HCSPLT_XACTPOS_ALL 104 * @requests: Number of requests issued for this channel since it was 105 * assigned to the current transfer (not counting PINGs) 106 * @schinfo: Scheduling micro-frame bitmap 107 * @ntd: Number of transfer descriptors for the transfer 108 * @halt_status: Reason for halting the host channel 109 * @hcint: Contents of the HCINT register when the interrupt came 110 * @qh: QH for the transfer being processed by this channel 111 * @hc_list_entry: For linking to list of host channels 112 * @desc_list_addr: Current QH's descriptor list DMA address 113 * @desc_list_sz: Current QH's descriptor list size 114 * @split_order_list_entry: List entry for keeping track of the order of splits 115 * 116 * This structure represents the state of a single host channel when acting in 117 * host mode. It contains the data items needed to transfer packets to an 118 * endpoint via a host channel. 119 */ 120 struct dwc2_host_chan { 121 u8 hc_num; 122 123 unsigned dev_addr:7; 124 unsigned ep_num:4; 125 unsigned ep_is_in:1; 126 unsigned speed:4; 127 unsigned ep_type:2; 128 unsigned max_packet:11; 129 unsigned data_pid_start:2; 130 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 131 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 132 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 133 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 134 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 135 136 unsigned multi_count:2; 137 138 struct usb_dma *xfer_usbdma; 139 u8 *xfer_buf; 140 dma_addr_t xfer_dma; 141 dma_addr_t align_buf; 142 u32 xfer_len; 143 u32 xfer_count; 144 u16 start_pkt_count; 145 u8 xfer_started; 146 u8 do_ping; 147 u8 error_state; 148 u8 halt_on_queue; 149 u8 halt_pending; 150 u8 do_split; 151 u8 complete_split; 152 u8 hub_addr; 153 u8 hub_port; 154 u8 xact_pos; 155 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 156 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 157 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 158 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 159 160 u8 requests; 161 u8 schinfo; 162 u16 ntd; 163 enum dwc2_halt_status halt_status; 164 u32 hcint; 165 struct dwc2_qh *qh; 166 struct list_head hc_list_entry; 167 struct usb_dma desc_list_usbdma; 168 dma_addr_t desc_list_addr; 169 u32 desc_list_sz; 170 struct list_head split_order_list_entry; 171 }; 172 173 struct dwc2_hcd_pipe_info { 174 u8 dev_addr; 175 u8 ep_num; 176 u8 pipe_type; 177 u8 pipe_dir; 178 u16 maxp; 179 u16 maxp_mult; 180 }; 181 182 struct dwc2_hcd_iso_packet_desc { 183 u32 offset; 184 u32 length; 185 u32 actual_length; 186 u32 status; 187 }; 188 189 struct dwc2_qtd; 190 191 struct dwc2_hcd_urb { 192 void *priv; 193 struct dwc2_qtd *qtd; 194 struct usb_dma *usbdma; 195 void *buf; 196 dma_addr_t dma; 197 struct usb_dma *setup_usbdma; 198 void *setup_packet; 199 dma_addr_t setup_dma; 200 u32 length; 201 u32 actual_length; 202 u32 status; 203 u32 error_count; 204 u32 packet_count; 205 u32 flags; 206 u16 interval; 207 struct dwc2_hcd_pipe_info pipe_info; 208 struct dwc2_hcd_iso_packet_desc iso_descs[]; 209 }; 210 211 /* Phases for control transfers */ 212 enum dwc2_control_phase { 213 DWC2_CONTROL_SETUP, 214 DWC2_CONTROL_DATA, 215 DWC2_CONTROL_STATUS, 216 }; 217 218 /* Transaction types */ 219 enum dwc2_transaction_type { 220 DWC2_TRANSACTION_NONE, 221 DWC2_TRANSACTION_PERIODIC, 222 DWC2_TRANSACTION_NON_PERIODIC, 223 DWC2_TRANSACTION_ALL, 224 }; 225 226 /* The number of elements per LS bitmap (per port on multi_tt) */ 227 #define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \ 228 BITS_PER_LONG) 229 230 /** 231 * struct dwc2_tt - dwc2 data associated with a usb_tt 232 * 233 * @refcount: Number of Queue Heads (QHs) holding a reference. 234 * @usb_tt: Pointer back to the official usb_tt. 235 * @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted 236 * for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP 237 * elements (so sizeof(long) times that in bytes). 238 * 239 * This structure is stored in the hcpriv of the official usb_tt. 240 */ 241 struct dwc2_tt { 242 int refcount; 243 struct usbd_tt *usb_tt; 244 unsigned long periodic_bitmaps[]; 245 }; 246 247 /** 248 * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus. 249 * 250 * @start_schedule_us: The start time on the main bus schedule. Note that 251 * the main bus schedule is tightly packed and this 252 * time should be interpreted as tightly packed (so 253 * uFrame 0 starts at 0 us, uFrame 1 starts at 100 us 254 * instead of 125 us). 255 * @duration_us: How long this transfer goes. 256 */ 257 258 struct dwc2_hs_transfer_time { 259 u32 start_schedule_us; 260 u16 duration_us; 261 }; 262 263 /** 264 * struct dwc2_qh - Software queue head structure 265 * 266 * @hsotg: The HCD state structure for the DWC OTG controller 267 * @ep_type: Endpoint type. One of the following values: 268 * - USB_ENDPOINT_XFER_CONTROL 269 * - USB_ENDPOINT_XFER_BULK 270 * - USB_ENDPOINT_XFER_INT 271 * - USB_ENDPOINT_XFER_ISOC 272 * @ep_is_in: Endpoint direction 273 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 274 * @maxp_mult: Multiplier for maxp 275 * @dev_speed: Device speed. One of the following values: 276 * - USB_SPEED_LOW 277 * - USB_SPEED_FULL 278 * - USB_SPEED_HIGH 279 * @data_toggle: Determines the PID of the next data packet for 280 * non-controltransfers. Ignored for control transfers. 281 * One of the following values: 282 * - DWC2_HC_PID_DATA0 283 * - DWC2_HC_PID_DATA1 284 * @ping_state: Ping state 285 * @do_split: Full/low speed endpoint on high-speed hub requires split 286 * @td_first: Index of first activated isochronous transfer descriptor 287 * @td_last: Index of last activated isochronous transfer descriptor 288 * @host_us: Bandwidth in microseconds per transfer as seen by host 289 * @device_us: Bandwidth in microseconds per transfer as seen by device 290 * @host_interval: Interval between transfers as seen by the host. If 291 * the host is high speed and the device is low speed this 292 * will be 8 times device interval. 293 * @device_interval: Interval between transfers as seen by the device. 294 * interval. 295 * @next_active_frame: (Micro)frame _before_ we next need to put something on 296 * the bus. We'll move the qh to active here. If the 297 * host is in high speed mode this will be a uframe. If 298 * the host is in low speed mode this will be a full frame. 299 * @start_active_frame: If we are partway through a split transfer, this will be 300 * what next_active_frame was when we started. Otherwise 301 * it should always be the same as next_active_frame. 302 * @num_hs_transfers: Number of transfers in hs_transfers. 303 * Normally this is 1 but can be more than one for splits. 304 * Always >= 1 unless the host is in low/full speed mode. 305 * @hs_transfers: Transfers that are scheduled as seen by the high speed 306 * bus. Not used if host is in low or full speed mode (but 307 * note that it IS USED if the device is low or full speed 308 * as long as the HOST is in high speed mode). 309 * @ls_start_schedule_slice: Start time (in slices) on the low speed bus 310 * schedule that's being used by this device. This 311 * will be on the periodic_bitmap in a 312 * "struct dwc2_tt". Not used if this device is high 313 * speed. Note that this is in "schedule slice" which 314 * is tightly packed. 315 * @ntd: Actual number of transfer descriptors in a list 316 * @dw_align_buf: Used instead of original buffer if its physical address 317 * is not dword-aligned 318 * @dw_align_buf_dma: DMA address for dw_align_buf 319 * @qtd_list: List of QTDs for this QH 320 * @channel: Host channel currently processing transfers for this QH 321 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 322 * schedule 323 * @desc_list: List of transfer descriptors 324 * @desc_list_dma: Physical address of desc_list 325 * @desc_list_sz: Size of descriptors list 326 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 327 * descriptor and indicates original XferSize value for the 328 * descriptor 329 * @unreserve_timer: Timer for releasing periodic reservation. 330 * @wait_timer: Timer used to wait before re-queuing. 331 * @dwc_tt: Pointer to our tt info (or NULL if no tt). 332 * @ttport: Port number within our tt. 333 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 334 * @unreserve_pending: True if we planned to unreserve but haven't yet. 335 * @schedule_low_speed: True if we have a low/full speed component (either the 336 * host is in low/full speed mode or do_split). 337 * @want_wait: We should wait before re-queuing; only matters for non- 338 * periodic transfers and is ignored for periodic ones. 339 * @wait_timer_cancel: Set to true to cancel the wait_timer. 340 * 341 * @tt_buffer_dirty: True if EP's TT buffer is not clean. 342 * A Queue Head (QH) holds the static characteristics of an endpoint and 343 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 344 * be entered in either the non-periodic or periodic schedule. 345 */ 346 struct dwc2_qh { 347 struct dwc2_hsotg *hsotg; 348 u8 ep_type; 349 u8 ep_is_in; 350 u16 maxp; 351 u16 maxp_mult; 352 u8 dev_speed; 353 u8 data_toggle; 354 u8 ping_state; 355 u8 do_split; 356 u8 td_first; 357 u8 td_last; 358 u16 host_us; 359 u16 device_us; 360 u16 host_interval; 361 u16 device_interval; 362 u16 next_active_frame; 363 u16 start_active_frame; 364 s16 num_hs_transfers; 365 struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES]; 366 u32 ls_start_schedule_slice; 367 u16 ntd; 368 u8 *dw_align_buf; 369 int dw_align_buf_size; 370 dma_addr_t dw_align_buf_dma; 371 struct usb_dma dw_align_buf_usbdma; 372 struct list_head qtd_list; 373 struct dwc2_host_chan *channel; 374 struct list_head qh_list_entry; 375 struct usb_dma desc_list_usbdma; 376 struct dwc2_dma_desc *desc_list; 377 dma_addr_t desc_list_dma; 378 u32 desc_list_sz; 379 u32 *n_bytes; 380 struct timeout unreserve_timer; 381 struct timeout wait_timer; 382 struct dwc2_tt *dwc_tt; 383 int ttport; 384 unsigned tt_buffer_dirty:1; 385 unsigned unreserve_pending:1; 386 unsigned schedule_low_speed:1; 387 unsigned want_wait:1; 388 unsigned wait_timer_cancel:1; 389 }; 390 391 /** 392 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 393 * 394 * @control_phase: Current phase for control transfers (Setup, Data, or 395 * Status) 396 * @in_process: Indicates if this QTD is currently processed by HW 397 * @data_toggle: Determines the PID of the next data packet for the 398 * data phase of control transfers. Ignored for other 399 * transfer types. One of the following values: 400 * - DWC2_HC_PID_DATA0 401 * - DWC2_HC_PID_DATA1 402 * @complete_split: Keeps track of the current split type for FS/LS 403 * endpoints on a HS Hub 404 * @isoc_split_pos: Position of the ISOC split in full/low speed 405 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 406 * transfer. A frame descriptor describes the buffer 407 * position and length of the data to be transferred in the 408 * next scheduled (micro)frame of an isochronous transfer. 409 * It also holds status for that transaction. The frame 410 * index starts at 0. 411 * @isoc_split_offset: Position of the ISOC split in the buffer for the 412 * current frame 413 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 414 * @error_count: Holds the number of bus errors that have occurred for 415 * a transaction within this transfer 416 * @n_desc: Number of DMA descriptors for this QTD 417 * @isoc_frame_index_last: Last activated frame (packet) index, used in 418 * descriptor DMA mode only 419 * @num_naks: Number of NAKs received on this QTD. 420 * @urb: URB for this transfer 421 * @qh: Queue head for this QTD 422 * @qtd_list_entry: For linking to the QH's list of QTDs 423 * @isoc_td_first: Index of first activated isochronous transfer 424 * descriptor in Descriptor DMA mode 425 * @isoc_td_last: Index of last activated isochronous transfer 426 * descriptor in Descriptor DMA mode 427 * 428 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 429 * interrupt, or isochronous transfer. A single QTD is created for each URB 430 * (of one of these types) submitted to the HCD. The transfer associated with 431 * a QTD may require one or multiple transactions. 432 * 433 * A QTD is linked to a Queue Head, which is entered in either the 434 * non-periodic or periodic schedule for execution. When a QTD is chosen for 435 * execution, some or all of its transactions may be executed. After 436 * execution, the state of the QTD is updated. The QTD may be retired if all 437 * its transactions are complete or if an error occurred. Otherwise, it 438 * remains in the schedule so more transactions can be executed later. 439 */ 440 struct dwc2_qtd { 441 enum dwc2_control_phase control_phase; 442 u8 in_process; 443 u8 data_toggle; 444 u8 complete_split; 445 u8 isoc_split_pos; 446 u16 isoc_frame_index; 447 u16 isoc_split_offset; 448 u16 isoc_td_last; 449 u16 isoc_td_first; 450 u32 ssplit_out_xfer_count; 451 u8 error_count; 452 u8 n_desc; 453 u16 isoc_frame_index_last; 454 u16 num_naks; 455 struct dwc2_hcd_urb *urb; 456 struct dwc2_qh *qh; 457 struct list_head qtd_list_entry; 458 }; 459 460 #ifdef DEBUG 461 struct hc_xfer_info { 462 struct dwc2_hsotg *hsotg; 463 struct dwc2_host_chan *chan; 464 }; 465 #endif 466 467 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 468 469 #if 0 470 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 471 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 472 { 473 return (struct usb_hcd *)hsotg->priv; 474 } 475 #endif 476 477 /* 478 * Inline used to disable one channel interrupt. Channel interrupts are 479 * disabled when the channel is halted or released by the interrupt handler. 480 * There is no need to handle further interrupts of that type until the 481 * channel is re-assigned. In fact, subsequent handling may cause crashes 482 * because the channel structures are cleaned up when the channel is released. 483 */ 484 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 485 { 486 u32 mask = dwc2_readl(hsotg, HCINTMSK(chnum)); 487 488 mask &= ~intr; 489 dwc2_writel(hsotg, mask, HCINTMSK(chnum)); 490 } 491 492 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 493 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 494 enum dwc2_halt_status halt_status); 495 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 496 struct dwc2_host_chan *chan); 497 498 /* 499 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 500 * are read as 1, they won't clear when written back. 501 */ 502 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 503 { 504 u32 hprt0 = dwc2_readl(hsotg, HPRT0); 505 506 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 507 return hprt0; 508 } 509 510 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 511 { 512 return pipe->ep_num; 513 } 514 515 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 516 { 517 return pipe->pipe_type; 518 } 519 520 static inline u16 dwc2_hcd_get_maxp(struct dwc2_hcd_pipe_info *pipe) 521 { 522 return pipe->maxp; 523 } 524 525 static inline u16 dwc2_hcd_get_maxp_mult(struct dwc2_hcd_pipe_info *pipe) 526 { 527 return pipe->maxp_mult; 528 } 529 530 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 531 { 532 return pipe->dev_addr; 533 } 534 535 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 536 { 537 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 538 } 539 540 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 541 { 542 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 543 } 544 545 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 546 { 547 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 548 } 549 550 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 551 { 552 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 553 } 554 555 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 556 { 557 return pipe->pipe_dir == USB_DIR_IN; 558 } 559 560 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 561 { 562 return !dwc2_hcd_is_pipe_in(pipe); 563 } 564 565 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg); 566 //extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 567 568 /* Transaction Execution Functions */ 569 extern enum dwc2_transaction_type dwc2_hcd_select_transactions( 570 struct dwc2_hsotg *hsotg); 571 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 572 enum dwc2_transaction_type tr_type); 573 574 /* Schedule Queue Functions */ 575 /* Implemented in hcd_queue.c */ 576 extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg); 577 extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 578 struct dwc2_hcd_urb *urb, 579 gfp_t mem_flags); 580 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 581 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 582 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 583 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 584 int sched_csplit); 585 586 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 587 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 588 struct dwc2_qh *qh); 589 590 /* Unlinks and frees a QTD */ 591 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 592 struct dwc2_qtd *qtd, 593 struct dwc2_qh *qh) 594 { 595 struct dwc2_softc *sc = hsotg->hsotg_sc; 596 597 list_del(&qtd->qtd_list_entry); 598 pool_put(&sc->sc_qtdpool, qtd); 599 } 600 601 /* Descriptor DMA support functions */ 602 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 603 struct dwc2_qh *qh); 604 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 605 struct dwc2_host_chan *chan, int chnum, 606 enum dwc2_halt_status halt_status); 607 608 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 609 gfp_t mem_flags); 610 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 611 612 /* Check if QH is non-periodic */ 613 #define dwc2_qh_is_non_per(_qh_ptr_) \ 614 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 615 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 616 617 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 618 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 619 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 620 static inline bool dbg_urb(struct urb *urb) { return true; } 621 static inline bool dbg_perio(void) { return true; } 622 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 623 static inline bool dbg_hc(struct dwc2_host_chan *hc) 624 { 625 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 626 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 627 } 628 629 static inline bool dbg_qh(struct dwc2_qh *qh) 630 { 631 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 632 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 633 } 634 635 #if 0 636 static inline bool dbg_urb(struct urb *urb) 637 { 638 return usb_pipetype(urb->pipe) == PIPE_BULK || 639 usb_pipetype(urb->pipe) == PIPE_CONTROL; 640 } 641 #endif 642 643 static inline bool dbg_perio(void) { return false; } 644 #endif 645 646 /* 647 * Returns true if frame1 index is greater than frame2 index. The comparison 648 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the 649 * frame number when the max index frame number is reached. 650 */ 651 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2) 652 { 653 u16 diff = fr_idx1 - fr_idx2; 654 u16 sign = diff & (FRLISTEN_64_SIZE >> 1); 655 656 return diff && !sign; 657 } 658 659 /* 660 * Returns true if frame1 is less than or equal to frame2. The comparison is 661 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 662 * frame number when the max frame number is reached. 663 */ 664 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 665 { 666 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 667 } 668 669 /* 670 * Returns true if frame1 is greater than frame2. The comparison is done 671 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 672 * number when the max frame number is reached. 673 */ 674 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 675 { 676 return (frame1 != frame2) && 677 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 678 } 679 680 /* 681 * Increments frame by the amount specified by inc. The addition is done 682 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 683 */ 684 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 685 { 686 return (frame + inc) & HFNUM_MAX_FRNUM; 687 } 688 689 static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec) 690 { 691 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM; 692 } 693 694 static inline u16 dwc2_full_frame_num(u16 frame) 695 { 696 return (frame & HFNUM_MAX_FRNUM) >> 3; 697 } 698 699 static inline u16 dwc2_micro_frame_num(u16 frame) 700 { 701 return frame & 0x7; 702 } 703 704 /* 705 * Returns the Core Interrupt Status register contents, ANDed with the Core 706 * Interrupt Mask register contents 707 */ 708 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 709 { 710 return dwc2_readl(hsotg, GINTSTS) & 711 dwc2_readl(hsotg, GINTMSK); 712 } 713 714 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 715 { 716 return dwc2_urb->status; 717 } 718 719 static inline u32 dwc2_hcd_urb_get_actual_length( 720 struct dwc2_hcd_urb *dwc2_urb) 721 { 722 return dwc2_urb->actual_length; 723 } 724 725 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 726 { 727 return dwc2_urb->error_count; 728 } 729 730 static inline void dwc2_hcd_urb_set_iso_desc_params( 731 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 732 u32 length) 733 { 734 dwc2_urb->iso_descs[desc_num].offset = offset; 735 dwc2_urb->iso_descs[desc_num].length = length; 736 } 737 738 static inline u32 dwc2_hcd_urb_get_iso_desc_status( 739 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 740 { 741 return dwc2_urb->iso_descs[desc_num].status; 742 } 743 744 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 745 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 746 { 747 return dwc2_urb->iso_descs[desc_num].actual_length; 748 } 749 750 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 751 struct usbd_xfer *xfer) 752 { 753 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 754 struct dwc2_qh *qh = dpipe->priv; 755 756 if (qh && !list_empty(&qh->qh_list_entry)) 757 return 1; 758 759 return 0; 760 } 761 762 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 763 struct dwc2_pipe *dpipe) 764 { 765 struct dwc2_qh *qh = dpipe->priv; 766 767 if (!qh) { 768 WARN_ON(1); 769 return 0; 770 } 771 772 return qh->host_us; 773 } 774 775 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 776 struct dwc2_host_chan *chan, int chnum, 777 struct dwc2_qtd *qtd); 778 779 /* HCD Core API */ 780 781 /** 782 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 783 * 784 * @hsotg: The DWC2 HCD 785 * 786 * Returns IRQ_HANDLED if interrupt is handled 787 * Return IRQ_NONE if interrupt is not handled 788 */ 789 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 790 791 /** 792 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 793 * 794 * @hsotg: The DWC2 HCD 795 */ 796 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 797 798 /** 799 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 800 * and 0 otherwise 801 * 802 * @hsotg: The DWC2 HCD 803 */ 804 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 805 806 /** 807 * dwc2_hcd_dump_state() - Dumps hsotg state 808 * 809 * @hsotg: The DWC2 HCD 810 * 811 * NOTE: This function will be removed once the peripheral controller code 812 * is integrated and the driver is stable 813 */ 814 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 815 816 /* URB interface */ 817 818 /* Transfer flags */ 819 #define URB_GIVEBACK_ASAP 0x1 820 #define URB_SEND_ZERO_PACKET 0x2 821 822 /* Host driver callbacks */ 823 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, 824 void *context, gfp_t mem_flags, 825 int *ttport); 826 827 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, 828 struct dwc2_tt *dwc_tt); 829 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 830 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 831 int status); 832 833 /* Required for OpenBSD */ 834 struct dwc2_hcd_urb * dwc2_hcd_urb_alloc(struct dwc2_hsotg *, int, gfp_t); 835 void dwc2_hcd_urb_free(struct dwc2_hsotg *, struct dwc2_hcd_urb *, int); 836 int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *, struct dwc2_hcd_urb *); 837 int dwc2_hcd_hub_control(struct dwc2_hsotg *, u16, u16, u16, char *, u16); 838 void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *, struct dwc2_hcd_urb *, 839 u8, u8, u8, u8, u16, u16); 840 841 int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 842 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 843 struct dwc2_qtd *qtd); 844 void dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *, u16, struct usbd_xfer *); 845 846 long dwc2_usb_calc_bus_time(int, int, int, int); 847 int dwc2_ttthink_to_ns(struct dwc2_hsotg *, void *, int); 848 849 #endif /* __DWC2_HCD_H__ */ 850