1 /* $OpenBSD: dwc2_hcdqueue.c,v 1.9 2017/09/08 05:36:53 deraadt Exp $ */ 2 /* $NetBSD: dwc2_hcdqueue.c,v 1.11 2014/09/03 10:00:08 skrll Exp $ */ 3 4 /* 5 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * This file contains the functions to manage Queue Heads and Queue 42 * Transfer Descriptors for Host mode 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/pool.h> 49 50 #include <machine/bus.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 #include <dev/usb/usbdivar.h> 55 #include <dev/usb/usb_mem.h> 56 57 #include <dev/usb/dwc2/dwc2.h> 58 #include <dev/usb/dwc2/dwc2var.h> 59 60 #include <dev/usb/dwc2/dwc2_core.h> 61 #include <dev/usb/dwc2/dwc2_hcd.h> 62 63 STATIC u32 dwc2_calc_bus_time(struct dwc2_hsotg *, int, int, int, int); 64 65 /** 66 * dwc2_qh_init() - Initializes a QH structure 67 * 68 * @hsotg: The HCD state structure for the DWC OTG controller 69 * @qh: The QH to init 70 * @urb: Holds the information about the device/endpoint needed to initialize 71 * the QH 72 */ 73 #define SCHEDULE_SLOP 10 74 STATIC void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 75 struct dwc2_hcd_urb *urb) 76 { 77 int dev_speed, hub_addr, hub_port; 78 79 dev_vdbg(hsotg->dev, "%s()\n", __func__); 80 81 /* Initialize QH */ 82 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 83 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; 84 85 qh->data_toggle = DWC2_HC_PID_DATA0; 86 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info); 87 TAILQ_INIT(&qh->qtd_list); 88 qh->linked = 0; 89 90 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */ 91 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 92 93 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 94 qh->nak_frame = 0xffff; 95 96 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) && 97 hub_addr != 0 && hub_addr != 1) { 98 dev_vdbg(hsotg->dev, 99 "QH init: EP %d: TT found at hub addr %d, for port %d\n", 100 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr, 101 hub_port); 102 qh->do_split = 1; 103 } 104 105 if (qh->ep_type == USB_ENDPOINT_XFER_INT || 106 qh->ep_type == USB_ENDPOINT_XFER_ISOC) { 107 /* Compute scheduling parameters once and save them */ 108 u32 hprt, prtspd; 109 110 /* Todo: Account for split transfers in the bus time */ 111 int bytecount = 112 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp); 113 114 qh->usecs = dwc2_calc_bus_time(hsotg, qh->do_split ? 115 USB_SPEED_HIGH : dev_speed, qh->ep_is_in, 116 qh->ep_type == USB_ENDPOINT_XFER_ISOC, 117 bytecount); 118 /* Start in a slightly future (micro)frame */ 119 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number, 120 SCHEDULE_SLOP); 121 qh->interval = urb->interval; 122 #if 0 123 /* Increase interrupt polling rate for debugging */ 124 if (qh->ep_type == USB_ENDPOINT_XFER_INT) 125 qh->interval = 8; 126 #endif 127 hprt = DWC2_READ_4(hsotg, HPRT0); 128 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 129 if (prtspd == HPRT0_SPD_HIGH_SPEED && 130 (dev_speed == USB_SPEED_LOW || 131 dev_speed == USB_SPEED_FULL)) { 132 qh->interval *= 8; 133 qh->sched_frame |= 0x7; 134 qh->start_split_frame = qh->sched_frame; 135 } 136 dev_dbg(hsotg->dev, "interval=%d\n", qh->interval); 137 } 138 139 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n"); 140 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh); 141 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n", 142 dwc2_hcd_get_dev_addr(&urb->pipe_info)); 143 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n", 144 dwc2_hcd_get_ep_num(&urb->pipe_info), 145 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); 146 147 qh->dev_speed = dev_speed; 148 149 #ifdef DWC2_DEBUG 150 const char *speed, *type; 151 switch (dev_speed) { 152 case USB_SPEED_LOW: 153 speed = "low"; 154 break; 155 case USB_SPEED_FULL: 156 speed = "full"; 157 break; 158 case USB_SPEED_HIGH: 159 speed = "high"; 160 break; 161 default: 162 speed = "?"; 163 break; 164 } 165 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed); 166 167 switch (qh->ep_type) { 168 case USB_ENDPOINT_XFER_ISOC: 169 type = "isochronous"; 170 break; 171 case USB_ENDPOINT_XFER_INT: 172 type = "interrupt"; 173 break; 174 case USB_ENDPOINT_XFER_CONTROL: 175 type = "control"; 176 break; 177 case USB_ENDPOINT_XFER_BULK: 178 type = "bulk"; 179 break; 180 default: 181 type = "?"; 182 break; 183 } 184 185 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type); 186 #endif 187 188 if (qh->ep_type == USB_ENDPOINT_XFER_INT) { 189 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n", 190 qh->usecs); 191 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n", 192 qh->interval); 193 } 194 } 195 196 /** 197 * dwc2_hcd_qh_create() - Allocates and initializes a QH 198 * 199 * @hsotg: The HCD state structure for the DWC OTG controller 200 * @urb: Holds the information about the device/endpoint needed 201 * to initialize the QH 202 * @mem_flags: Flag to do atomic allocation if needed 203 * 204 * Return: Pointer to the newly allocated QH, or NULL on error 205 */ 206 STATIC struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 207 struct dwc2_hcd_urb *urb, 208 gfp_t mem_flags) 209 { 210 struct dwc2_softc *sc = hsotg->hsotg_sc; 211 struct dwc2_qh *qh; 212 213 if (!urb->priv) 214 return NULL; 215 216 /* Allocate memory */ 217 qh = pool_get(&sc->sc_qhpool, PR_NOWAIT); 218 if (!qh) 219 return NULL; 220 221 memset(qh, 0, sizeof(*qh)); 222 dwc2_qh_init(hsotg, qh, urb); 223 224 if (hsotg->core_params->dma_desc_enable > 0 && 225 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { 226 dwc2_hcd_qh_free(hsotg, qh); 227 return NULL; 228 } 229 230 return qh; 231 } 232 233 /** 234 * dwc2_hcd_qh_free() - Frees the QH 235 * 236 * @hsotg: HCD instance 237 * @qh: The QH to free 238 * 239 * QH should already be removed from the list. QTD list should already be empty 240 * if called from URB Dequeue. 241 * 242 * Must NOT be called with interrupt disabled or spinlock held 243 */ 244 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 245 { 246 struct dwc2_softc *sc = hsotg->hsotg_sc; 247 248 if (hsotg->core_params->dma_desc_enable > 0) { 249 dwc2_hcd_qh_free_ddma(hsotg, qh); 250 } else if (qh->dw_align_buf) { 251 /* XXXNH */ 252 usb_freemem(&hsotg->hsotg_sc->sc_bus, &qh->dw_align_buf_usbdma); 253 } 254 255 pool_put(&sc->sc_qhpool, qh); 256 } 257 258 /** 259 * dwc2_periodic_channel_available() - Checks that a channel is available for a 260 * periodic transfer 261 * 262 * @hsotg: The HCD state structure for the DWC OTG controller 263 * 264 * Return: 0 if successful, negative error code otherwise 265 */ 266 STATIC int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) 267 { 268 /* 269 * Currently assuming that there is a dedicated host channel for 270 * each periodic transaction plus at least one host channel for 271 * non-periodic transactions 272 */ 273 int status; 274 int num_channels; 275 276 num_channels = hsotg->core_params->host_channels; 277 if (hsotg->periodic_channels + hsotg->non_periodic_channels < 278 num_channels 279 && hsotg->periodic_channels < num_channels - 1) { 280 status = 0; 281 } else { 282 dev_dbg(hsotg->dev, 283 "%s: Total channels: %d, Periodic: %d, " 284 "Non-periodic: %d\n", __func__, num_channels, 285 hsotg->periodic_channels, hsotg->non_periodic_channels); 286 status = -ENOSPC; 287 } 288 289 return status; 290 } 291 292 /** 293 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth 294 * for the specified QH in the periodic schedule 295 * 296 * @hsotg: The HCD state structure for the DWC OTG controller 297 * @qh: QH containing periodic bandwidth required 298 * 299 * Return: 0 if successful, negative error code otherwise 300 * 301 * For simplicity, this calculation assumes that all the transfers in the 302 * periodic schedule may occur in the same (micro)frame 303 */ 304 STATIC int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg, 305 struct dwc2_qh *qh) 306 { 307 int status; 308 s16 max_claimed_usecs; 309 310 status = 0; 311 312 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 313 /* 314 * High speed mode 315 * Max periodic usecs is 80% x 125 usec = 100 usec 316 */ 317 max_claimed_usecs = 100 - qh->usecs; 318 } else { 319 /* 320 * Full speed mode 321 * Max periodic usecs is 90% x 1000 usec = 900 usec 322 */ 323 max_claimed_usecs = 900 - qh->usecs; 324 } 325 326 if (hsotg->periodic_usecs > max_claimed_usecs) { 327 dev_err(hsotg->dev, 328 "%s: already claimed usecs %d, required usecs %d\n", 329 __func__, hsotg->periodic_usecs, qh->usecs); 330 status = -ENOSPC; 331 } 332 333 return status; 334 } 335 336 /** 337 * Microframe scheduler 338 * track the total use in hsotg->frame_usecs 339 * keep each qh use in qh->frame_usecs 340 * when surrendering the qh then donate the time back 341 */ 342 STATIC const unsigned short max_uframe_usecs[] = { 343 100, 100, 100, 100, 100, 100, 30, 0 344 }; 345 346 void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg) 347 { 348 int i; 349 350 for (i = 0; i < 8; i++) 351 hsotg->frame_usecs[i] = max_uframe_usecs[i]; 352 } 353 354 STATIC int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 355 { 356 unsigned short utime = qh->usecs; 357 int i; 358 359 for (i = 0; i < 8; i++) { 360 /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */ 361 if (utime <= hsotg->frame_usecs[i]) { 362 hsotg->frame_usecs[i] -= utime; 363 qh->frame_usecs[i] += utime; 364 return i; 365 } 366 } 367 return -ENOSPC; 368 } 369 370 /* 371 * use this for FS apps that can span multiple uframes 372 */ 373 STATIC int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 374 { 375 unsigned short utime = qh->usecs; 376 unsigned short xtime; 377 int t_left; 378 int i; 379 int j; 380 int k; 381 382 for (i = 0; i < 8; i++) { 383 if (hsotg->frame_usecs[i] <= 0) 384 continue; 385 386 /* 387 * we need n consecutive slots so use j as a start slot 388 * j plus j+1 must be enough time (for now) 389 */ 390 xtime = hsotg->frame_usecs[i]; 391 for (j = i + 1; j < 8; j++) { 392 /* 393 * if we add this frame remaining time to xtime we may 394 * be OK, if not we need to test j for a complete frame 395 */ 396 if (xtime + hsotg->frame_usecs[j] < utime) { 397 if (hsotg->frame_usecs[j] < 398 max_uframe_usecs[j]) 399 continue; 400 } 401 if (xtime >= utime) { 402 t_left = utime; 403 for (k = i; k < 8; k++) { 404 t_left -= hsotg->frame_usecs[k]; 405 if (t_left <= 0) { 406 qh->frame_usecs[k] += 407 hsotg->frame_usecs[k] 408 + t_left; 409 hsotg->frame_usecs[k] = -t_left; 410 return i; 411 } else { 412 qh->frame_usecs[k] += 413 hsotg->frame_usecs[k]; 414 hsotg->frame_usecs[k] = 0; 415 } 416 } 417 } 418 /* add the frame time to x time */ 419 xtime += hsotg->frame_usecs[j]; 420 /* we must have a fully available next frame or break */ 421 if (xtime < utime && 422 hsotg->frame_usecs[j] == max_uframe_usecs[j]) 423 continue; 424 } 425 } 426 return -ENOSPC; 427 } 428 429 STATIC int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 430 { 431 int ret; 432 433 if (qh->dev_speed == USB_SPEED_HIGH) { 434 /* if this is a hs transaction we need a full frame */ 435 ret = dwc2_find_single_uframe(hsotg, qh); 436 } else { 437 /* 438 * if this is a fs transaction we may need a sequence 439 * of frames 440 */ 441 ret = dwc2_find_multi_uframe(hsotg, qh); 442 } 443 return ret; 444 } 445 446 /** 447 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a 448 * host channel is large enough to handle the maximum data transfer in a single 449 * (micro)frame for a periodic transfer 450 * 451 * @hsotg: The HCD state structure for the DWC OTG controller 452 * @qh: QH for a periodic endpoint 453 * 454 * Return: 0 if successful, negative error code otherwise 455 */ 456 STATIC int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg, 457 struct dwc2_qh *qh) 458 { 459 u32 max_xfer_size; 460 u32 max_channel_xfer_size; 461 int status = 0; 462 463 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp); 464 max_channel_xfer_size = hsotg->core_params->max_transfer_size; 465 466 if (max_xfer_size > max_channel_xfer_size) { 467 dev_err(hsotg->dev, 468 "%s: Periodic xfer length %d > max xfer length for channel %d\n", 469 __func__, max_xfer_size, max_channel_xfer_size); 470 status = -ENOSPC; 471 } 472 473 return status; 474 } 475 476 /** 477 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in 478 * the periodic schedule 479 * 480 * @hsotg: The HCD state structure for the DWC OTG controller 481 * @qh: QH for the periodic transfer. The QH should already contain the 482 * scheduling information. 483 * 484 * Return: 0 if successful, negative error code otherwise 485 */ 486 STATIC int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 487 { 488 int status; 489 490 if (hsotg->core_params->uframe_sched > 0) { 491 int frame = -1; 492 493 status = dwc2_find_uframe(hsotg, qh); 494 if (status == 0) 495 frame = 7; 496 else if (status > 0) 497 frame = status - 1; 498 499 /* Set the new frame up */ 500 if (frame >= 0) { 501 qh->sched_frame &= ~0x7; 502 qh->sched_frame |= (frame & 7); 503 } 504 505 if (status > 0) 506 status = 0; 507 } else { 508 status = dwc2_periodic_channel_available(hsotg); 509 if (status) { 510 dev_info(hsotg->dev, 511 "%s: No host channel available for periodic transfer\n", 512 __func__); 513 return status; 514 } 515 516 status = dwc2_check_periodic_bandwidth(hsotg, qh); 517 } 518 519 if (status) { 520 dev_dbg(hsotg->dev, 521 "%s: Insufficient periodic bandwidth for periodic transfer\n", 522 __func__); 523 return status; 524 } 525 526 status = dwc2_check_max_xfer_size(hsotg, qh); 527 if (status) { 528 dev_dbg(hsotg->dev, 529 "%s: Channel max transfer size too small for periodic transfer\n", 530 __func__); 531 return status; 532 } 533 534 if (hsotg->core_params->dma_desc_enable > 0) 535 /* Don't rely on SOF and start in ready schedule */ 536 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_ready, qh, qh_list_entry); 537 else 538 /* Always start in inactive schedule */ 539 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_inactive, qh, qh_list_entry); 540 qh->linked = 1; 541 542 if (hsotg->core_params->uframe_sched <= 0) 543 /* Reserve periodic channel */ 544 hsotg->periodic_channels++; 545 546 /* Update claimed usecs per (micro)frame */ 547 hsotg->periodic_usecs += qh->usecs; 548 549 return status; 550 } 551 552 /** 553 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer 554 * from the periodic schedule 555 * 556 * @hsotg: The HCD state structure for the DWC OTG controller 557 * @qh: QH for the periodic transfer 558 */ 559 STATIC void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg, 560 struct dwc2_qh *qh) 561 { 562 int i; 563 564 qh->linked = 0; 565 566 /* Update claimed usecs per (micro)frame */ 567 hsotg->periodic_usecs -= qh->usecs; 568 569 if (hsotg->core_params->uframe_sched > 0) { 570 for (i = 0; i < 8; i++) { 571 hsotg->frame_usecs[i] += qh->frame_usecs[i]; 572 qh->frame_usecs[i] = 0; 573 } 574 } else { 575 /* Release periodic channel reservation */ 576 hsotg->periodic_channels--; 577 } 578 } 579 580 /** 581 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic 582 * schedule if it is not already in the schedule. If the QH is already in 583 * the schedule, no action is taken. 584 * 585 * @hsotg: The HCD state structure for the DWC OTG controller 586 * @qh: The QH to add 587 * 588 * Return: 0 if successful, negative error code otherwise 589 */ 590 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 591 { 592 int status; 593 u32 intr_mask; 594 595 if (dbg_qh(qh)) 596 dev_vdbg(hsotg->dev, "%s()\n", __func__); 597 598 if (qh->linked != 0) { 599 /* QH already in a schedule */ 600 return 0; 601 } 602 603 /* Add the new QH to the appropriate schedule */ 604 if (dwc2_qh_is_non_per(qh)) { 605 /* Always start in inactive schedule */ 606 TAILQ_INSERT_TAIL(&hsotg->non_periodic_sched_inactive, qh, qh_list_entry); 607 qh->linked = 1; 608 return 0; 609 } 610 status = dwc2_schedule_periodic(hsotg, qh); 611 if (status) 612 return status; 613 if (!hsotg->periodic_qh_count) { 614 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 615 intr_mask |= GINTSTS_SOF; 616 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 617 } 618 hsotg->periodic_qh_count++; 619 620 return 0; 621 } 622 623 /** 624 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic 625 * schedule. Memory is not freed. 626 * 627 * @hsotg: The HCD state structure 628 * @qh: QH to remove from schedule 629 */ 630 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 631 { 632 u32 intr_mask; 633 634 dev_vdbg(hsotg->dev, "%s()\n", __func__); 635 636 if (qh->linked == 0) { 637 /* QH is not in a schedule */ 638 return; 639 } 640 641 if (dwc2_qh_is_non_per(qh)) { 642 if (hsotg->non_periodic_qh_ptr == qh) { 643 hsotg->non_periodic_qh_ptr = 644 TAILQ_NEXT(qh, qh_list_entry); 645 } 646 647 if (qh->channel) { 648 TAILQ_REMOVE(&hsotg->non_periodic_sched_active, qh, qh_list_entry); 649 } else { 650 TAILQ_REMOVE(&hsotg->non_periodic_sched_inactive, qh, qh_list_entry); 651 } 652 qh->linked = 0; 653 654 if (hsotg->non_periodic_qh_ptr == NULL) 655 hsotg->non_periodic_qh_ptr = TAILQ_FIRST(&hsotg->non_periodic_sched_active); 656 return; 657 } 658 dwc2_deschedule_periodic(hsotg, qh); 659 hsotg->periodic_qh_count--; 660 if (!hsotg->periodic_qh_count) { 661 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 662 intr_mask &= ~GINTSTS_SOF; 663 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 664 } 665 } 666 667 /* 668 * Schedule the next continuing periodic split transfer 669 */ 670 STATIC void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg, 671 struct dwc2_qh *qh, u16 frame_number, 672 int sched_next_periodic_split) 673 { 674 u16 incr; 675 676 if (sched_next_periodic_split) { 677 qh->sched_frame = frame_number; 678 incr = dwc2_frame_num_inc(qh->start_split_frame, 1); 679 if (dwc2_frame_num_le(frame_number, incr)) { 680 /* 681 * Allow one frame to elapse after start split 682 * microframe before scheduling complete split, but 683 * DON'T if we are doing the next start split in the 684 * same frame for an ISOC out 685 */ 686 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC || 687 qh->ep_is_in != 0) { 688 qh->sched_frame = 689 dwc2_frame_num_inc(qh->sched_frame, 1); 690 } 691 } 692 } else { 693 qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame, 694 qh->interval); 695 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 696 qh->sched_frame = frame_number; 697 qh->sched_frame |= 0x7; 698 qh->start_split_frame = qh->sched_frame; 699 } 700 } 701 702 /* 703 * Deactivates a QH. For non-periodic QHs, removes the QH from the active 704 * non-periodic schedule. The QH is added to the inactive non-periodic 705 * schedule if any QTDs are still attached to the QH. 706 * 707 * For periodic QHs, the QH is removed from the periodic queued schedule. If 708 * there are any QTDs still attached to the QH, the QH is added to either the 709 * periodic inactive schedule or the periodic ready schedule and its next 710 * scheduled frame is calculated. The QH is placed in the ready schedule if 711 * the scheduled frame has been reached already. Otherwise it's placed in the 712 * inactive schedule. If there are no QTDs attached to the QH, the QH is 713 * completely removed from the periodic schedule. 714 */ 715 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 716 int sched_next_periodic_split) 717 { 718 u16 frame_number; 719 720 if (dbg_qh(qh)) 721 dev_vdbg(hsotg->dev, "%s()\n", __func__); 722 723 if (dwc2_qh_is_non_per(qh)) { 724 dwc2_hcd_qh_unlink(hsotg, qh); 725 if (!TAILQ_EMPTY(&qh->qtd_list)) 726 /* Add back to inactive non-periodic schedule */ 727 dwc2_hcd_qh_add(hsotg, qh); 728 return; 729 } 730 731 frame_number = dwc2_hcd_get_frame_number(hsotg); 732 733 if (qh->do_split) { 734 dwc2_sched_periodic_split(hsotg, qh, frame_number, 735 sched_next_periodic_split); 736 } else { 737 qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame, 738 qh->interval); 739 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 740 qh->sched_frame = frame_number; 741 } 742 743 if (TAILQ_EMPTY(&qh->qtd_list)) { 744 dwc2_hcd_qh_unlink(hsotg, qh); 745 return; 746 } 747 /* 748 * Remove from periodic_sched_queued and move to 749 * appropriate queue 750 */ 751 TAILQ_REMOVE(&hsotg->periodic_sched_queued, qh, qh_list_entry); 752 if ((hsotg->core_params->uframe_sched > 0 && 753 dwc2_frame_num_le(qh->sched_frame, frame_number)) || 754 (hsotg->core_params->uframe_sched <= 0 && 755 qh->sched_frame == frame_number)) { 756 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_ready, qh, qh_list_entry); 757 } else { 758 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_inactive, qh, qh_list_entry); 759 } 760 } 761 762 /** 763 * dwc2_hcd_qtd_init() - Initializes a QTD structure 764 * 765 * @qtd: The QTD to initialize 766 * @urb: The associated URB 767 */ 768 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 769 { 770 qtd->urb = urb; 771 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == 772 USB_ENDPOINT_XFER_CONTROL) { 773 /* 774 * The only time the QTD data toggle is used is on the data 775 * phase of control transfers. This phase always starts with 776 * DATA1. 777 */ 778 qtd->data_toggle = DWC2_HC_PID_DATA1; 779 qtd->control_phase = DWC2_CONTROL_SETUP; 780 } 781 782 /* Start split */ 783 qtd->complete_split = 0; 784 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 785 qtd->isoc_split_offset = 0; 786 qtd->in_process = 0; 787 788 /* Store the qtd ptr in the urb to reference the QTD */ 789 urb->qtd = qtd; 790 } 791 792 /** 793 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH 794 * 795 * @hsotg: The DWC HCD structure 796 * @qtd: The QTD to add 797 * @qh: Out parameter to return queue head 798 * @mem_flags: Flag to do atomic alloc if needed 799 * 800 * Return: 0 if successful, negative error code otherwise 801 * 802 * Finds the correct QH to place the QTD into. If it does not find a QH, it 803 * will create a new QH. If the QH to which the QTD is added is not currently 804 * scheduled, it is placed into the proper schedule based on its EP type. 805 * 806 * HCD lock must be held and interrupts must be disabled on entry 807 */ 808 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 809 struct dwc2_qh **qh, gfp_t mem_flags) 810 { 811 struct dwc2_hcd_urb *urb = qtd->urb; 812 int allocated = 0; 813 int retval; 814 815 /* 816 * Get the QH which holds the QTD-list to insert to. Create QH if it 817 * doesn't exist. 818 */ 819 if (*qh == NULL) { 820 *qh = dwc2_hcd_qh_create(hsotg, urb, mem_flags); 821 if (*qh == NULL) 822 return -ENOMEM; 823 allocated = 1; 824 } 825 826 retval = dwc2_hcd_qh_add(hsotg, *qh); 827 if (retval) 828 goto fail; 829 830 qtd->qh = *qh; 831 TAILQ_INSERT_TAIL(&(*qh)->qtd_list, qtd, qtd_list_entry); 832 833 return 0; 834 835 fail: 836 if (allocated) { 837 struct dwc2_qtd *qtd2, *qtd2_tmp; 838 struct dwc2_qh *qh_tmp = *qh; 839 840 *qh = NULL; 841 dwc2_hcd_qh_unlink(hsotg, qh_tmp); 842 843 /* Free each QTD in the QH's QTD list */ 844 TAILQ_FOREACH_SAFE(qtd2, &qh_tmp->qtd_list, qtd_list_entry, qtd2_tmp) 845 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh_tmp); 846 847 dwc2_hcd_qh_free(hsotg, qh_tmp); 848 } 849 850 return retval; 851 } 852 853 void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 854 struct dwc2_qtd *qtd, 855 struct dwc2_qh *qh) 856 { 857 struct dwc2_softc *sc = hsotg->hsotg_sc; 858 859 TAILQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); 860 pool_put(&sc->sc_qtdpool, qtd); 861 } 862 863 #define BITSTUFFTIME(bytecount) ((8 * 7 * (bytecount)) / 6) 864 #define HS_HOST_DELAY 5 /* nanoseconds */ 865 #define FS_LS_HOST_DELAY 1000 /* nanoseconds */ 866 #define HUB_LS_SETUP 333 /* nanoseconds */ 867 868 STATIC u32 dwc2_calc_bus_time(struct dwc2_hsotg *hsotg, int speed, int is_in, 869 int is_isoc, int bytecount) 870 { 871 unsigned long retval; 872 873 switch (speed) { 874 case USB_SPEED_HIGH: 875 if (is_isoc) 876 retval = 877 ((38 * 8 * 2083) + 878 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 879 HS_HOST_DELAY; 880 else 881 retval = 882 ((55 * 8 * 2083) + 883 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 884 HS_HOST_DELAY; 885 break; 886 case USB_SPEED_FULL: 887 if (is_isoc) { 888 retval = 889 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 890 if (is_in) 891 retval = 7268 + FS_LS_HOST_DELAY + retval; 892 else 893 retval = 6265 + FS_LS_HOST_DELAY + retval; 894 } else { 895 retval = 896 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 897 retval = 9107 + FS_LS_HOST_DELAY + retval; 898 } 899 break; 900 case USB_SPEED_LOW: 901 if (is_in) { 902 retval = 903 (67667 * (31 + 10 * BITSTUFFTIME(bytecount))) / 904 1000; 905 retval = 906 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 907 retval; 908 } else { 909 retval = 910 (66700 * (31 + 10 * BITSTUFFTIME(bytecount))) / 911 1000; 912 retval = 913 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 914 retval; 915 } 916 break; 917 default: 918 dev_warn(hsotg->dev, "Unknown device speed\n"); 919 retval = -1; 920 } 921 922 return NS_TO_US(retval); 923 } 924