1 /* $OpenBSD: dwc2_hcdqueue.c,v 1.4 2015/02/10 13:49:48 uebayasi Exp $ */ 2 /* $NetBSD: dwc2_hcdqueue.c,v 1.11 2014/09/03 10:00:08 skrll Exp $ */ 3 4 /* 5 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * This file contains the functions to manage Queue Heads and Queue 42 * Transfer Descriptors for Host mode 43 */ 44 45 #if 0 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: dwc2_hcdqueue.c,v 1.11 2014/09/03 10:00:08 skrll Exp $"); 48 #endif 49 50 #include <sys/param.h> 51 #include <sys/types.h> 52 #include <sys/malloc.h> 53 #include <sys/pool.h> 54 55 #include <machine/bus.h> 56 57 #include <dev/usb/usb.h> 58 #include <dev/usb/usbdi.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usb_mem.h> 61 62 #include <dev/usb/dwc2/linux/kernel.h> 63 64 #include <dev/usb/dwc2/dwc2.h> 65 #include <dev/usb/dwc2/dwc2var.h> 66 67 #include <dev/usb/dwc2/dwc2_core.h> 68 #include <dev/usb/dwc2/dwc2_hcd.h> 69 70 static u32 dwc2_calc_bus_time(struct dwc2_hsotg *, int, int, int, int); 71 72 /** 73 * dwc2_qh_init() - Initializes a QH structure 74 * 75 * @hsotg: The HCD state structure for the DWC OTG controller 76 * @qh: The QH to init 77 * @urb: Holds the information about the device/endpoint needed to initialize 78 * the QH 79 */ 80 #define SCHEDULE_SLOP 10 81 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 82 struct dwc2_hcd_urb *urb) 83 { 84 int dev_speed, hub_addr, hub_port; 85 86 dev_vdbg(hsotg->dev, "%s()\n", __func__); 87 88 /* Initialize QH */ 89 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 90 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; 91 92 qh->data_toggle = DWC2_HC_PID_DATA0; 93 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info); 94 INIT_LIST_HEAD(&qh->qtd_list); 95 INIT_LIST_HEAD(&qh->qh_list_entry); 96 97 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */ 98 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 99 100 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 101 qh->nak_frame = 0xffff; 102 103 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) && 104 hub_addr != 0 && hub_addr != 1) { 105 dev_vdbg(hsotg->dev, 106 "QH init: EP %d: TT found at hub addr %d, for port %d\n", 107 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr, 108 hub_port); 109 qh->do_split = 1; 110 } 111 112 if (qh->ep_type == USB_ENDPOINT_XFER_INT || 113 qh->ep_type == USB_ENDPOINT_XFER_ISOC) { 114 /* Compute scheduling parameters once and save them */ 115 u32 hprt, prtspd; 116 117 /* Todo: Account for split transfers in the bus time */ 118 int bytecount = 119 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp); 120 121 qh->usecs = dwc2_calc_bus_time(hsotg, qh->do_split ? 122 USB_SPEED_HIGH : dev_speed, qh->ep_is_in, 123 qh->ep_type == USB_ENDPOINT_XFER_ISOC, 124 bytecount); 125 /* Start in a slightly future (micro)frame */ 126 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number, 127 SCHEDULE_SLOP); 128 qh->interval = urb->interval; 129 #if 0 130 /* Increase interrupt polling rate for debugging */ 131 if (qh->ep_type == USB_ENDPOINT_XFER_INT) 132 qh->interval = 8; 133 #endif 134 hprt = DWC2_READ_4(hsotg, HPRT0); 135 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 136 if (prtspd == HPRT0_SPD_HIGH_SPEED && 137 (dev_speed == USB_SPEED_LOW || 138 dev_speed == USB_SPEED_FULL)) { 139 qh->interval *= 8; 140 qh->sched_frame |= 0x7; 141 qh->start_split_frame = qh->sched_frame; 142 } 143 dev_dbg(hsotg->dev, "interval=%d\n", qh->interval); 144 } 145 146 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n"); 147 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh); 148 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n", 149 dwc2_hcd_get_dev_addr(&urb->pipe_info)); 150 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n", 151 dwc2_hcd_get_ep_num(&urb->pipe_info), 152 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); 153 154 qh->dev_speed = dev_speed; 155 156 #ifdef DWC2_DEBUG 157 const char *speed, *type; 158 switch (dev_speed) { 159 case USB_SPEED_LOW: 160 speed = "low"; 161 break; 162 case USB_SPEED_FULL: 163 speed = "full"; 164 break; 165 case USB_SPEED_HIGH: 166 speed = "high"; 167 break; 168 default: 169 speed = "?"; 170 break; 171 } 172 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed); 173 174 switch (qh->ep_type) { 175 case USB_ENDPOINT_XFER_ISOC: 176 type = "isochronous"; 177 break; 178 case USB_ENDPOINT_XFER_INT: 179 type = "interrupt"; 180 break; 181 case USB_ENDPOINT_XFER_CONTROL: 182 type = "control"; 183 break; 184 case USB_ENDPOINT_XFER_BULK: 185 type = "bulk"; 186 break; 187 default: 188 type = "?"; 189 break; 190 } 191 192 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type); 193 #endif 194 195 if (qh->ep_type == USB_ENDPOINT_XFER_INT) { 196 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n", 197 qh->usecs); 198 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n", 199 qh->interval); 200 } 201 } 202 203 /** 204 * dwc2_hcd_qh_create() - Allocates and initializes a QH 205 * 206 * @hsotg: The HCD state structure for the DWC OTG controller 207 * @urb: Holds the information about the device/endpoint needed 208 * to initialize the QH 209 * @mem_flags: Flag to do atomic allocation if needed 210 * 211 * Return: Pointer to the newly allocated QH, or NULL on error 212 */ 213 static struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 214 struct dwc2_hcd_urb *urb, 215 gfp_t mem_flags) 216 { 217 struct dwc2_softc *sc = hsotg->hsotg_sc; 218 struct dwc2_qh *qh; 219 220 if (!urb->priv) 221 return NULL; 222 223 /* Allocate memory */ 224 qh = pool_get(sc->sc_qhpool, PR_NOWAIT); 225 if (!qh) 226 return NULL; 227 228 memset(qh, 0, sizeof(*qh)); 229 dwc2_qh_init(hsotg, qh, urb); 230 231 if (hsotg->core_params->dma_desc_enable > 0 && 232 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { 233 dwc2_hcd_qh_free(hsotg, qh); 234 return NULL; 235 } 236 237 return qh; 238 } 239 240 /** 241 * dwc2_hcd_qh_free() - Frees the QH 242 * 243 * @hsotg: HCD instance 244 * @qh: The QH to free 245 * 246 * QH should already be removed from the list. QTD list should already be empty 247 * if called from URB Dequeue. 248 * 249 * Must NOT be called with interrupt disabled or spinlock held 250 */ 251 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 252 { 253 struct dwc2_softc *sc = hsotg->hsotg_sc; 254 255 if (hsotg->core_params->dma_desc_enable > 0) { 256 dwc2_hcd_qh_free_ddma(hsotg, qh); 257 } else if (qh->dw_align_buf) { 258 /* XXXNH */ 259 usb_freemem(&hsotg->hsotg_sc->sc_bus, &qh->dw_align_buf_usbdma); 260 } 261 262 pool_put(sc->sc_qhpool, qh); 263 } 264 265 /** 266 * dwc2_periodic_channel_available() - Checks that a channel is available for a 267 * periodic transfer 268 * 269 * @hsotg: The HCD state structure for the DWC OTG controller 270 * 271 * Return: 0 if successful, negative error code otherwise 272 */ 273 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) 274 { 275 /* 276 * Currently assuming that there is a dedicated host channel for 277 * each periodic transaction plus at least one host channel for 278 * non-periodic transactions 279 */ 280 int status; 281 int num_channels; 282 283 num_channels = hsotg->core_params->host_channels; 284 if (hsotg->periodic_channels + hsotg->non_periodic_channels < 285 num_channels 286 && hsotg->periodic_channels < num_channels - 1) { 287 status = 0; 288 } else { 289 dev_dbg(hsotg->dev, 290 "%s: Total channels: %d, Periodic: %d, " 291 "Non-periodic: %d\n", __func__, num_channels, 292 hsotg->periodic_channels, hsotg->non_periodic_channels); 293 status = -ENOSPC; 294 } 295 296 return status; 297 } 298 299 /** 300 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth 301 * for the specified QH in the periodic schedule 302 * 303 * @hsotg: The HCD state structure for the DWC OTG controller 304 * @qh: QH containing periodic bandwidth required 305 * 306 * Return: 0 if successful, negative error code otherwise 307 * 308 * For simplicity, this calculation assumes that all the transfers in the 309 * periodic schedule may occur in the same (micro)frame 310 */ 311 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg, 312 struct dwc2_qh *qh) 313 { 314 int status; 315 s16 max_claimed_usecs; 316 317 status = 0; 318 319 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 320 /* 321 * High speed mode 322 * Max periodic usecs is 80% x 125 usec = 100 usec 323 */ 324 max_claimed_usecs = 100 - qh->usecs; 325 } else { 326 /* 327 * Full speed mode 328 * Max periodic usecs is 90% x 1000 usec = 900 usec 329 */ 330 max_claimed_usecs = 900 - qh->usecs; 331 } 332 333 if (hsotg->periodic_usecs > max_claimed_usecs) { 334 dev_err(hsotg->dev, 335 "%s: already claimed usecs %d, required usecs %d\n", 336 __func__, hsotg->periodic_usecs, qh->usecs); 337 status = -ENOSPC; 338 } 339 340 return status; 341 } 342 343 /** 344 * Microframe scheduler 345 * track the total use in hsotg->frame_usecs 346 * keep each qh use in qh->frame_usecs 347 * when surrendering the qh then donate the time back 348 */ 349 static const unsigned short max_uframe_usecs[] = { 350 100, 100, 100, 100, 100, 100, 30, 0 351 }; 352 353 void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg) 354 { 355 int i; 356 357 for (i = 0; i < 8; i++) 358 hsotg->frame_usecs[i] = max_uframe_usecs[i]; 359 } 360 361 static int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 362 { 363 unsigned short utime = qh->usecs; 364 int i; 365 366 for (i = 0; i < 8; i++) { 367 /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */ 368 if (utime <= hsotg->frame_usecs[i]) { 369 hsotg->frame_usecs[i] -= utime; 370 qh->frame_usecs[i] += utime; 371 return i; 372 } 373 } 374 return -ENOSPC; 375 } 376 377 /* 378 * use this for FS apps that can span multiple uframes 379 */ 380 static int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 381 { 382 unsigned short utime = qh->usecs; 383 unsigned short xtime; 384 int t_left; 385 int i; 386 int j; 387 int k; 388 389 for (i = 0; i < 8; i++) { 390 if (hsotg->frame_usecs[i] <= 0) 391 continue; 392 393 /* 394 * we need n consecutive slots so use j as a start slot 395 * j plus j+1 must be enough time (for now) 396 */ 397 xtime = hsotg->frame_usecs[i]; 398 for (j = i + 1; j < 8; j++) { 399 /* 400 * if we add this frame remaining time to xtime we may 401 * be OK, if not we need to test j for a complete frame 402 */ 403 if (xtime + hsotg->frame_usecs[j] < utime) { 404 if (hsotg->frame_usecs[j] < 405 max_uframe_usecs[j]) 406 continue; 407 } 408 if (xtime >= utime) { 409 t_left = utime; 410 for (k = i; k < 8; k++) { 411 t_left -= hsotg->frame_usecs[k]; 412 if (t_left <= 0) { 413 qh->frame_usecs[k] += 414 hsotg->frame_usecs[k] 415 + t_left; 416 hsotg->frame_usecs[k] = -t_left; 417 return i; 418 } else { 419 qh->frame_usecs[k] += 420 hsotg->frame_usecs[k]; 421 hsotg->frame_usecs[k] = 0; 422 } 423 } 424 } 425 /* add the frame time to x time */ 426 xtime += hsotg->frame_usecs[j]; 427 /* we must have a fully available next frame or break */ 428 if (xtime < utime && 429 hsotg->frame_usecs[j] == max_uframe_usecs[j]) 430 continue; 431 } 432 } 433 return -ENOSPC; 434 } 435 436 static int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 437 { 438 int ret; 439 440 if (qh->dev_speed == USB_SPEED_HIGH) { 441 /* if this is a hs transaction we need a full frame */ 442 ret = dwc2_find_single_uframe(hsotg, qh); 443 } else { 444 /* 445 * if this is a fs transaction we may need a sequence 446 * of frames 447 */ 448 ret = dwc2_find_multi_uframe(hsotg, qh); 449 } 450 return ret; 451 } 452 453 /** 454 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a 455 * host channel is large enough to handle the maximum data transfer in a single 456 * (micro)frame for a periodic transfer 457 * 458 * @hsotg: The HCD state structure for the DWC OTG controller 459 * @qh: QH for a periodic endpoint 460 * 461 * Return: 0 if successful, negative error code otherwise 462 */ 463 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg, 464 struct dwc2_qh *qh) 465 { 466 u32 max_xfer_size; 467 u32 max_channel_xfer_size; 468 int status = 0; 469 470 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp); 471 max_channel_xfer_size = hsotg->core_params->max_transfer_size; 472 473 if (max_xfer_size > max_channel_xfer_size) { 474 dev_err(hsotg->dev, 475 "%s: Periodic xfer length %d > max xfer length for channel %d\n", 476 __func__, max_xfer_size, max_channel_xfer_size); 477 status = -ENOSPC; 478 } 479 480 return status; 481 } 482 483 /** 484 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in 485 * the periodic schedule 486 * 487 * @hsotg: The HCD state structure for the DWC OTG controller 488 * @qh: QH for the periodic transfer. The QH should already contain the 489 * scheduling information. 490 * 491 * Return: 0 if successful, negative error code otherwise 492 */ 493 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 494 { 495 int status; 496 497 if (hsotg->core_params->uframe_sched > 0) { 498 int frame = -1; 499 500 status = dwc2_find_uframe(hsotg, qh); 501 if (status == 0) 502 frame = 7; 503 else if (status > 0) 504 frame = status - 1; 505 506 /* Set the new frame up */ 507 if (frame >= 0) { 508 qh->sched_frame &= ~0x7; 509 qh->sched_frame |= (frame & 7); 510 } 511 512 if (status > 0) 513 status = 0; 514 } else { 515 status = dwc2_periodic_channel_available(hsotg); 516 if (status) { 517 dev_info(hsotg->dev, 518 "%s: No host channel available for periodic transfer\n", 519 __func__); 520 return status; 521 } 522 523 status = dwc2_check_periodic_bandwidth(hsotg, qh); 524 } 525 526 if (status) { 527 dev_dbg(hsotg->dev, 528 "%s: Insufficient periodic bandwidth for periodic transfer\n", 529 __func__); 530 return status; 531 } 532 533 status = dwc2_check_max_xfer_size(hsotg, qh); 534 if (status) { 535 dev_dbg(hsotg->dev, 536 "%s: Channel max transfer size too small for periodic transfer\n", 537 __func__); 538 return status; 539 } 540 541 if (hsotg->core_params->dma_desc_enable > 0) 542 /* Don't rely on SOF and start in ready schedule */ 543 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready); 544 else 545 /* Always start in inactive schedule */ 546 list_add_tail(&qh->qh_list_entry, 547 &hsotg->periodic_sched_inactive); 548 549 if (hsotg->core_params->uframe_sched <= 0) 550 /* Reserve periodic channel */ 551 hsotg->periodic_channels++; 552 553 /* Update claimed usecs per (micro)frame */ 554 hsotg->periodic_usecs += qh->usecs; 555 556 return status; 557 } 558 559 /** 560 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer 561 * from the periodic schedule 562 * 563 * @hsotg: The HCD state structure for the DWC OTG controller 564 * @qh: QH for the periodic transfer 565 */ 566 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg, 567 struct dwc2_qh *qh) 568 { 569 int i; 570 571 list_del_init(&qh->qh_list_entry); 572 573 /* Update claimed usecs per (micro)frame */ 574 hsotg->periodic_usecs -= qh->usecs; 575 576 if (hsotg->core_params->uframe_sched > 0) { 577 for (i = 0; i < 8; i++) { 578 hsotg->frame_usecs[i] += qh->frame_usecs[i]; 579 qh->frame_usecs[i] = 0; 580 } 581 } else { 582 /* Release periodic channel reservation */ 583 hsotg->periodic_channels--; 584 } 585 } 586 587 /** 588 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic 589 * schedule if it is not already in the schedule. If the QH is already in 590 * the schedule, no action is taken. 591 * 592 * @hsotg: The HCD state structure for the DWC OTG controller 593 * @qh: The QH to add 594 * 595 * Return: 0 if successful, negative error code otherwise 596 */ 597 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 598 { 599 int status; 600 u32 intr_mask; 601 602 if (dbg_qh(qh)) 603 dev_vdbg(hsotg->dev, "%s()\n", __func__); 604 605 if (!list_empty(&qh->qh_list_entry)) 606 /* QH already in a schedule */ 607 return 0; 608 609 /* Add the new QH to the appropriate schedule */ 610 if (dwc2_qh_is_non_per(qh)) { 611 /* Always start in inactive schedule */ 612 list_add_tail(&qh->qh_list_entry, 613 &hsotg->non_periodic_sched_inactive); 614 return 0; 615 } 616 status = dwc2_schedule_periodic(hsotg, qh); 617 if (status) 618 return status; 619 if (!hsotg->periodic_qh_count) { 620 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 621 intr_mask |= GINTSTS_SOF; 622 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 623 } 624 hsotg->periodic_qh_count++; 625 626 return 0; 627 } 628 629 /** 630 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic 631 * schedule. Memory is not freed. 632 * 633 * @hsotg: The HCD state structure 634 * @qh: QH to remove from schedule 635 */ 636 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 637 { 638 u32 intr_mask; 639 640 dev_vdbg(hsotg->dev, "%s()\n", __func__); 641 642 if (list_empty(&qh->qh_list_entry)) 643 /* QH is not in a schedule */ 644 return; 645 646 if (dwc2_qh_is_non_per(qh)) { 647 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry) 648 hsotg->non_periodic_qh_ptr = 649 hsotg->non_periodic_qh_ptr->next; 650 list_del_init(&qh->qh_list_entry); 651 return; 652 } 653 dwc2_deschedule_periodic(hsotg, qh); 654 hsotg->periodic_qh_count--; 655 if (!hsotg->periodic_qh_count) { 656 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 657 intr_mask &= ~GINTSTS_SOF; 658 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 659 } 660 } 661 662 /* 663 * Schedule the next continuing periodic split transfer 664 */ 665 static void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg, 666 struct dwc2_qh *qh, u16 frame_number, 667 int sched_next_periodic_split) 668 { 669 u16 incr; 670 671 if (sched_next_periodic_split) { 672 qh->sched_frame = frame_number; 673 incr = dwc2_frame_num_inc(qh->start_split_frame, 1); 674 if (dwc2_frame_num_le(frame_number, incr)) { 675 /* 676 * Allow one frame to elapse after start split 677 * microframe before scheduling complete split, but 678 * DON'T if we are doing the next start split in the 679 * same frame for an ISOC out 680 */ 681 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC || 682 qh->ep_is_in != 0) { 683 qh->sched_frame = 684 dwc2_frame_num_inc(qh->sched_frame, 1); 685 } 686 } 687 } else { 688 qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame, 689 qh->interval); 690 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 691 qh->sched_frame = frame_number; 692 qh->sched_frame |= 0x7; 693 qh->start_split_frame = qh->sched_frame; 694 } 695 } 696 697 /* 698 * Deactivates a QH. For non-periodic QHs, removes the QH from the active 699 * non-periodic schedule. The QH is added to the inactive non-periodic 700 * schedule if any QTDs are still attached to the QH. 701 * 702 * For periodic QHs, the QH is removed from the periodic queued schedule. If 703 * there are any QTDs still attached to the QH, the QH is added to either the 704 * periodic inactive schedule or the periodic ready schedule and its next 705 * scheduled frame is calculated. The QH is placed in the ready schedule if 706 * the scheduled frame has been reached already. Otherwise it's placed in the 707 * inactive schedule. If there are no QTDs attached to the QH, the QH is 708 * completely removed from the periodic schedule. 709 */ 710 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 711 int sched_next_periodic_split) 712 { 713 u16 frame_number; 714 715 if (dbg_qh(qh)) 716 dev_vdbg(hsotg->dev, "%s()\n", __func__); 717 718 if (dwc2_qh_is_non_per(qh)) { 719 dwc2_hcd_qh_unlink(hsotg, qh); 720 if (!list_empty(&qh->qtd_list)) 721 /* Add back to inactive non-periodic schedule */ 722 dwc2_hcd_qh_add(hsotg, qh); 723 return; 724 } 725 726 frame_number = dwc2_hcd_get_frame_number(hsotg); 727 728 if (qh->do_split) { 729 dwc2_sched_periodic_split(hsotg, qh, frame_number, 730 sched_next_periodic_split); 731 } else { 732 qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame, 733 qh->interval); 734 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 735 qh->sched_frame = frame_number; 736 } 737 738 if (list_empty(&qh->qtd_list)) { 739 dwc2_hcd_qh_unlink(hsotg, qh); 740 return; 741 } 742 /* 743 * Remove from periodic_sched_queued and move to 744 * appropriate queue 745 */ 746 if ((hsotg->core_params->uframe_sched > 0 && 747 dwc2_frame_num_le(qh->sched_frame, frame_number)) || 748 (hsotg->core_params->uframe_sched <= 0 && 749 qh->sched_frame == frame_number)) 750 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_ready); 751 else 752 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_inactive); 753 } 754 755 /** 756 * dwc2_hcd_qtd_init() - Initializes a QTD structure 757 * 758 * @qtd: The QTD to initialize 759 * @urb: The associated URB 760 */ 761 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 762 { 763 qtd->urb = urb; 764 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == 765 USB_ENDPOINT_XFER_CONTROL) { 766 /* 767 * The only time the QTD data toggle is used is on the data 768 * phase of control transfers. This phase always starts with 769 * DATA1. 770 */ 771 qtd->data_toggle = DWC2_HC_PID_DATA1; 772 qtd->control_phase = DWC2_CONTROL_SETUP; 773 } 774 775 /* Start split */ 776 qtd->complete_split = 0; 777 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 778 qtd->isoc_split_offset = 0; 779 qtd->in_process = 0; 780 781 /* Store the qtd ptr in the urb to reference the QTD */ 782 urb->qtd = qtd; 783 } 784 785 /** 786 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH 787 * 788 * @hsotg: The DWC HCD structure 789 * @qtd: The QTD to add 790 * @qh: Out parameter to return queue head 791 * @mem_flags: Flag to do atomic alloc if needed 792 * 793 * Return: 0 if successful, negative error code otherwise 794 * 795 * Finds the correct QH to place the QTD into. If it does not find a QH, it 796 * will create a new QH. If the QH to which the QTD is added is not currently 797 * scheduled, it is placed into the proper schedule based on its EP type. 798 * 799 * HCD lock must be held and interrupts must be disabled on entry 800 */ 801 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 802 struct dwc2_qh **qh, gfp_t mem_flags) 803 { 804 struct dwc2_hcd_urb *urb = qtd->urb; 805 int allocated = 0; 806 int retval; 807 808 /* 809 * Get the QH which holds the QTD-list to insert to. Create QH if it 810 * doesn't exist. 811 */ 812 if (*qh == NULL) { 813 *qh = dwc2_hcd_qh_create(hsotg, urb, mem_flags); 814 if (*qh == NULL) 815 return -ENOMEM; 816 allocated = 1; 817 } 818 819 retval = dwc2_hcd_qh_add(hsotg, *qh); 820 if (retval) 821 goto fail; 822 823 qtd->qh = *qh; 824 list_add_tail(&qtd->qtd_list_entry, &(*qh)->qtd_list); 825 826 return 0; 827 828 fail: 829 if (allocated) { 830 struct dwc2_qtd *qtd2, *qtd2_tmp; 831 struct dwc2_qh *qh_tmp = *qh; 832 833 *qh = NULL; 834 dwc2_hcd_qh_unlink(hsotg, qh_tmp); 835 836 /* Free each QTD in the QH's QTD list */ 837 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh_tmp->qtd_list, 838 qtd_list_entry) 839 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh_tmp); 840 841 dwc2_hcd_qh_free(hsotg, qh_tmp); 842 } 843 844 return retval; 845 } 846 847 void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 848 struct dwc2_qtd *qtd, 849 struct dwc2_qh *qh) 850 { 851 struct dwc2_softc *sc = hsotg->hsotg_sc; 852 853 list_del_init(&qtd->qtd_list_entry); 854 pool_put(sc->sc_qtdpool, qtd); 855 } 856 857 #define BITSTUFFTIME(bytecount) ((8 * 7 * (bytecount)) / 6) 858 #define HS_HOST_DELAY 5 /* nanoseconds */ 859 #define FS_LS_HOST_DELAY 1000 /* nanoseconds */ 860 #define HUB_LS_SETUP 333 /* nanoseconds */ 861 862 static u32 dwc2_calc_bus_time(struct dwc2_hsotg *hsotg, int speed, int is_in, 863 int is_isoc, int bytecount) 864 { 865 unsigned long retval; 866 867 switch (speed) { 868 case USB_SPEED_HIGH: 869 if (is_isoc) 870 retval = 871 ((38 * 8 * 2083) + 872 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 873 HS_HOST_DELAY; 874 else 875 retval = 876 ((55 * 8 * 2083) + 877 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 878 HS_HOST_DELAY; 879 break; 880 case USB_SPEED_FULL: 881 if (is_isoc) { 882 retval = 883 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 884 if (is_in) 885 retval = 7268 + FS_LS_HOST_DELAY + retval; 886 else 887 retval = 6265 + FS_LS_HOST_DELAY + retval; 888 } else { 889 retval = 890 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 891 retval = 9107 + FS_LS_HOST_DELAY + retval; 892 } 893 break; 894 case USB_SPEED_LOW: 895 if (is_in) { 896 retval = 897 (67667 * (31 + 10 * BITSTUFFTIME(bytecount))) / 898 1000; 899 retval = 900 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 901 retval; 902 } else { 903 retval = 904 (66700 * (31 + 10 * BITSTUFFTIME(bytecount))) / 905 1000; 906 retval = 907 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 908 retval; 909 } 910 break; 911 default: 912 dev_warn(hsotg->dev, "Unknown device speed\n"); 913 retval = -1; 914 } 915 916 return NS_TO_US(retval); 917 } 918