1 /* $OpenBSD: dwc2var.h,v 1.22 2021/07/30 18:05:24 mglocker Exp $ */ 2 /* $NetBSD: dwc2var.h,v 1.3 2013/10/22 12:57:40 skrll Exp $ */ 3 4 /*- 5 * Copyright (c) 2013 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Nick Hudson 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DWC2VAR_H_ 34 #define _DWC2VAR_H_ 35 36 #include <sys/pool.h> 37 #include <sys/task.h> 38 39 struct dwc2_hsotg; 40 struct dwc2_qtd; 41 42 struct dwc2_xfer { 43 struct usbd_xfer xfer; /* Needs to be first */ 44 45 struct dwc2_hcd_urb *urb; 46 47 TAILQ_ENTRY(dwc2_xfer) xnext; /* list of complete xfers */ 48 usbd_status intr_status; 49 }; 50 51 struct dwc2_pipe { 52 struct usbd_pipe pipe; /* Must be first */ 53 54 /* Current transfer */ 55 void *priv; /* QH */ 56 57 /* DMA buffer for control endpoint requests */ 58 struct usb_dma req_dma; 59 }; 60 61 62 #define DWC2_BUS2SC(bus) ((void *)(bus)) 63 #define DWC2_PIPE2SC(pipe) DWC2_BUS2SC((pipe)->device->bus) 64 #define DWC2_XFER2SC(xfer) DWC2_PIPE2SC((xfer)->pipe) 65 #define DWC2_DPIPE2SC(d) DWC2_BUS2SC((d)->pipe.device->bus) 66 67 #define DWC2_XFER2DXFER(x) (struct dwc2_xfer *)(x) 68 69 #define DWC2_XFER2DPIPE(x) (struct dwc2_pipe *)(x)->pipe; 70 #define DWC2_PIPE2DPIPE(p) (struct dwc2_pipe *)(p) 71 72 73 typedef struct dwc2_softc { 74 struct usbd_bus sc_bus; 75 76 bus_space_tag_t sc_iot; 77 bus_space_handle_t sc_ioh; 78 struct dwc2_core_params *sc_params; 79 int (*sc_set_dma_addr)(struct device *, bus_addr_t, int); 80 81 /* 82 * Private 83 */ 84 85 struct dwc2_hsotg *sc_hsotg; 86 87 struct mutex sc_lock; 88 89 bool sc_hcdenabled; 90 void *sc_rhc_si; 91 92 struct usbd_xfer *sc_intrxfer; 93 94 struct device *sc_child; /* /dev/usb# device */ 95 96 char sc_vendor[32]; /* vendor string for root hub */ 97 98 TAILQ_HEAD(, dwc2_xfer) sc_complete; /* complete transfers */ 99 100 struct pool sc_xferpool; 101 struct pool sc_qhpool; 102 struct pool sc_qtdpool; 103 104 uint8_t sc_addr; /* device address */ 105 uint8_t sc_conf; /* device configuration */ 106 107 } dwc2_softc_t; 108 109 int dwc2_init(struct dwc2_softc *); 110 int dwc2_intr(void *); 111 int dwc2_detach(dwc2_softc_t *, int); 112 113 void dwc2_worker(struct task *, void *); 114 115 void dwc2_host_complete(struct dwc2_hsotg *, struct dwc2_qtd *, 116 int); 117 118 static inline void 119 dwc2_root_intr(dwc2_softc_t *sc) 120 { 121 122 softintr_schedule(sc->sc_rhc_si); 123 } 124 125 /* 126 * XXX Compat 127 */ 128 #define DWC2_MAXISOCPACKETS 40 /* XXX: Fix nframes handling */ 129 #define ENOSR 90 130 #define device_xname(d) ((d)->dv_xname) 131 #define jiffies hardclock_ticks 132 #define mstohz(ms) \ 133 (__predict_false((ms) >= 0x20000) ? \ 134 ((ms +0u) / 1000u) * hz : \ 135 ((ms +0u) * hz) / 1000u) 136 #define msecs_to_jiffies mstohz 137 #define IS_ENABLED(option) (option) 138 139 #endif /* _DWC_OTGVAR_H_ */ 140