1 /* $OpenBSD: dwc2var.h,v 1.17 2016/09/24 12:59:42 kettenis Exp $ */ 2 /* $NetBSD: dwc2var.h,v 1.3 2013/10/22 12:57:40 skrll Exp $ */ 3 4 /*- 5 * Copyright (c) 2013 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Nick Hudson 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DWC2VAR_H_ 34 #define _DWC2VAR_H_ 35 36 #include <sys/pool.h> 37 38 struct task; 39 40 #define DWC2_MAXISOCPACKETS 16 41 struct dwc2_hsotg; 42 struct dwc2_qtd; 43 44 struct dwc2_xfer { 45 struct usbd_xfer xfer; /* Needs to be first */ 46 47 struct dwc2_hcd_urb *urb; 48 int packet_count; 49 50 TAILQ_ENTRY(dwc2_xfer) xnext; /* list of complete xfers */ 51 52 u_int32_t flags; 53 #define DWC2_XFER_ABORTING 0x0001 /* xfer is aborting. */ 54 #define DWC2_XFER_ABORTWAIT 0x0002 /* abort completion is being awaited. */ 55 }; 56 57 struct dwc2_pipe { 58 struct usbd_pipe pipe; /* Must be first */ 59 60 /* Current transfer */ 61 void *priv; /* QH */ 62 63 /* DMA buffer for control endpoint requests */ 64 struct usb_dma req_dma; 65 }; 66 67 68 #define DWC2_BUS2SC(bus) ((void *)(bus)) 69 #define DWC2_PIPE2SC(pipe) DWC2_BUS2SC((pipe)->device->bus) 70 #define DWC2_XFER2SC(xfer) DWC2_PIPE2SC((xfer)->pipe) 71 #define DWC2_DPIPE2SC(d) DWC2_BUS2SC((d)->pipe.device->bus) 72 73 #define DWC2_XFER2DXFER(x) (struct dwc2_xfer *)(x) 74 75 #define DWC2_XFER2DPIPE(x) (struct dwc2_pipe *)(x)->pipe; 76 #define DWC2_PIPE2DPIPE(p) (struct dwc2_pipe *)(p) 77 78 79 typedef struct dwc2_softc { 80 struct usbd_bus sc_bus; 81 82 bus_space_tag_t sc_iot; 83 bus_space_handle_t sc_ioh; 84 struct dwc2_core_params *sc_params; 85 struct dwc2_core_dma_config *sc_dma_config; 86 87 /* 88 * Private 89 */ 90 91 struct dwc2_hsotg *sc_hsotg; 92 93 bool sc_hcdenabled; 94 void *sc_rhc_si; 95 96 struct usbd_xfer *sc_intrxfer; 97 98 struct device *sc_child; /* /dev/usb# device */ 99 char sc_dying; 100 #if 0 101 struct usb_dma_reserve sc_dma_reserve; 102 #endif 103 104 char sc_vendor[32]; /* vendor string for root hub */ 105 int sc_id_vendor; /* vendor ID for root hub */ 106 107 TAILQ_HEAD(, dwc2_xfer) sc_complete; /* complete transfers */ 108 109 uint8_t sc_addr; /* device address */ 110 uint8_t sc_conf; /* device configuration */ 111 112 struct pool sc_xferpool; 113 struct pool sc_qhpool; 114 struct pool sc_qtdpool; 115 116 } dwc2_softc_t; 117 118 int dwc2_init(struct dwc2_softc *); 119 int dwc2_dma_config(struct dwc2_softc *, 120 struct dwc2_core_dma_config *); 121 int dwc2_intr(void *); 122 int dwc2_detach(dwc2_softc_t *, int); 123 124 void dwc2_worker(struct task *, void *); 125 126 void dwc2_host_complete(struct dwc2_hsotg *, struct dwc2_qtd *, 127 int); 128 129 #define DWC2_READ_4(hsotg, reg) \ 130 bus_space_read_4((hsotg)->hsotg_sc->sc_iot, (hsotg)->hsotg_sc->sc_ioh, \ 131 (reg)) 132 #define DWC2_WRITE_4(hsotg, reg, data) \ 133 bus_space_write_4((hsotg)->hsotg_sc->sc_iot, (hsotg)->hsotg_sc->sc_ioh, \ 134 (reg), (data)) 135 136 static inline void 137 dwc2_root_intr(dwc2_softc_t *sc) 138 { 139 140 softintr_schedule(sc->sc_rhc_si); 141 } 142 143 // XXX compat 144 145 #define mtx_owned(x) ((void)(x), 1) 146 147 #define ENOSR 90 148 #define EPROTO 96 149 150 #ifndef mstohz 151 #define mstohz(ms) \ 152 (__predict_false((ms) >= 0x20000) ? \ 153 ((ms +0u) / 1000u) * hz : \ 154 ((ms +0u) * hz) / 1000u) 155 #endif 156 157 #define timeout_reset(x, t, f, a) \ 158 do { \ 159 timeout_set((x), (f), (a)); \ 160 timeout_add((x), (t)); \ 161 } while (0) 162 163 #define device_xname(d) ((d)->dv_xname) 164 165 #endif /* _DWC_OTGVAR_H_ */ 166