1 /* $OpenBSD: ehci.c,v 1.106 2009/11/26 12:27:48 deraadt Exp $ */ 2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 10 * Jeremy Morse (jeremy.morse@gmail.com). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/usb_20.zip 41 */ 42 43 /* 44 * TODO: 45 * 1) The hub driver needs to handle and schedule the transaction translator, 46 * to assign place in frame where different devices get to go. See chapter 47 * on hubs in USB 2.0 for details. 48 * 49 * 2) Command failures are not recovered correctly. 50 */ 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/rwlock.h> 56 #include <sys/malloc.h> 57 #include <sys/device.h> 58 #include <sys/selinfo.h> 59 #include <sys/proc.h> 60 #include <sys/queue.h> 61 #include <sys/timeout.h> 62 63 #include <machine/bus.h> 64 #include <machine/endian.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 #include <dev/usb/usbdivar.h> 69 #include <dev/usb/usb_mem.h> 70 #include <dev/usb/usb_quirks.h> 71 72 #include <dev/usb/ehcireg.h> 73 #include <dev/usb/ehcivar.h> 74 75 #include <dev/rndvar.h> 76 77 struct cfdriver ehci_cd = { 78 NULL, "ehci", DV_DULL 79 }; 80 81 #ifdef EHCI_DEBUG 82 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 83 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 84 int ehcidebug = 0; 85 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n,x) 89 #endif 90 91 #define mstohz(ms) ((ms) * hz / 1000) 92 93 struct ehci_pipe { 94 struct usbd_pipe pipe; 95 96 ehci_soft_qh_t *sqh; 97 union { 98 ehci_soft_qtd_t *qtd; 99 /* ehci_soft_itd_t *itd; */ 100 } tail; 101 union { 102 /* Control pipe */ 103 struct { 104 usb_dma_t reqdma; 105 u_int length; 106 /*ehci_soft_qtd_t *setup, *data, *stat;*/ 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 u_int length; 111 } intr; 112 /* Bulk pipe */ 113 struct { 114 u_int length; 115 } bulk; 116 /* Iso pipe */ 117 struct { 118 u_int next_frame; 119 u_int cur_xfers; 120 } isoc; 121 } u; 122 }; 123 124 u_int8_t ehci_reverse_bits(u_int8_t, int); 125 126 void ehci_power(int, void *); 127 128 usbd_status ehci_open(usbd_pipe_handle); 129 void ehci_poll(struct usbd_bus *); 130 void ehci_softintr(void *); 131 int ehci_intr1(ehci_softc_t *); 132 void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 133 void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 134 void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 135 void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 136 void ehci_idone(struct ehci_xfer *); 137 void ehci_timeout(void *); 138 void ehci_timeout_task(void *); 139 void ehci_intrlist_timeout(void *); 140 141 usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 142 void ehci_freem(struct usbd_bus *, usb_dma_t *); 143 144 usbd_xfer_handle ehci_allocx(struct usbd_bus *); 145 void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 146 147 usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 148 usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 149 void ehci_root_ctrl_abort(usbd_xfer_handle); 150 void ehci_root_ctrl_close(usbd_pipe_handle); 151 void ehci_root_ctrl_done(usbd_xfer_handle); 152 153 usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 154 usbd_status ehci_root_intr_start(usbd_xfer_handle); 155 void ehci_root_intr_abort(usbd_xfer_handle); 156 void ehci_root_intr_close(usbd_pipe_handle); 157 void ehci_root_intr_done(usbd_xfer_handle); 158 159 usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 160 usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 161 void ehci_device_ctrl_abort(usbd_xfer_handle); 162 void ehci_device_ctrl_close(usbd_pipe_handle); 163 void ehci_device_ctrl_done(usbd_xfer_handle); 164 165 usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 166 usbd_status ehci_device_bulk_start(usbd_xfer_handle); 167 void ehci_device_bulk_abort(usbd_xfer_handle); 168 void ehci_device_bulk_close(usbd_pipe_handle); 169 void ehci_device_bulk_done(usbd_xfer_handle); 170 171 usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 172 usbd_status ehci_device_intr_start(usbd_xfer_handle); 173 void ehci_device_intr_abort(usbd_xfer_handle); 174 void ehci_device_intr_close(usbd_pipe_handle); 175 void ehci_device_intr_done(usbd_xfer_handle); 176 177 usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 178 usbd_status ehci_device_isoc_start(usbd_xfer_handle); 179 void ehci_device_isoc_abort(usbd_xfer_handle); 180 void ehci_device_isoc_close(usbd_pipe_handle); 181 void ehci_device_isoc_done(usbd_xfer_handle); 182 183 void ehci_device_clear_toggle(usbd_pipe_handle pipe); 184 void ehci_noop(usbd_pipe_handle pipe); 185 186 int ehci_str(usb_string_descriptor_t *, int, const char *); 187 void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 188 void ehci_disown(ehci_softc_t *, int, int); 189 190 ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 191 void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 192 193 ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 194 void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 195 usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 196 ehci_softc_t *, u_int, int, usbd_xfer_handle, 197 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 198 void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 199 ehci_soft_qtd_t *); 200 201 ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 202 void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 203 void ehci_rem_free_itd_chain(ehci_softc_t *sc, 204 struct ehci_xfer *exfer); 205 void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 206 usbd_status status); 207 208 usbd_status ehci_device_request(usbd_xfer_handle xfer); 209 210 usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 211 int ival); 212 213 void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 214 void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 215 ehci_soft_qh_t *); 216 void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 217 void ehci_sync_hc(ehci_softc_t *); 218 219 void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 220 void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 221 222 #ifdef EHCI_DEBUG 223 void ehci_dump_regs(ehci_softc_t *); 224 void ehci_dump(void); 225 ehci_softc_t *theehci; 226 void ehci_dump_link(ehci_link_t, int); 227 void ehci_dump_sqtds(ehci_soft_qtd_t *); 228 void ehci_dump_sqtd(ehci_soft_qtd_t *); 229 void ehci_dump_qtd(ehci_qtd_t *); 230 void ehci_dump_sqh(ehci_soft_qh_t *); 231 #if notyet 232 void ehci_dump_sitd(struct ehci_soft_itd *itd); 233 void ehci_dump_itd(struct ehci_soft_itd *); 234 #endif 235 #ifdef DIAGNOSTIC 236 void ehci_dump_exfer(struct ehci_xfer *); 237 #endif 238 #endif 239 240 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 241 242 #define EHCI_INTR_ENDPT 1 243 244 #define ehci_add_intr_list(sc, ex) \ 245 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 246 #define ehci_del_intr_list(sc, ex) \ 247 do { \ 248 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 249 (ex)->inext.tqe_prev = NULL; \ 250 } while (0) 251 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 252 253 struct usbd_bus_methods ehci_bus_methods = { 254 ehci_open, 255 ehci_softintr, 256 ehci_poll, 257 ehci_allocm, 258 ehci_freem, 259 ehci_allocx, 260 ehci_freex, 261 }; 262 263 struct usbd_pipe_methods ehci_root_ctrl_methods = { 264 ehci_root_ctrl_transfer, 265 ehci_root_ctrl_start, 266 ehci_root_ctrl_abort, 267 ehci_root_ctrl_close, 268 ehci_noop, 269 ehci_root_ctrl_done, 270 }; 271 272 struct usbd_pipe_methods ehci_root_intr_methods = { 273 ehci_root_intr_transfer, 274 ehci_root_intr_start, 275 ehci_root_intr_abort, 276 ehci_root_intr_close, 277 ehci_noop, 278 ehci_root_intr_done, 279 }; 280 281 struct usbd_pipe_methods ehci_device_ctrl_methods = { 282 ehci_device_ctrl_transfer, 283 ehci_device_ctrl_start, 284 ehci_device_ctrl_abort, 285 ehci_device_ctrl_close, 286 ehci_noop, 287 ehci_device_ctrl_done, 288 }; 289 290 struct usbd_pipe_methods ehci_device_intr_methods = { 291 ehci_device_intr_transfer, 292 ehci_device_intr_start, 293 ehci_device_intr_abort, 294 ehci_device_intr_close, 295 ehci_device_clear_toggle, 296 ehci_device_intr_done, 297 }; 298 299 struct usbd_pipe_methods ehci_device_bulk_methods = { 300 ehci_device_bulk_transfer, 301 ehci_device_bulk_start, 302 ehci_device_bulk_abort, 303 ehci_device_bulk_close, 304 ehci_device_clear_toggle, 305 ehci_device_bulk_done, 306 }; 307 308 struct usbd_pipe_methods ehci_device_isoc_methods = { 309 ehci_device_isoc_transfer, 310 ehci_device_isoc_start, 311 ehci_device_isoc_abort, 312 ehci_device_isoc_close, 313 ehci_noop, 314 ehci_device_isoc_done, 315 }; 316 317 /* 318 * Reverse a number with nbits bits. Used to evenly distribute lower-level 319 * interrupt heads in the periodic schedule. 320 * Suitable for use with EHCI_IPOLLRATES <= 9. 321 */ 322 u_int8_t 323 ehci_reverse_bits(u_int8_t c, int nbits) 324 { 325 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa); 326 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc); 327 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0); 328 329 return c >> (8 - nbits); 330 } 331 332 usbd_status 333 ehci_init(ehci_softc_t *sc) 334 { 335 u_int32_t sparams, cparams, hcr; 336 u_int i, j; 337 usbd_status err; 338 ehci_soft_qh_t *sqh; 339 340 #ifdef EHCI_DEBUG 341 u_int32_t vers; 342 theehci = sc; 343 344 DPRINTF(("ehci_init: start\n")); 345 346 vers = EREAD2(sc, EHCI_HCIVERSION); 347 DPRINTF(("%s: EHCI version %x.%x\n", sc->sc_bus.bdev.dv_xname, 348 vers >> 8, vers & 0xff)); 349 #endif 350 351 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 352 353 sparams = EREAD4(sc, EHCI_HCSPARAMS); 354 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 355 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 356 cparams = EREAD4(sc, EHCI_HCCPARAMS); 357 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 358 359 /* MUST clear segment register if 64 bit capable. */ 360 if (EHCI_HCC_64BIT(cparams)) 361 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 362 363 sc->sc_bus.usbrev = USBREV_2_0; 364 365 /* Reset the controller */ 366 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 367 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 368 usb_delay_ms(&sc->sc_bus, 1); 369 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 370 for (i = 0; i < 100; i++) { 371 usb_delay_ms(&sc->sc_bus, 1); 372 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 373 if (!hcr) 374 break; 375 } 376 if (hcr) { 377 printf("%s: reset timeout\n", 378 sc->sc_bus.bdev.dv_xname); 379 return (USBD_IOERROR); 380 } 381 382 /* XXX need proper intr scheduling */ 383 sc->sc_rand = 96; 384 385 /* frame list size at default, read back what we got and use that */ 386 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 387 case 0: 388 sc->sc_flsize = 1024; 389 break; 390 case 1: 391 sc->sc_flsize = 512; 392 break; 393 case 2: 394 sc->sc_flsize = 256; 395 break; 396 case 3: 397 return (USBD_IOERROR); 398 } 399 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 400 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 401 if (err) 402 return (err); 403 DPRINTF(("%s: flsize=%d\n", sc->sc_bus.bdev.dv_xname,sc->sc_flsize)); 404 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 405 406 for (i = 0; i < sc->sc_flsize; i++) 407 sc->sc_flist[i] = EHCI_NULL; 408 409 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 410 411 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 412 M_USB, M_NOWAIT | M_ZERO); 413 if (sc->sc_softitds == NULL) 414 return (ENOMEM); 415 LIST_INIT(&sc->sc_freeitds); 416 TAILQ_INIT(&sc->sc_intrhead); 417 418 /* Set up the bus struct. */ 419 sc->sc_bus.methods = &ehci_bus_methods; 420 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 421 422 sc->sc_powerhook = powerhook_establish(ehci_power, sc); 423 424 sc->sc_eintrs = EHCI_NORMAL_INTRS; 425 426 /* 427 * Allocate the interrupt dummy QHs. These are arranged to give poll 428 * intervals that are powers of 2 times 1ms. 429 */ 430 for (i = 0; i < EHCI_INTRQHS; i++) { 431 sqh = ehci_alloc_sqh(sc); 432 if (sqh == NULL) { 433 err = USBD_NOMEM; 434 goto bad1; 435 } 436 sc->sc_islots[i].sqh = sqh; 437 } 438 for (i = 0; i < EHCI_INTRQHS; i++) { 439 sqh = sc->sc_islots[i].sqh; 440 if (i == 0) { 441 /* The last (1ms) QH terminates. */ 442 sqh->qh.qh_link = EHCI_NULL; 443 sqh->next = NULL; 444 } else { 445 /* Otherwise the next QH has half the poll interval */ 446 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 447 sqh->qh.qh_link = htole32(sqh->next->physaddr | 448 EHCI_LINK_QH); 449 } 450 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 451 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 452 sqh->qh.qh_curqtd = EHCI_NULL; 453 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 454 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 455 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 456 sqh->sqtd = NULL; 457 } 458 /* Point the frame list at the last level (128ms). */ 459 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++) 460 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1)) 461 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[ 462 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits( 463 i, EHCI_IPOLLRATES - 1))].sqh->physaddr); 464 465 /* Allocate dummy QH that starts the async list. */ 466 sqh = ehci_alloc_sqh(sc); 467 if (sqh == NULL) { 468 err = USBD_NOMEM; 469 goto bad1; 470 } 471 /* Fill the QH */ 472 sqh->qh.qh_endp = 473 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 474 sqh->qh.qh_link = 475 htole32(sqh->physaddr | EHCI_LINK_QH); 476 sqh->qh.qh_curqtd = EHCI_NULL; 477 sqh->prev = sqh; /*It's a circular list.. */ 478 sqh->next = sqh; 479 /* Fill the overlay qTD */ 480 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 481 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 482 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 483 sqh->sqtd = NULL; 484 #ifdef EHCI_DEBUG 485 if (ehcidebug) 486 ehci_dump_sqh(sqh); 487 #endif 488 489 /* Point to async list */ 490 sc->sc_async_head = sqh; 491 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 492 493 timeout_set(&sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 494 495 rw_init(&sc->sc_doorbell_lock, "ehcidb"); 496 497 /* Turn on controller */ 498 EOWRITE4(sc, EHCI_USBCMD, 499 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 500 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 501 EHCI_CMD_ASE | 502 EHCI_CMD_PSE | 503 EHCI_CMD_RS); 504 505 /* Take over port ownership */ 506 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 507 508 for (i = 0; i < 100; i++) { 509 usb_delay_ms(&sc->sc_bus, 1); 510 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 511 if (!hcr) 512 break; 513 } 514 if (hcr) { 515 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 516 return (USBD_IOERROR); 517 } 518 519 /* Enable interrupts */ 520 DPRINTFN(1,("ehci_init: enabling\n")); 521 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 522 523 return (USBD_NORMAL_COMPLETION); 524 525 #if 0 526 bad2: 527 ehci_free_sqh(sc, sc->sc_async_head); 528 #endif 529 bad1: 530 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 531 return (err); 532 } 533 534 int 535 ehci_intr(void *v) 536 { 537 ehci_softc_t *sc = v; 538 539 if (sc == NULL || sc->sc_dying) 540 return (0); 541 542 /* If we get an interrupt while polling, then just ignore it. */ 543 if (sc->sc_bus.use_polling) { 544 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 545 546 if (intrs) 547 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 548 return (0); 549 } 550 551 return (ehci_intr1(sc)); 552 } 553 554 int 555 ehci_intr1(ehci_softc_t *sc) 556 { 557 u_int32_t intrs, eintrs; 558 559 DPRINTFN(20,("ehci_intr1: enter\n")); 560 561 /* In case the interrupt occurs before initialization has completed. */ 562 if (sc == NULL) { 563 #ifdef DIAGNOSTIC 564 printf("ehci_intr1: sc == NULL\n"); 565 #endif 566 return (0); 567 } 568 569 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 570 if (intrs == 0xffffffff) { 571 sc->sc_dying = 1; 572 return (0); 573 } 574 if (!intrs) 575 return (0); 576 577 eintrs = intrs & sc->sc_eintrs; 578 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 579 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), (u_int)eintrs)); 580 if (!eintrs) 581 return (0); 582 583 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 584 sc->sc_bus.intr_context++; 585 sc->sc_bus.no_intrs++; 586 if (eintrs & EHCI_STS_IAA) { 587 DPRINTF(("ehci_intr1: door bell\n")); 588 wakeup(&sc->sc_async_head); 589 eintrs &= ~EHCI_STS_IAA; 590 } 591 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 592 DPRINTFN(5,("ehci_intr1: %s %s\n", 593 eintrs & EHCI_STS_INT ? "INT" : "", 594 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 595 usb_schedsoftintr(&sc->sc_bus); 596 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 597 } 598 if (eintrs & EHCI_STS_HSE) { 599 printf("%s: unrecoverable error, controller halted\n", 600 sc->sc_bus.bdev.dv_xname); 601 /* XXX what else */ 602 } 603 if (eintrs & EHCI_STS_PCD) { 604 ehci_pcd(sc, sc->sc_intrxfer); 605 eintrs &= ~EHCI_STS_PCD; 606 } 607 608 sc->sc_bus.intr_context--; 609 610 if (eintrs != 0) { 611 /* Block unprocessed interrupts. */ 612 sc->sc_eintrs &= ~eintrs; 613 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 614 printf("%s: blocking intrs 0x%x\n", 615 sc->sc_bus.bdev.dv_xname, eintrs); 616 } 617 618 return (1); 619 } 620 621 void 622 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 623 { 624 u_char *p; 625 int i, m; 626 627 if (xfer == NULL) { 628 /* Just ignore the change. */ 629 return; 630 } 631 632 p = KERNADDR(&xfer->dmabuf, 0); 633 m = min(sc->sc_noport, xfer->length * 8 - 1); 634 memset(p, 0, xfer->length); 635 for (i = 1; i <= m; i++) { 636 /* Pick out CHANGE bits from the status reg. */ 637 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 638 p[i/8] |= 1 << (i%8); 639 } 640 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 641 xfer->actlen = xfer->length; 642 xfer->status = USBD_NORMAL_COMPLETION; 643 644 usb_transfer_complete(xfer); 645 } 646 647 void 648 ehci_softintr(void *v) 649 { 650 ehci_softc_t *sc = v; 651 struct ehci_xfer *ex, *nextex; 652 653 DPRINTFN(10,("%s: ehci_softintr (%d)\n", sc->sc_bus.bdev.dv_xname, 654 sc->sc_bus.intr_context)); 655 656 sc->sc_bus.intr_context++; 657 658 /* 659 * The only explanation I can think of for why EHCI is as brain dead 660 * as UHCI interrupt-wise is that Intel was involved in both. 661 * An interrupt just tells us that something is done, we have no 662 * clue what, so we need to scan through all active transfers. :-( 663 */ 664 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 665 nextex = TAILQ_NEXT(ex, inext); 666 ehci_check_intr(sc, ex); 667 } 668 669 /* Schedule a callout to catch any dropped transactions. */ 670 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 671 !TAILQ_EMPTY(&sc->sc_intrhead)) { 672 timeout_add_sec(&sc->sc_tmo_intrlist, 1); 673 } 674 675 if (sc->sc_softwake) { 676 sc->sc_softwake = 0; 677 wakeup(&sc->sc_softwake); 678 } 679 680 sc->sc_bus.intr_context--; 681 } 682 683 /* Check for an interrupt. */ 684 void 685 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 686 { 687 int attr; 688 689 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 690 691 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 692 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 693 ehci_check_itd_intr(sc, ex); 694 else 695 ehci_check_qh_intr(sc, ex); 696 697 return; 698 } 699 700 void 701 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 702 { 703 ehci_soft_qtd_t *sqtd, *lsqtd; 704 __uint32_t status; 705 706 if (ex->sqtdstart == NULL) { 707 printf("ehci_check_qh_intr: not valid sqtd\n"); 708 return; 709 } 710 711 lsqtd = ex->sqtdend; 712 #ifdef DIAGNOSTIC 713 if (lsqtd == NULL) { 714 printf("ehci_check_qh_intr: lsqtd==0\n"); 715 return; 716 } 717 #endif 718 /* 719 * If the last TD is still active we need to check whether there 720 * is a an error somewhere in the middle, or whether there was a 721 * short packet (SPD and not ACTIVE). 722 */ 723 if (letoh32(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 724 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 725 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 726 status = letoh32(sqtd->qtd.qtd_status); 727 /* If there's an active QTD the xfer isn't done. */ 728 if (status & EHCI_QTD_ACTIVE) 729 break; 730 /* Any kind of error makes the xfer done. */ 731 if (status & EHCI_QTD_HALTED) 732 goto done; 733 /* We want short packets, and it is short: it's done */ 734 if (EHCI_QTD_GET_BYTES(status) != 0) 735 goto done; 736 } 737 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 738 ex, ex->sqtdstart)); 739 return; 740 } 741 done: 742 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 743 timeout_del(&ex->xfer.timeout_handle); 744 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task); 745 ehci_idone(ex); 746 } 747 748 void 749 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 750 ehci_soft_itd_t *itd; 751 int i; 752 753 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 754 return; 755 756 if (ex->itdstart == NULL) { 757 printf("ehci_check_itd_intr: not valid itd\n"); 758 return; 759 } 760 761 itd = ex->itdend; 762 #ifdef DIAGNOSTIC 763 if (itd == NULL) { 764 printf("ehci_check_itd_intr: itdend == 0\n"); 765 return; 766 } 767 #endif 768 769 /* 770 * Step 1, check no active transfers in last itd, meaning we're finished 771 * check no active transfers in last itd, meaning we're finished 772 */ 773 for (i = 0; i < 8; i++) { 774 if (letoh32(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 775 break; 776 } 777 778 if (i == 8) { 779 goto done; /* All 8 descriptors inactive, it's done */ 780 } 781 782 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 783 ex->itdstart)); 784 return; 785 done: 786 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 787 timeout_del(&ex->xfer.timeout_handle); 788 ehci_idone(ex); 789 } 790 791 void 792 ehci_idone(struct ehci_xfer *ex) 793 { 794 usbd_xfer_handle xfer = &ex->xfer; 795 #ifdef EHCI_DEBUG 796 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 797 #endif 798 ehci_soft_qtd_t *sqtd, *lsqtd; 799 u_int32_t status = 0, nstatus = 0; 800 int actlen, cerr; 801 802 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 803 #ifdef DIAGNOSTIC 804 { 805 int s = splhigh(); 806 if (ex->isdone) { 807 splx(s); 808 #ifdef EHCI_DEBUG 809 printf("ehci_idone: ex is done!\n "); 810 ehci_dump_exfer(ex); 811 #else 812 printf("ehci_idone: ex=%p is done!\n", ex); 813 #endif 814 return; 815 } 816 ex->isdone = 1; 817 splx(s); 818 } 819 #endif 820 if (xfer->status == USBD_CANCELLED || 821 xfer->status == USBD_TIMEOUT) { 822 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 823 return; 824 } 825 826 #ifdef EHCI_DEBUG 827 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 828 if (ehcidebug > 10) 829 ehci_dump_sqtds(ex->sqtdstart); 830 #endif 831 832 /* The transfer is done, compute actual length and status. */ 833 834 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 835 == UE_ISOCHRONOUS) { 836 /* Isoc transfer */ 837 struct ehci_soft_itd *itd; 838 int i, nframes, len, uframes; 839 840 nframes = 0; 841 actlen = 0; 842 843 switch (xfer->pipe->endpoint->edesc->bInterval) { 844 case 0: 845 panic("ehci: isoc xfer suddenly has 0 bInterval, " 846 "invalid"); 847 case 1: 848 uframes = 1; 849 break; 850 case 2: 851 uframes = 2; 852 break; 853 case 3: 854 uframes = 4; 855 break; 856 default: 857 uframes = 8; 858 break; 859 } 860 861 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 862 for (i = 0; i < 8; i += uframes) { 863 /* XXX - driver didn't fill in the frame full 864 * of uframes. This leads to scheduling 865 * inefficiencies, but working around 866 * this doubles complexity of tracking 867 * an xfer. 868 */ 869 if (nframes >= xfer->nframes) 870 break; 871 872 status = letoh32(itd->itd.itd_ctl[i]); 873 len = EHCI_ITD_GET_LEN(status); 874 if (EHCI_ITD_GET_STATUS(status) != 0) 875 len = 0; /*No valid data on error*/ 876 877 xfer->frlengths[nframes++] = len; 878 actlen += len; 879 } 880 881 if (nframes >= xfer->nframes) 882 break; 883 } 884 885 xfer->actlen = actlen; 886 xfer->status = USBD_NORMAL_COMPLETION; 887 888 goto end; 889 } 890 891 /* Continue processing xfers using queue heads */ 892 893 lsqtd = ex->sqtdend; 894 actlen = 0; 895 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; 896 sqtd = sqtd->nextqtd) { 897 nstatus = letoh32(sqtd->qtd.qtd_status); 898 if (nstatus & EHCI_QTD_ACTIVE) 899 break; 900 901 status = nstatus; 902 /* halt is ok if descriptor is last, and complete */ 903 if (sqtd->qtd.qtd_next == EHCI_NULL && 904 EHCI_QTD_GET_BYTES(status) == 0) 905 status &= ~EHCI_QTD_HALTED; 906 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 907 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 908 } 909 910 cerr = EHCI_QTD_GET_CERR(status); 911 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 912 "status=0x%x\n", xfer->length, actlen, cerr, status)); 913 xfer->actlen = actlen; 914 if ((status & EHCI_QTD_HALTED) != 0) { 915 #ifdef EHCI_DEBUG 916 char sbuf[128]; 917 918 bitmask_snprintf((u_int32_t)status, 919 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 920 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 921 922 DPRINTFN(2, 923 ("ehci_idone: error, addr=%d, endpt=0x%02x, " 924 "status 0x%s\n", 925 xfer->pipe->device->address, 926 xfer->pipe->endpoint->edesc->bEndpointAddress, 927 sbuf)); 928 if (ehcidebug > 2) { 929 ehci_dump_sqh(epipe->sqh); 930 ehci_dump_sqtds(ex->sqtdstart); 931 } 932 #endif 933 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0) 934 xfer->status = USBD_STALLED; 935 else 936 xfer->status = USBD_IOERROR; /* more info XXX */ 937 } else 938 xfer->status = USBD_NORMAL_COMPLETION; 939 end: 940 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 941 * during this call, before methods->done is called: dma sync required 942 * beforehand? */ 943 usb_transfer_complete(xfer); 944 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 945 } 946 947 /* 948 * Wait here until controller claims to have an interrupt. 949 * Then call ehci_intr and return. Use timeout to avoid waiting 950 * too long. 951 */ 952 void 953 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 954 { 955 int timo; 956 u_int32_t intrs; 957 958 xfer->status = USBD_IN_PROGRESS; 959 for (timo = xfer->timeout; timo >= 0; timo--) { 960 usb_delay_ms(&sc->sc_bus, 1); 961 if (sc->sc_dying) 962 break; 963 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 964 sc->sc_eintrs; 965 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 966 #ifdef EHCI_DEBUG 967 if (ehcidebug > 15) 968 ehci_dump_regs(sc); 969 #endif 970 if (intrs) { 971 ehci_intr1(sc); 972 if (xfer->status != USBD_IN_PROGRESS) 973 return; 974 } 975 } 976 977 /* Timeout */ 978 DPRINTF(("ehci_waitintr: timeout\n")); 979 xfer->status = USBD_TIMEOUT; 980 usb_transfer_complete(xfer); 981 /* XXX should free TD */ 982 } 983 984 void 985 ehci_poll(struct usbd_bus *bus) 986 { 987 ehci_softc_t *sc = (ehci_softc_t *)bus; 988 #ifdef EHCI_DEBUG 989 static int last; 990 int new; 991 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 992 if (new != last) { 993 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 994 last = new; 995 } 996 #endif 997 998 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 999 ehci_intr1(sc); 1000 } 1001 1002 int 1003 ehci_detach(struct ehci_softc *sc, int flags) 1004 { 1005 int rv = 0; 1006 1007 if (sc->sc_child != NULL) 1008 rv = config_detach(sc->sc_child, flags); 1009 1010 if (rv != 0) 1011 return (rv); 1012 1013 timeout_del(&sc->sc_tmo_intrlist); 1014 1015 if (sc->sc_powerhook != NULL) 1016 powerhook_disestablish(sc->sc_powerhook); 1017 if (sc->sc_shutdownhook != NULL) 1018 shutdownhook_disestablish(sc->sc_shutdownhook); 1019 1020 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1021 1022 /* XXX free other data structures XXX */ 1023 1024 return (rv); 1025 } 1026 1027 1028 int 1029 ehci_activate(struct device *self, int act) 1030 { 1031 struct ehci_softc *sc = (struct ehci_softc *)self; 1032 int rv = 0; 1033 1034 switch (act) { 1035 case DVACT_ACTIVATE: 1036 break; 1037 1038 case DVACT_DEACTIVATE: 1039 if (sc->sc_child != NULL) 1040 rv = config_deactivate(sc->sc_child); 1041 sc->sc_dying = 1; 1042 break; 1043 case DVACT_SUSPEND: 1044 ehci_power(PWR_SUSPEND, sc); 1045 break; 1046 case DVACT_RESUME: 1047 ehci_power(PWR_RESUME, sc); 1048 rv = config_activate_children(self, act); 1049 break; 1050 } 1051 return (rv); 1052 } 1053 1054 /* 1055 * Handle suspend/resume. 1056 * 1057 * We need to switch to polling mode here, because this routine is 1058 * called from an interrupt context. This is all right since we 1059 * are almost suspended anyway. 1060 */ 1061 void 1062 ehci_power(int why, void *v) 1063 { 1064 ehci_softc_t *sc = v; 1065 u_int32_t cmd, hcr; 1066 int s, i; 1067 1068 #ifdef EHCI_DEBUG 1069 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 1070 if (ehcidebug > 0) 1071 ehci_dump_regs(sc); 1072 #endif 1073 1074 s = splhardusb(); 1075 switch (why) { 1076 case PWR_SUSPEND: 1077 case PWR_STANDBY: 1078 sc->sc_bus.use_polling++; 1079 1080 for (i = 1; i <= sc->sc_noport; i++) { 1081 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1082 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE) 1083 EOWRITE4(sc, EHCI_PORTSC(i), 1084 cmd | EHCI_PS_SUSP); 1085 } 1086 1087 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1088 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1089 EOWRITE4(sc, EHCI_USBCMD, cmd); 1090 1091 for (i = 0; i < 100; i++) { 1092 hcr = EOREAD4(sc, EHCI_USBSTS) & 1093 (EHCI_STS_ASS | EHCI_STS_PSS); 1094 if (hcr == 0) 1095 break; 1096 1097 usb_delay_ms(&sc->sc_bus, 1); 1098 } 1099 if (hcr != 0) 1100 printf("%s: reset timeout\n", 1101 sc->sc_bus.bdev.dv_xname); 1102 1103 cmd &= ~EHCI_CMD_RS; 1104 EOWRITE4(sc, EHCI_USBCMD, cmd); 1105 1106 for (i = 0; i < 100; i++) { 1107 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1108 if (hcr == EHCI_STS_HCH) 1109 break; 1110 1111 usb_delay_ms(&sc->sc_bus, 1); 1112 } 1113 if (hcr != EHCI_STS_HCH) 1114 printf("%s: config timeout\n", 1115 sc->sc_bus.bdev.dv_xname); 1116 1117 sc->sc_bus.use_polling--; 1118 break; 1119 1120 case PWR_RESUME: 1121 sc->sc_bus.use_polling++; 1122 1123 /* restore things in case the bios sucks */ 1124 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1125 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1126 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1127 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1128 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1129 1130 hcr = 0; 1131 for (i = 1; i <= sc->sc_noport; i++) { 1132 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1133 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP) { 1134 EOWRITE4(sc, EHCI_PORTSC(i), 1135 cmd | EHCI_PS_FPR); 1136 hcr = 1; 1137 } 1138 } 1139 1140 if (hcr) { 1141 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1142 for (i = 1; i <= sc->sc_noport; i++) { 1143 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1144 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == 1145 EHCI_PS_SUSP) 1146 EOWRITE4(sc, EHCI_PORTSC(i), 1147 cmd & ~EHCI_PS_FPR); 1148 } 1149 } 1150 1151 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1152 1153 /* Take over port ownership */ 1154 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 1155 1156 for (i = 0; i < 100; i++) { 1157 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1158 if (hcr != EHCI_STS_HCH) 1159 break; 1160 1161 usb_delay_ms(&sc->sc_bus, 1); 1162 } 1163 if (hcr == EHCI_STS_HCH) 1164 printf("%s: config timeout\n", 1165 sc->sc_bus.bdev.dv_xname); 1166 1167 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1168 1169 sc->sc_bus.use_polling--; 1170 break; 1171 } 1172 splx(s); 1173 1174 #ifdef EHCI_DEBUG 1175 DPRINTF(("ehci_power: sc=%p\n", sc)); 1176 if (ehcidebug > 0) 1177 ehci_dump_regs(sc); 1178 #endif 1179 } 1180 1181 /* 1182 * Shut down the controller when the system is going down. 1183 */ 1184 void 1185 ehci_shutdown(void *v) 1186 { 1187 ehci_softc_t *sc = v; 1188 1189 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1190 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1191 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1192 } 1193 1194 usbd_status 1195 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1196 { 1197 struct ehci_softc *sc = (struct ehci_softc *)bus; 1198 usbd_status err; 1199 1200 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1201 #ifdef EHCI_DEBUG 1202 if (err) 1203 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1204 #endif 1205 return (err); 1206 } 1207 1208 void 1209 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1210 { 1211 struct ehci_softc *sc = (struct ehci_softc *)bus; 1212 1213 usb_freemem(&sc->sc_bus, dma); 1214 } 1215 1216 usbd_xfer_handle 1217 ehci_allocx(struct usbd_bus *bus) 1218 { 1219 struct ehci_softc *sc = (struct ehci_softc *)bus; 1220 usbd_xfer_handle xfer; 1221 1222 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1223 if (xfer != NULL) { 1224 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1225 #ifdef DIAGNOSTIC 1226 if (xfer->busy_free != XFER_FREE) 1227 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", 1228 xfer, xfer->busy_free); 1229 #endif 1230 } else 1231 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1232 1233 if (xfer != NULL) { 1234 memset(xfer, 0, sizeof(struct ehci_xfer)); 1235 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task, 1236 xfer); 1237 EXFER(xfer)->ehci_xfer_flags = 0; 1238 #ifdef DIAGNOSTIC 1239 EXFER(xfer)->isdone = 1; 1240 xfer->busy_free = XFER_BUSY; 1241 #endif 1242 } 1243 return (xfer); 1244 } 1245 1246 void 1247 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1248 { 1249 struct ehci_softc *sc = (struct ehci_softc *)bus; 1250 1251 #ifdef DIAGNOSTIC 1252 if (xfer->busy_free != XFER_BUSY) { 1253 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1254 xfer->busy_free); 1255 return; 1256 } 1257 xfer->busy_free = XFER_FREE; 1258 if (!EXFER(xfer)->isdone) { 1259 printf("ehci_freex: !isdone\n"); 1260 return; 1261 } 1262 #endif 1263 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1264 } 1265 1266 void 1267 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1268 { 1269 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1270 1271 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1272 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1273 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 1274 if (ehcidebug) 1275 usbd_dump_pipe(pipe); 1276 #endif 1277 #ifdef DIAGNOSTIC 1278 if ((epipe->sqh->qh.qh_qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) != 0) 1279 panic("ehci_device_clear_toggle: queue active"); 1280 #endif 1281 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1282 } 1283 1284 void 1285 ehci_noop(usbd_pipe_handle pipe) 1286 { 1287 } 1288 1289 #ifdef EHCI_DEBUG 1290 void 1291 ehci_dump_regs(ehci_softc_t *sc) 1292 { 1293 int i; 1294 1295 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1296 EOREAD4(sc, EHCI_USBCMD), 1297 EOREAD4(sc, EHCI_USBSTS), 1298 EOREAD4(sc, EHCI_USBINTR)); 1299 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1300 EOREAD4(sc, EHCI_FRINDEX), 1301 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1302 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1303 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1304 for (i = 1; i <= sc->sc_noport; i++) 1305 printf("port %d status=0x%08x\n", i, 1306 EOREAD4(sc, EHCI_PORTSC(i))); 1307 } 1308 1309 /* 1310 * Unused function - this is meant to be called from a kernel 1311 * debugger. 1312 */ 1313 void 1314 ehci_dump() 1315 { 1316 ehci_dump_regs(theehci); 1317 } 1318 1319 void 1320 ehci_dump_link(ehci_link_t link, int type) 1321 { 1322 link = letoh32(link); 1323 printf("0x%08x", link); 1324 if (link & EHCI_LINK_TERMINATE) 1325 printf("<T>"); 1326 else { 1327 printf("<"); 1328 if (type) { 1329 switch (EHCI_LINK_TYPE(link)) { 1330 case EHCI_LINK_ITD: 1331 printf("ITD"); 1332 break; 1333 case EHCI_LINK_QH: 1334 printf("QH"); 1335 break; 1336 case EHCI_LINK_SITD: 1337 printf("SITD"); 1338 break; 1339 case EHCI_LINK_FSTN: 1340 printf("FSTN"); 1341 break; 1342 } 1343 } 1344 printf(">"); 1345 } 1346 } 1347 1348 void 1349 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1350 { 1351 int i; 1352 u_int32_t stop; 1353 1354 stop = 0; 1355 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1356 ehci_dump_sqtd(sqtd); 1357 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1358 } 1359 if (!stop) 1360 printf("dump aborted, too many TDs\n"); 1361 } 1362 1363 void 1364 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1365 { 1366 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1367 ehci_dump_qtd(&sqtd->qtd); 1368 } 1369 1370 void 1371 ehci_dump_qtd(ehci_qtd_t *qtd) 1372 { 1373 u_int32_t s; 1374 char sbuf[128]; 1375 1376 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1377 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1378 printf("\n"); 1379 s = letoh32(qtd->qtd_status); 1380 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED" 1381 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING", 1382 sbuf, sizeof(sbuf)); 1383 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1384 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1385 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1386 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1387 EHCI_QTD_GET_PID(s), sbuf); 1388 for (s = 0; s < 5; s++) 1389 printf(" buffer[%d]=0x%08x\n", s, letoh32(qtd->qtd_buffer[s])); 1390 } 1391 1392 void 1393 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1394 { 1395 ehci_qh_t *qh = &sqh->qh; 1396 u_int32_t endp, endphub; 1397 1398 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1399 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1400 endp = letoh32(qh->qh_endp); 1401 printf(" endp=0x%08x\n", endp); 1402 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1403 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1404 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1405 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1406 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1407 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1408 EHCI_QH_GET_NRL(endp)); 1409 endphub = letoh32(qh->qh_endphub); 1410 printf(" endphub=0x%08x\n", endphub); 1411 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1412 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1413 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1414 EHCI_QH_GET_MULT(endphub)); 1415 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1416 printf("Overlay qTD:\n"); 1417 ehci_dump_qtd(&qh->qh_qtd); 1418 } 1419 1420 #if notyet 1421 void 1422 ehci_dump_itd(struct ehci_soft_itd *itd) 1423 { 1424 ehci_isoc_trans_t t; 1425 ehci_isoc_bufr_ptr_t b, b2, b3; 1426 int i; 1427 1428 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1429 1430 for (i = 0; i < 8;i++) { 1431 t = letoh32(itd->itd.itd_ctl[i]); 1432 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1433 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1434 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1435 EHCI_ITD_GET_OFFS(t)); 1436 } 1437 printf("ITDbufr: "); 1438 for (i = 0; i < 7; i++) 1439 printf("%X,", EHCI_ITD_GET_BPTR(letoh32(itd->itd.itd_bufr[i]))); 1440 1441 b = letoh32(itd->itd.itd_bufr[0]); 1442 b2 = letoh32(itd->itd.itd_bufr[1]); 1443 b3 = letoh32(itd->itd.itd_bufr[2]); 1444 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1445 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1446 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1447 } 1448 1449 void 1450 ehci_dump_sitd(struct ehci_soft_itd *itd) 1451 { 1452 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1453 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1454 itd->xfer_next, itd->physaddr, itd->slot); 1455 } 1456 #endif 1457 1458 #ifdef DIAGNOSTIC 1459 void 1460 ehci_dump_exfer(struct ehci_xfer *ex) 1461 { 1462 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p " 1463 "isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, 1464 ex->itdend, ex->isdone); 1465 } 1466 #endif 1467 1468 #endif /* EHCI_DEBUG */ 1469 1470 usbd_status 1471 ehci_open(usbd_pipe_handle pipe) 1472 { 1473 usbd_device_handle dev = pipe->device; 1474 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1475 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1476 u_int8_t addr = dev->address; 1477 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1478 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1479 ehci_soft_qh_t *sqh; 1480 usbd_status err; 1481 int s; 1482 int ival, speed, naks; 1483 int hshubaddr, hshubport; 1484 1485 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1486 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1487 1488 if (sc->sc_dying) 1489 return (USBD_IOERROR); 1490 1491 if (dev->myhsport) { 1492 hshubaddr = dev->myhsport->parent->address; 1493 hshubport = dev->myhsport->portno; 1494 } else { 1495 hshubaddr = 0; 1496 hshubport = 0; 1497 } 1498 1499 if (addr == sc->sc_addr) { 1500 switch (ed->bEndpointAddress) { 1501 case USB_CONTROL_ENDPOINT: 1502 pipe->methods = &ehci_root_ctrl_methods; 1503 break; 1504 case UE_DIR_IN | EHCI_INTR_ENDPT: 1505 pipe->methods = &ehci_root_intr_methods; 1506 break; 1507 default: 1508 return (USBD_INVAL); 1509 } 1510 return (USBD_NORMAL_COMPLETION); 1511 } 1512 1513 /* XXX All this stuff is only valid for async. */ 1514 switch (dev->speed) { 1515 case USB_SPEED_LOW: 1516 speed = EHCI_QH_SPEED_LOW; 1517 break; 1518 case USB_SPEED_FULL: 1519 speed = EHCI_QH_SPEED_FULL; 1520 break; 1521 case USB_SPEED_HIGH: 1522 speed = EHCI_QH_SPEED_HIGH; 1523 break; 1524 default: 1525 panic("ehci_open: bad device speed %d", dev->speed); 1526 } 1527 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1528 printf("%s: Error opening low/full speed isoc endpoint.\n" 1529 "A low/full speed device is attached to a USB2 hub, and " 1530 "transaction translations are not yet supported.\n" 1531 "Reattach the device to the root hub instead.\n", 1532 sc->sc_bus.bdev.dv_xname); 1533 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1534 hshubaddr, hshubport)); 1535 return (USBD_INVAL); 1536 } 1537 1538 naks = 8; /* XXX */ 1539 1540 /* Allocate sqh for everything, save isoc xfers */ 1541 if (xfertype != UE_ISOCHRONOUS) { 1542 sqh = ehci_alloc_sqh(sc); 1543 if (sqh == NULL) 1544 return (USBD_NOMEM); 1545 /* qh_link filled when the QH is added */ 1546 sqh->qh.qh_endp = htole32( 1547 EHCI_QH_SET_ADDR(addr) | 1548 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1549 EHCI_QH_SET_EPS(speed) | 1550 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1551 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1552 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1553 EHCI_QH_CTL : 0) | 1554 EHCI_QH_SET_NRL(naks) 1555 ); 1556 sqh->qh.qh_endphub = htole32( 1557 EHCI_QH_SET_MULT(1) | 1558 EHCI_QH_SET_HUBA(hshubaddr) | 1559 EHCI_QH_SET_PORT(hshubport) | 1560 EHCI_QH_SET_CMASK(0x1c) | /* XXX */ 1561 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1562 ); 1563 sqh->qh.qh_curqtd = EHCI_NULL; 1564 /* Fill the overlay qTD */ 1565 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1566 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1567 sqh->qh.qh_qtd.qtd_status = 1568 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1569 epipe->sqh = sqh; 1570 } else { 1571 sqh = NULL; 1572 } /*xfertype == UE_ISOC*/ 1573 1574 switch (xfertype) { 1575 case UE_CONTROL: 1576 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1577 0, &epipe->u.ctl.reqdma); 1578 #ifdef EHCI_DEBUG 1579 if (err) 1580 printf("ehci_open: usb_allocmem()=%d\n", err); 1581 #endif 1582 if (err) 1583 goto bad; 1584 pipe->methods = &ehci_device_ctrl_methods; 1585 s = splusb(); 1586 ehci_add_qh(sqh, sc->sc_async_head); 1587 splx(s); 1588 break; 1589 case UE_BULK: 1590 pipe->methods = &ehci_device_bulk_methods; 1591 s = splusb(); 1592 ehci_add_qh(sqh, sc->sc_async_head); 1593 splx(s); 1594 break; 1595 case UE_INTERRUPT: 1596 pipe->methods = &ehci_device_intr_methods; 1597 ival = pipe->interval; 1598 if (ival == USBD_DEFAULT_INTERVAL) 1599 ival = ed->bInterval; 1600 s = splusb(); 1601 err = ehci_device_setintr(sc, sqh, ival); 1602 splx(s); 1603 return (err); 1604 case UE_ISOCHRONOUS: 1605 pipe->methods = &ehci_device_isoc_methods; 1606 if (ed->bInterval == 0 || ed->bInterval > 16) { 1607 printf("ehci: opening pipe with invalid bInterval\n"); 1608 err = USBD_INVAL; 1609 goto bad; 1610 } 1611 if (UGETW(ed->wMaxPacketSize) == 0) { 1612 printf("ehci: zero length endpoint open request\n"); 1613 err = USBD_INVAL; 1614 goto bad; 1615 } 1616 epipe->u.isoc.next_frame = 0; 1617 epipe->u.isoc.cur_xfers = 0; 1618 break; 1619 default: 1620 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1621 return (USBD_INVAL); 1622 } 1623 return (USBD_NORMAL_COMPLETION); 1624 1625 bad: 1626 if (sqh != NULL) 1627 ehci_free_sqh(sc, sqh); 1628 return (err); 1629 } 1630 1631 /* 1632 * Add an ED to the schedule. Called at splusb(). 1633 * If in the async schedule, it will always have a next. 1634 * If in the intr schedule it may not. 1635 */ 1636 void 1637 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1638 { 1639 SPLUSBCHECK; 1640 1641 sqh->next = head->next; 1642 sqh->prev = head; 1643 sqh->qh.qh_link = head->qh.qh_link; 1644 head->next = sqh; 1645 if (sqh->next) 1646 sqh->next->prev = sqh; 1647 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1648 1649 #ifdef EHCI_DEBUG 1650 if (ehcidebug > 5) { 1651 printf("ehci_add_qh:\n"); 1652 ehci_dump_sqh(sqh); 1653 } 1654 #endif 1655 } 1656 1657 /* 1658 * Remove an ED from the schedule. Called at splusb(). 1659 * Will always have a 'next' if it's in the async list as it's circular. 1660 */ 1661 void 1662 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1663 { 1664 SPLUSBCHECK; 1665 /* XXX */ 1666 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1667 sqh->prev->next = sqh->next; 1668 if (sqh->next) 1669 sqh->next->prev = sqh->prev; 1670 ehci_sync_hc(sc); 1671 } 1672 1673 void 1674 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1675 { 1676 int i; 1677 u_int32_t status; 1678 1679 /* Save toggle bit and ping status. */ 1680 status = sqh->qh.qh_qtd.qtd_status & 1681 htole32(EHCI_QTD_TOGGLE_MASK | 1682 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1683 /* Set HALTED to make hw leave it alone. */ 1684 sqh->qh.qh_qtd.qtd_status = 1685 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1686 sqh->qh.qh_curqtd = 0; 1687 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1688 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1689 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1690 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1691 sqh->sqtd = sqtd; 1692 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1693 sqh->qh.qh_qtd.qtd_status = status; 1694 } 1695 1696 /* 1697 * Ensure that the HC has released all references to the QH. We do this 1698 * by asking for a Async Advance Doorbell interrupt and then we wait for 1699 * the interrupt. 1700 * To make this easier we first obtain exclusive use of the doorbell. 1701 */ 1702 void 1703 ehci_sync_hc(ehci_softc_t *sc) 1704 { 1705 int s, error; 1706 int tries = 0; 1707 1708 if (sc->sc_dying) { 1709 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1710 return; 1711 } 1712 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1713 /* get doorbell */ 1714 rw_enter_write(&sc->sc_doorbell_lock); 1715 s = splhardusb(); 1716 do { 1717 /* ask for doorbell */ 1718 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | 1719 EHCI_CMD_IAAD); 1720 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1721 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1722 /* bell wait */ 1723 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz / 2); 1724 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1725 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1726 } while (error && ++tries < 10); 1727 splx(s); 1728 /* release doorbell */ 1729 rw_exit_write(&sc->sc_doorbell_lock); 1730 #ifdef DIAGNOSTIC 1731 if (error) 1732 printf("ehci_sync_hc: tsleep() = %d\n", error); 1733 #endif 1734 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1735 } 1736 1737 /*Call at splusb*/ 1738 void 1739 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1740 { 1741 struct ehci_soft_itd *itd, *prev; 1742 1743 prev = NULL; 1744 1745 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1746 panic("ehci isoc xfer being freed, but with no itd chain"); 1747 1748 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1749 prev = itd->u.frame_list.prev; 1750 /* Unlink itd from hardware chain, or frame array */ 1751 if (prev == NULL) { /* We're at the table head */ 1752 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1753 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1754 1755 if (itd->u.frame_list.next != NULL) 1756 itd->u.frame_list.next->u.frame_list.prev = 1757 NULL; 1758 } else { 1759 /* XXX this part is untested... */ 1760 prev->itd.itd_next = itd->itd.itd_next; 1761 prev->u.frame_list.next = itd->u.frame_list.next; 1762 if (itd->u.frame_list.next != NULL) 1763 itd->u.frame_list.next->u.frame_list.prev = 1764 prev; 1765 } 1766 } 1767 1768 prev = NULL; 1769 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1770 if (prev != NULL) 1771 ehci_free_itd(sc, prev); 1772 prev = itd; 1773 } 1774 if (prev) 1775 ehci_free_itd(sc, prev); 1776 exfer->itdstart = NULL; 1777 exfer->itdend = NULL; 1778 } 1779 1780 /***********/ 1781 1782 /* 1783 * Data structures and routines to emulate the root hub. 1784 */ 1785 usb_device_descriptor_t ehci_devd = { 1786 USB_DEVICE_DESCRIPTOR_SIZE, 1787 UDESC_DEVICE, /* type */ 1788 {0x00, 0x02}, /* USB version */ 1789 UDCLASS_HUB, /* class */ 1790 UDSUBCLASS_HUB, /* subclass */ 1791 UDPROTO_HSHUBSTT, /* protocol */ 1792 64, /* max packet */ 1793 {0},{0},{0x00,0x01}, /* device id */ 1794 1,2,0, /* string indicies */ 1795 1 /* # of configurations */ 1796 }; 1797 1798 usb_device_qualifier_t ehci_odevd = { 1799 USB_DEVICE_DESCRIPTOR_SIZE, 1800 UDESC_DEVICE_QUALIFIER, /* type */ 1801 {0x00, 0x02}, /* USB version */ 1802 UDCLASS_HUB, /* class */ 1803 UDSUBCLASS_HUB, /* subclass */ 1804 UDPROTO_FSHUB, /* protocol */ 1805 64, /* max packet */ 1806 1, /* # of configurations */ 1807 0 1808 }; 1809 1810 usb_config_descriptor_t ehci_confd = { 1811 USB_CONFIG_DESCRIPTOR_SIZE, 1812 UDESC_CONFIG, 1813 {USB_CONFIG_DESCRIPTOR_SIZE + 1814 USB_INTERFACE_DESCRIPTOR_SIZE + 1815 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1816 1, 1817 1, 1818 0, 1819 UC_SELF_POWERED, 1820 0 /* max power */ 1821 }; 1822 1823 usb_interface_descriptor_t ehci_ifcd = { 1824 USB_INTERFACE_DESCRIPTOR_SIZE, 1825 UDESC_INTERFACE, 1826 0, 1827 0, 1828 1, 1829 UICLASS_HUB, 1830 UISUBCLASS_HUB, 1831 UIPROTO_HSHUBSTT, 1832 0 1833 }; 1834 1835 usb_endpoint_descriptor_t ehci_endpd = { 1836 USB_ENDPOINT_DESCRIPTOR_SIZE, 1837 UDESC_ENDPOINT, 1838 UE_DIR_IN | EHCI_INTR_ENDPT, 1839 UE_INTERRUPT, 1840 {8, 0}, /* max packet */ 1841 255 1842 }; 1843 1844 usb_hub_descriptor_t ehci_hubd = { 1845 USB_HUB_DESCRIPTOR_SIZE, 1846 UDESC_HUB, 1847 0, 1848 {0,0}, 1849 0, 1850 0, 1851 {0}, 1852 }; 1853 1854 int 1855 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 1856 { 1857 int i; 1858 1859 if (l == 0) 1860 return (0); 1861 p->bLength = 2 * strlen(s) + 2; 1862 if (l == 1) 1863 return (1); 1864 p->bDescriptorType = UDESC_STRING; 1865 l -= 2; 1866 for (i = 0; s[i] && l > 1; i++, l -= 2) 1867 USETW2(p->bString[i], 0, s[i]); 1868 return (2*i+2); 1869 } 1870 1871 /* 1872 * Simulate a hardware hub by handling all the necessary requests. 1873 */ 1874 usbd_status 1875 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1876 { 1877 usbd_status err; 1878 1879 /* Insert last in queue. */ 1880 err = usb_insert_transfer(xfer); 1881 if (err) 1882 return (err); 1883 1884 /* Pipe isn't running, start first */ 1885 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1886 } 1887 1888 usbd_status 1889 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1890 { 1891 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1892 usb_device_request_t *req; 1893 void *buf = NULL; 1894 int port, i; 1895 int s, len, value, index, l, totlen = 0; 1896 usb_port_status_t ps; 1897 usb_hub_descriptor_t hubd; 1898 usbd_status err; 1899 u_int32_t v; 1900 1901 if (sc->sc_dying) 1902 return (USBD_IOERROR); 1903 1904 #ifdef DIAGNOSTIC 1905 if (!(xfer->rqflags & URQ_REQUEST)) 1906 /* XXX panic */ 1907 return (USBD_INVAL); 1908 #endif 1909 req = &xfer->request; 1910 1911 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1912 req->bmRequestType, req->bRequest)); 1913 1914 len = UGETW(req->wLength); 1915 value = UGETW(req->wValue); 1916 index = UGETW(req->wIndex); 1917 1918 if (len != 0) 1919 buf = KERNADDR(&xfer->dmabuf, 0); 1920 1921 #define C(x,y) ((x) | ((y) << 8)) 1922 switch(C(req->bRequest, req->bmRequestType)) { 1923 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1924 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1925 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1926 /* 1927 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1928 * for the integrated root hub. 1929 */ 1930 break; 1931 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1932 if (len > 0) { 1933 *(u_int8_t *)buf = sc->sc_conf; 1934 totlen = 1; 1935 } 1936 break; 1937 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1938 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1939 switch(value >> 8) { 1940 case UDESC_DEVICE: 1941 if ((value & 0xff) != 0) { 1942 err = USBD_IOERROR; 1943 goto ret; 1944 } 1945 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1946 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1947 memcpy(buf, &ehci_devd, l); 1948 break; 1949 /* 1950 * We can't really operate at another speed, but the spec says 1951 * we need this descriptor. 1952 */ 1953 case UDESC_DEVICE_QUALIFIER: 1954 if ((value & 0xff) != 0) { 1955 err = USBD_IOERROR; 1956 goto ret; 1957 } 1958 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1959 memcpy(buf, &ehci_odevd, l); 1960 break; 1961 /* 1962 * We can't really operate at another speed, but the spec says 1963 * we need this descriptor. 1964 */ 1965 case UDESC_OTHER_SPEED_CONFIGURATION: 1966 case UDESC_CONFIG: 1967 if ((value & 0xff) != 0) { 1968 err = USBD_IOERROR; 1969 goto ret; 1970 } 1971 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1972 memcpy(buf, &ehci_confd, l); 1973 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1974 value >> 8; 1975 buf = (char *)buf + l; 1976 len -= l; 1977 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1978 totlen += l; 1979 memcpy(buf, &ehci_ifcd, l); 1980 buf = (char *)buf + l; 1981 len -= l; 1982 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1983 totlen += l; 1984 memcpy(buf, &ehci_endpd, l); 1985 break; 1986 case UDESC_STRING: 1987 if (len == 0) 1988 break; 1989 *(u_int8_t *)buf = 0; 1990 totlen = 1; 1991 switch (value & 0xff) { 1992 case 0: /* Language table */ 1993 totlen = ehci_str(buf, len, "\001"); 1994 break; 1995 case 1: /* Vendor */ 1996 totlen = ehci_str(buf, len, sc->sc_vendor); 1997 break; 1998 case 2: /* Product */ 1999 totlen = ehci_str(buf, len, "EHCI root hub"); 2000 break; 2001 } 2002 break; 2003 default: 2004 err = USBD_IOERROR; 2005 goto ret; 2006 } 2007 break; 2008 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2009 if (len > 0) { 2010 *(u_int8_t *)buf = 0; 2011 totlen = 1; 2012 } 2013 break; 2014 case C(UR_GET_STATUS, UT_READ_DEVICE): 2015 if (len > 1) { 2016 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2017 totlen = 2; 2018 } 2019 break; 2020 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2021 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2022 if (len > 1) { 2023 USETW(((usb_status_t *)buf)->wStatus, 0); 2024 totlen = 2; 2025 } 2026 break; 2027 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2028 if (value >= USB_MAX_DEVICES) { 2029 err = USBD_IOERROR; 2030 goto ret; 2031 } 2032 sc->sc_addr = value; 2033 break; 2034 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2035 if (value != 0 && value != 1) { 2036 err = USBD_IOERROR; 2037 goto ret; 2038 } 2039 sc->sc_conf = value; 2040 break; 2041 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2042 break; 2043 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2044 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2045 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2046 err = USBD_IOERROR; 2047 goto ret; 2048 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2049 break; 2050 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2051 break; 2052 /* Hub requests */ 2053 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2054 break; 2055 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2056 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2057 "port=%d feature=%d\n", index, value)); 2058 if (index < 1 || index > sc->sc_noport) { 2059 err = USBD_IOERROR; 2060 goto ret; 2061 } 2062 port = EHCI_PORTSC(index); 2063 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2064 switch(value) { 2065 case UHF_PORT_ENABLE: 2066 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2067 break; 2068 case UHF_PORT_SUSPEND: 2069 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 2070 break; 2071 case UHF_PORT_POWER: 2072 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2073 break; 2074 case UHF_PORT_TEST: 2075 DPRINTFN(2,("ehci_root_ctrl_start: " 2076 "clear port test %d\n", index)); 2077 break; 2078 case UHF_PORT_INDICATOR: 2079 DPRINTFN(2,("ehci_root_ctrl_start: " 2080 "clear port index %d\n", index)); 2081 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2082 break; 2083 case UHF_C_PORT_CONNECTION: 2084 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2085 break; 2086 case UHF_C_PORT_ENABLE: 2087 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2088 break; 2089 case UHF_C_PORT_SUSPEND: 2090 /* how? */ 2091 break; 2092 case UHF_C_PORT_OVER_CURRENT: 2093 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2094 break; 2095 case UHF_C_PORT_RESET: 2096 sc->sc_isreset = 0; 2097 break; 2098 default: 2099 err = USBD_IOERROR; 2100 goto ret; 2101 } 2102 break; 2103 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2104 if ((value & 0xff) != 0) { 2105 err = USBD_IOERROR; 2106 goto ret; 2107 } 2108 hubd = ehci_hubd; 2109 hubd.bNbrPorts = sc->sc_noport; 2110 v = EOREAD4(sc, EHCI_HCSPARAMS); 2111 USETW(hubd.wHubCharacteristics, 2112 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2113 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2114 ? UHD_PORT_IND : 0); 2115 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2116 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2117 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2118 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2119 l = min(len, hubd.bDescLength); 2120 totlen = l; 2121 memcpy(buf, &hubd, l); 2122 break; 2123 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2124 if (len != 4) { 2125 err = USBD_IOERROR; 2126 goto ret; 2127 } 2128 memset(buf, 0, len); /* ? XXX */ 2129 totlen = len; 2130 break; 2131 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2132 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2133 index)); 2134 if (index < 1 || index > sc->sc_noport) { 2135 err = USBD_IOERROR; 2136 goto ret; 2137 } 2138 if (len != 4) { 2139 err = USBD_IOERROR; 2140 goto ret; 2141 } 2142 v = EOREAD4(sc, EHCI_PORTSC(index)); 2143 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2144 i = UPS_HIGH_SPEED; 2145 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2146 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2147 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2148 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2149 if (v & EHCI_PS_PR) i |= UPS_RESET; 2150 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2151 USETW(ps.wPortStatus, i); 2152 i = 0; 2153 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2154 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2155 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2156 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2157 USETW(ps.wPortChange, i); 2158 l = min(len, sizeof(ps)); 2159 memcpy(buf, &ps, l); 2160 totlen = l; 2161 break; 2162 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2163 err = USBD_IOERROR; 2164 goto ret; 2165 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2166 break; 2167 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2168 if (index < 1 || index > sc->sc_noport) { 2169 err = USBD_IOERROR; 2170 goto ret; 2171 } 2172 port = EHCI_PORTSC(index); 2173 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2174 switch(value) { 2175 case UHF_PORT_ENABLE: 2176 EOWRITE4(sc, port, v | EHCI_PS_PE); 2177 break; 2178 case UHF_PORT_SUSPEND: 2179 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2180 break; 2181 case UHF_PORT_DISOWN_TO_1_1: 2182 /* enter to Port Reset State */ 2183 v &= ~EHCI_PS_PE; 2184 EOWRITE4(sc, port, v | EHCI_PS_PR); 2185 ehci_disown(sc, index, 0); 2186 break; 2187 case UHF_PORT_RESET: 2188 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2189 index)); 2190 if (EHCI_PS_IS_LOWSPEED(v)) { 2191 /* Low speed device, give up ownership. */ 2192 ehci_disown(sc, index, 1); 2193 break; 2194 } 2195 /* Start reset sequence. */ 2196 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2197 EOWRITE4(sc, port, v | EHCI_PS_PR); 2198 /* Wait for reset to complete. */ 2199 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2200 if (sc->sc_dying) { 2201 err = USBD_IOERROR; 2202 goto ret; 2203 } 2204 /* Terminate reset sequence. */ 2205 v = EOREAD4(sc, port); 2206 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2207 /* Wait for HC to complete reset. */ 2208 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2209 if (sc->sc_dying) { 2210 err = USBD_IOERROR; 2211 goto ret; 2212 } 2213 v = EOREAD4(sc, port); 2214 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2215 if (v & EHCI_PS_PR) { 2216 printf("%s: port reset timeout\n", 2217 sc->sc_bus.bdev.dv_xname); 2218 return (USBD_TIMEOUT); 2219 } 2220 if (!(v & EHCI_PS_PE)) { 2221 /* Not a high speed device, give up ownership.*/ 2222 ehci_disown(sc, index, 0); 2223 break; 2224 } 2225 sc->sc_isreset = 1; 2226 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2227 index, v)); 2228 break; 2229 case UHF_PORT_POWER: 2230 DPRINTFN(2,("ehci_root_ctrl_start: " 2231 "set port power %d\n", index)); 2232 EOWRITE4(sc, port, v | EHCI_PS_PP); 2233 break; 2234 case UHF_PORT_TEST: 2235 DPRINTFN(2,("ehci_root_ctrl_start: " 2236 "set port test %d\n", index)); 2237 break; 2238 case UHF_PORT_INDICATOR: 2239 DPRINTFN(2,("ehci_root_ctrl_start: " 2240 "set port ind %d\n", index)); 2241 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2242 break; 2243 default: 2244 err = USBD_IOERROR; 2245 goto ret; 2246 } 2247 break; 2248 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2249 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2250 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2251 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2252 break; 2253 default: 2254 err = USBD_IOERROR; 2255 goto ret; 2256 } 2257 xfer->actlen = totlen; 2258 err = USBD_NORMAL_COMPLETION; 2259 ret: 2260 xfer->status = err; 2261 s = splusb(); 2262 usb_transfer_complete(xfer); 2263 splx(s); 2264 return (USBD_IN_PROGRESS); 2265 } 2266 2267 void 2268 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2269 { 2270 int port; 2271 u_int32_t v; 2272 2273 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2274 2275 port = EHCI_PORTSC(index); 2276 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2277 EOWRITE4(sc, port, v | EHCI_PS_PO); 2278 } 2279 2280 /* Abort a root control request. */ 2281 void 2282 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2283 { 2284 /* Nothing to do, all transfers are synchronous. */ 2285 } 2286 2287 /* Close the root pipe. */ 2288 void 2289 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2290 { 2291 DPRINTF(("ehci_root_ctrl_close\n")); 2292 /* Nothing to do. */ 2293 } 2294 2295 void 2296 ehci_root_intr_done(usbd_xfer_handle xfer) 2297 { 2298 } 2299 2300 usbd_status 2301 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2302 { 2303 usbd_status err; 2304 2305 /* Insert last in queue. */ 2306 err = usb_insert_transfer(xfer); 2307 if (err) 2308 return (err); 2309 2310 /* Pipe isn't running, start first */ 2311 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2312 } 2313 2314 usbd_status 2315 ehci_root_intr_start(usbd_xfer_handle xfer) 2316 { 2317 usbd_pipe_handle pipe = xfer->pipe; 2318 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2319 2320 if (sc->sc_dying) 2321 return (USBD_IOERROR); 2322 2323 sc->sc_intrxfer = xfer; 2324 2325 return (USBD_IN_PROGRESS); 2326 } 2327 2328 /* Abort a root interrupt request. */ 2329 void 2330 ehci_root_intr_abort(usbd_xfer_handle xfer) 2331 { 2332 int s; 2333 2334 if (xfer->pipe->intrxfer == xfer) { 2335 DPRINTF(("ehci_root_intr_abort: remove\n")); 2336 xfer->pipe->intrxfer = NULL; 2337 } 2338 xfer->status = USBD_CANCELLED; 2339 s = splusb(); 2340 usb_transfer_complete(xfer); 2341 splx(s); 2342 } 2343 2344 /* Close the root pipe. */ 2345 void 2346 ehci_root_intr_close(usbd_pipe_handle pipe) 2347 { 2348 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2349 2350 DPRINTF(("ehci_root_intr_close\n")); 2351 2352 sc->sc_intrxfer = NULL; 2353 } 2354 2355 void 2356 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2357 { 2358 } 2359 2360 /************************/ 2361 2362 ehci_soft_qh_t * 2363 ehci_alloc_sqh(ehci_softc_t *sc) 2364 { 2365 ehci_soft_qh_t *sqh; 2366 usbd_status err; 2367 int i, offs; 2368 usb_dma_t dma; 2369 2370 if (sc->sc_freeqhs == NULL) { 2371 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2372 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2373 EHCI_PAGE_SIZE, &dma); 2374 #ifdef EHCI_DEBUG 2375 if (err) 2376 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2377 #endif 2378 if (err) 2379 return (NULL); 2380 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2381 offs = i * EHCI_SQH_SIZE; 2382 sqh = KERNADDR(&dma, offs); 2383 sqh->physaddr = DMAADDR(&dma, offs); 2384 sqh->next = sc->sc_freeqhs; 2385 sc->sc_freeqhs = sqh; 2386 } 2387 } 2388 sqh = sc->sc_freeqhs; 2389 sc->sc_freeqhs = sqh->next; 2390 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2391 sqh->next = NULL; 2392 sqh->prev = NULL; 2393 return (sqh); 2394 } 2395 2396 void 2397 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2398 { 2399 sqh->next = sc->sc_freeqhs; 2400 sc->sc_freeqhs = sqh; 2401 } 2402 2403 ehci_soft_qtd_t * 2404 ehci_alloc_sqtd(ehci_softc_t *sc) 2405 { 2406 ehci_soft_qtd_t *sqtd; 2407 usbd_status err; 2408 int i, offs; 2409 usb_dma_t dma; 2410 int s; 2411 2412 if (sc->sc_freeqtds == NULL) { 2413 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2414 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2415 EHCI_PAGE_SIZE, &dma); 2416 #ifdef EHCI_DEBUG 2417 if (err) 2418 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2419 #endif 2420 if (err) 2421 return (NULL); 2422 s = splusb(); 2423 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2424 offs = i * EHCI_SQTD_SIZE; 2425 sqtd = KERNADDR(&dma, offs); 2426 sqtd->physaddr = DMAADDR(&dma, offs); 2427 sqtd->nextqtd = sc->sc_freeqtds; 2428 sc->sc_freeqtds = sqtd; 2429 } 2430 splx(s); 2431 } 2432 2433 s = splusb(); 2434 sqtd = sc->sc_freeqtds; 2435 sc->sc_freeqtds = sqtd->nextqtd; 2436 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2437 sqtd->nextqtd = NULL; 2438 sqtd->xfer = NULL; 2439 splx(s); 2440 2441 return (sqtd); 2442 } 2443 2444 void 2445 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2446 { 2447 int s; 2448 2449 s = splusb(); 2450 sqtd->nextqtd = sc->sc_freeqtds; 2451 sc->sc_freeqtds = sqtd; 2452 splx(s); 2453 } 2454 2455 usbd_status 2456 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, u_int alen, 2457 int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2458 { 2459 ehci_soft_qtd_t *next, *cur; 2460 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2461 u_int32_t qtdstatus; 2462 u_int len, curlen; 2463 int mps, i, iscontrol, forceshort; 2464 usb_dma_t *dma = &xfer->dmabuf; 2465 2466 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2467 2468 len = alen; 2469 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2470 UE_CONTROL; 2471 2472 dataphys = DMAADDR(dma, 0); 2473 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2474 qtdstatus = EHCI_QTD_ACTIVE | 2475 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2476 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */ 2477 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2478 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2479 len % mps == 0; 2480 /* 2481 * The control transfer data stage always starts with a toggle of 1. 2482 * For other transfers we let the hardware track the toggle state. 2483 */ 2484 if (iscontrol) 2485 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2486 2487 cur = ehci_alloc_sqtd(sc); 2488 *sp = cur; 2489 if (cur == NULL) 2490 goto nomem; 2491 for (;;) { 2492 dataphyspage = EHCI_PAGE(dataphys); 2493 /* The EHCI hardware can handle at most 5 pages. */ 2494 if (dataphyslastpage - dataphyspage < 2495 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2496 /* we can handle it in this QTD */ 2497 curlen = len; 2498 } else { 2499 /* must use multiple TDs, fill as much as possible. */ 2500 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2501 EHCI_PAGE_OFFSET(dataphys); 2502 #ifdef DIAGNOSTIC 2503 if (curlen > len) { 2504 printf("ehci_alloc_sqtd_chain: curlen=%u " 2505 "len=%u offs=0x%x\n", curlen, len, 2506 EHCI_PAGE_OFFSET(dataphys)); 2507 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2508 dataphyslastpage, dataphyspage, dataphys); 2509 curlen = len; 2510 } 2511 #endif 2512 /* the length must be a multiple of the max size */ 2513 curlen -= curlen % mps; 2514 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2515 "curlen=%u\n", curlen)); 2516 #ifdef DIAGNOSTIC 2517 if (curlen == 0) 2518 panic("ehci_alloc_std: curlen == 0"); 2519 #endif 2520 } 2521 2522 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2523 "dataphyslastpage=0x%08x len=%u curlen=%u\n", 2524 dataphys, dataphyslastpage, len, curlen)); 2525 len -= curlen; 2526 2527 /* 2528 * Allocate another transfer if there's more data left, 2529 * or if force last short transfer flag is set and we're 2530 * allocating a multiple of the max packet size. 2531 */ 2532 if (len != 0 || forceshort) { 2533 next = ehci_alloc_sqtd(sc); 2534 if (next == NULL) 2535 goto nomem; 2536 nextphys = htole32(next->physaddr); 2537 } else { 2538 next = NULL; 2539 nextphys = EHCI_NULL; 2540 } 2541 2542 for (i = 0; i * EHCI_PAGE_SIZE < 2543 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2544 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2545 if (i != 0) /* use offset only in first buffer */ 2546 a = EHCI_PAGE(a); 2547 #ifdef DIAGNOSTIC 2548 if (i >= EHCI_QTD_NBUFFERS) { 2549 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2550 goto nomem; 2551 } 2552 #endif 2553 cur->qtd.qtd_buffer[i] = htole32(a); 2554 cur->qtd.qtd_buffer_hi[i] = 0; 2555 } 2556 cur->nextqtd = next; 2557 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2558 cur->qtd.qtd_status = htole32(qtdstatus | 2559 EHCI_QTD_SET_BYTES(curlen)); 2560 cur->xfer = xfer; 2561 cur->len = curlen; 2562 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2563 dataphys, dataphys + curlen)); 2564 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%u\n", curlen)); 2565 if (iscontrol) { 2566 /* 2567 * adjust the toggle based on the number of packets 2568 * in this qtd 2569 */ 2570 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2571 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2572 } 2573 if (len == 0) { 2574 if (! forceshort) 2575 break; 2576 forceshort = 0; 2577 } 2578 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2579 dataphys += curlen; 2580 cur = next; 2581 } 2582 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2583 *ep = cur; 2584 2585 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2586 *sp, *ep)); 2587 2588 return (USBD_NORMAL_COMPLETION); 2589 2590 nomem: 2591 /* XXX free chain */ 2592 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2593 return (USBD_NOMEM); 2594 } 2595 2596 void 2597 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2598 ehci_soft_qtd_t *sqtdend) 2599 { 2600 ehci_soft_qtd_t *p; 2601 int i; 2602 2603 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2604 sqtd, sqtdend)); 2605 2606 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2607 p = sqtd->nextqtd; 2608 ehci_free_sqtd(sc, sqtd); 2609 } 2610 } 2611 2612 ehci_soft_itd_t * 2613 ehci_alloc_itd(ehci_softc_t *sc) 2614 { 2615 struct ehci_soft_itd *itd, *freeitd; 2616 usbd_status err; 2617 int i, s, offs, frindex, previndex; 2618 usb_dma_t dma; 2619 2620 s = splusb(); 2621 2622 /* Find an itd that wasn't freed this frame or last frame. This can 2623 * discard itds that were freed before frindex wrapped around 2624 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2625 * interrupt and fiddling with list when that happens */ 2626 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2627 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2628 2629 freeitd = NULL; 2630 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2631 if (itd == NULL) 2632 break; 2633 if (itd->slot != frindex && itd->slot != previndex) { 2634 freeitd = itd; 2635 break; 2636 } 2637 } 2638 2639 if (freeitd == NULL) { 2640 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2641 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2642 EHCI_PAGE_SIZE, &dma); 2643 2644 if (err) { 2645 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2646 return (NULL); 2647 } 2648 2649 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2650 offs = i * EHCI_ITD_SIZE; 2651 itd = KERNADDR(&dma, offs); 2652 itd->physaddr = DMAADDR(&dma, offs); 2653 itd->dma = dma; 2654 itd->offs = offs; 2655 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2656 } 2657 freeitd = LIST_FIRST(&sc->sc_freeitds); 2658 } 2659 2660 itd = freeitd; 2661 LIST_REMOVE(itd, u.free_list); 2662 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2663 itd->u.frame_list.next = NULL; 2664 itd->u.frame_list.prev = NULL; 2665 itd->xfer_next = NULL; 2666 itd->slot = 0; 2667 splx(s); 2668 2669 return (itd); 2670 } 2671 2672 void 2673 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2674 { 2675 int s; 2676 2677 s = splusb(); 2678 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2679 splx(s); 2680 } 2681 2682 /****************/ 2683 2684 /* 2685 * Close a reqular pipe. 2686 * Assumes that there are no pending transactions. 2687 */ 2688 void 2689 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2690 { 2691 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2692 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2693 ehci_soft_qh_t *sqh = epipe->sqh; 2694 int s; 2695 2696 s = splusb(); 2697 ehci_rem_qh(sc, sqh, head); 2698 splx(s); 2699 pipe->endpoint->savedtoggle = 2700 EHCI_QTD_GET_TOGGLE(letoh32(sqh->qh.qh_qtd.qtd_status)); 2701 ehci_free_sqh(sc, epipe->sqh); 2702 } 2703 2704 /* 2705 * Abort a device request. 2706 * If this routine is called at splusb() it guarantees that the request 2707 * will be removed from the hardware scheduling and that the callback 2708 * for it will be called with USBD_CANCELLED status. 2709 * It's impossible to guarantee that the requested transfer will not 2710 * have happened since the hardware runs concurrently. 2711 * If the transaction has already happened we rely on the ordinary 2712 * interrupt processing to process it. 2713 */ 2714 void 2715 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2716 { 2717 #define exfer EXFER(xfer) 2718 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2719 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2720 ehci_soft_qh_t *sqh = epipe->sqh; 2721 ehci_soft_qtd_t *sqtd, *snext, **psqtd; 2722 ehci_physaddr_t cur, us, next; 2723 int s; 2724 int hit; 2725 ehci_soft_qh_t *psqh; 2726 2727 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2728 2729 if (sc->sc_dying) { 2730 /* If we're dying, just do the software part. */ 2731 s = splusb(); 2732 xfer->status = status; /* make software ignore it */ 2733 timeout_del(&xfer->timeout_handle); 2734 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2735 usb_transfer_complete(xfer); 2736 splx(s); 2737 return; 2738 } 2739 2740 if (xfer->device->bus->intr_context) 2741 panic("ehci_abort_xfer: not in process context"); 2742 2743 /* 2744 * If an abort is already in progress then just wait for it to 2745 * complete and return. 2746 */ 2747 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2748 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2749 /* No need to wait if we're aborting from a timeout. */ 2750 if (status == USBD_TIMEOUT) 2751 return; 2752 /* Override the status which might be USBD_TIMEOUT. */ 2753 xfer->status = status; 2754 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2755 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2756 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 2757 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciaw", 0); 2758 return; 2759 } 2760 2761 /* 2762 * Step 1: Make interrupt routine and timeouts ignore xfer. 2763 */ 2764 s = splusb(); 2765 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2766 xfer->status = status; /* make software ignore it */ 2767 timeout_del(&xfer->timeout_handle); 2768 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2769 splx(s); 2770 2771 /* 2772 * Step 2: Wait until we know hardware has finished any possible 2773 * use of the xfer. We do this by removing the entire 2774 * queue from the async schedule and waiting for the doorbell. 2775 * Nothing else should be touching the queue now. 2776 */ 2777 psqh = sqh->prev; 2778 ehci_rem_qh(sc, sqh, psqh); 2779 2780 /* 2781 * Step 3: Deactivate all of the qTDs that we will be removing, 2782 * otherwise the queue head may go active again. The EHCI spec 2783 * suggests we should perform the deactivation before removing the 2784 * queue head from the schedule, however the VT6202 (at least) only 2785 * behaves correctly when we deactivate them afterwards. 2786 */ 2787 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2788 sqtd->qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2789 if (sqtd == exfer->sqtdend) 2790 break; 2791 } 2792 ehci_sync_hc(sc); 2793 2794 /* 2795 * Step 4: make sure the soft interrupt routine 2796 * has run. This should remove any completed items off the queue. 2797 * The hardware has no reference to completed items (TDs). 2798 * It's safe to remove them at any time. 2799 * use of the xfer. Also make sure the soft interrupt routine 2800 * has run. 2801 */ 2802 s = splusb(); 2803 sc->sc_softwake = 1; 2804 usb_schedsoftintr(&sc->sc_bus); 2805 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2806 2807 /* 2808 * Step 5: Remove any vestiges of the xfer from the hardware. 2809 * The complication here is that the hardware may have executed 2810 * into or even beyond the xfer we're trying to abort. 2811 * So as we're scanning the TDs of this xfer we check if 2812 * the hardware points to any of them. 2813 * 2814 * first we need to see if there are any transfers 2815 * on this queue before the xfer we are aborting.. we need 2816 * to update any pointers that point to us to point past 2817 * the aborting xfer. (If there is something past us). 2818 * Hardware and software. 2819 */ 2820 cur = EHCI_LINK_ADDR(letoh32(sqh->qh.qh_curqtd)); 2821 hit = 0; 2822 2823 /* If they initially point here. */ 2824 us = exfer->sqtdstart->physaddr; 2825 2826 /* We will change them to point here */ 2827 snext = exfer->sqtdend->nextqtd; 2828 next = snext ? snext->physaddr : EHCI_NULL; 2829 2830 /* 2831 * Now loop through any qTDs before us and keep track of the pointer 2832 * that points to us for the end. 2833 */ 2834 psqtd = &sqh->sqtd; 2835 sqtd = sqh->sqtd; 2836 while (sqtd && sqtd != exfer->sqtdstart) { 2837 hit |= (cur == sqtd->physaddr); 2838 if (EHCI_LINK_ADDR(letoh32(sqtd->qtd.qtd_next)) == us) 2839 sqtd->qtd.qtd_next = next; 2840 if (EHCI_LINK_ADDR(letoh32(sqtd->qtd.qtd_altnext)) == us) 2841 sqtd->qtd.qtd_altnext = next; 2842 psqtd = &sqtd->nextqtd; 2843 sqtd = sqtd->nextqtd; 2844 } 2845 /* make the software pointer bypass us too */ 2846 *psqtd = exfer->sqtdend->nextqtd; 2847 2848 /* 2849 * If we already saw the active one then we are pretty much done. 2850 * We've done all the relinking we need to do. 2851 */ 2852 if (!hit) { 2853 2854 /* 2855 * Now reinitialise the QH to point to the next qTD 2856 * (if there is one). We only need to do this if 2857 * it was previously pointing to us. 2858 * XXX Not quite sure what to do about the data toggle. 2859 */ 2860 sqtd = exfer->sqtdstart; 2861 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2862 if (cur == sqtd->physaddr) { 2863 hit++; 2864 } 2865 if (sqtd == exfer->sqtdend) 2866 break; 2867 } 2868 /* 2869 * Only need to alter the QH if it was pointing at a qTD 2870 * that we are removing. 2871 */ 2872 if (hit) { 2873 if (snext) { 2874 ehci_set_qh_qtd(sqh, snext); 2875 } else { 2876 2877 sqh->qh.qh_curqtd = 0; /* unlink qTDs */ 2878 sqh->qh.qh_qtd.qtd_status = 0; 2879 sqh->qh.qh_qtd.qtd_next = 2880 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2881 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2882 } 2883 } 2884 } 2885 ehci_add_qh(sqh, psqh); 2886 2887 /* 2888 * Step 6: Execute callback. 2889 */ 2890 #ifdef DIAGNOSTIC 2891 exfer->isdone = 1; 2892 #endif 2893 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2894 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 2895 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 2896 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 2897 wakeup(&exfer->ehci_xfer_flags); 2898 } 2899 usb_transfer_complete(xfer); 2900 2901 splx(s); 2902 #undef exfer 2903 } 2904 2905 void 2906 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 2907 { 2908 ehci_isoc_trans_t trans_status; 2909 struct ehci_pipe *epipe; 2910 struct ehci_xfer *exfer; 2911 ehci_softc_t *sc; 2912 struct ehci_soft_itd *itd; 2913 int s, i, wake; 2914 2915 epipe = (struct ehci_pipe *) xfer->pipe; 2916 exfer = EXFER(xfer); 2917 sc = (ehci_softc_t *)epipe->pipe.device->bus; 2918 2919 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 2920 2921 if (sc->sc_dying) { 2922 s = splusb(); 2923 xfer->status = status; 2924 timeout_del(&xfer->timeout_handle); 2925 usb_transfer_complete(xfer); 2926 splx(s); 2927 return; 2928 } 2929 2930 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2931 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 2932 2933 #ifdef DIAGNOSTIC 2934 if (status == USBD_TIMEOUT) 2935 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2936 #endif 2937 2938 xfer->status = status; 2939 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2940 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2941 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 2942 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciiaw", 0); 2943 return; 2944 } 2945 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2946 2947 xfer->status = status; 2948 timeout_del(&xfer->timeout_handle); 2949 2950 s = splusb(); 2951 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2952 for (i = 0; i < 8; i++) { 2953 trans_status = letoh32(itd->itd.itd_ctl[i]); 2954 trans_status &= ~EHCI_ITD_ACTIVE; 2955 itd->itd.itd_ctl[i] = htole32(trans_status); 2956 } 2957 } 2958 splx(s); 2959 2960 s = splusb(); 2961 sc->sc_softwake = 1; 2962 usb_schedsoftintr(&sc->sc_bus); 2963 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2964 splx(s); 2965 2966 #ifdef DIAGNOSTIC 2967 exfer->isdone = 1; 2968 #endif 2969 wake = exfer->ehci_xfer_flags & EHCI_XFER_ABORTING; 2970 exfer->ehci_xfer_flags &= ~(EHCI_XFER_ABORTING | EHCI_XFER_ABORTWAIT); 2971 usb_transfer_complete(xfer); 2972 if (wake) 2973 wakeup(&exfer->ehci_xfer_flags); 2974 2975 return; 2976 } 2977 2978 void 2979 ehci_timeout(void *addr) 2980 { 2981 struct ehci_xfer *exfer = addr; 2982 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 2983 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2984 2985 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 2986 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 2987 if (ehcidebug > 1) 2988 usbd_dump_pipe(exfer->xfer.pipe); 2989 #endif 2990 2991 if (sc->sc_dying) { 2992 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 2993 return; 2994 } 2995 2996 /* Execute the abort in a process context. */ 2997 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task); 2998 } 2999 3000 void 3001 ehci_timeout_task(void *addr) 3002 { 3003 usbd_xfer_handle xfer = addr; 3004 int s; 3005 3006 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3007 3008 s = splusb(); 3009 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3010 splx(s); 3011 } 3012 3013 /* 3014 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3015 * qTD status, or miss signalling occasionally under heavy load. If the host 3016 * machine is too fast, we we can miss transaction completion - when we scan 3017 * the active list the transaction still seems to be active. This generally 3018 * exhibits itself as a umass stall that never recovers. 3019 * 3020 * We work around this behaviour by setting up this callback after any softintr 3021 * that completes with transactions still pending, giving us another chance to 3022 * check for completion after the writeback has taken place. 3023 */ 3024 void 3025 ehci_intrlist_timeout(void *arg) 3026 { 3027 ehci_softc_t *sc = arg; 3028 int s = splusb(); 3029 3030 DPRINTFN(1, ("ehci_intrlist_timeout\n")); 3031 usb_schedsoftintr(&sc->sc_bus); 3032 3033 splx(s); 3034 } 3035 3036 /************************/ 3037 3038 usbd_status 3039 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3040 { 3041 usbd_status err; 3042 3043 /* Insert last in queue. */ 3044 err = usb_insert_transfer(xfer); 3045 if (err) 3046 return (err); 3047 3048 /* Pipe isn't running, start first */ 3049 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3050 } 3051 3052 usbd_status 3053 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3054 { 3055 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3056 usbd_status err; 3057 3058 if (sc->sc_dying) 3059 return (USBD_IOERROR); 3060 3061 #ifdef DIAGNOSTIC 3062 if (!(xfer->rqflags & URQ_REQUEST)) { 3063 /* XXX panic */ 3064 printf("ehci_device_ctrl_transfer: not a request\n"); 3065 return (USBD_INVAL); 3066 } 3067 #endif 3068 3069 err = ehci_device_request(xfer); 3070 if (err) 3071 return (err); 3072 3073 if (sc->sc_bus.use_polling) 3074 ehci_waitintr(sc, xfer); 3075 return (USBD_IN_PROGRESS); 3076 } 3077 3078 void 3079 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3080 { 3081 struct ehci_xfer *ex = EXFER(xfer); 3082 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3083 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 3084 3085 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3086 3087 #ifdef DIAGNOSTIC 3088 if (!(xfer->rqflags & URQ_REQUEST)) { 3089 panic("ehci_ctrl_done: not a request"); 3090 } 3091 #endif 3092 3093 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3094 ehci_del_intr_list(sc, ex); /* remove from active list */ 3095 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3096 } 3097 3098 DPRINTFN(5, ("ehci_ctrl_done: length=%u\n", xfer->actlen)); 3099 } 3100 3101 /* Abort a device control request. */ 3102 void 3103 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3104 { 3105 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3106 ehci_abort_xfer(xfer, USBD_CANCELLED); 3107 } 3108 3109 /* Close a device control pipe. */ 3110 void 3111 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3112 { 3113 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3114 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3115 3116 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3117 ehci_close_pipe(pipe, sc->sc_async_head); 3118 } 3119 3120 usbd_status 3121 ehci_device_request(usbd_xfer_handle xfer) 3122 { 3123 #define exfer EXFER(xfer) 3124 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3125 usb_device_request_t *req = &xfer->request; 3126 usbd_device_handle dev = epipe->pipe.device; 3127 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3128 int addr = dev->address; 3129 ehci_soft_qtd_t *setup, *stat, *next; 3130 ehci_soft_qh_t *sqh; 3131 int isread; 3132 u_int len; 3133 usbd_status err; 3134 int s; 3135 3136 isread = req->bmRequestType & UT_READ; 3137 len = UGETW(req->wLength); 3138 3139 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3140 "wValue=0x%04x, wIndex=0x%04x len=%u, addr=%d, endpt=%d\n", 3141 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3142 UGETW(req->wIndex), len, addr, 3143 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3144 3145 setup = ehci_alloc_sqtd(sc); 3146 if (setup == NULL) { 3147 err = USBD_NOMEM; 3148 goto bad1; 3149 } 3150 stat = ehci_alloc_sqtd(sc); 3151 if (stat == NULL) { 3152 err = USBD_NOMEM; 3153 goto bad2; 3154 } 3155 3156 sqh = epipe->sqh; 3157 epipe->u.ctl.length = len; 3158 3159 /* Update device address and length since they may have changed 3160 during the setup of the control pipe in usbd_new_device(). */ 3161 /* XXX This only needs to be done once, but it's too early in open. */ 3162 /* XXXX Should not touch ED here! */ 3163 sqh->qh.qh_endp = 3164 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3165 htole32( 3166 EHCI_QH_SET_ADDR(addr) | 3167 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3168 ); 3169 3170 /* Set up data transaction */ 3171 if (len != 0) { 3172 ehci_soft_qtd_t *end; 3173 3174 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3175 &next, &end); 3176 if (err) 3177 goto bad3; 3178 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3179 end->nextqtd = stat; 3180 end->qtd.qtd_next = 3181 end->qtd.qtd_altnext = htole32(stat->physaddr); 3182 } else { 3183 next = stat; 3184 } 3185 3186 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3187 3188 /* Clear toggle */ 3189 setup->qtd.qtd_status = htole32( 3190 EHCI_QTD_ACTIVE | 3191 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3192 EHCI_QTD_SET_CERR(3) | 3193 EHCI_QTD_SET_TOGGLE(0) | 3194 EHCI_QTD_SET_BYTES(sizeof(*req))); 3195 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3196 setup->qtd.qtd_buffer_hi[0] = 0; 3197 setup->nextqtd = next; 3198 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3199 setup->xfer = xfer; 3200 setup->len = sizeof(*req); 3201 3202 stat->qtd.qtd_status = htole32( 3203 EHCI_QTD_ACTIVE | 3204 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3205 EHCI_QTD_SET_CERR(3) | 3206 EHCI_QTD_SET_TOGGLE(1) | 3207 EHCI_QTD_IOC); 3208 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3209 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3210 stat->nextqtd = NULL; 3211 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3212 stat->xfer = xfer; 3213 stat->len = 0; 3214 3215 #ifdef EHCI_DEBUG 3216 if (ehcidebug > 5) { 3217 DPRINTF(("ehci_device_request:\n")); 3218 ehci_dump_sqh(sqh); 3219 ehci_dump_sqtds(setup); 3220 } 3221 #endif 3222 3223 exfer->sqtdstart = setup; 3224 exfer->sqtdend = stat; 3225 #ifdef DIAGNOSTIC 3226 if (!exfer->isdone) { 3227 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3228 } 3229 exfer->isdone = 0; 3230 #endif 3231 3232 /* Insert qTD in QH list. */ 3233 s = splusb(); 3234 ehci_set_qh_qtd(sqh, setup); 3235 if (xfer->timeout && !sc->sc_bus.use_polling) { 3236 timeout_del(&xfer->timeout_handle); 3237 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3238 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3239 } 3240 ehci_add_intr_list(sc, exfer); 3241 xfer->status = USBD_IN_PROGRESS; 3242 splx(s); 3243 3244 #ifdef EHCI_DEBUG 3245 if (ehcidebug > 10) { 3246 DPRINTF(("ehci_device_request: status=%x\n", 3247 EOREAD4(sc, EHCI_USBSTS))); 3248 delay(10000); 3249 ehci_dump_regs(sc); 3250 ehci_dump_sqh(sc->sc_async_head); 3251 ehci_dump_sqh(sqh); 3252 ehci_dump_sqtds(setup); 3253 } 3254 #endif 3255 3256 return (USBD_NORMAL_COMPLETION); 3257 3258 bad3: 3259 ehci_free_sqtd(sc, stat); 3260 bad2: 3261 ehci_free_sqtd(sc, setup); 3262 bad1: 3263 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3264 xfer->status = err; 3265 usb_transfer_complete(xfer); 3266 return (err); 3267 #undef exfer 3268 } 3269 3270 /************************/ 3271 3272 usbd_status 3273 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3274 { 3275 usbd_status err; 3276 3277 /* Insert last in queue. */ 3278 err = usb_insert_transfer(xfer); 3279 if (err) 3280 return (err); 3281 3282 /* Pipe isn't running, start first */ 3283 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3284 } 3285 3286 usbd_status 3287 ehci_device_bulk_start(usbd_xfer_handle xfer) 3288 { 3289 #define exfer EXFER(xfer) 3290 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3291 usbd_device_handle dev = epipe->pipe.device; 3292 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3293 ehci_soft_qtd_t *data, *dataend; 3294 ehci_soft_qh_t *sqh; 3295 usbd_status err; 3296 u_int len; 3297 int isread, endpt; 3298 int s; 3299 3300 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%u flags=%d\n", 3301 xfer, xfer->length, xfer->flags)); 3302 3303 if (sc->sc_dying) 3304 return (USBD_IOERROR); 3305 3306 #ifdef DIAGNOSTIC 3307 if (xfer->rqflags & URQ_REQUEST) 3308 panic("ehci_device_bulk_start: a request"); 3309 #endif 3310 3311 len = xfer->length; 3312 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3313 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3314 sqh = epipe->sqh; 3315 3316 epipe->u.bulk.length = len; 3317 3318 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3319 &dataend); 3320 if (err) { 3321 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n")); 3322 xfer->status = err; 3323 usb_transfer_complete(xfer); 3324 return (err); 3325 } 3326 3327 #ifdef EHCI_DEBUG 3328 if (ehcidebug > 5) { 3329 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3330 ehci_dump_sqh(sqh); 3331 ehci_dump_sqtds(data); 3332 } 3333 #endif 3334 3335 /* Set up interrupt info. */ 3336 exfer->sqtdstart = data; 3337 exfer->sqtdend = dataend; 3338 #ifdef DIAGNOSTIC 3339 if (!exfer->isdone) { 3340 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3341 } 3342 exfer->isdone = 0; 3343 #endif 3344 3345 s = splusb(); 3346 ehci_set_qh_qtd(sqh, data); 3347 if (xfer->timeout && !sc->sc_bus.use_polling) { 3348 timeout_del(&xfer->timeout_handle); 3349 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3350 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3351 } 3352 ehci_add_intr_list(sc, exfer); 3353 xfer->status = USBD_IN_PROGRESS; 3354 splx(s); 3355 3356 #ifdef EHCI_DEBUG 3357 if (ehcidebug > 10) { 3358 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3359 delay(10000); 3360 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3361 ehci_dump_regs(sc); 3362 #if 0 3363 printf("async_head:\n"); 3364 ehci_dump_sqh(sc->sc_async_head); 3365 #endif 3366 printf("sqh:\n"); 3367 ehci_dump_sqh(sqh); 3368 ehci_dump_sqtds(data); 3369 } 3370 #endif 3371 3372 if (sc->sc_bus.use_polling) 3373 ehci_waitintr(sc, xfer); 3374 3375 return (USBD_IN_PROGRESS); 3376 #undef exfer 3377 } 3378 3379 void 3380 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3381 { 3382 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3383 ehci_abort_xfer(xfer, USBD_CANCELLED); 3384 } 3385 3386 /* 3387 * Close a device bulk pipe. 3388 */ 3389 void 3390 ehci_device_bulk_close(usbd_pipe_handle pipe) 3391 { 3392 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3393 3394 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3395 ehci_close_pipe(pipe, sc->sc_async_head); 3396 } 3397 3398 void 3399 ehci_device_bulk_done(usbd_xfer_handle xfer) 3400 { 3401 struct ehci_xfer *ex = EXFER(xfer); 3402 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3403 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 3404 3405 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3406 xfer, xfer->actlen)); 3407 3408 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3409 ehci_del_intr_list(sc, ex); /* remove from active list */ 3410 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3411 } 3412 3413 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3414 } 3415 3416 /************************/ 3417 3418 usbd_status 3419 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3420 { 3421 struct ehci_soft_islot *isp; 3422 int islot, lev; 3423 3424 /* Find a poll rate that is large enough. */ 3425 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3426 if (EHCI_ILEV_IVAL(lev) <= ival) 3427 break; 3428 3429 /* Pick an interrupt slot at the right level. */ 3430 /* XXX could do better than picking at random */ 3431 if (cold) { 3432 /* XXX prevent panics at boot by not using arc4random */ 3433 sc->sc_rand = (sc->sc_rand + 192) % sc->sc_flsize; 3434 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3435 } else 3436 islot = EHCI_IQHIDX(lev, arc4random()); 3437 3438 sqh->islot = islot; 3439 isp = &sc->sc_islots[islot]; 3440 ehci_add_qh(sqh, isp->sqh); 3441 3442 return (USBD_NORMAL_COMPLETION); 3443 } 3444 3445 usbd_status 3446 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3447 { 3448 usbd_status err; 3449 3450 /* Insert last in queue. */ 3451 err = usb_insert_transfer(xfer); 3452 if (err) 3453 return (err); 3454 3455 /* 3456 * Pipe isn't running (otherwise err would be USBD_INPROG), 3457 * so start it first. 3458 */ 3459 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3460 } 3461 3462 usbd_status 3463 ehci_device_intr_start(usbd_xfer_handle xfer) 3464 { 3465 #define exfer EXFER(xfer) 3466 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3467 usbd_device_handle dev = xfer->pipe->device; 3468 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3469 ehci_soft_qtd_t *data, *dataend; 3470 ehci_soft_qh_t *sqh; 3471 usbd_status err; 3472 u_int len; 3473 int isread, endpt; 3474 int s; 3475 3476 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%u flags=%d\n", 3477 xfer, xfer->length, xfer->flags)); 3478 3479 if (sc->sc_dying) 3480 return (USBD_IOERROR); 3481 3482 #ifdef DIAGNOSTIC 3483 if (xfer->rqflags & URQ_REQUEST) 3484 panic("ehci_device_intr_start: a request"); 3485 #endif 3486 3487 len = xfer->length; 3488 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3489 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3490 sqh = epipe->sqh; 3491 3492 epipe->u.intr.length = len; 3493 3494 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3495 &dataend); 3496 if (err) { 3497 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3498 xfer->status = err; 3499 usb_transfer_complete(xfer); 3500 return (err); 3501 } 3502 3503 #ifdef EHCI_DEBUG 3504 if (ehcidebug > 5) { 3505 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3506 ehci_dump_sqh(sqh); 3507 ehci_dump_sqtds(data); 3508 } 3509 #endif 3510 3511 /* Set up interrupt info. */ 3512 exfer->sqtdstart = data; 3513 exfer->sqtdend = dataend; 3514 #ifdef DIAGNOSTIC 3515 if (!exfer->isdone) 3516 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3517 exfer->isdone = 0; 3518 #endif 3519 3520 s = splusb(); 3521 ehci_set_qh_qtd(sqh, data); 3522 if (xfer->timeout && !sc->sc_bus.use_polling) { 3523 timeout_del(&xfer->timeout_handle); 3524 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3525 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3526 } 3527 ehci_add_intr_list(sc, exfer); 3528 xfer->status = USBD_IN_PROGRESS; 3529 splx(s); 3530 3531 #ifdef EHCI_DEBUG 3532 if (ehcidebug > 10) { 3533 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3534 delay(10000); 3535 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3536 ehci_dump_regs(sc); 3537 printf("sqh:\n"); 3538 ehci_dump_sqh(sqh); 3539 ehci_dump_sqtds(data); 3540 } 3541 #endif 3542 3543 if (sc->sc_bus.use_polling) 3544 ehci_waitintr(sc, xfer); 3545 3546 return (USBD_IN_PROGRESS); 3547 #undef exfer 3548 } 3549 3550 void 3551 ehci_device_intr_abort(usbd_xfer_handle xfer) 3552 { 3553 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3554 if (xfer->pipe->intrxfer == xfer) { 3555 DPRINTFN(1, ("ehci_device_intr_abort: remove\n")); 3556 xfer->pipe->intrxfer = NULL; 3557 } 3558 /* 3559 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3560 * async doorbell. That's dependant on the async list, wheras 3561 * intr xfers are periodic, should not use this? 3562 */ 3563 ehci_abort_xfer(xfer, USBD_CANCELLED); 3564 } 3565 3566 void 3567 ehci_device_intr_close(usbd_pipe_handle pipe) 3568 { 3569 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3570 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3571 struct ehci_soft_islot *isp; 3572 3573 isp = &sc->sc_islots[epipe->sqh->islot]; 3574 ehci_close_pipe(pipe, isp->sqh); 3575 } 3576 3577 void 3578 ehci_device_intr_done(usbd_xfer_handle xfer) 3579 { 3580 #define exfer EXFER(xfer) 3581 struct ehci_xfer *ex = EXFER(xfer); 3582 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3583 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3584 ehci_soft_qtd_t *data, *dataend; 3585 ehci_soft_qh_t *sqh; 3586 usbd_status err; 3587 u_int len; 3588 int isread, endpt, s; 3589 3590 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3591 xfer, xfer->actlen)); 3592 3593 if (xfer->pipe->repeat) { 3594 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3595 3596 len = epipe->u.intr.length; 3597 xfer->length = len; 3598 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3599 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3600 sqh = epipe->sqh; 3601 3602 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3603 &data, &dataend); 3604 if (err) { 3605 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3606 xfer->status = err; 3607 return; 3608 } 3609 3610 /* Set up interrupt info. */ 3611 exfer->sqtdstart = data; 3612 exfer->sqtdend = dataend; 3613 #ifdef DIAGNOSTIC 3614 if (!exfer->isdone) { 3615 printf("ehci_device_intr_done: not done, ex=%p\n", 3616 exfer); 3617 } 3618 exfer->isdone = 0; 3619 #endif 3620 3621 s = splusb(); 3622 ehci_set_qh_qtd(sqh, data); 3623 if (xfer->timeout && !sc->sc_bus.use_polling) { 3624 timeout_del(&xfer->timeout_handle); 3625 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3626 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3627 } 3628 splx(s); 3629 3630 xfer->status = USBD_IN_PROGRESS; 3631 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3632 ehci_del_intr_list(sc, ex); /* remove from active list */ 3633 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3634 } 3635 #undef exfer 3636 } 3637 3638 /************************/ 3639 3640 usbd_status 3641 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3642 { 3643 usbd_status err; 3644 3645 err = usb_insert_transfer(xfer); 3646 if (err && err != USBD_IN_PROGRESS) 3647 return (err); 3648 3649 return (ehci_device_isoc_start(xfer)); 3650 } 3651 3652 usbd_status 3653 ehci_device_isoc_start(usbd_xfer_handle xfer) 3654 { 3655 struct ehci_pipe *epipe; 3656 ehci_softc_t *sc; 3657 struct ehci_xfer *exfer; 3658 ehci_soft_itd_t *itd, *prev, *start, *stop; 3659 usb_dma_t *dma_buf; 3660 int i, j, k, frames, uframes, ufrperframe; 3661 int s, trans_count, offs, total_length; 3662 int frindex; 3663 3664 start = NULL; 3665 prev = NULL; 3666 itd = NULL; 3667 trans_count = 0; 3668 total_length = 0; 3669 exfer = (struct ehci_xfer *) xfer; 3670 sc = (ehci_softc_t *)xfer->pipe->device->bus; 3671 epipe = (struct ehci_pipe *)xfer->pipe; 3672 3673 /* 3674 * To allow continuous transfers, above we start all transfers 3675 * immediately. However, we're still going to get usbd_start_next call 3676 * this when another xfer completes. So, check if this is already 3677 * in progress or not 3678 */ 3679 3680 if (exfer->itdstart != NULL) 3681 return (USBD_IN_PROGRESS); 3682 3683 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %u flags %d\n", 3684 xfer, xfer->length, xfer->flags)); 3685 3686 if (sc->sc_dying) 3687 return (USBD_IOERROR); 3688 3689 /* 3690 * To avoid complication, don't allow a request right now that'll span 3691 * the entire frame table. To within 4 frames, to allow some leeway 3692 * on either side of where the hc currently is. 3693 */ 3694 if ((1 << (epipe->pipe.endpoint->edesc->bInterval - 1)) * 3695 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3696 printf("ehci: isoc descriptor requested that spans the entire " 3697 "frametable, too many frames\n"); 3698 return (USBD_INVAL); 3699 } 3700 3701 #ifdef DIAGNOSTIC 3702 if (xfer->rqflags & URQ_REQUEST) 3703 panic("ehci_device_isoc_start: request"); 3704 3705 if (!exfer->isdone) 3706 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3707 exfer->isdone = 0; 3708 #endif 3709 3710 /* 3711 * Step 1: Allocate and initialize itds, how many do we need? 3712 * One per transfer if interval >= 8 microframes, fewer if we use 3713 * multiple microframes per frame. 3714 */ 3715 3716 i = epipe->pipe.endpoint->edesc->bInterval; 3717 if (i > 16 || i == 0) { 3718 /* Spec page 271 says intervals > 16 are invalid */ 3719 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3720 return (USBD_INVAL); 3721 } 3722 3723 switch (i) { 3724 case 1: 3725 ufrperframe = 8; 3726 break; 3727 case 2: 3728 ufrperframe = 4; 3729 break; 3730 case 3: 3731 ufrperframe = 2; 3732 break; 3733 default: 3734 ufrperframe = 1; 3735 break; 3736 } 3737 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3738 uframes = 8 / ufrperframe; 3739 3740 if (frames == 0) { 3741 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3742 return (USBD_INVAL); 3743 } 3744 3745 dma_buf = &xfer->dmabuf; 3746 offs = 0; 3747 3748 for (i = 0; i < frames; i++) { 3749 int froffs = offs; 3750 itd = ehci_alloc_itd(sc); 3751 3752 if (prev != NULL) { 3753 prev->itd.itd_next = 3754 htole32(itd->physaddr | EHCI_LINK_ITD); 3755 prev->xfer_next = itd; 3756 } else { 3757 start = itd; 3758 } 3759 3760 /* 3761 * Step 1.5, initialize uframes 3762 */ 3763 for (j = 0; j < 8; j += uframes) { 3764 /* Calculate which page in the list this starts in */ 3765 int addr = DMAADDR(dma_buf, froffs); 3766 addr = EHCI_PAGE_OFFSET(addr); 3767 addr += (offs - froffs); 3768 addr = EHCI_PAGE(addr); 3769 addr /= EHCI_PAGE_SIZE; 3770 3771 /* This gets the initial offset into the first page, 3772 * looks how far further along the current uframe 3773 * offset is. Works out how many pages that is. 3774 */ 3775 3776 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3777 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3778 EHCI_ITD_SET_PG(addr) | 3779 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf, 3780 offs)))); 3781 3782 total_length += xfer->frlengths[trans_count]; 3783 offs += xfer->frlengths[trans_count]; 3784 trans_count++; 3785 3786 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3787 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3788 break; 3789 } 3790 } 3791 3792 /* Step 1.75, set buffer pointers. To simplify matters, all 3793 * pointers are filled out for the next 7 hardware pages in 3794 * the dma block, so no need to worry what pages to cover 3795 * and what to not. 3796 */ 3797 3798 for (j=0; j < 7; j++) { 3799 /* 3800 * Don't try to lookup a page that's past the end 3801 * of buffer 3802 */ 3803 int page_offs = EHCI_PAGE(froffs + 3804 (EHCI_PAGE_SIZE * j)); 3805 3806 if (page_offs >= dma_buf->block->size) 3807 break; 3808 3809 long long page = DMAADDR(dma_buf, page_offs); 3810 page = EHCI_PAGE(page); 3811 itd->itd.itd_bufr[j] = 3812 htole32(EHCI_ITD_SET_BPTR(page)); 3813 itd->itd.itd_bufr_hi[j] = 3814 htole32(page >> 32); 3815 } 3816 3817 /* 3818 * Other special values 3819 */ 3820 3821 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3822 itd->itd.itd_bufr[0] |= 3823 htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3824 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3825 3826 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3827 ? 1 : 0; 3828 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3829 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3830 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3831 3832 /* FIXME: handle invalid trans */ 3833 itd->itd.itd_bufr[2] |= 3834 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3835 prev = itd; 3836 } /* End of frame */ 3837 3838 stop = itd; 3839 stop->xfer_next = NULL; 3840 exfer->isoc_len = total_length; 3841 3842 /* 3843 * Part 2: Transfer descriptors have now been set up, now they must 3844 * be scheduled into the period frame list. Erk. Not wanting to 3845 * complicate matters, transfer is denied if the transfer spans 3846 * more than the period frame list. 3847 */ 3848 3849 s = splusb(); 3850 3851 /* Start inserting frames */ 3852 if (epipe->u.isoc.cur_xfers > 0) { 3853 frindex = epipe->u.isoc.next_frame; 3854 } else { 3855 frindex = EOREAD4(sc, EHCI_FRINDEX); 3856 frindex = frindex >> 3; /* Erase microframe index */ 3857 frindex += 2; 3858 } 3859 3860 if (frindex >= sc->sc_flsize) 3861 frindex &= (sc->sc_flsize - 1); 3862 3863 /* Whats the frame interval? */ 3864 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 3865 if (i / 8 == 0) 3866 i = 1; 3867 else 3868 i /= 8; 3869 3870 itd = start; 3871 for (j = 0; j < frames; j++) { 3872 if (itd == NULL) 3873 panic("ehci: unexpectedly ran out of isoc itds, " 3874 "isoc_start"); 3875 3876 itd->itd.itd_next = sc->sc_flist[frindex]; 3877 if (itd->itd.itd_next == 0) 3878 /* FIXME: frindex table gets initialized to NULL 3879 * or EHCI_NULL? */ 3880 itd->itd.itd_next = htole32(EHCI_NULL); 3881 3882 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 3883 itd->u.frame_list.next = sc->sc_softitds[frindex]; 3884 sc->sc_softitds[frindex] = itd; 3885 if (itd->u.frame_list.next != NULL) 3886 itd->u.frame_list.next->u.frame_list.prev = itd; 3887 itd->slot = frindex; 3888 itd->u.frame_list.prev = NULL; 3889 3890 frindex += i; 3891 if (frindex >= sc->sc_flsize) 3892 frindex -= sc->sc_flsize; 3893 3894 itd = itd->xfer_next; 3895 } 3896 3897 epipe->u.isoc.cur_xfers++; 3898 epipe->u.isoc.next_frame = frindex; 3899 3900 exfer->itdstart = start; 3901 exfer->itdend = stop; 3902 exfer->sqtdstart = NULL; 3903 exfer->sqtdstart = NULL; 3904 3905 ehci_add_intr_list(sc, exfer); 3906 xfer->status = USBD_IN_PROGRESS; 3907 xfer->done = 0; 3908 splx(s); 3909 3910 if (sc->sc_bus.use_polling) { 3911 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 3912 ehci_waitintr(sc, xfer); 3913 } 3914 3915 return (USBD_IN_PROGRESS); 3916 } 3917 3918 void 3919 ehci_device_isoc_abort(usbd_xfer_handle xfer) 3920 { 3921 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 3922 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 3923 } 3924 3925 void 3926 ehci_device_isoc_close(usbd_pipe_handle pipe) 3927 { 3928 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 3929 } 3930 3931 void 3932 ehci_device_isoc_done(usbd_xfer_handle xfer) 3933 { 3934 struct ehci_xfer *exfer; 3935 ehci_softc_t *sc; 3936 struct ehci_pipe *epipe; 3937 int s; 3938 3939 exfer = EXFER(xfer); 3940 sc = (ehci_softc_t *)xfer->pipe->device->bus; 3941 epipe = (struct ehci_pipe *) xfer->pipe; 3942 3943 s = splusb(); 3944 epipe->u.isoc.cur_xfers--; 3945 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 3946 ehci_del_intr_list(sc, exfer); 3947 ehci_rem_free_itd_chain(sc, exfer); 3948 } 3949 splx(s); 3950 } 3951