1 /* $OpenBSD: ehci.c,v 1.115 2010/12/14 16:13:16 jakemsr Exp $ */ 2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 10 * Jeremy Morse (jeremy.morse@gmail.com). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/usb_20.zip 41 */ 42 43 /* 44 * TODO: 45 * 1) The hub driver needs to handle and schedule the transaction translator, 46 * to assign place in frame where different devices get to go. See chapter 47 * on hubs in USB 2.0 for details. 48 * 49 * 2) Command failures are not recovered correctly. 50 */ 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/rwlock.h> 56 #include <sys/malloc.h> 57 #include <sys/device.h> 58 #include <sys/selinfo.h> 59 #include <sys/proc.h> 60 #include <sys/queue.h> 61 #include <sys/timeout.h> 62 63 #include <machine/bus.h> 64 #include <machine/endian.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 #include <dev/usb/usbdivar.h> 69 #include <dev/usb/usb_mem.h> 70 #include <dev/usb/usb_quirks.h> 71 72 #include <dev/usb/ehcireg.h> 73 #include <dev/usb/ehcivar.h> 74 75 #include <dev/rndvar.h> 76 77 struct cfdriver ehci_cd = { 78 NULL, "ehci", DV_DULL 79 }; 80 81 #ifdef EHCI_DEBUG 82 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 83 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 84 int ehcidebug = 0; 85 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n,x) 89 #endif 90 91 #define mstohz(ms) ((ms) * hz / 1000) 92 93 struct ehci_pipe { 94 struct usbd_pipe pipe; 95 96 ehci_soft_qh_t *sqh; 97 union { 98 ehci_soft_qtd_t *qtd; 99 /* ehci_soft_itd_t *itd; */ 100 } tail; 101 union { 102 /* Control pipe */ 103 struct { 104 usb_dma_t reqdma; 105 u_int length; 106 /*ehci_soft_qtd_t *setup, *data, *stat;*/ 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 u_int length; 111 } intr; 112 /* Bulk pipe */ 113 struct { 114 u_int length; 115 } bulk; 116 /* Iso pipe */ 117 struct { 118 u_int next_frame; 119 u_int cur_xfers; 120 } isoc; 121 } u; 122 }; 123 124 u_int8_t ehci_reverse_bits(u_int8_t, int); 125 126 usbd_status ehci_open(usbd_pipe_handle); 127 void ehci_poll(struct usbd_bus *); 128 void ehci_softintr(void *); 129 int ehci_intr1(ehci_softc_t *); 130 void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 131 void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 132 void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 133 void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 134 void ehci_idone(struct ehci_xfer *); 135 void ehci_timeout(void *); 136 void ehci_timeout_task(void *); 137 void ehci_intrlist_timeout(void *); 138 139 usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 140 void ehci_freem(struct usbd_bus *, usb_dma_t *); 141 142 usbd_xfer_handle ehci_allocx(struct usbd_bus *); 143 void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 144 145 usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 146 usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 147 void ehci_root_ctrl_abort(usbd_xfer_handle); 148 void ehci_root_ctrl_close(usbd_pipe_handle); 149 void ehci_root_ctrl_done(usbd_xfer_handle); 150 151 usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 152 usbd_status ehci_root_intr_start(usbd_xfer_handle); 153 void ehci_root_intr_abort(usbd_xfer_handle); 154 void ehci_root_intr_close(usbd_pipe_handle); 155 void ehci_root_intr_done(usbd_xfer_handle); 156 157 usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 158 usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 159 void ehci_device_ctrl_abort(usbd_xfer_handle); 160 void ehci_device_ctrl_close(usbd_pipe_handle); 161 void ehci_device_ctrl_done(usbd_xfer_handle); 162 163 usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 164 usbd_status ehci_device_bulk_start(usbd_xfer_handle); 165 void ehci_device_bulk_abort(usbd_xfer_handle); 166 void ehci_device_bulk_close(usbd_pipe_handle); 167 void ehci_device_bulk_done(usbd_xfer_handle); 168 169 usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 170 usbd_status ehci_device_intr_start(usbd_xfer_handle); 171 void ehci_device_intr_abort(usbd_xfer_handle); 172 void ehci_device_intr_close(usbd_pipe_handle); 173 void ehci_device_intr_done(usbd_xfer_handle); 174 175 usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 176 usbd_status ehci_device_isoc_start(usbd_xfer_handle); 177 void ehci_device_isoc_abort(usbd_xfer_handle); 178 void ehci_device_isoc_close(usbd_pipe_handle); 179 void ehci_device_isoc_done(usbd_xfer_handle); 180 181 void ehci_device_clear_toggle(usbd_pipe_handle pipe); 182 void ehci_noop(usbd_pipe_handle pipe); 183 184 int ehci_str(usb_string_descriptor_t *, int, const char *); 185 void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 186 void ehci_disown(ehci_softc_t *, int, int); 187 188 ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 189 void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 190 191 ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 192 void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 193 usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 194 ehci_softc_t *, u_int, int, usbd_xfer_handle, 195 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 196 void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 197 ehci_soft_qtd_t *); 198 199 ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 200 void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 201 void ehci_rem_free_itd_chain(ehci_softc_t *sc, 202 struct ehci_xfer *exfer); 203 void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 204 usbd_status status); 205 206 usbd_status ehci_device_request(usbd_xfer_handle xfer); 207 208 usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 209 int ival); 210 211 void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 212 void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 213 ehci_soft_qh_t *); 214 void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 215 void ehci_sync_hc(ehci_softc_t *); 216 217 void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 218 void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 219 220 #ifdef EHCI_DEBUG 221 void ehci_dump_regs(ehci_softc_t *); 222 void ehci_dump(void); 223 ehci_softc_t *theehci; 224 void ehci_dump_link(ehci_link_t, int); 225 void ehci_dump_sqtds(ehci_soft_qtd_t *); 226 void ehci_dump_sqtd(ehci_soft_qtd_t *); 227 void ehci_dump_qtd(ehci_qtd_t *); 228 void ehci_dump_sqh(ehci_soft_qh_t *); 229 #if notyet 230 void ehci_dump_sitd(struct ehci_soft_itd *itd); 231 void ehci_dump_itd(struct ehci_soft_itd *); 232 #endif 233 #ifdef DIAGNOSTIC 234 void ehci_dump_exfer(struct ehci_xfer *); 235 #endif 236 #endif 237 238 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 239 240 #define EHCI_INTR_ENDPT 1 241 242 #define ehci_add_intr_list(sc, ex) \ 243 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 244 #define ehci_del_intr_list(sc, ex) \ 245 do { \ 246 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 247 (ex)->inext.tqe_prev = NULL; \ 248 } while (0) 249 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 250 251 struct usbd_bus_methods ehci_bus_methods = { 252 ehci_open, 253 ehci_softintr, 254 ehci_poll, 255 ehci_allocm, 256 ehci_freem, 257 ehci_allocx, 258 ehci_freex, 259 }; 260 261 struct usbd_pipe_methods ehci_root_ctrl_methods = { 262 ehci_root_ctrl_transfer, 263 ehci_root_ctrl_start, 264 ehci_root_ctrl_abort, 265 ehci_root_ctrl_close, 266 ehci_noop, 267 ehci_root_ctrl_done, 268 }; 269 270 struct usbd_pipe_methods ehci_root_intr_methods = { 271 ehci_root_intr_transfer, 272 ehci_root_intr_start, 273 ehci_root_intr_abort, 274 ehci_root_intr_close, 275 ehci_noop, 276 ehci_root_intr_done, 277 }; 278 279 struct usbd_pipe_methods ehci_device_ctrl_methods = { 280 ehci_device_ctrl_transfer, 281 ehci_device_ctrl_start, 282 ehci_device_ctrl_abort, 283 ehci_device_ctrl_close, 284 ehci_noop, 285 ehci_device_ctrl_done, 286 }; 287 288 struct usbd_pipe_methods ehci_device_intr_methods = { 289 ehci_device_intr_transfer, 290 ehci_device_intr_start, 291 ehci_device_intr_abort, 292 ehci_device_intr_close, 293 ehci_device_clear_toggle, 294 ehci_device_intr_done, 295 }; 296 297 struct usbd_pipe_methods ehci_device_bulk_methods = { 298 ehci_device_bulk_transfer, 299 ehci_device_bulk_start, 300 ehci_device_bulk_abort, 301 ehci_device_bulk_close, 302 ehci_device_clear_toggle, 303 ehci_device_bulk_done, 304 }; 305 306 struct usbd_pipe_methods ehci_device_isoc_methods = { 307 ehci_device_isoc_transfer, 308 ehci_device_isoc_start, 309 ehci_device_isoc_abort, 310 ehci_device_isoc_close, 311 ehci_noop, 312 ehci_device_isoc_done, 313 }; 314 315 /* 316 * Reverse a number with nbits bits. Used to evenly distribute lower-level 317 * interrupt heads in the periodic schedule. 318 * Suitable for use with EHCI_IPOLLRATES <= 9. 319 */ 320 u_int8_t 321 ehci_reverse_bits(u_int8_t c, int nbits) 322 { 323 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa); 324 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc); 325 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0); 326 327 return c >> (8 - nbits); 328 } 329 330 usbd_status 331 ehci_init(ehci_softc_t *sc) 332 { 333 u_int32_t sparams, cparams, hcr; 334 u_int i, j; 335 usbd_status err; 336 ehci_soft_qh_t *sqh; 337 338 #ifdef EHCI_DEBUG 339 u_int32_t vers; 340 theehci = sc; 341 342 DPRINTF(("ehci_init: start\n")); 343 344 vers = EREAD2(sc, EHCI_HCIVERSION); 345 DPRINTF(("%s: EHCI version %x.%x\n", sc->sc_bus.bdev.dv_xname, 346 vers >> 8, vers & 0xff)); 347 #endif 348 349 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 350 351 sparams = EREAD4(sc, EHCI_HCSPARAMS); 352 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 353 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 354 cparams = EREAD4(sc, EHCI_HCCPARAMS); 355 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 356 357 /* MUST clear segment register if 64 bit capable. */ 358 if (EHCI_HCC_64BIT(cparams)) 359 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 360 361 sc->sc_bus.usbrev = USBREV_2_0; 362 363 /* Reset the controller */ 364 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 365 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 366 usb_delay_ms(&sc->sc_bus, 1); 367 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 368 for (i = 0; i < 100; i++) { 369 usb_delay_ms(&sc->sc_bus, 1); 370 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 371 if (!hcr) 372 break; 373 } 374 if (hcr) { 375 printf("%s: reset timeout\n", 376 sc->sc_bus.bdev.dv_xname); 377 return (USBD_IOERROR); 378 } 379 380 /* XXX need proper intr scheduling */ 381 sc->sc_rand = 96; 382 383 /* frame list size at default, read back what we got and use that */ 384 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 385 case 0: 386 sc->sc_flsize = 1024; 387 break; 388 case 1: 389 sc->sc_flsize = 512; 390 break; 391 case 2: 392 sc->sc_flsize = 256; 393 break; 394 case 3: 395 return (USBD_IOERROR); 396 } 397 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 398 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 399 if (err) 400 return (err); 401 DPRINTF(("%s: flsize=%d\n", sc->sc_bus.bdev.dv_xname,sc->sc_flsize)); 402 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 403 404 for (i = 0; i < sc->sc_flsize; i++) 405 sc->sc_flist[i] = EHCI_NULL; 406 407 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 408 409 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 410 M_USB, M_NOWAIT | M_ZERO); 411 if (sc->sc_softitds == NULL) 412 return (ENOMEM); 413 LIST_INIT(&sc->sc_freeitds); 414 TAILQ_INIT(&sc->sc_intrhead); 415 416 /* Set up the bus struct. */ 417 sc->sc_bus.methods = &ehci_bus_methods; 418 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 419 420 sc->sc_eintrs = EHCI_NORMAL_INTRS; 421 422 /* 423 * Allocate the interrupt dummy QHs. These are arranged to give poll 424 * intervals that are powers of 2 times 1ms. 425 */ 426 for (i = 0; i < EHCI_INTRQHS; i++) { 427 sqh = ehci_alloc_sqh(sc); 428 if (sqh == NULL) { 429 err = USBD_NOMEM; 430 goto bad1; 431 } 432 sc->sc_islots[i].sqh = sqh; 433 } 434 for (i = 0; i < EHCI_INTRQHS; i++) { 435 sqh = sc->sc_islots[i].sqh; 436 if (i == 0) { 437 /* The last (1ms) QH terminates. */ 438 sqh->qh.qh_link = EHCI_NULL; 439 sqh->next = NULL; 440 } else { 441 /* Otherwise the next QH has half the poll interval */ 442 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 443 sqh->qh.qh_link = htole32(sqh->next->physaddr | 444 EHCI_LINK_QH); 445 } 446 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 447 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 448 sqh->qh.qh_curqtd = EHCI_NULL; 449 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 450 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 451 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 452 sqh->sqtd = NULL; 453 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 454 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 455 } 456 /* Point the frame list at the last level (128ms). */ 457 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++) 458 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1)) 459 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[ 460 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits( 461 i, EHCI_IPOLLRATES - 1))].sqh->physaddr); 462 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 463 BUS_DMASYNC_PREWRITE); 464 465 /* Allocate dummy QH that starts the async list. */ 466 sqh = ehci_alloc_sqh(sc); 467 if (sqh == NULL) { 468 err = USBD_NOMEM; 469 goto bad1; 470 } 471 /* Fill the QH */ 472 sqh->qh.qh_endp = 473 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 474 sqh->qh.qh_link = 475 htole32(sqh->physaddr | EHCI_LINK_QH); 476 sqh->qh.qh_curqtd = EHCI_NULL; 477 sqh->prev = sqh; /*It's a circular list.. */ 478 sqh->next = sqh; 479 /* Fill the overlay qTD */ 480 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 481 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 482 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 483 sqh->sqtd = NULL; 484 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 485 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 486 #ifdef EHCI_DEBUG 487 if (ehcidebug) 488 ehci_dump_sqh(sqh); 489 #endif 490 491 /* Point to async list */ 492 sc->sc_async_head = sqh; 493 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 494 495 timeout_set(&sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 496 497 rw_init(&sc->sc_doorbell_lock, "ehcidb"); 498 499 /* Turn on controller */ 500 EOWRITE4(sc, EHCI_USBCMD, 501 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 502 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 503 EHCI_CMD_ASE | 504 EHCI_CMD_PSE | 505 EHCI_CMD_RS); 506 507 /* Take over port ownership */ 508 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 509 510 for (i = 0; i < 100; i++) { 511 usb_delay_ms(&sc->sc_bus, 1); 512 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 513 if (!hcr) 514 break; 515 } 516 if (hcr) { 517 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 518 return (USBD_IOERROR); 519 } 520 521 /* Enable interrupts */ 522 DPRINTFN(1,("ehci_init: enabling\n")); 523 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 524 525 return (USBD_NORMAL_COMPLETION); 526 527 #if 0 528 bad2: 529 ehci_free_sqh(sc, sc->sc_async_head); 530 #endif 531 bad1: 532 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 533 return (err); 534 } 535 536 int 537 ehci_intr(void *v) 538 { 539 ehci_softc_t *sc = v; 540 541 if (sc == NULL || sc->sc_bus.dying) 542 return (0); 543 544 /* If we get an interrupt while polling, then just ignore it. */ 545 if (sc->sc_bus.use_polling) { 546 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 547 548 if (intrs) 549 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 550 return (0); 551 } 552 553 return (ehci_intr1(sc)); 554 } 555 556 int 557 ehci_intr1(ehci_softc_t *sc) 558 { 559 u_int32_t intrs, eintrs; 560 561 DPRINTFN(20,("ehci_intr1: enter\n")); 562 563 /* In case the interrupt occurs before initialization has completed. */ 564 if (sc == NULL) { 565 #ifdef DIAGNOSTIC 566 printf("ehci_intr1: sc == NULL\n"); 567 #endif 568 return (0); 569 } 570 571 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 572 if (intrs == 0xffffffff) { 573 sc->sc_bus.dying = 1; 574 return (0); 575 } 576 if (!intrs) 577 return (0); 578 579 eintrs = intrs & sc->sc_eintrs; 580 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 581 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), (u_int)eintrs)); 582 if (!eintrs) 583 return (0); 584 585 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 586 sc->sc_bus.intr_context++; 587 sc->sc_bus.no_intrs++; 588 if (eintrs & EHCI_STS_HSE) { 589 printf("%s: unrecoverable error, controller halted\n", 590 sc->sc_bus.bdev.dv_xname); 591 sc->sc_bus.dying = 1; 592 sc->sc_bus.intr_context--; 593 return (1); 594 } 595 if (eintrs & EHCI_STS_IAA) { 596 DPRINTF(("ehci_intr1: door bell\n")); 597 wakeup(&sc->sc_async_head); 598 eintrs &= ~EHCI_STS_IAA; 599 } 600 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 601 DPRINTFN(5,("ehci_intr1: %s %s\n", 602 eintrs & EHCI_STS_INT ? "INT" : "", 603 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 604 usb_schedsoftintr(&sc->sc_bus); 605 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 606 } 607 if (eintrs & EHCI_STS_PCD) { 608 ehci_pcd(sc, sc->sc_intrxfer); 609 eintrs &= ~EHCI_STS_PCD; 610 } 611 612 sc->sc_bus.intr_context--; 613 614 if (eintrs != 0) { 615 /* Block unprocessed interrupts. */ 616 sc->sc_eintrs &= ~eintrs; 617 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 618 printf("%s: blocking intrs 0x%x\n", 619 sc->sc_bus.bdev.dv_xname, eintrs); 620 } 621 622 return (1); 623 } 624 625 void 626 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 627 { 628 u_char *p; 629 int i, m; 630 631 if (xfer == NULL) { 632 /* Just ignore the change. */ 633 return; 634 } 635 636 p = KERNADDR(&xfer->dmabuf, 0); 637 m = min(sc->sc_noport, xfer->length * 8 - 1); 638 memset(p, 0, xfer->length); 639 for (i = 1; i <= m; i++) { 640 /* Pick out CHANGE bits from the status reg. */ 641 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 642 p[i/8] |= 1 << (i%8); 643 } 644 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 645 xfer->actlen = xfer->length; 646 xfer->status = USBD_NORMAL_COMPLETION; 647 648 usb_transfer_complete(xfer); 649 } 650 651 void 652 ehci_softintr(void *v) 653 { 654 ehci_softc_t *sc = v; 655 struct ehci_xfer *ex, *nextex; 656 657 DPRINTFN(10,("%s: ehci_softintr (%d)\n", sc->sc_bus.bdev.dv_xname, 658 sc->sc_bus.intr_context)); 659 660 if (sc->sc_bus.dying) 661 return; 662 663 sc->sc_bus.intr_context++; 664 665 /* 666 * The only explanation I can think of for why EHCI is as brain dead 667 * as UHCI interrupt-wise is that Intel was involved in both. 668 * An interrupt just tells us that something is done, we have no 669 * clue what, so we need to scan through all active transfers. :-( 670 */ 671 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 672 nextex = TAILQ_NEXT(ex, inext); 673 ehci_check_intr(sc, ex); 674 } 675 676 /* Schedule a callout to catch any dropped transactions. */ 677 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 678 !TAILQ_EMPTY(&sc->sc_intrhead)) { 679 timeout_add_sec(&sc->sc_tmo_intrlist, 1); 680 } 681 682 if (sc->sc_softwake) { 683 sc->sc_softwake = 0; 684 wakeup(&sc->sc_softwake); 685 } 686 687 sc->sc_bus.intr_context--; 688 } 689 690 /* Check for an interrupt. */ 691 void 692 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 693 { 694 int attr; 695 696 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 697 698 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 699 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 700 ehci_check_itd_intr(sc, ex); 701 else 702 ehci_check_qh_intr(sc, ex); 703 704 return; 705 } 706 707 void 708 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 709 { 710 ehci_soft_qtd_t *sqtd, *lsqtd; 711 __uint32_t status; 712 713 if (ex->sqtdstart == NULL) { 714 printf("ehci_check_qh_intr: not valid sqtd\n"); 715 return; 716 } 717 718 lsqtd = ex->sqtdend; 719 #ifdef DIAGNOSTIC 720 if (lsqtd == NULL) { 721 printf("ehci_check_qh_intr: lsqtd==0\n"); 722 return; 723 } 724 #endif 725 /* 726 * If the last TD is still active we need to check whether there 727 * is a an error somewhere in the middle, or whether there was a 728 * short packet (SPD and not ACTIVE). 729 */ 730 usb_syncmem(&lsqtd->dma, 731 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 732 sizeof(lsqtd->qtd.qtd_status), 733 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 734 if (letoh32(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 735 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 736 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 737 usb_syncmem(&sqtd->dma, 738 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 739 sizeof(sqtd->qtd.qtd_status), 740 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 741 status = letoh32(sqtd->qtd.qtd_status); 742 usb_syncmem(&sqtd->dma, 743 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 744 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 745 /* If there's an active QTD the xfer isn't done. */ 746 if (status & EHCI_QTD_ACTIVE) 747 break; 748 /* Any kind of error makes the xfer done. */ 749 if (status & EHCI_QTD_HALTED) 750 goto done; 751 /* We want short packets, and it is short: it's done */ 752 if (EHCI_QTD_GET_BYTES(status) != 0) 753 goto done; 754 } 755 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 756 ex, ex->sqtdstart)); 757 usb_syncmem(&lsqtd->dma, 758 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 759 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 760 return; 761 } 762 done: 763 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 764 timeout_del(&ex->xfer.timeout_handle); 765 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task); 766 ehci_idone(ex); 767 } 768 769 void 770 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 771 ehci_soft_itd_t *itd; 772 int i; 773 774 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 775 return; 776 777 if (ex->itdstart == NULL) { 778 printf("ehci_check_itd_intr: not valid itd\n"); 779 return; 780 } 781 782 itd = ex->itdend; 783 #ifdef DIAGNOSTIC 784 if (itd == NULL) { 785 printf("ehci_check_itd_intr: itdend == 0\n"); 786 return; 787 } 788 #endif 789 790 /* 791 * check no active transfers in last itd, meaning we're finished 792 */ 793 794 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 795 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 796 BUS_DMASYNC_POSTREAD); 797 798 for (i = 0; i < 8; i++) { 799 if (letoh32(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 800 break; 801 } 802 803 if (i == 8) { 804 goto done; /* All 8 descriptors inactive, it's done */ 805 } 806 807 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 808 ex->itdstart)); 809 return; 810 done: 811 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 812 timeout_del(&ex->xfer.timeout_handle); 813 ehci_idone(ex); 814 } 815 816 void 817 ehci_idone(struct ehci_xfer *ex) 818 { 819 usbd_xfer_handle xfer = &ex->xfer; 820 #ifdef EHCI_DEBUG 821 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 822 #endif 823 ehci_soft_qtd_t *sqtd, *lsqtd; 824 u_int32_t status = 0, nstatus = 0; 825 int actlen, cerr; 826 827 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 828 #ifdef DIAGNOSTIC 829 { 830 int s = splhigh(); 831 if (ex->isdone) { 832 splx(s); 833 #ifdef EHCI_DEBUG 834 printf("ehci_idone: ex is done!\n "); 835 ehci_dump_exfer(ex); 836 #else 837 printf("ehci_idone: ex=%p is done!\n", ex); 838 #endif 839 return; 840 } 841 ex->isdone = 1; 842 splx(s); 843 } 844 #endif 845 if (xfer->status == USBD_CANCELLED || 846 xfer->status == USBD_TIMEOUT) { 847 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 848 return; 849 } 850 851 #ifdef EHCI_DEBUG 852 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 853 if (ehcidebug > 10) 854 ehci_dump_sqtds(ex->sqtdstart); 855 #endif 856 857 /* The transfer is done, compute actual length and status. */ 858 859 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 860 == UE_ISOCHRONOUS) { 861 /* Isoc transfer */ 862 struct ehci_soft_itd *itd; 863 int i, nframes, len, uframes; 864 865 nframes = 0; 866 actlen = 0; 867 868 switch (xfer->pipe->endpoint->edesc->bInterval) { 869 case 0: 870 panic("ehci: isoc xfer suddenly has 0 bInterval, " 871 "invalid"); 872 case 1: 873 uframes = 1; 874 break; 875 case 2: 876 uframes = 2; 877 break; 878 case 3: 879 uframes = 4; 880 break; 881 default: 882 uframes = 8; 883 break; 884 } 885 886 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 887 usb_syncmem(&itd->dma, 888 itd->offs + offsetof(ehci_itd_t, itd_ctl), 889 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 890 BUS_DMASYNC_POSTREAD); 891 892 for (i = 0; i < 8; i += uframes) { 893 /* XXX - driver didn't fill in the frame full 894 * of uframes. This leads to scheduling 895 * inefficiencies, but working around 896 * this doubles complexity of tracking 897 * an xfer. 898 */ 899 if (nframes >= xfer->nframes) 900 break; 901 902 status = letoh32(itd->itd.itd_ctl[i]); 903 len = EHCI_ITD_GET_LEN(status); 904 if (EHCI_ITD_GET_STATUS(status) != 0) 905 len = 0; /*No valid data on error*/ 906 907 xfer->frlengths[nframes++] = len; 908 actlen += len; 909 } 910 911 if (nframes >= xfer->nframes) 912 break; 913 } 914 915 xfer->actlen = actlen; 916 xfer->status = USBD_NORMAL_COMPLETION; 917 918 goto end; 919 } 920 921 /* Continue processing xfers using queue heads */ 922 923 lsqtd = ex->sqtdend; 924 actlen = 0; 925 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; 926 sqtd = sqtd->nextqtd) { 927 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 928 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 929 nstatus = letoh32(sqtd->qtd.qtd_status); 930 if (nstatus & EHCI_QTD_ACTIVE) 931 break; 932 933 status = nstatus; 934 /* halt is ok if descriptor is last, and complete */ 935 if (sqtd->qtd.qtd_next == EHCI_NULL && 936 EHCI_QTD_GET_BYTES(status) == 0) 937 status &= ~EHCI_QTD_HALTED; 938 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 939 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 940 } 941 942 cerr = EHCI_QTD_GET_CERR(status); 943 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 944 "status=0x%x\n", xfer->length, actlen, cerr, status)); 945 xfer->actlen = actlen; 946 if ((status & EHCI_QTD_HALTED) != 0) { 947 #ifdef EHCI_DEBUG 948 char sbuf[128]; 949 950 bitmask_snprintf((u_int32_t)status, 951 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 952 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 953 954 DPRINTFN(2, 955 ("ehci_idone: error, addr=%d, endpt=0x%02x, " 956 "status 0x%s\n", 957 xfer->pipe->device->address, 958 xfer->pipe->endpoint->edesc->bEndpointAddress, 959 sbuf)); 960 if (ehcidebug > 2) { 961 ehci_dump_sqh(epipe->sqh); 962 ehci_dump_sqtds(ex->sqtdstart); 963 } 964 #endif 965 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0) 966 xfer->status = USBD_STALLED; 967 else 968 xfer->status = USBD_IOERROR; /* more info XXX */ 969 } else 970 xfer->status = USBD_NORMAL_COMPLETION; 971 end: 972 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 973 * during this call, before methods->done is called: dma sync required 974 * beforehand? */ 975 usb_transfer_complete(xfer); 976 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 977 } 978 979 /* 980 * Wait here until controller claims to have an interrupt. 981 * Then call ehci_intr and return. Use timeout to avoid waiting 982 * too long. 983 */ 984 void 985 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 986 { 987 int timo; 988 u_int32_t intrs; 989 990 xfer->status = USBD_IN_PROGRESS; 991 for (timo = xfer->timeout; timo >= 0; timo--) { 992 usb_delay_ms(&sc->sc_bus, 1); 993 if (sc->sc_bus.dying) 994 break; 995 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 996 sc->sc_eintrs; 997 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 998 #ifdef EHCI_DEBUG 999 if (ehcidebug > 15) 1000 ehci_dump_regs(sc); 1001 #endif 1002 if (intrs) { 1003 ehci_intr1(sc); 1004 if (xfer->status != USBD_IN_PROGRESS) 1005 return; 1006 } 1007 } 1008 1009 /* Timeout */ 1010 DPRINTF(("ehci_waitintr: timeout\n")); 1011 xfer->status = USBD_TIMEOUT; 1012 usb_transfer_complete(xfer); 1013 /* XXX should free TD */ 1014 } 1015 1016 void 1017 ehci_poll(struct usbd_bus *bus) 1018 { 1019 ehci_softc_t *sc = (ehci_softc_t *)bus; 1020 #ifdef EHCI_DEBUG 1021 static int last; 1022 int new; 1023 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1024 if (new != last) { 1025 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1026 last = new; 1027 } 1028 #endif 1029 1030 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1031 ehci_intr1(sc); 1032 } 1033 1034 int 1035 ehci_detach(struct ehci_softc *sc, int flags) 1036 { 1037 int rv = 0; 1038 1039 if (sc->sc_child != NULL) 1040 rv = config_detach(sc->sc_child, flags); 1041 1042 if (rv != 0) 1043 return (rv); 1044 1045 timeout_del(&sc->sc_tmo_intrlist); 1046 1047 if (sc->sc_shutdownhook != NULL) 1048 shutdownhook_disestablish(sc->sc_shutdownhook); 1049 1050 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1051 1052 /* XXX free other data structures XXX */ 1053 1054 return (rv); 1055 } 1056 1057 1058 int 1059 ehci_activate(struct device *self, int act) 1060 { 1061 struct ehci_softc *sc = (struct ehci_softc *)self; 1062 u_int32_t cmd, hcr; 1063 int i, rv = 0; 1064 1065 switch (act) { 1066 case DVACT_ACTIVATE: 1067 break; 1068 case DVACT_QUIESCE: 1069 rv = config_activate_children(self, act); 1070 break; 1071 case DVACT_SUSPEND: 1072 sc->sc_bus.use_polling++; 1073 1074 for (i = 1; i <= sc->sc_noport; i++) { 1075 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1076 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE) 1077 EOWRITE4(sc, EHCI_PORTSC(i), 1078 cmd | EHCI_PS_SUSP); 1079 } 1080 1081 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1082 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1083 EOWRITE4(sc, EHCI_USBCMD, cmd); 1084 1085 for (i = 0; i < 100; i++) { 1086 hcr = EOREAD4(sc, EHCI_USBSTS) & 1087 (EHCI_STS_ASS | EHCI_STS_PSS); 1088 if (hcr == 0) 1089 break; 1090 1091 usb_delay_ms(&sc->sc_bus, 1); 1092 } 1093 if (hcr != 0) 1094 printf("%s: reset timeout\n", 1095 sc->sc_bus.bdev.dv_xname); 1096 1097 cmd &= ~EHCI_CMD_RS; 1098 EOWRITE4(sc, EHCI_USBCMD, cmd); 1099 1100 for (i = 0; i < 100; i++) { 1101 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1102 if (hcr == EHCI_STS_HCH) 1103 break; 1104 1105 usb_delay_ms(&sc->sc_bus, 1); 1106 } 1107 if (hcr != EHCI_STS_HCH) 1108 printf("%s: config timeout\n", 1109 sc->sc_bus.bdev.dv_xname); 1110 1111 sc->sc_bus.use_polling--; 1112 break; 1113 case DVACT_RESUME: 1114 sc->sc_bus.use_polling++; 1115 1116 /* restore things in case the bios sucks */ 1117 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1118 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1119 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1120 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1121 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1122 1123 hcr = 0; 1124 for (i = 1; i <= sc->sc_noport; i++) { 1125 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1126 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP) { 1127 EOWRITE4(sc, EHCI_PORTSC(i), 1128 cmd | EHCI_PS_FPR); 1129 hcr = 1; 1130 } 1131 } 1132 1133 if (hcr) { 1134 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1135 for (i = 1; i <= sc->sc_noport; i++) { 1136 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1137 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == 1138 EHCI_PS_SUSP) 1139 EOWRITE4(sc, EHCI_PORTSC(i), 1140 cmd & ~EHCI_PS_FPR); 1141 } 1142 } 1143 1144 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1145 1146 /* Take over port ownership */ 1147 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 1148 1149 for (i = 0; i < 100; i++) { 1150 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1151 if (hcr != EHCI_STS_HCH) 1152 break; 1153 1154 usb_delay_ms(&sc->sc_bus, 1); 1155 } 1156 if (hcr == EHCI_STS_HCH) 1157 printf("%s: config timeout\n", 1158 sc->sc_bus.bdev.dv_xname); 1159 1160 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1161 1162 sc->sc_bus.use_polling--; 1163 rv = config_activate_children(self, act); 1164 break; 1165 case DVACT_DEACTIVATE: 1166 if (sc->sc_child != NULL) 1167 rv = config_deactivate(sc->sc_child); 1168 sc->sc_bus.dying = 1; 1169 break; 1170 } 1171 return (rv); 1172 } 1173 1174 /* 1175 * Shut down the controller when the system is going down. 1176 */ 1177 void 1178 ehci_shutdown(void *v) 1179 { 1180 ehci_softc_t *sc = v; 1181 1182 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1183 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1184 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1185 } 1186 1187 usbd_status 1188 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1189 { 1190 struct ehci_softc *sc = (struct ehci_softc *)bus; 1191 usbd_status err; 1192 1193 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1194 #ifdef EHCI_DEBUG 1195 if (err) 1196 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1197 #endif 1198 return (err); 1199 } 1200 1201 void 1202 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1203 { 1204 struct ehci_softc *sc = (struct ehci_softc *)bus; 1205 1206 usb_freemem(&sc->sc_bus, dma); 1207 } 1208 1209 usbd_xfer_handle 1210 ehci_allocx(struct usbd_bus *bus) 1211 { 1212 struct ehci_softc *sc = (struct ehci_softc *)bus; 1213 usbd_xfer_handle xfer; 1214 1215 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1216 if (xfer != NULL) { 1217 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1218 #ifdef DIAGNOSTIC 1219 if (xfer->busy_free != XFER_FREE) 1220 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", 1221 xfer, xfer->busy_free); 1222 #endif 1223 } else 1224 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1225 1226 if (xfer != NULL) { 1227 memset(xfer, 0, sizeof(struct ehci_xfer)); 1228 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task, 1229 xfer, USB_TASK_TYPE_ABORT); 1230 EXFER(xfer)->ehci_xfer_flags = 0; 1231 #ifdef DIAGNOSTIC 1232 EXFER(xfer)->isdone = 1; 1233 xfer->busy_free = XFER_BUSY; 1234 #endif 1235 } 1236 return (xfer); 1237 } 1238 1239 void 1240 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1241 { 1242 struct ehci_softc *sc = (struct ehci_softc *)bus; 1243 1244 #ifdef DIAGNOSTIC 1245 if (xfer->busy_free != XFER_BUSY) { 1246 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1247 xfer->busy_free); 1248 return; 1249 } 1250 xfer->busy_free = XFER_FREE; 1251 if (!EXFER(xfer)->isdone) { 1252 printf("ehci_freex: !isdone\n"); 1253 return; 1254 } 1255 #endif 1256 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1257 } 1258 1259 void 1260 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1261 { 1262 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1263 1264 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1265 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1266 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 1267 if (ehcidebug) 1268 usbd_dump_pipe(pipe); 1269 #endif 1270 #ifdef DIAGNOSTIC 1271 if ((epipe->sqh->qh.qh_qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) != 0) 1272 panic("ehci_device_clear_toggle: queue active"); 1273 #endif 1274 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1275 } 1276 1277 void 1278 ehci_noop(usbd_pipe_handle pipe) 1279 { 1280 } 1281 1282 #ifdef EHCI_DEBUG 1283 void 1284 ehci_dump_regs(ehci_softc_t *sc) 1285 { 1286 int i; 1287 1288 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1289 EOREAD4(sc, EHCI_USBCMD), 1290 EOREAD4(sc, EHCI_USBSTS), 1291 EOREAD4(sc, EHCI_USBINTR)); 1292 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1293 EOREAD4(sc, EHCI_FRINDEX), 1294 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1295 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1296 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1297 for (i = 1; i <= sc->sc_noport; i++) 1298 printf("port %d status=0x%08x\n", i, 1299 EOREAD4(sc, EHCI_PORTSC(i))); 1300 } 1301 1302 /* 1303 * Unused function - this is meant to be called from a kernel 1304 * debugger. 1305 */ 1306 void 1307 ehci_dump() 1308 { 1309 ehci_dump_regs(theehci); 1310 } 1311 1312 void 1313 ehci_dump_link(ehci_link_t link, int type) 1314 { 1315 link = letoh32(link); 1316 printf("0x%08x", link); 1317 if (link & EHCI_LINK_TERMINATE) 1318 printf("<T>"); 1319 else { 1320 printf("<"); 1321 if (type) { 1322 switch (EHCI_LINK_TYPE(link)) { 1323 case EHCI_LINK_ITD: 1324 printf("ITD"); 1325 break; 1326 case EHCI_LINK_QH: 1327 printf("QH"); 1328 break; 1329 case EHCI_LINK_SITD: 1330 printf("SITD"); 1331 break; 1332 case EHCI_LINK_FSTN: 1333 printf("FSTN"); 1334 break; 1335 } 1336 } 1337 printf(">"); 1338 } 1339 } 1340 1341 void 1342 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1343 { 1344 int i; 1345 u_int32_t stop; 1346 1347 stop = 0; 1348 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1349 ehci_dump_sqtd(sqtd); 1350 usb_syncmem(&sqtd->dma, 1351 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1352 sizeof(sqtd->qtd), 1353 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1354 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1355 usb_syncmem(&sqtd->dma, 1356 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1357 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1358 } 1359 if (!stop) 1360 printf("dump aborted, too many TDs\n"); 1361 } 1362 1363 void 1364 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1365 { 1366 usb_syncmem(&sqtd->dma, sqtd->offs, 1367 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1368 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1369 ehci_dump_qtd(&sqtd->qtd); 1370 usb_syncmem(&sqtd->dma, sqtd->offs, 1371 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1372 } 1373 1374 void 1375 ehci_dump_qtd(ehci_qtd_t *qtd) 1376 { 1377 u_int32_t s; 1378 char sbuf[128]; 1379 1380 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1381 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1382 printf("\n"); 1383 s = letoh32(qtd->qtd_status); 1384 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED" 1385 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING", 1386 sbuf, sizeof(sbuf)); 1387 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1388 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1389 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1390 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1391 EHCI_QTD_GET_PID(s), sbuf); 1392 for (s = 0; s < 5; s++) 1393 printf(" buffer[%d]=0x%08x\n", s, letoh32(qtd->qtd_buffer[s])); 1394 } 1395 1396 void 1397 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1398 { 1399 ehci_qh_t *qh = &sqh->qh; 1400 u_int32_t endp, endphub; 1401 1402 usb_syncmem(&sqh->dma, sqh->offs, 1403 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1404 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1405 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1406 endp = letoh32(qh->qh_endp); 1407 printf(" endp=0x%08x\n", endp); 1408 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1409 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1410 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1411 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1412 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1413 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1414 EHCI_QH_GET_NRL(endp)); 1415 endphub = letoh32(qh->qh_endphub); 1416 printf(" endphub=0x%08x\n", endphub); 1417 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1418 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1419 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1420 EHCI_QH_GET_MULT(endphub)); 1421 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1422 printf("Overlay qTD:\n"); 1423 ehci_dump_qtd(&qh->qh_qtd); 1424 usb_syncmem(&sqh->dma, sqh->offs, 1425 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1426 } 1427 1428 #if notyet 1429 void 1430 ehci_dump_itd(struct ehci_soft_itd *itd) 1431 { 1432 ehci_isoc_trans_t t; 1433 ehci_isoc_bufr_ptr_t b, b2, b3; 1434 int i; 1435 1436 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1437 1438 for (i = 0; i < 8;i++) { 1439 t = letoh32(itd->itd.itd_ctl[i]); 1440 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1441 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1442 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1443 EHCI_ITD_GET_OFFS(t)); 1444 } 1445 printf("ITDbufr: "); 1446 for (i = 0; i < 7; i++) 1447 printf("%X,", EHCI_ITD_GET_BPTR(letoh32(itd->itd.itd_bufr[i]))); 1448 1449 b = letoh32(itd->itd.itd_bufr[0]); 1450 b2 = letoh32(itd->itd.itd_bufr[1]); 1451 b3 = letoh32(itd->itd.itd_bufr[2]); 1452 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1453 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1454 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1455 } 1456 1457 void 1458 ehci_dump_sitd(struct ehci_soft_itd *itd) 1459 { 1460 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1461 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1462 itd->xfer_next, itd->physaddr, itd->slot); 1463 } 1464 #endif 1465 1466 #ifdef DIAGNOSTIC 1467 void 1468 ehci_dump_exfer(struct ehci_xfer *ex) 1469 { 1470 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p " 1471 "isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, 1472 ex->itdend, ex->isdone); 1473 } 1474 #endif 1475 1476 #endif /* EHCI_DEBUG */ 1477 1478 usbd_status 1479 ehci_open(usbd_pipe_handle pipe) 1480 { 1481 usbd_device_handle dev = pipe->device; 1482 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1483 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1484 u_int8_t addr = dev->address; 1485 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1486 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1487 ehci_soft_qh_t *sqh; 1488 usbd_status err; 1489 int s; 1490 int ival, speed, naks; 1491 int hshubaddr, hshubport; 1492 1493 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1494 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1495 1496 if (sc->sc_bus.dying) 1497 return (USBD_IOERROR); 1498 1499 if (dev->myhsport) { 1500 hshubaddr = dev->myhsport->parent->address; 1501 hshubport = dev->myhsport->portno; 1502 } else { 1503 hshubaddr = 0; 1504 hshubport = 0; 1505 } 1506 1507 if (addr == sc->sc_addr) { 1508 switch (ed->bEndpointAddress) { 1509 case USB_CONTROL_ENDPOINT: 1510 pipe->methods = &ehci_root_ctrl_methods; 1511 break; 1512 case UE_DIR_IN | EHCI_INTR_ENDPT: 1513 pipe->methods = &ehci_root_intr_methods; 1514 break; 1515 default: 1516 return (USBD_INVAL); 1517 } 1518 return (USBD_NORMAL_COMPLETION); 1519 } 1520 1521 /* XXX All this stuff is only valid for async. */ 1522 switch (dev->speed) { 1523 case USB_SPEED_LOW: 1524 speed = EHCI_QH_SPEED_LOW; 1525 break; 1526 case USB_SPEED_FULL: 1527 speed = EHCI_QH_SPEED_FULL; 1528 break; 1529 case USB_SPEED_HIGH: 1530 speed = EHCI_QH_SPEED_HIGH; 1531 break; 1532 default: 1533 panic("ehci_open: bad device speed %d", dev->speed); 1534 } 1535 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1536 printf("%s: Error opening low/full speed isoc endpoint.\n" 1537 "A low/full speed device is attached to a USB2 hub, and " 1538 "transaction translations are not yet supported.\n" 1539 "Reattach the device to the root hub instead.\n", 1540 sc->sc_bus.bdev.dv_xname); 1541 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1542 hshubaddr, hshubport)); 1543 return (USBD_INVAL); 1544 } 1545 1546 naks = 8; /* XXX */ 1547 1548 /* Allocate sqh for everything, save isoc xfers */ 1549 if (xfertype != UE_ISOCHRONOUS) { 1550 sqh = ehci_alloc_sqh(sc); 1551 if (sqh == NULL) 1552 return (USBD_NOMEM); 1553 /* qh_link filled when the QH is added */ 1554 sqh->qh.qh_endp = htole32( 1555 EHCI_QH_SET_ADDR(addr) | 1556 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1557 EHCI_QH_SET_EPS(speed) | 1558 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1559 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1560 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1561 EHCI_QH_CTL : 0) | 1562 EHCI_QH_SET_NRL(naks) 1563 ); 1564 sqh->qh.qh_endphub = htole32( 1565 EHCI_QH_SET_MULT(1) | 1566 EHCI_QH_SET_HUBA(hshubaddr) | 1567 EHCI_QH_SET_PORT(hshubport) | 1568 EHCI_QH_SET_CMASK(0x1c) | /* XXX */ 1569 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1570 ); 1571 sqh->qh.qh_curqtd = EHCI_NULL; 1572 /* Fill the overlay qTD */ 1573 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1574 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1575 sqh->qh.qh_qtd.qtd_status = 1576 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1577 1578 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1579 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1580 epipe->sqh = sqh; 1581 } else { 1582 sqh = NULL; 1583 } /*xfertype == UE_ISOC*/ 1584 1585 switch (xfertype) { 1586 case UE_CONTROL: 1587 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1588 0, &epipe->u.ctl.reqdma); 1589 #ifdef EHCI_DEBUG 1590 if (err) 1591 printf("ehci_open: usb_allocmem()=%d\n", err); 1592 #endif 1593 if (err) 1594 goto bad; 1595 pipe->methods = &ehci_device_ctrl_methods; 1596 s = splusb(); 1597 ehci_add_qh(sqh, sc->sc_async_head); 1598 splx(s); 1599 break; 1600 case UE_BULK: 1601 pipe->methods = &ehci_device_bulk_methods; 1602 s = splusb(); 1603 ehci_add_qh(sqh, sc->sc_async_head); 1604 splx(s); 1605 break; 1606 case UE_INTERRUPT: 1607 pipe->methods = &ehci_device_intr_methods; 1608 ival = pipe->interval; 1609 if (ival == USBD_DEFAULT_INTERVAL) 1610 ival = ed->bInterval; 1611 s = splusb(); 1612 err = ehci_device_setintr(sc, sqh, ival); 1613 splx(s); 1614 return (err); 1615 case UE_ISOCHRONOUS: 1616 pipe->methods = &ehci_device_isoc_methods; 1617 if (ed->bInterval == 0 || ed->bInterval > 16) { 1618 printf("ehci: opening pipe with invalid bInterval\n"); 1619 err = USBD_INVAL; 1620 goto bad; 1621 } 1622 if (UGETW(ed->wMaxPacketSize) == 0) { 1623 printf("ehci: zero length endpoint open request\n"); 1624 err = USBD_INVAL; 1625 goto bad; 1626 } 1627 epipe->u.isoc.next_frame = 0; 1628 epipe->u.isoc.cur_xfers = 0; 1629 break; 1630 default: 1631 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1632 return (USBD_INVAL); 1633 } 1634 return (USBD_NORMAL_COMPLETION); 1635 1636 bad: 1637 if (sqh != NULL) 1638 ehci_free_sqh(sc, sqh); 1639 return (err); 1640 } 1641 1642 /* 1643 * Add an ED to the schedule. Called at splusb(). 1644 * If in the async schedule, it will always have a next. 1645 * If in the intr schedule it may not. 1646 */ 1647 void 1648 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1649 { 1650 SPLUSBCHECK; 1651 1652 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1653 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1654 sqh->next = head->next; 1655 sqh->prev = head; 1656 sqh->qh.qh_link = head->qh.qh_link; 1657 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1658 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1659 head->next = sqh; 1660 if (sqh->next) 1661 sqh->next->prev = sqh; 1662 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1663 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1664 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1665 1666 #ifdef EHCI_DEBUG 1667 if (ehcidebug > 5) { 1668 printf("ehci_add_qh:\n"); 1669 ehci_dump_sqh(sqh); 1670 } 1671 #endif 1672 } 1673 1674 /* 1675 * Remove an ED from the schedule. Called at splusb(). 1676 * Will always have a 'next' if it's in the async list as it's circular. 1677 */ 1678 void 1679 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1680 { 1681 SPLUSBCHECK; 1682 /* XXX */ 1683 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1684 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1685 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1686 sqh->prev->next = sqh->next; 1687 if (sqh->next) 1688 sqh->next->prev = sqh->prev; 1689 usb_syncmem(&sqh->prev->dma, 1690 sqh->prev->offs + offsetof(ehci_qh_t, qh_link), 1691 sizeof(sqh->prev->qh.qh_link), BUS_DMASYNC_PREWRITE); 1692 1693 ehci_sync_hc(sc); 1694 } 1695 1696 void 1697 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1698 { 1699 int i; 1700 u_int32_t status; 1701 1702 /* Save toggle bit and ping status. */ 1703 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1704 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1705 status = sqh->qh.qh_qtd.qtd_status & 1706 htole32(EHCI_QTD_TOGGLE_MASK | 1707 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1708 /* Set HALTED to make hw leave it alone. */ 1709 sqh->qh.qh_qtd.qtd_status = 1710 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1711 usb_syncmem(&sqh->dma, 1712 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1713 sizeof(sqh->qh.qh_qtd.qtd_status), 1714 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1715 sqh->qh.qh_curqtd = 0; 1716 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1717 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1718 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1719 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1720 sqh->sqtd = sqtd; 1721 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1722 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1723 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1724 sqh->qh.qh_qtd.qtd_status = status; 1725 usb_syncmem(&sqh->dma, 1726 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1727 sizeof(sqh->qh.qh_qtd.qtd_status), 1728 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1729 } 1730 1731 /* 1732 * Ensure that the HC has released all references to the QH. We do this 1733 * by asking for a Async Advance Doorbell interrupt and then we wait for 1734 * the interrupt. 1735 * To make this easier we first obtain exclusive use of the doorbell. 1736 */ 1737 void 1738 ehci_sync_hc(ehci_softc_t *sc) 1739 { 1740 int s, error; 1741 int tries = 0; 1742 1743 if (sc->sc_bus.dying) { 1744 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1745 return; 1746 } 1747 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1748 /* get doorbell */ 1749 rw_enter_write(&sc->sc_doorbell_lock); 1750 s = splhardusb(); 1751 do { 1752 /* ask for doorbell */ 1753 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | 1754 EHCI_CMD_IAAD); 1755 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1756 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1757 /* bell wait */ 1758 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz / 2); 1759 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1760 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1761 } while (error && ++tries < 10); 1762 splx(s); 1763 /* release doorbell */ 1764 rw_exit_write(&sc->sc_doorbell_lock); 1765 #ifdef DIAGNOSTIC 1766 if (error) 1767 printf("ehci_sync_hc: tsleep() = %d\n", error); 1768 #endif 1769 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1770 } 1771 1772 /*Call at splusb*/ 1773 void 1774 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1775 { 1776 struct ehci_soft_itd *itd, *prev; 1777 1778 prev = NULL; 1779 1780 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1781 panic("ehci isoc xfer being freed, but with no itd chain"); 1782 1783 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1784 prev = itd->u.frame_list.prev; 1785 /* Unlink itd from hardware chain, or frame array */ 1786 if (prev == NULL) { /* We're at the table head */ 1787 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1788 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1789 usb_syncmem(&sc->sc_fldma, 1790 sizeof(ehci_link_t) * itd->slot, 1791 sizeof(ehci_link_t), 1792 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1793 1794 if (itd->u.frame_list.next != NULL) 1795 itd->u.frame_list.next->u.frame_list.prev = 1796 NULL; 1797 } else { 1798 /* XXX this part is untested... */ 1799 prev->itd.itd_next = itd->itd.itd_next; 1800 usb_syncmem(&itd->dma, 1801 itd->offs + offsetof(ehci_itd_t, itd_next), 1802 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1803 1804 prev->u.frame_list.next = itd->u.frame_list.next; 1805 if (itd->u.frame_list.next != NULL) 1806 itd->u.frame_list.next->u.frame_list.prev = 1807 prev; 1808 } 1809 } 1810 1811 prev = NULL; 1812 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1813 if (prev != NULL) 1814 ehci_free_itd(sc, prev); 1815 prev = itd; 1816 } 1817 if (prev) 1818 ehci_free_itd(sc, prev); 1819 exfer->itdstart = NULL; 1820 exfer->itdend = NULL; 1821 } 1822 1823 /***********/ 1824 1825 /* 1826 * Data structures and routines to emulate the root hub. 1827 */ 1828 usb_device_descriptor_t ehci_devd = { 1829 USB_DEVICE_DESCRIPTOR_SIZE, 1830 UDESC_DEVICE, /* type */ 1831 {0x00, 0x02}, /* USB version */ 1832 UDCLASS_HUB, /* class */ 1833 UDSUBCLASS_HUB, /* subclass */ 1834 UDPROTO_HSHUBSTT, /* protocol */ 1835 64, /* max packet */ 1836 {0},{0},{0x00,0x01}, /* device id */ 1837 1,2,0, /* string indicies */ 1838 1 /* # of configurations */ 1839 }; 1840 1841 usb_device_qualifier_t ehci_odevd = { 1842 USB_DEVICE_DESCRIPTOR_SIZE, 1843 UDESC_DEVICE_QUALIFIER, /* type */ 1844 {0x00, 0x02}, /* USB version */ 1845 UDCLASS_HUB, /* class */ 1846 UDSUBCLASS_HUB, /* subclass */ 1847 UDPROTO_FSHUB, /* protocol */ 1848 64, /* max packet */ 1849 1, /* # of configurations */ 1850 0 1851 }; 1852 1853 usb_config_descriptor_t ehci_confd = { 1854 USB_CONFIG_DESCRIPTOR_SIZE, 1855 UDESC_CONFIG, 1856 {USB_CONFIG_DESCRIPTOR_SIZE + 1857 USB_INTERFACE_DESCRIPTOR_SIZE + 1858 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1859 1, 1860 1, 1861 0, 1862 UC_SELF_POWERED, 1863 0 /* max power */ 1864 }; 1865 1866 usb_interface_descriptor_t ehci_ifcd = { 1867 USB_INTERFACE_DESCRIPTOR_SIZE, 1868 UDESC_INTERFACE, 1869 0, 1870 0, 1871 1, 1872 UICLASS_HUB, 1873 UISUBCLASS_HUB, 1874 UIPROTO_HSHUBSTT, 1875 0 1876 }; 1877 1878 usb_endpoint_descriptor_t ehci_endpd = { 1879 USB_ENDPOINT_DESCRIPTOR_SIZE, 1880 UDESC_ENDPOINT, 1881 UE_DIR_IN | EHCI_INTR_ENDPT, 1882 UE_INTERRUPT, 1883 {8, 0}, /* max packet */ 1884 255 1885 }; 1886 1887 usb_hub_descriptor_t ehci_hubd = { 1888 USB_HUB_DESCRIPTOR_SIZE, 1889 UDESC_HUB, 1890 0, 1891 {0,0}, 1892 0, 1893 0, 1894 {0}, 1895 }; 1896 1897 int 1898 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 1899 { 1900 int i; 1901 1902 if (l == 0) 1903 return (0); 1904 p->bLength = 2 * strlen(s) + 2; 1905 if (l == 1) 1906 return (1); 1907 p->bDescriptorType = UDESC_STRING; 1908 l -= 2; 1909 for (i = 0; s[i] && l > 1; i++, l -= 2) 1910 USETW2(p->bString[i], 0, s[i]); 1911 return (2*i+2); 1912 } 1913 1914 /* 1915 * Simulate a hardware hub by handling all the necessary requests. 1916 */ 1917 usbd_status 1918 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1919 { 1920 usbd_status err; 1921 1922 /* Insert last in queue. */ 1923 err = usb_insert_transfer(xfer); 1924 if (err) 1925 return (err); 1926 1927 /* Pipe isn't running, start first */ 1928 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1929 } 1930 1931 usbd_status 1932 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1933 { 1934 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1935 usb_device_request_t *req; 1936 void *buf = NULL; 1937 int port, i; 1938 int s, len, value, index, l, totlen = 0; 1939 usb_port_status_t ps; 1940 usb_hub_descriptor_t hubd; 1941 usbd_status err; 1942 u_int32_t v; 1943 1944 if (sc->sc_bus.dying) 1945 return (USBD_IOERROR); 1946 1947 #ifdef DIAGNOSTIC 1948 if (!(xfer->rqflags & URQ_REQUEST)) 1949 /* XXX panic */ 1950 return (USBD_INVAL); 1951 #endif 1952 req = &xfer->request; 1953 1954 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1955 req->bmRequestType, req->bRequest)); 1956 1957 len = UGETW(req->wLength); 1958 value = UGETW(req->wValue); 1959 index = UGETW(req->wIndex); 1960 1961 if (len != 0) 1962 buf = KERNADDR(&xfer->dmabuf, 0); 1963 1964 #define C(x,y) ((x) | ((y) << 8)) 1965 switch(C(req->bRequest, req->bmRequestType)) { 1966 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1967 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1968 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1969 /* 1970 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1971 * for the integrated root hub. 1972 */ 1973 break; 1974 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1975 if (len > 0) { 1976 *(u_int8_t *)buf = sc->sc_conf; 1977 totlen = 1; 1978 } 1979 break; 1980 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1981 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1982 switch(value >> 8) { 1983 case UDESC_DEVICE: 1984 if ((value & 0xff) != 0) { 1985 err = USBD_IOERROR; 1986 goto ret; 1987 } 1988 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1989 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1990 memcpy(buf, &ehci_devd, l); 1991 break; 1992 /* 1993 * We can't really operate at another speed, but the spec says 1994 * we need this descriptor. 1995 */ 1996 case UDESC_DEVICE_QUALIFIER: 1997 if ((value & 0xff) != 0) { 1998 err = USBD_IOERROR; 1999 goto ret; 2000 } 2001 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2002 memcpy(buf, &ehci_odevd, l); 2003 break; 2004 /* 2005 * We can't really operate at another speed, but the spec says 2006 * we need this descriptor. 2007 */ 2008 case UDESC_OTHER_SPEED_CONFIGURATION: 2009 case UDESC_CONFIG: 2010 if ((value & 0xff) != 0) { 2011 err = USBD_IOERROR; 2012 goto ret; 2013 } 2014 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2015 memcpy(buf, &ehci_confd, l); 2016 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2017 value >> 8; 2018 buf = (char *)buf + l; 2019 len -= l; 2020 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2021 totlen += l; 2022 memcpy(buf, &ehci_ifcd, l); 2023 buf = (char *)buf + l; 2024 len -= l; 2025 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2026 totlen += l; 2027 memcpy(buf, &ehci_endpd, l); 2028 break; 2029 case UDESC_STRING: 2030 if (len == 0) 2031 break; 2032 *(u_int8_t *)buf = 0; 2033 totlen = 1; 2034 switch (value & 0xff) { 2035 case 0: /* Language table */ 2036 totlen = ehci_str(buf, len, "\001"); 2037 break; 2038 case 1: /* Vendor */ 2039 totlen = ehci_str(buf, len, sc->sc_vendor); 2040 break; 2041 case 2: /* Product */ 2042 totlen = ehci_str(buf, len, "EHCI root hub"); 2043 break; 2044 } 2045 break; 2046 default: 2047 err = USBD_IOERROR; 2048 goto ret; 2049 } 2050 break; 2051 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2052 if (len > 0) { 2053 *(u_int8_t *)buf = 0; 2054 totlen = 1; 2055 } 2056 break; 2057 case C(UR_GET_STATUS, UT_READ_DEVICE): 2058 if (len > 1) { 2059 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2060 totlen = 2; 2061 } 2062 break; 2063 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2064 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2065 if (len > 1) { 2066 USETW(((usb_status_t *)buf)->wStatus, 0); 2067 totlen = 2; 2068 } 2069 break; 2070 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2071 if (value >= USB_MAX_DEVICES) { 2072 err = USBD_IOERROR; 2073 goto ret; 2074 } 2075 sc->sc_addr = value; 2076 break; 2077 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2078 if (value != 0 && value != 1) { 2079 err = USBD_IOERROR; 2080 goto ret; 2081 } 2082 sc->sc_conf = value; 2083 break; 2084 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2085 break; 2086 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2087 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2088 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2089 err = USBD_IOERROR; 2090 goto ret; 2091 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2092 break; 2093 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2094 break; 2095 /* Hub requests */ 2096 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2097 break; 2098 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2099 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2100 "port=%d feature=%d\n", index, value)); 2101 if (index < 1 || index > sc->sc_noport) { 2102 err = USBD_IOERROR; 2103 goto ret; 2104 } 2105 port = EHCI_PORTSC(index); 2106 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2107 switch(value) { 2108 case UHF_PORT_ENABLE: 2109 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2110 break; 2111 case UHF_PORT_SUSPEND: 2112 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 2113 break; 2114 case UHF_PORT_POWER: 2115 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2116 break; 2117 case UHF_PORT_TEST: 2118 DPRINTFN(2,("ehci_root_ctrl_start: " 2119 "clear port test %d\n", index)); 2120 break; 2121 case UHF_PORT_INDICATOR: 2122 DPRINTFN(2,("ehci_root_ctrl_start: " 2123 "clear port index %d\n", index)); 2124 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2125 break; 2126 case UHF_C_PORT_CONNECTION: 2127 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2128 break; 2129 case UHF_C_PORT_ENABLE: 2130 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2131 break; 2132 case UHF_C_PORT_SUSPEND: 2133 /* how? */ 2134 break; 2135 case UHF_C_PORT_OVER_CURRENT: 2136 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2137 break; 2138 case UHF_C_PORT_RESET: 2139 sc->sc_isreset = 0; 2140 break; 2141 default: 2142 err = USBD_IOERROR; 2143 goto ret; 2144 } 2145 break; 2146 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2147 if ((value & 0xff) != 0) { 2148 err = USBD_IOERROR; 2149 goto ret; 2150 } 2151 hubd = ehci_hubd; 2152 hubd.bNbrPorts = sc->sc_noport; 2153 v = EOREAD4(sc, EHCI_HCSPARAMS); 2154 USETW(hubd.wHubCharacteristics, 2155 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2156 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2157 ? UHD_PORT_IND : 0); 2158 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2159 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2160 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2161 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2162 l = min(len, hubd.bDescLength); 2163 totlen = l; 2164 memcpy(buf, &hubd, l); 2165 break; 2166 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2167 if (len != 4) { 2168 err = USBD_IOERROR; 2169 goto ret; 2170 } 2171 memset(buf, 0, len); /* ? XXX */ 2172 totlen = len; 2173 break; 2174 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2175 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2176 index)); 2177 if (index < 1 || index > sc->sc_noport) { 2178 err = USBD_IOERROR; 2179 goto ret; 2180 } 2181 if (len != 4) { 2182 err = USBD_IOERROR; 2183 goto ret; 2184 } 2185 v = EOREAD4(sc, EHCI_PORTSC(index)); 2186 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2187 i = UPS_HIGH_SPEED; 2188 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2189 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2190 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2191 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2192 if (v & EHCI_PS_PR) i |= UPS_RESET; 2193 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2194 USETW(ps.wPortStatus, i); 2195 i = 0; 2196 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2197 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2198 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2199 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2200 USETW(ps.wPortChange, i); 2201 l = min(len, sizeof(ps)); 2202 memcpy(buf, &ps, l); 2203 totlen = l; 2204 break; 2205 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2206 err = USBD_IOERROR; 2207 goto ret; 2208 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2209 break; 2210 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2211 if (index < 1 || index > sc->sc_noport) { 2212 err = USBD_IOERROR; 2213 goto ret; 2214 } 2215 port = EHCI_PORTSC(index); 2216 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2217 switch(value) { 2218 case UHF_PORT_ENABLE: 2219 EOWRITE4(sc, port, v | EHCI_PS_PE); 2220 break; 2221 case UHF_PORT_SUSPEND: 2222 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2223 break; 2224 case UHF_PORT_DISOWN_TO_1_1: 2225 /* enter to Port Reset State */ 2226 v &= ~EHCI_PS_PE; 2227 EOWRITE4(sc, port, v | EHCI_PS_PR); 2228 ehci_disown(sc, index, 0); 2229 break; 2230 case UHF_PORT_RESET: 2231 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2232 index)); 2233 if (EHCI_PS_IS_LOWSPEED(v)) { 2234 /* Low speed device, give up ownership. */ 2235 ehci_disown(sc, index, 1); 2236 break; 2237 } 2238 /* Start reset sequence. */ 2239 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2240 EOWRITE4(sc, port, v | EHCI_PS_PR); 2241 /* Wait for reset to complete. */ 2242 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2243 if (sc->sc_bus.dying) { 2244 err = USBD_IOERROR; 2245 goto ret; 2246 } 2247 /* Terminate reset sequence. */ 2248 v = EOREAD4(sc, port); 2249 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2250 /* Wait for HC to complete reset. */ 2251 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2252 if (sc->sc_bus.dying) { 2253 err = USBD_IOERROR; 2254 goto ret; 2255 } 2256 v = EOREAD4(sc, port); 2257 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2258 if (v & EHCI_PS_PR) { 2259 printf("%s: port reset timeout\n", 2260 sc->sc_bus.bdev.dv_xname); 2261 err = USBD_IOERROR; 2262 goto ret; 2263 } 2264 if (!(v & EHCI_PS_PE)) { 2265 /* Not a high speed device, give up ownership.*/ 2266 ehci_disown(sc, index, 0); 2267 break; 2268 } 2269 sc->sc_isreset = 1; 2270 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2271 index, v)); 2272 break; 2273 case UHF_PORT_POWER: 2274 DPRINTFN(2,("ehci_root_ctrl_start: " 2275 "set port power %d\n", index)); 2276 EOWRITE4(sc, port, v | EHCI_PS_PP); 2277 break; 2278 case UHF_PORT_TEST: 2279 DPRINTFN(2,("ehci_root_ctrl_start: " 2280 "set port test %d\n", index)); 2281 break; 2282 case UHF_PORT_INDICATOR: 2283 DPRINTFN(2,("ehci_root_ctrl_start: " 2284 "set port ind %d\n", index)); 2285 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2286 break; 2287 default: 2288 err = USBD_IOERROR; 2289 goto ret; 2290 } 2291 break; 2292 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2293 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2294 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2295 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2296 break; 2297 default: 2298 err = USBD_IOERROR; 2299 goto ret; 2300 } 2301 xfer->actlen = totlen; 2302 err = USBD_NORMAL_COMPLETION; 2303 ret: 2304 xfer->status = err; 2305 s = splusb(); 2306 usb_transfer_complete(xfer); 2307 splx(s); 2308 return (USBD_IN_PROGRESS); 2309 } 2310 2311 void 2312 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2313 { 2314 int port; 2315 u_int32_t v; 2316 2317 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2318 2319 port = EHCI_PORTSC(index); 2320 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2321 EOWRITE4(sc, port, v | EHCI_PS_PO); 2322 } 2323 2324 /* Abort a root control request. */ 2325 void 2326 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2327 { 2328 /* Nothing to do, all transfers are synchronous. */ 2329 } 2330 2331 /* Close the root pipe. */ 2332 void 2333 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2334 { 2335 DPRINTF(("ehci_root_ctrl_close\n")); 2336 /* Nothing to do. */ 2337 } 2338 2339 void 2340 ehci_root_intr_done(usbd_xfer_handle xfer) 2341 { 2342 } 2343 2344 usbd_status 2345 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2346 { 2347 usbd_status err; 2348 2349 /* Insert last in queue. */ 2350 err = usb_insert_transfer(xfer); 2351 if (err) 2352 return (err); 2353 2354 /* Pipe isn't running, start first */ 2355 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2356 } 2357 2358 usbd_status 2359 ehci_root_intr_start(usbd_xfer_handle xfer) 2360 { 2361 usbd_pipe_handle pipe = xfer->pipe; 2362 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2363 2364 if (sc->sc_bus.dying) 2365 return (USBD_IOERROR); 2366 2367 sc->sc_intrxfer = xfer; 2368 2369 return (USBD_IN_PROGRESS); 2370 } 2371 2372 /* Abort a root interrupt request. */ 2373 void 2374 ehci_root_intr_abort(usbd_xfer_handle xfer) 2375 { 2376 int s; 2377 2378 if (xfer->pipe->intrxfer == xfer) { 2379 DPRINTF(("ehci_root_intr_abort: remove\n")); 2380 xfer->pipe->intrxfer = NULL; 2381 } 2382 xfer->status = USBD_CANCELLED; 2383 s = splusb(); 2384 usb_transfer_complete(xfer); 2385 splx(s); 2386 } 2387 2388 /* Close the root pipe. */ 2389 void 2390 ehci_root_intr_close(usbd_pipe_handle pipe) 2391 { 2392 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2393 2394 DPRINTF(("ehci_root_intr_close\n")); 2395 2396 sc->sc_intrxfer = NULL; 2397 } 2398 2399 void 2400 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2401 { 2402 } 2403 2404 /************************/ 2405 2406 ehci_soft_qh_t * 2407 ehci_alloc_sqh(ehci_softc_t *sc) 2408 { 2409 ehci_soft_qh_t *sqh; 2410 usbd_status err; 2411 int i, offs; 2412 usb_dma_t dma; 2413 2414 if (sc->sc_freeqhs == NULL) { 2415 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2416 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2417 EHCI_PAGE_SIZE, &dma); 2418 #ifdef EHCI_DEBUG 2419 if (err) 2420 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2421 #endif 2422 if (err) 2423 return (NULL); 2424 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2425 offs = i * EHCI_SQH_SIZE; 2426 sqh = KERNADDR(&dma, offs); 2427 sqh->physaddr = DMAADDR(&dma, offs); 2428 sqh->dma = dma; 2429 sqh->offs = offs; 2430 sqh->next = sc->sc_freeqhs; 2431 sc->sc_freeqhs = sqh; 2432 } 2433 } 2434 sqh = sc->sc_freeqhs; 2435 sc->sc_freeqhs = sqh->next; 2436 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2437 sqh->next = NULL; 2438 sqh->prev = NULL; 2439 return (sqh); 2440 } 2441 2442 void 2443 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2444 { 2445 sqh->next = sc->sc_freeqhs; 2446 sc->sc_freeqhs = sqh; 2447 } 2448 2449 ehci_soft_qtd_t * 2450 ehci_alloc_sqtd(ehci_softc_t *sc) 2451 { 2452 ehci_soft_qtd_t *sqtd; 2453 usbd_status err; 2454 int i, offs; 2455 usb_dma_t dma; 2456 int s; 2457 2458 if (sc->sc_freeqtds == NULL) { 2459 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2460 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2461 EHCI_PAGE_SIZE, &dma); 2462 #ifdef EHCI_DEBUG 2463 if (err) 2464 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2465 #endif 2466 if (err) 2467 return (NULL); 2468 s = splusb(); 2469 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2470 offs = i * EHCI_SQTD_SIZE; 2471 sqtd = KERNADDR(&dma, offs); 2472 sqtd->physaddr = DMAADDR(&dma, offs); 2473 sqtd->dma = dma; 2474 sqtd->offs = offs; 2475 sqtd->nextqtd = sc->sc_freeqtds; 2476 sc->sc_freeqtds = sqtd; 2477 } 2478 splx(s); 2479 } 2480 2481 s = splusb(); 2482 sqtd = sc->sc_freeqtds; 2483 sc->sc_freeqtds = sqtd->nextqtd; 2484 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2485 sqtd->nextqtd = NULL; 2486 sqtd->xfer = NULL; 2487 splx(s); 2488 2489 return (sqtd); 2490 } 2491 2492 void 2493 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2494 { 2495 int s; 2496 2497 s = splusb(); 2498 sqtd->nextqtd = sc->sc_freeqtds; 2499 sc->sc_freeqtds = sqtd; 2500 splx(s); 2501 } 2502 2503 usbd_status 2504 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, u_int alen, 2505 int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2506 { 2507 ehci_soft_qtd_t *next, *cur; 2508 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2509 u_int32_t qtdstatus; 2510 u_int len, curlen; 2511 int mps, i, iscontrol, forceshort; 2512 usb_dma_t *dma = &xfer->dmabuf; 2513 2514 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2515 2516 len = alen; 2517 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2518 UE_CONTROL; 2519 2520 dataphys = DMAADDR(dma, 0); 2521 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2522 qtdstatus = EHCI_QTD_ACTIVE | 2523 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2524 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */ 2525 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2526 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2527 len % mps == 0; 2528 /* 2529 * The control transfer data stage always starts with a toggle of 1. 2530 * For other transfers we let the hardware track the toggle state. 2531 */ 2532 if (iscontrol) 2533 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2534 2535 cur = ehci_alloc_sqtd(sc); 2536 *sp = cur; 2537 if (cur == NULL) 2538 goto nomem; 2539 2540 usb_syncmem(dma, 0, alen, 2541 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2542 for (;;) { 2543 dataphyspage = EHCI_PAGE(dataphys); 2544 /* The EHCI hardware can handle at most 5 pages. */ 2545 if (dataphyslastpage - dataphyspage < 2546 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2547 /* we can handle it in this QTD */ 2548 curlen = len; 2549 } else { 2550 /* must use multiple TDs, fill as much as possible. */ 2551 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2552 EHCI_PAGE_OFFSET(dataphys); 2553 #ifdef DIAGNOSTIC 2554 if (curlen > len) { 2555 printf("ehci_alloc_sqtd_chain: curlen=%u " 2556 "len=%u offs=0x%x\n", curlen, len, 2557 EHCI_PAGE_OFFSET(dataphys)); 2558 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2559 dataphyslastpage, dataphyspage, dataphys); 2560 curlen = len; 2561 } 2562 #endif 2563 /* the length must be a multiple of the max size */ 2564 curlen -= curlen % mps; 2565 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2566 "curlen=%u\n", curlen)); 2567 #ifdef DIAGNOSTIC 2568 if (curlen == 0) 2569 panic("ehci_alloc_std: curlen == 0"); 2570 #endif 2571 } 2572 2573 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2574 "dataphyslastpage=0x%08x len=%u curlen=%u\n", 2575 dataphys, dataphyslastpage, len, curlen)); 2576 len -= curlen; 2577 2578 /* 2579 * Allocate another transfer if there's more data left, 2580 * or if force last short transfer flag is set and we're 2581 * allocating a multiple of the max packet size. 2582 */ 2583 if (len != 0 || forceshort) { 2584 next = ehci_alloc_sqtd(sc); 2585 if (next == NULL) 2586 goto nomem; 2587 nextphys = htole32(next->physaddr); 2588 } else { 2589 next = NULL; 2590 nextphys = EHCI_NULL; 2591 } 2592 2593 for (i = 0; i * EHCI_PAGE_SIZE < 2594 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2595 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2596 if (i != 0) /* use offset only in first buffer */ 2597 a = EHCI_PAGE(a); 2598 #ifdef DIAGNOSTIC 2599 if (i >= EHCI_QTD_NBUFFERS) { 2600 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2601 goto nomem; 2602 } 2603 #endif 2604 cur->qtd.qtd_buffer[i] = htole32(a); 2605 cur->qtd.qtd_buffer_hi[i] = 0; 2606 } 2607 cur->nextqtd = next; 2608 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2609 cur->qtd.qtd_status = htole32(qtdstatus | 2610 EHCI_QTD_SET_BYTES(curlen)); 2611 cur->xfer = xfer; 2612 cur->len = curlen; 2613 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2614 dataphys, dataphys + curlen)); 2615 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%u\n", curlen)); 2616 if (iscontrol) { 2617 /* 2618 * adjust the toggle based on the number of packets 2619 * in this qtd 2620 */ 2621 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2622 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2623 } 2624 if (len == 0) { 2625 if (! forceshort) 2626 break; 2627 forceshort = 0; 2628 } 2629 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2630 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2631 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2632 dataphys += curlen; 2633 cur = next; 2634 } 2635 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2636 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2637 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2638 *ep = cur; 2639 2640 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2641 *sp, *ep)); 2642 2643 return (USBD_NORMAL_COMPLETION); 2644 2645 nomem: 2646 /* XXX free chain */ 2647 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2648 return (USBD_NOMEM); 2649 } 2650 2651 void 2652 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2653 ehci_soft_qtd_t *sqtdend) 2654 { 2655 ehci_soft_qtd_t *p; 2656 int i; 2657 2658 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2659 sqtd, sqtdend)); 2660 2661 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2662 p = sqtd->nextqtd; 2663 ehci_free_sqtd(sc, sqtd); 2664 } 2665 } 2666 2667 ehci_soft_itd_t * 2668 ehci_alloc_itd(ehci_softc_t *sc) 2669 { 2670 struct ehci_soft_itd *itd, *freeitd; 2671 usbd_status err; 2672 int i, s, offs, frindex, previndex; 2673 usb_dma_t dma; 2674 2675 s = splusb(); 2676 2677 /* Find an itd that wasn't freed this frame or last frame. This can 2678 * discard itds that were freed before frindex wrapped around 2679 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2680 * interrupt and fiddling with list when that happens */ 2681 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2682 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2683 2684 freeitd = NULL; 2685 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2686 if (itd == NULL) 2687 break; 2688 if (itd->slot != frindex && itd->slot != previndex) { 2689 freeitd = itd; 2690 break; 2691 } 2692 } 2693 2694 if (freeitd == NULL) { 2695 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2696 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2697 EHCI_PAGE_SIZE, &dma); 2698 2699 if (err) { 2700 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2701 return (NULL); 2702 } 2703 2704 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2705 offs = i * EHCI_ITD_SIZE; 2706 itd = KERNADDR(&dma, offs); 2707 itd->physaddr = DMAADDR(&dma, offs); 2708 itd->dma = dma; 2709 itd->offs = offs; 2710 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2711 } 2712 freeitd = LIST_FIRST(&sc->sc_freeitds); 2713 } 2714 2715 itd = freeitd; 2716 LIST_REMOVE(itd, u.free_list); 2717 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2718 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2719 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2720 BUS_DMASYNC_PREREAD); 2721 2722 itd->u.frame_list.next = NULL; 2723 itd->u.frame_list.prev = NULL; 2724 itd->xfer_next = NULL; 2725 itd->slot = 0; 2726 splx(s); 2727 2728 return (itd); 2729 } 2730 2731 void 2732 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2733 { 2734 int s; 2735 2736 s = splusb(); 2737 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2738 splx(s); 2739 } 2740 2741 /****************/ 2742 2743 /* 2744 * Close a reqular pipe. 2745 * Assumes that there are no pending transactions. 2746 */ 2747 void 2748 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2749 { 2750 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2751 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2752 ehci_soft_qh_t *sqh = epipe->sqh; 2753 int s; 2754 2755 s = splusb(); 2756 ehci_rem_qh(sc, sqh, head); 2757 splx(s); 2758 pipe->endpoint->savedtoggle = 2759 EHCI_QTD_GET_TOGGLE(letoh32(sqh->qh.qh_qtd.qtd_status)); 2760 ehci_free_sqh(sc, epipe->sqh); 2761 } 2762 2763 /* 2764 * Abort a device request. 2765 * If this routine is called at splusb() it guarantees that the request 2766 * will be removed from the hardware scheduling and that the callback 2767 * for it will be called with USBD_CANCELLED status. 2768 * It's impossible to guarantee that the requested transfer will not 2769 * have happened since the hardware runs concurrently. 2770 * If the transaction has already happened we rely on the ordinary 2771 * interrupt processing to process it. 2772 */ 2773 void 2774 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2775 { 2776 #define exfer EXFER(xfer) 2777 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2778 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2779 ehci_soft_qh_t *sqh = epipe->sqh; 2780 ehci_soft_qtd_t *sqtd, *snext, **psqtd; 2781 ehci_physaddr_t cur, us, next; 2782 int s; 2783 int hit; 2784 ehci_soft_qh_t *psqh; 2785 2786 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2787 2788 if (sc->sc_bus.dying) { 2789 /* If we're dying, just do the software part. */ 2790 s = splusb(); 2791 xfer->status = status; /* make software ignore it */ 2792 timeout_del(&xfer->timeout_handle); 2793 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2794 usb_transfer_complete(xfer); 2795 splx(s); 2796 return; 2797 } 2798 2799 if (xfer->device->bus->intr_context) 2800 panic("ehci_abort_xfer: not in process context"); 2801 2802 /* 2803 * If an abort is already in progress then just wait for it to 2804 * complete and return. 2805 */ 2806 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2807 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2808 /* No need to wait if we're aborting from a timeout. */ 2809 if (status == USBD_TIMEOUT) 2810 return; 2811 /* Override the status which might be USBD_TIMEOUT. */ 2812 xfer->status = status; 2813 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2814 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2815 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 2816 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciaw", 0); 2817 return; 2818 } 2819 2820 /* 2821 * Step 1: Make interrupt routine and timeouts ignore xfer. 2822 */ 2823 s = splusb(); 2824 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2825 xfer->status = status; /* make software ignore it */ 2826 timeout_del(&xfer->timeout_handle); 2827 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2828 splx(s); 2829 2830 /* 2831 * Step 2: Wait until we know hardware has finished any possible 2832 * use of the xfer. We do this by removing the entire 2833 * queue from the async schedule and waiting for the doorbell. 2834 * Nothing else should be touching the queue now. 2835 */ 2836 psqh = sqh->prev; 2837 ehci_rem_qh(sc, sqh, psqh); 2838 2839 /* 2840 * Step 3: Deactivate all of the qTDs that we will be removing, 2841 * otherwise the queue head may go active again. The EHCI spec 2842 * suggests we should perform the deactivation before removing the 2843 * queue head from the schedule, however the VT6202 (at least) only 2844 * behaves correctly when we deactivate them afterwards. 2845 */ 2846 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2847 usb_syncmem(&sqtd->dma, 2848 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2849 sizeof(sqtd->qtd.qtd_status), 2850 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2851 sqtd->qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2852 usb_syncmem(&sqtd->dma, 2853 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2854 sizeof(sqtd->qtd.qtd_status), 2855 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2856 if (sqtd == exfer->sqtdend) 2857 break; 2858 } 2859 ehci_sync_hc(sc); 2860 2861 /* 2862 * Step 4: make sure the soft interrupt routine 2863 * has run. This should remove any completed items off the queue. 2864 * The hardware has no reference to completed items (TDs). 2865 * It's safe to remove them at any time. 2866 * use of the xfer. Also make sure the soft interrupt routine 2867 * has run. 2868 */ 2869 s = splusb(); 2870 sc->sc_softwake = 1; 2871 usb_schedsoftintr(&sc->sc_bus); 2872 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2873 2874 /* 2875 * Step 5: Remove any vestiges of the xfer from the hardware. 2876 * The complication here is that the hardware may have executed 2877 * into or even beyond the xfer we're trying to abort. 2878 * So as we're scanning the TDs of this xfer we check if 2879 * the hardware points to any of them. 2880 * 2881 * first we need to see if there are any transfers 2882 * on this queue before the xfer we are aborting.. we need 2883 * to update any pointers that point to us to point past 2884 * the aborting xfer. (If there is something past us). 2885 * Hardware and software. 2886 */ 2887 usb_syncmem(&sqh->dma, 2888 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2889 sizeof(sqh->qh.qh_curqtd), 2890 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2891 cur = EHCI_LINK_ADDR(letoh32(sqh->qh.qh_curqtd)); 2892 hit = 0; 2893 2894 /* If they initially point here. */ 2895 us = exfer->sqtdstart->physaddr; 2896 2897 /* We will change them to point here */ 2898 snext = exfer->sqtdend->nextqtd; 2899 next = snext ? snext->physaddr : EHCI_NULL; 2900 2901 /* 2902 * Now loop through any qTDs before us and keep track of the pointer 2903 * that points to us for the end. 2904 */ 2905 psqtd = &sqh->sqtd; 2906 sqtd = sqh->sqtd; 2907 while (sqtd && sqtd != exfer->sqtdstart) { 2908 hit |= (cur == sqtd->physaddr); 2909 if (EHCI_LINK_ADDR(letoh32(sqtd->qtd.qtd_next)) == us) 2910 sqtd->qtd.qtd_next = next; 2911 if (EHCI_LINK_ADDR(letoh32(sqtd->qtd.qtd_altnext)) == us) 2912 sqtd->qtd.qtd_altnext = next; 2913 psqtd = &sqtd->nextqtd; 2914 sqtd = sqtd->nextqtd; 2915 } 2916 /* make the software pointer bypass us too */ 2917 *psqtd = exfer->sqtdend->nextqtd; 2918 2919 /* 2920 * If we already saw the active one then we are pretty much done. 2921 * We've done all the relinking we need to do. 2922 */ 2923 if (!hit) { 2924 2925 /* 2926 * Now reinitialise the QH to point to the next qTD 2927 * (if there is one). We only need to do this if 2928 * it was previously pointing to us. 2929 * XXX Not quite sure what to do about the data toggle. 2930 */ 2931 sqtd = exfer->sqtdstart; 2932 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2933 if (cur == sqtd->physaddr) { 2934 hit++; 2935 } 2936 if (sqtd == exfer->sqtdend) 2937 break; 2938 } 2939 /* 2940 * Only need to alter the QH if it was pointing at a qTD 2941 * that we are removing. 2942 */ 2943 if (hit) { 2944 if (snext) { 2945 ehci_set_qh_qtd(sqh, snext); 2946 } else { 2947 2948 sqh->qh.qh_curqtd = 0; /* unlink qTDs */ 2949 sqh->qh.qh_qtd.qtd_status = 0; 2950 sqh->qh.qh_qtd.qtd_next = 2951 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2952 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2953 } 2954 } 2955 } 2956 ehci_add_qh(sqh, psqh); 2957 2958 /* 2959 * Step 6: Execute callback. 2960 */ 2961 #ifdef DIAGNOSTIC 2962 exfer->isdone = 1; 2963 #endif 2964 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2965 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 2966 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 2967 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 2968 wakeup(&exfer->ehci_xfer_flags); 2969 } 2970 usb_transfer_complete(xfer); 2971 2972 splx(s); 2973 #undef exfer 2974 } 2975 2976 void 2977 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 2978 { 2979 ehci_isoc_trans_t trans_status; 2980 struct ehci_pipe *epipe; 2981 struct ehci_xfer *exfer; 2982 ehci_softc_t *sc; 2983 struct ehci_soft_itd *itd; 2984 int s, i, wake; 2985 2986 epipe = (struct ehci_pipe *) xfer->pipe; 2987 exfer = EXFER(xfer); 2988 sc = (ehci_softc_t *)epipe->pipe.device->bus; 2989 2990 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 2991 2992 if (sc->sc_bus.dying) { 2993 s = splusb(); 2994 xfer->status = status; 2995 timeout_del(&xfer->timeout_handle); 2996 usb_transfer_complete(xfer); 2997 splx(s); 2998 return; 2999 } 3000 3001 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 3002 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3003 3004 #ifdef DIAGNOSTIC 3005 if (status == USBD_TIMEOUT) 3006 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3007 #endif 3008 3009 xfer->status = status; 3010 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3011 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 3012 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 3013 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciiaw", 0); 3014 return; 3015 } 3016 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 3017 3018 xfer->status = status; 3019 timeout_del(&xfer->timeout_handle); 3020 3021 s = splusb(); 3022 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3023 for (i = 0; i < 8; i++) { 3024 trans_status = letoh32(itd->itd.itd_ctl[i]); 3025 trans_status &= ~EHCI_ITD_ACTIVE; 3026 itd->itd.itd_ctl[i] = htole32(trans_status); 3027 } 3028 } 3029 splx(s); 3030 3031 s = splusb(); 3032 sc->sc_softwake = 1; 3033 usb_schedsoftintr(&sc->sc_bus); 3034 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3035 splx(s); 3036 3037 #ifdef DIAGNOSTIC 3038 exfer->isdone = 1; 3039 #endif 3040 wake = exfer->ehci_xfer_flags & EHCI_XFER_ABORTING; 3041 exfer->ehci_xfer_flags &= ~(EHCI_XFER_ABORTING | EHCI_XFER_ABORTWAIT); 3042 usb_transfer_complete(xfer); 3043 if (wake) 3044 wakeup(&exfer->ehci_xfer_flags); 3045 3046 return; 3047 } 3048 3049 void 3050 ehci_timeout(void *addr) 3051 { 3052 struct ehci_xfer *exfer = addr; 3053 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3054 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 3055 3056 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3057 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 3058 if (ehcidebug > 1) 3059 usbd_dump_pipe(exfer->xfer.pipe); 3060 #endif 3061 3062 if (sc->sc_bus.dying) { 3063 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3064 return; 3065 } 3066 3067 /* Execute the abort in a process context. */ 3068 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task); 3069 } 3070 3071 void 3072 ehci_timeout_task(void *addr) 3073 { 3074 usbd_xfer_handle xfer = addr; 3075 int s; 3076 3077 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3078 3079 s = splusb(); 3080 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3081 splx(s); 3082 } 3083 3084 /* 3085 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3086 * qTD status, or miss signalling occasionally under heavy load. If the host 3087 * machine is too fast, we we can miss transaction completion - when we scan 3088 * the active list the transaction still seems to be active. This generally 3089 * exhibits itself as a umass stall that never recovers. 3090 * 3091 * We work around this behaviour by setting up this callback after any softintr 3092 * that completes with transactions still pending, giving us another chance to 3093 * check for completion after the writeback has taken place. 3094 */ 3095 void 3096 ehci_intrlist_timeout(void *arg) 3097 { 3098 ehci_softc_t *sc = arg; 3099 int s; 3100 3101 if (sc->sc_bus.dying) 3102 return; 3103 3104 s = splusb(); 3105 DPRINTFN(1, ("ehci_intrlist_timeout\n")); 3106 usb_schedsoftintr(&sc->sc_bus); 3107 splx(s); 3108 } 3109 3110 /************************/ 3111 3112 usbd_status 3113 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3114 { 3115 usbd_status err; 3116 3117 /* Insert last in queue. */ 3118 err = usb_insert_transfer(xfer); 3119 if (err) 3120 return (err); 3121 3122 /* Pipe isn't running, start first */ 3123 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3124 } 3125 3126 usbd_status 3127 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3128 { 3129 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3130 usbd_status err; 3131 3132 if (sc->sc_bus.dying) 3133 return (USBD_IOERROR); 3134 3135 #ifdef DIAGNOSTIC 3136 if (!(xfer->rqflags & URQ_REQUEST)) { 3137 /* XXX panic */ 3138 printf("ehci_device_ctrl_transfer: not a request\n"); 3139 return (USBD_INVAL); 3140 } 3141 #endif 3142 3143 err = ehci_device_request(xfer); 3144 if (err) 3145 return (err); 3146 3147 if (sc->sc_bus.use_polling) 3148 ehci_waitintr(sc, xfer); 3149 return (USBD_IN_PROGRESS); 3150 } 3151 3152 void 3153 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3154 { 3155 struct ehci_xfer *ex = EXFER(xfer); 3156 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3157 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 3158 3159 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3160 3161 #ifdef DIAGNOSTIC 3162 if (!(xfer->rqflags & URQ_REQUEST)) { 3163 panic("ehci_ctrl_done: not a request"); 3164 } 3165 #endif 3166 3167 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3168 ehci_del_intr_list(sc, ex); /* remove from active list */ 3169 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3170 } 3171 3172 DPRINTFN(5, ("ehci_ctrl_done: length=%u\n", xfer->actlen)); 3173 } 3174 3175 /* Abort a device control request. */ 3176 void 3177 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3178 { 3179 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3180 ehci_abort_xfer(xfer, USBD_CANCELLED); 3181 } 3182 3183 /* Close a device control pipe. */ 3184 void 3185 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3186 { 3187 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3188 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3189 3190 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3191 ehci_close_pipe(pipe, sc->sc_async_head); 3192 } 3193 3194 usbd_status 3195 ehci_device_request(usbd_xfer_handle xfer) 3196 { 3197 #define exfer EXFER(xfer) 3198 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3199 usb_device_request_t *req = &xfer->request; 3200 usbd_device_handle dev = epipe->pipe.device; 3201 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3202 int addr = dev->address; 3203 ehci_soft_qtd_t *setup, *stat, *next; 3204 ehci_soft_qh_t *sqh; 3205 int isread; 3206 u_int len; 3207 usbd_status err; 3208 int s; 3209 3210 isread = req->bmRequestType & UT_READ; 3211 len = UGETW(req->wLength); 3212 3213 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3214 "wValue=0x%04x, wIndex=0x%04x len=%u, addr=%d, endpt=%d\n", 3215 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3216 UGETW(req->wIndex), len, addr, 3217 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3218 3219 setup = ehci_alloc_sqtd(sc); 3220 if (setup == NULL) { 3221 err = USBD_NOMEM; 3222 goto bad1; 3223 } 3224 stat = ehci_alloc_sqtd(sc); 3225 if (stat == NULL) { 3226 err = USBD_NOMEM; 3227 goto bad2; 3228 } 3229 3230 sqh = epipe->sqh; 3231 epipe->u.ctl.length = len; 3232 3233 /* Update device address and length since they may have changed 3234 during the setup of the control pipe in usbd_new_device(). */ 3235 /* XXX This only needs to be done once, but it's too early in open. */ 3236 /* XXXX Should not touch ED here! */ 3237 sqh->qh.qh_endp = 3238 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3239 htole32( 3240 EHCI_QH_SET_ADDR(addr) | 3241 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3242 ); 3243 3244 /* Set up data transaction */ 3245 if (len != 0) { 3246 ehci_soft_qtd_t *end; 3247 3248 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3249 &next, &end); 3250 if (err) 3251 goto bad3; 3252 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3253 end->nextqtd = stat; 3254 end->qtd.qtd_next = 3255 end->qtd.qtd_altnext = htole32(stat->physaddr); 3256 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3257 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3258 } else { 3259 next = stat; 3260 } 3261 3262 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3263 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3264 3265 /* Clear toggle */ 3266 setup->qtd.qtd_status = htole32( 3267 EHCI_QTD_ACTIVE | 3268 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3269 EHCI_QTD_SET_CERR(3) | 3270 EHCI_QTD_SET_TOGGLE(0) | 3271 EHCI_QTD_SET_BYTES(sizeof(*req))); 3272 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3273 setup->qtd.qtd_buffer_hi[0] = 0; 3274 setup->nextqtd = next; 3275 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3276 setup->xfer = xfer; 3277 setup->len = sizeof(*req); 3278 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3279 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3280 3281 stat->qtd.qtd_status = htole32( 3282 EHCI_QTD_ACTIVE | 3283 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3284 EHCI_QTD_SET_CERR(3) | 3285 EHCI_QTD_SET_TOGGLE(1) | 3286 EHCI_QTD_IOC); 3287 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3288 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3289 stat->nextqtd = NULL; 3290 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3291 stat->xfer = xfer; 3292 stat->len = 0; 3293 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3294 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3295 3296 #ifdef EHCI_DEBUG 3297 if (ehcidebug > 5) { 3298 DPRINTF(("ehci_device_request:\n")); 3299 ehci_dump_sqh(sqh); 3300 ehci_dump_sqtds(setup); 3301 } 3302 #endif 3303 3304 exfer->sqtdstart = setup; 3305 exfer->sqtdend = stat; 3306 #ifdef DIAGNOSTIC 3307 if (!exfer->isdone) { 3308 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3309 } 3310 exfer->isdone = 0; 3311 #endif 3312 3313 /* Insert qTD in QH list. */ 3314 s = splusb(); 3315 ehci_set_qh_qtd(sqh, setup); 3316 if (xfer->timeout && !sc->sc_bus.use_polling) { 3317 timeout_del(&xfer->timeout_handle); 3318 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3319 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3320 } 3321 ehci_add_intr_list(sc, exfer); 3322 xfer->status = USBD_IN_PROGRESS; 3323 splx(s); 3324 3325 #ifdef EHCI_DEBUG 3326 if (ehcidebug > 10) { 3327 DPRINTF(("ehci_device_request: status=%x\n", 3328 EOREAD4(sc, EHCI_USBSTS))); 3329 delay(10000); 3330 ehci_dump_regs(sc); 3331 ehci_dump_sqh(sc->sc_async_head); 3332 ehci_dump_sqh(sqh); 3333 ehci_dump_sqtds(setup); 3334 } 3335 #endif 3336 3337 return (USBD_NORMAL_COMPLETION); 3338 3339 bad3: 3340 ehci_free_sqtd(sc, stat); 3341 bad2: 3342 ehci_free_sqtd(sc, setup); 3343 bad1: 3344 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3345 xfer->status = err; 3346 usb_transfer_complete(xfer); 3347 return (err); 3348 #undef exfer 3349 } 3350 3351 /************************/ 3352 3353 usbd_status 3354 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3355 { 3356 usbd_status err; 3357 3358 /* Insert last in queue. */ 3359 err = usb_insert_transfer(xfer); 3360 if (err) 3361 return (err); 3362 3363 /* Pipe isn't running, start first */ 3364 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3365 } 3366 3367 usbd_status 3368 ehci_device_bulk_start(usbd_xfer_handle xfer) 3369 { 3370 #define exfer EXFER(xfer) 3371 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3372 usbd_device_handle dev = epipe->pipe.device; 3373 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3374 ehci_soft_qtd_t *data, *dataend; 3375 ehci_soft_qh_t *sqh; 3376 usbd_status err; 3377 u_int len; 3378 int isread, endpt; 3379 int s; 3380 3381 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%u flags=%d\n", 3382 xfer, xfer->length, xfer->flags)); 3383 3384 if (sc->sc_bus.dying) 3385 return (USBD_IOERROR); 3386 3387 #ifdef DIAGNOSTIC 3388 if (xfer->rqflags & URQ_REQUEST) 3389 panic("ehci_device_bulk_start: a request"); 3390 #endif 3391 3392 len = xfer->length; 3393 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3394 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3395 sqh = epipe->sqh; 3396 3397 epipe->u.bulk.length = len; 3398 3399 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3400 &dataend); 3401 if (err) { 3402 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n")); 3403 xfer->status = err; 3404 usb_transfer_complete(xfer); 3405 return (err); 3406 } 3407 3408 #ifdef EHCI_DEBUG 3409 if (ehcidebug > 5) { 3410 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3411 ehci_dump_sqh(sqh); 3412 ehci_dump_sqtds(data); 3413 } 3414 #endif 3415 3416 /* Set up interrupt info. */ 3417 exfer->sqtdstart = data; 3418 exfer->sqtdend = dataend; 3419 #ifdef DIAGNOSTIC 3420 if (!exfer->isdone) { 3421 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3422 } 3423 exfer->isdone = 0; 3424 #endif 3425 3426 s = splusb(); 3427 ehci_set_qh_qtd(sqh, data); 3428 if (xfer->timeout && !sc->sc_bus.use_polling) { 3429 timeout_del(&xfer->timeout_handle); 3430 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3431 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3432 } 3433 ehci_add_intr_list(sc, exfer); 3434 xfer->status = USBD_IN_PROGRESS; 3435 splx(s); 3436 3437 #ifdef EHCI_DEBUG 3438 if (ehcidebug > 10) { 3439 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3440 delay(10000); 3441 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3442 ehci_dump_regs(sc); 3443 #if 0 3444 printf("async_head:\n"); 3445 ehci_dump_sqh(sc->sc_async_head); 3446 #endif 3447 printf("sqh:\n"); 3448 ehci_dump_sqh(sqh); 3449 ehci_dump_sqtds(data); 3450 } 3451 #endif 3452 3453 if (sc->sc_bus.use_polling) 3454 ehci_waitintr(sc, xfer); 3455 3456 return (USBD_IN_PROGRESS); 3457 #undef exfer 3458 } 3459 3460 void 3461 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3462 { 3463 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3464 ehci_abort_xfer(xfer, USBD_CANCELLED); 3465 } 3466 3467 /* 3468 * Close a device bulk pipe. 3469 */ 3470 void 3471 ehci_device_bulk_close(usbd_pipe_handle pipe) 3472 { 3473 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3474 3475 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3476 ehci_close_pipe(pipe, sc->sc_async_head); 3477 } 3478 3479 void 3480 ehci_device_bulk_done(usbd_xfer_handle xfer) 3481 { 3482 struct ehci_xfer *ex = EXFER(xfer); 3483 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3484 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3485 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3486 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3487 3488 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3489 xfer, xfer->actlen)); 3490 3491 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3492 ehci_del_intr_list(sc, ex); /* remove from active list */ 3493 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3494 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3495 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3496 } 3497 3498 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3499 } 3500 3501 /************************/ 3502 3503 usbd_status 3504 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3505 { 3506 struct ehci_soft_islot *isp; 3507 int islot, lev; 3508 3509 /* Find a poll rate that is large enough. */ 3510 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3511 if (EHCI_ILEV_IVAL(lev) <= ival) 3512 break; 3513 3514 /* Pick an interrupt slot at the right level. */ 3515 /* XXX could do better than picking at random */ 3516 if (cold) { 3517 /* XXX prevent panics at boot by not using arc4random */ 3518 sc->sc_rand = (sc->sc_rand + 192) % sc->sc_flsize; 3519 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3520 } else 3521 islot = EHCI_IQHIDX(lev, arc4random()); 3522 3523 sqh->islot = islot; 3524 isp = &sc->sc_islots[islot]; 3525 ehci_add_qh(sqh, isp->sqh); 3526 3527 return (USBD_NORMAL_COMPLETION); 3528 } 3529 3530 usbd_status 3531 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3532 { 3533 usbd_status err; 3534 3535 /* Insert last in queue. */ 3536 err = usb_insert_transfer(xfer); 3537 if (err) 3538 return (err); 3539 3540 /* 3541 * Pipe isn't running (otherwise err would be USBD_INPROG), 3542 * so start it first. 3543 */ 3544 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3545 } 3546 3547 usbd_status 3548 ehci_device_intr_start(usbd_xfer_handle xfer) 3549 { 3550 #define exfer EXFER(xfer) 3551 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3552 usbd_device_handle dev = xfer->pipe->device; 3553 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3554 ehci_soft_qtd_t *data, *dataend; 3555 ehci_soft_qh_t *sqh; 3556 usbd_status err; 3557 u_int len; 3558 int isread, endpt; 3559 int s; 3560 3561 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%u flags=%d\n", 3562 xfer, xfer->length, xfer->flags)); 3563 3564 if (sc->sc_bus.dying) 3565 return (USBD_IOERROR); 3566 3567 #ifdef DIAGNOSTIC 3568 if (xfer->rqflags & URQ_REQUEST) 3569 panic("ehci_device_intr_start: a request"); 3570 #endif 3571 3572 len = xfer->length; 3573 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3574 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3575 sqh = epipe->sqh; 3576 3577 epipe->u.intr.length = len; 3578 3579 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3580 &dataend); 3581 if (err) { 3582 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3583 xfer->status = err; 3584 usb_transfer_complete(xfer); 3585 return (err); 3586 } 3587 3588 #ifdef EHCI_DEBUG 3589 if (ehcidebug > 5) { 3590 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3591 ehci_dump_sqh(sqh); 3592 ehci_dump_sqtds(data); 3593 } 3594 #endif 3595 3596 /* Set up interrupt info. */ 3597 exfer->sqtdstart = data; 3598 exfer->sqtdend = dataend; 3599 #ifdef DIAGNOSTIC 3600 if (!exfer->isdone) 3601 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3602 exfer->isdone = 0; 3603 #endif 3604 3605 s = splusb(); 3606 ehci_set_qh_qtd(sqh, data); 3607 if (xfer->timeout && !sc->sc_bus.use_polling) { 3608 timeout_del(&xfer->timeout_handle); 3609 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3610 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3611 } 3612 ehci_add_intr_list(sc, exfer); 3613 xfer->status = USBD_IN_PROGRESS; 3614 splx(s); 3615 3616 #ifdef EHCI_DEBUG 3617 if (ehcidebug > 10) { 3618 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3619 delay(10000); 3620 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3621 ehci_dump_regs(sc); 3622 printf("sqh:\n"); 3623 ehci_dump_sqh(sqh); 3624 ehci_dump_sqtds(data); 3625 } 3626 #endif 3627 3628 if (sc->sc_bus.use_polling) 3629 ehci_waitintr(sc, xfer); 3630 3631 return (USBD_IN_PROGRESS); 3632 #undef exfer 3633 } 3634 3635 void 3636 ehci_device_intr_abort(usbd_xfer_handle xfer) 3637 { 3638 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3639 if (xfer->pipe->intrxfer == xfer) { 3640 DPRINTFN(1, ("ehci_device_intr_abort: remove\n")); 3641 xfer->pipe->intrxfer = NULL; 3642 } 3643 /* 3644 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3645 * async doorbell. That's dependant on the async list, wheras 3646 * intr xfers are periodic, should not use this? 3647 */ 3648 ehci_abort_xfer(xfer, USBD_CANCELLED); 3649 } 3650 3651 void 3652 ehci_device_intr_close(usbd_pipe_handle pipe) 3653 { 3654 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3655 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3656 struct ehci_soft_islot *isp; 3657 3658 isp = &sc->sc_islots[epipe->sqh->islot]; 3659 ehci_close_pipe(pipe, isp->sqh); 3660 } 3661 3662 void 3663 ehci_device_intr_done(usbd_xfer_handle xfer) 3664 { 3665 #define exfer EXFER(xfer) 3666 struct ehci_xfer *ex = EXFER(xfer); 3667 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3668 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3669 ehci_soft_qtd_t *data, *dataend; 3670 ehci_soft_qh_t *sqh; 3671 usbd_status err; 3672 u_int len; 3673 int isread, endpt, s; 3674 3675 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3676 xfer, xfer->actlen)); 3677 3678 if (xfer->pipe->repeat) { 3679 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3680 3681 len = epipe->u.intr.length; 3682 xfer->length = len; 3683 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3684 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3685 usb_syncmem(&xfer->dmabuf, 0, len, 3686 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3687 sqh = epipe->sqh; 3688 3689 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3690 &data, &dataend); 3691 if (err) { 3692 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3693 xfer->status = err; 3694 return; 3695 } 3696 3697 /* Set up interrupt info. */ 3698 exfer->sqtdstart = data; 3699 exfer->sqtdend = dataend; 3700 #ifdef DIAGNOSTIC 3701 if (!exfer->isdone) { 3702 printf("ehci_device_intr_done: not done, ex=%p\n", 3703 exfer); 3704 } 3705 exfer->isdone = 0; 3706 #endif 3707 3708 s = splusb(); 3709 ehci_set_qh_qtd(sqh, data); 3710 if (xfer->timeout && !sc->sc_bus.use_polling) { 3711 timeout_del(&xfer->timeout_handle); 3712 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3713 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3714 } 3715 splx(s); 3716 3717 xfer->status = USBD_IN_PROGRESS; 3718 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3719 ehci_del_intr_list(sc, ex); /* remove from active list */ 3720 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3721 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3722 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3723 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3724 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3725 } 3726 #undef exfer 3727 } 3728 3729 /************************/ 3730 3731 usbd_status 3732 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3733 { 3734 usbd_status err; 3735 3736 err = usb_insert_transfer(xfer); 3737 if (err && err != USBD_IN_PROGRESS) 3738 return (err); 3739 3740 return (ehci_device_isoc_start(xfer)); 3741 } 3742 3743 usbd_status 3744 ehci_device_isoc_start(usbd_xfer_handle xfer) 3745 { 3746 struct ehci_pipe *epipe; 3747 ehci_softc_t *sc; 3748 struct ehci_xfer *exfer; 3749 ehci_soft_itd_t *itd, *prev, *start, *stop; 3750 usb_dma_t *dma_buf; 3751 int i, j, k, frames, uframes, ufrperframe; 3752 int s, trans_count, offs, total_length; 3753 int frindex; 3754 3755 start = NULL; 3756 prev = NULL; 3757 itd = NULL; 3758 trans_count = 0; 3759 total_length = 0; 3760 exfer = (struct ehci_xfer *) xfer; 3761 sc = (ehci_softc_t *)xfer->pipe->device->bus; 3762 epipe = (struct ehci_pipe *)xfer->pipe; 3763 3764 /* 3765 * To allow continuous transfers, above we start all transfers 3766 * immediately. However, we're still going to get usbd_start_next call 3767 * this when another xfer completes. So, check if this is already 3768 * in progress or not 3769 */ 3770 3771 if (exfer->itdstart != NULL) 3772 return (USBD_IN_PROGRESS); 3773 3774 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %u flags %d\n", 3775 xfer, xfer->length, xfer->flags)); 3776 3777 if (sc->sc_bus.dying) 3778 return (USBD_IOERROR); 3779 3780 /* 3781 * To avoid complication, don't allow a request right now that'll span 3782 * the entire frame table. To within 4 frames, to allow some leeway 3783 * on either side of where the hc currently is. 3784 */ 3785 if ((1 << (epipe->pipe.endpoint->edesc->bInterval - 1)) * 3786 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3787 printf("ehci: isoc descriptor requested that spans the entire " 3788 "frametable, too many frames\n"); 3789 return (USBD_INVAL); 3790 } 3791 3792 #ifdef DIAGNOSTIC 3793 if (xfer->rqflags & URQ_REQUEST) 3794 panic("ehci_device_isoc_start: request"); 3795 3796 if (!exfer->isdone) 3797 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3798 exfer->isdone = 0; 3799 #endif 3800 3801 /* 3802 * Step 1: Allocate and initialize itds, how many do we need? 3803 * One per transfer if interval >= 8 microframes, fewer if we use 3804 * multiple microframes per frame. 3805 */ 3806 3807 i = epipe->pipe.endpoint->edesc->bInterval; 3808 if (i > 16 || i == 0) { 3809 /* Spec page 271 says intervals > 16 are invalid */ 3810 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3811 return (USBD_INVAL); 3812 } 3813 3814 switch (i) { 3815 case 1: 3816 ufrperframe = 8; 3817 break; 3818 case 2: 3819 ufrperframe = 4; 3820 break; 3821 case 3: 3822 ufrperframe = 2; 3823 break; 3824 default: 3825 ufrperframe = 1; 3826 break; 3827 } 3828 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3829 uframes = 8 / ufrperframe; 3830 3831 if (frames == 0) { 3832 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3833 return (USBD_INVAL); 3834 } 3835 3836 dma_buf = &xfer->dmabuf; 3837 offs = 0; 3838 3839 for (i = 0; i < frames; i++) { 3840 int froffs = offs; 3841 itd = ehci_alloc_itd(sc); 3842 3843 if (prev != NULL) { 3844 prev->itd.itd_next = 3845 htole32(itd->physaddr | EHCI_LINK_ITD); 3846 prev->xfer_next = itd; 3847 } else { 3848 start = itd; 3849 } 3850 3851 /* 3852 * Step 1.5, initialize uframes 3853 */ 3854 for (j = 0; j < 8; j += uframes) { 3855 /* Calculate which page in the list this starts in */ 3856 int addr = DMAADDR(dma_buf, froffs); 3857 addr = EHCI_PAGE_OFFSET(addr); 3858 addr += (offs - froffs); 3859 addr = EHCI_PAGE(addr); 3860 addr /= EHCI_PAGE_SIZE; 3861 3862 /* This gets the initial offset into the first page, 3863 * looks how far further along the current uframe 3864 * offset is. Works out how many pages that is. 3865 */ 3866 3867 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3868 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3869 EHCI_ITD_SET_PG(addr) | 3870 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf, 3871 offs)))); 3872 3873 total_length += xfer->frlengths[trans_count]; 3874 offs += xfer->frlengths[trans_count]; 3875 trans_count++; 3876 3877 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3878 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3879 break; 3880 } 3881 } 3882 3883 /* Step 1.75, set buffer pointers. To simplify matters, all 3884 * pointers are filled out for the next 7 hardware pages in 3885 * the dma block, so no need to worry what pages to cover 3886 * and what to not. 3887 */ 3888 3889 for (j=0; j < 7; j++) { 3890 /* 3891 * Don't try to lookup a page that's past the end 3892 * of buffer 3893 */ 3894 int page_offs = EHCI_PAGE(froffs + 3895 (EHCI_PAGE_SIZE * j)); 3896 3897 if (page_offs >= dma_buf->block->size) 3898 break; 3899 3900 long long page = DMAADDR(dma_buf, page_offs); 3901 page = EHCI_PAGE(page); 3902 itd->itd.itd_bufr[j] = 3903 htole32(EHCI_ITD_SET_BPTR(page)); 3904 itd->itd.itd_bufr_hi[j] = 3905 htole32(page >> 32); 3906 } 3907 3908 /* 3909 * Other special values 3910 */ 3911 3912 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3913 itd->itd.itd_bufr[0] |= 3914 htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3915 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3916 3917 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3918 ? 1 : 0; 3919 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3920 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3921 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3922 3923 /* FIXME: handle invalid trans */ 3924 itd->itd.itd_bufr[2] |= 3925 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3926 prev = itd; 3927 } /* End of frame */ 3928 3929 stop = itd; 3930 stop->xfer_next = NULL; 3931 exfer->isoc_len = total_length; 3932 3933 /* 3934 * Part 2: Transfer descriptors have now been set up, now they must 3935 * be scheduled into the period frame list. Erk. Not wanting to 3936 * complicate matters, transfer is denied if the transfer spans 3937 * more than the period frame list. 3938 */ 3939 3940 s = splusb(); 3941 3942 /* Start inserting frames */ 3943 if (epipe->u.isoc.cur_xfers > 0) { 3944 frindex = epipe->u.isoc.next_frame; 3945 } else { 3946 frindex = EOREAD4(sc, EHCI_FRINDEX); 3947 frindex = frindex >> 3; /* Erase microframe index */ 3948 frindex += 2; 3949 } 3950 3951 if (frindex >= sc->sc_flsize) 3952 frindex &= (sc->sc_flsize - 1); 3953 3954 /* Whats the frame interval? */ 3955 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 3956 if (i / 8 == 0) 3957 i = 1; 3958 else 3959 i /= 8; 3960 3961 itd = start; 3962 for (j = 0; j < frames; j++) { 3963 if (itd == NULL) 3964 panic("ehci: unexpectedly ran out of isoc itds, " 3965 "isoc_start"); 3966 3967 itd->itd.itd_next = sc->sc_flist[frindex]; 3968 if (itd->itd.itd_next == 0) 3969 /* FIXME: frindex table gets initialized to NULL 3970 * or EHCI_NULL? */ 3971 itd->itd.itd_next = htole32(EHCI_NULL); 3972 3973 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 3974 itd->u.frame_list.next = sc->sc_softitds[frindex]; 3975 sc->sc_softitds[frindex] = itd; 3976 if (itd->u.frame_list.next != NULL) 3977 itd->u.frame_list.next->u.frame_list.prev = itd; 3978 itd->slot = frindex; 3979 itd->u.frame_list.prev = NULL; 3980 3981 frindex += i; 3982 if (frindex >= sc->sc_flsize) 3983 frindex -= sc->sc_flsize; 3984 3985 itd = itd->xfer_next; 3986 } 3987 3988 epipe->u.isoc.cur_xfers++; 3989 epipe->u.isoc.next_frame = frindex; 3990 3991 exfer->itdstart = start; 3992 exfer->itdend = stop; 3993 exfer->sqtdstart = NULL; 3994 exfer->sqtdstart = NULL; 3995 3996 ehci_add_intr_list(sc, exfer); 3997 xfer->status = USBD_IN_PROGRESS; 3998 xfer->done = 0; 3999 splx(s); 4000 4001 if (sc->sc_bus.use_polling) { 4002 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4003 ehci_waitintr(sc, xfer); 4004 } 4005 4006 return (USBD_IN_PROGRESS); 4007 } 4008 4009 void 4010 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4011 { 4012 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4013 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4014 } 4015 4016 void 4017 ehci_device_isoc_close(usbd_pipe_handle pipe) 4018 { 4019 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4020 } 4021 4022 void 4023 ehci_device_isoc_done(usbd_xfer_handle xfer) 4024 { 4025 struct ehci_xfer *exfer; 4026 ehci_softc_t *sc; 4027 struct ehci_pipe *epipe; 4028 int s; 4029 4030 exfer = EXFER(xfer); 4031 sc = (ehci_softc_t *)xfer->pipe->device->bus; 4032 epipe = (struct ehci_pipe *) xfer->pipe; 4033 4034 s = splusb(); 4035 epipe->u.isoc.cur_xfers--; 4036 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4037 ehci_del_intr_list(sc, exfer); 4038 ehci_rem_free_itd_chain(sc, exfer); 4039 } 4040 splx(s); 4041 } 4042