1 /* $OpenBSD: ehci.c,v 1.117 2011/07/03 15:47:17 matthew Exp $ */ 2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 10 * Jeremy Morse (jeremy.morse@gmail.com). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/usb_20.zip 41 */ 42 43 /* 44 * TODO: 45 * 1) The hub driver needs to handle and schedule the transaction translator, 46 * to assign place in frame where different devices get to go. See chapter 47 * on hubs in USB 2.0 for details. 48 * 49 * 2) Command failures are not recovered correctly. 50 */ 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/rwlock.h> 56 #include <sys/malloc.h> 57 #include <sys/device.h> 58 #include <sys/selinfo.h> 59 #include <sys/proc.h> 60 #include <sys/queue.h> 61 #include <sys/timeout.h> 62 63 #include <machine/bus.h> 64 #include <machine/endian.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 #include <dev/usb/usbdivar.h> 69 #include <dev/usb/usb_mem.h> 70 #include <dev/usb/usb_quirks.h> 71 72 #include <dev/usb/ehcireg.h> 73 #include <dev/usb/ehcivar.h> 74 75 #include <dev/rndvar.h> 76 77 struct cfdriver ehci_cd = { 78 NULL, "ehci", DV_DULL 79 }; 80 81 #ifdef EHCI_DEBUG 82 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 83 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 84 int ehcidebug = 0; 85 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n,x) 89 #endif 90 91 #define mstohz(ms) ((ms) * hz / 1000) 92 93 struct ehci_pipe { 94 struct usbd_pipe pipe; 95 96 ehci_soft_qh_t *sqh; 97 union { 98 ehci_soft_qtd_t *qtd; 99 /* ehci_soft_itd_t *itd; */ 100 } tail; 101 union { 102 /* Control pipe */ 103 struct { 104 usb_dma_t reqdma; 105 u_int length; 106 /*ehci_soft_qtd_t *setup, *data, *stat;*/ 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 u_int length; 111 } intr; 112 /* Bulk pipe */ 113 struct { 114 u_int length; 115 } bulk; 116 /* Iso pipe */ 117 struct { 118 u_int next_frame; 119 u_int cur_xfers; 120 } isoc; 121 } u; 122 }; 123 124 u_int8_t ehci_reverse_bits(u_int8_t, int); 125 126 usbd_status ehci_open(usbd_pipe_handle); 127 void ehci_poll(struct usbd_bus *); 128 void ehci_softintr(void *); 129 int ehci_intr1(ehci_softc_t *); 130 void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 131 void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 132 void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 133 void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 134 void ehci_idone(struct ehci_xfer *); 135 void ehci_timeout(void *); 136 void ehci_timeout_task(void *); 137 void ehci_intrlist_timeout(void *); 138 139 usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 140 void ehci_freem(struct usbd_bus *, usb_dma_t *); 141 142 usbd_xfer_handle ehci_allocx(struct usbd_bus *); 143 void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 144 145 usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 146 usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 147 void ehci_root_ctrl_abort(usbd_xfer_handle); 148 void ehci_root_ctrl_close(usbd_pipe_handle); 149 void ehci_root_ctrl_done(usbd_xfer_handle); 150 151 usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 152 usbd_status ehci_root_intr_start(usbd_xfer_handle); 153 void ehci_root_intr_abort(usbd_xfer_handle); 154 void ehci_root_intr_close(usbd_pipe_handle); 155 void ehci_root_intr_done(usbd_xfer_handle); 156 157 usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 158 usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 159 void ehci_device_ctrl_abort(usbd_xfer_handle); 160 void ehci_device_ctrl_close(usbd_pipe_handle); 161 void ehci_device_ctrl_done(usbd_xfer_handle); 162 163 usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 164 usbd_status ehci_device_bulk_start(usbd_xfer_handle); 165 void ehci_device_bulk_abort(usbd_xfer_handle); 166 void ehci_device_bulk_close(usbd_pipe_handle); 167 void ehci_device_bulk_done(usbd_xfer_handle); 168 169 usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 170 usbd_status ehci_device_intr_start(usbd_xfer_handle); 171 void ehci_device_intr_abort(usbd_xfer_handle); 172 void ehci_device_intr_close(usbd_pipe_handle); 173 void ehci_device_intr_done(usbd_xfer_handle); 174 175 usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 176 usbd_status ehci_device_isoc_start(usbd_xfer_handle); 177 void ehci_device_isoc_abort(usbd_xfer_handle); 178 void ehci_device_isoc_close(usbd_pipe_handle); 179 void ehci_device_isoc_done(usbd_xfer_handle); 180 181 void ehci_device_clear_toggle(usbd_pipe_handle pipe); 182 void ehci_noop(usbd_pipe_handle pipe); 183 184 int ehci_str(usb_string_descriptor_t *, int, const char *); 185 void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 186 void ehci_disown(ehci_softc_t *, int, int); 187 188 ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 189 void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 190 191 ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 192 void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 193 usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 194 ehci_softc_t *, u_int, int, usbd_xfer_handle, 195 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 196 void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 197 ehci_soft_qtd_t *); 198 199 ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 200 void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 201 void ehci_rem_free_itd_chain(ehci_softc_t *sc, 202 struct ehci_xfer *exfer); 203 void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 204 usbd_status status); 205 206 usbd_status ehci_device_request(usbd_xfer_handle xfer); 207 208 usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 209 int ival); 210 211 void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 212 void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 213 ehci_soft_qh_t *); 214 void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 215 void ehci_sync_hc(ehci_softc_t *); 216 217 void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 218 void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 219 220 #ifdef EHCI_DEBUG 221 void ehci_dump_regs(ehci_softc_t *); 222 void ehci_dump(void); 223 ehci_softc_t *theehci; 224 void ehci_dump_link(ehci_link_t, int); 225 void ehci_dump_sqtds(ehci_soft_qtd_t *); 226 void ehci_dump_sqtd(ehci_soft_qtd_t *); 227 void ehci_dump_qtd(ehci_qtd_t *); 228 void ehci_dump_sqh(ehci_soft_qh_t *); 229 #if notyet 230 void ehci_dump_sitd(struct ehci_soft_itd *itd); 231 void ehci_dump_itd(struct ehci_soft_itd *); 232 #endif 233 #ifdef DIAGNOSTIC 234 void ehci_dump_exfer(struct ehci_xfer *); 235 #endif 236 #endif 237 238 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 239 240 #define EHCI_INTR_ENDPT 1 241 242 #define ehci_add_intr_list(sc, ex) \ 243 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 244 #define ehci_del_intr_list(sc, ex) \ 245 do { \ 246 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 247 (ex)->inext.tqe_prev = NULL; \ 248 } while (0) 249 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 250 251 struct usbd_bus_methods ehci_bus_methods = { 252 ehci_open, 253 ehci_softintr, 254 ehci_poll, 255 ehci_allocm, 256 ehci_freem, 257 ehci_allocx, 258 ehci_freex, 259 }; 260 261 struct usbd_pipe_methods ehci_root_ctrl_methods = { 262 ehci_root_ctrl_transfer, 263 ehci_root_ctrl_start, 264 ehci_root_ctrl_abort, 265 ehci_root_ctrl_close, 266 ehci_noop, 267 ehci_root_ctrl_done, 268 }; 269 270 struct usbd_pipe_methods ehci_root_intr_methods = { 271 ehci_root_intr_transfer, 272 ehci_root_intr_start, 273 ehci_root_intr_abort, 274 ehci_root_intr_close, 275 ehci_noop, 276 ehci_root_intr_done, 277 }; 278 279 struct usbd_pipe_methods ehci_device_ctrl_methods = { 280 ehci_device_ctrl_transfer, 281 ehci_device_ctrl_start, 282 ehci_device_ctrl_abort, 283 ehci_device_ctrl_close, 284 ehci_noop, 285 ehci_device_ctrl_done, 286 }; 287 288 struct usbd_pipe_methods ehci_device_intr_methods = { 289 ehci_device_intr_transfer, 290 ehci_device_intr_start, 291 ehci_device_intr_abort, 292 ehci_device_intr_close, 293 ehci_device_clear_toggle, 294 ehci_device_intr_done, 295 }; 296 297 struct usbd_pipe_methods ehci_device_bulk_methods = { 298 ehci_device_bulk_transfer, 299 ehci_device_bulk_start, 300 ehci_device_bulk_abort, 301 ehci_device_bulk_close, 302 ehci_device_clear_toggle, 303 ehci_device_bulk_done, 304 }; 305 306 struct usbd_pipe_methods ehci_device_isoc_methods = { 307 ehci_device_isoc_transfer, 308 ehci_device_isoc_start, 309 ehci_device_isoc_abort, 310 ehci_device_isoc_close, 311 ehci_noop, 312 ehci_device_isoc_done, 313 }; 314 315 /* 316 * Reverse a number with nbits bits. Used to evenly distribute lower-level 317 * interrupt heads in the periodic schedule. 318 * Suitable for use with EHCI_IPOLLRATES <= 9. 319 */ 320 u_int8_t 321 ehci_reverse_bits(u_int8_t c, int nbits) 322 { 323 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa); 324 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc); 325 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0); 326 327 return c >> (8 - nbits); 328 } 329 330 usbd_status 331 ehci_init(ehci_softc_t *sc) 332 { 333 u_int32_t sparams, cparams, hcr; 334 u_int i, j; 335 usbd_status err; 336 ehci_soft_qh_t *sqh; 337 338 #ifdef EHCI_DEBUG 339 u_int32_t vers; 340 theehci = sc; 341 342 DPRINTF(("ehci_init: start\n")); 343 344 vers = EREAD2(sc, EHCI_HCIVERSION); 345 DPRINTF(("%s: EHCI version %x.%x\n", sc->sc_bus.bdev.dv_xname, 346 vers >> 8, vers & 0xff)); 347 #endif 348 349 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 350 351 sparams = EREAD4(sc, EHCI_HCSPARAMS); 352 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 353 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 354 cparams = EREAD4(sc, EHCI_HCCPARAMS); 355 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 356 357 /* MUST clear segment register if 64 bit capable. */ 358 if (EHCI_HCC_64BIT(cparams)) 359 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 360 361 sc->sc_bus.usbrev = USBREV_2_0; 362 363 /* Reset the controller */ 364 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 365 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 366 usb_delay_ms(&sc->sc_bus, 1); 367 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 368 for (i = 0; i < 100; i++) { 369 usb_delay_ms(&sc->sc_bus, 1); 370 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 371 if (!hcr) 372 break; 373 } 374 if (hcr) { 375 printf("%s: reset timeout\n", 376 sc->sc_bus.bdev.dv_xname); 377 return (USBD_IOERROR); 378 } 379 380 /* XXX need proper intr scheduling */ 381 sc->sc_rand = 96; 382 383 /* frame list size at default, read back what we got and use that */ 384 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 385 case 0: 386 sc->sc_flsize = 1024; 387 break; 388 case 1: 389 sc->sc_flsize = 512; 390 break; 391 case 2: 392 sc->sc_flsize = 256; 393 break; 394 case 3: 395 return (USBD_IOERROR); 396 } 397 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 398 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 399 if (err) 400 return (err); 401 DPRINTF(("%s: flsize=%d\n", sc->sc_bus.bdev.dv_xname,sc->sc_flsize)); 402 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 403 404 for (i = 0; i < sc->sc_flsize; i++) 405 sc->sc_flist[i] = EHCI_NULL; 406 407 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 408 409 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 410 M_USB, M_NOWAIT | M_ZERO); 411 if (sc->sc_softitds == NULL) 412 return (ENOMEM); 413 LIST_INIT(&sc->sc_freeitds); 414 TAILQ_INIT(&sc->sc_intrhead); 415 416 /* Set up the bus struct. */ 417 sc->sc_bus.methods = &ehci_bus_methods; 418 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 419 420 sc->sc_eintrs = EHCI_NORMAL_INTRS; 421 422 /* 423 * Allocate the interrupt dummy QHs. These are arranged to give poll 424 * intervals that are powers of 2 times 1ms. 425 */ 426 for (i = 0; i < EHCI_INTRQHS; i++) { 427 sqh = ehci_alloc_sqh(sc); 428 if (sqh == NULL) { 429 err = USBD_NOMEM; 430 goto bad1; 431 } 432 sc->sc_islots[i].sqh = sqh; 433 } 434 for (i = 0; i < EHCI_INTRQHS; i++) { 435 sqh = sc->sc_islots[i].sqh; 436 if (i == 0) { 437 /* The last (1ms) QH terminates. */ 438 sqh->qh.qh_link = EHCI_NULL; 439 sqh->next = NULL; 440 } else { 441 /* Otherwise the next QH has half the poll interval */ 442 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 443 sqh->qh.qh_link = htole32(sqh->next->physaddr | 444 EHCI_LINK_QH); 445 } 446 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 447 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 448 sqh->qh.qh_curqtd = EHCI_NULL; 449 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 450 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 451 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 452 sqh->sqtd = NULL; 453 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 454 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 455 } 456 /* Point the frame list at the last level (128ms). */ 457 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++) 458 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1)) 459 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[ 460 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits( 461 i, EHCI_IPOLLRATES - 1))].sqh->physaddr); 462 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 463 BUS_DMASYNC_PREWRITE); 464 465 /* Allocate dummy QH that starts the async list. */ 466 sqh = ehci_alloc_sqh(sc); 467 if (sqh == NULL) { 468 err = USBD_NOMEM; 469 goto bad1; 470 } 471 /* Fill the QH */ 472 sqh->qh.qh_endp = 473 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 474 sqh->qh.qh_link = 475 htole32(sqh->physaddr | EHCI_LINK_QH); 476 sqh->qh.qh_curqtd = EHCI_NULL; 477 sqh->prev = sqh; /*It's a circular list.. */ 478 sqh->next = sqh; 479 /* Fill the overlay qTD */ 480 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 481 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 482 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 483 sqh->sqtd = NULL; 484 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 485 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 486 #ifdef EHCI_DEBUG 487 if (ehcidebug) 488 ehci_dump_sqh(sqh); 489 #endif 490 491 /* Point to async list */ 492 sc->sc_async_head = sqh; 493 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 494 495 timeout_set(&sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 496 497 rw_init(&sc->sc_doorbell_lock, "ehcidb"); 498 499 /* Turn on controller */ 500 EOWRITE4(sc, EHCI_USBCMD, 501 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 502 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 503 EHCI_CMD_ASE | 504 EHCI_CMD_PSE | 505 EHCI_CMD_RS); 506 507 /* Take over port ownership */ 508 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 509 510 for (i = 0; i < 100; i++) { 511 usb_delay_ms(&sc->sc_bus, 1); 512 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 513 if (!hcr) 514 break; 515 } 516 if (hcr) { 517 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 518 return (USBD_IOERROR); 519 } 520 521 /* Enable interrupts */ 522 DPRINTFN(1,("ehci_init: enabling\n")); 523 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 524 525 return (USBD_NORMAL_COMPLETION); 526 527 #if 0 528 bad2: 529 ehci_free_sqh(sc, sc->sc_async_head); 530 #endif 531 bad1: 532 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 533 return (err); 534 } 535 536 int 537 ehci_intr(void *v) 538 { 539 ehci_softc_t *sc = v; 540 541 if (sc == NULL || sc->sc_bus.dying) 542 return (0); 543 544 /* If we get an interrupt while polling, then just ignore it. */ 545 if (sc->sc_bus.use_polling) { 546 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 547 548 if (intrs) 549 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 550 return (0); 551 } 552 553 return (ehci_intr1(sc)); 554 } 555 556 int 557 ehci_intr1(ehci_softc_t *sc) 558 { 559 u_int32_t intrs, eintrs; 560 561 DPRINTFN(20,("ehci_intr1: enter\n")); 562 563 /* In case the interrupt occurs before initialization has completed. */ 564 if (sc == NULL) { 565 #ifdef DIAGNOSTIC 566 printf("ehci_intr1: sc == NULL\n"); 567 #endif 568 return (0); 569 } 570 571 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 572 if (intrs == 0xffffffff) { 573 sc->sc_bus.dying = 1; 574 return (0); 575 } 576 if (!intrs) 577 return (0); 578 579 eintrs = intrs & sc->sc_eintrs; 580 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 581 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), (u_int)eintrs)); 582 if (!eintrs) 583 return (0); 584 585 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 586 sc->sc_bus.intr_context++; 587 sc->sc_bus.no_intrs++; 588 if (eintrs & EHCI_STS_HSE) { 589 printf("%s: unrecoverable error, controller halted\n", 590 sc->sc_bus.bdev.dv_xname); 591 sc->sc_bus.dying = 1; 592 sc->sc_bus.intr_context--; 593 return (1); 594 } 595 if (eintrs & EHCI_STS_IAA) { 596 DPRINTF(("ehci_intr1: door bell\n")); 597 wakeup(&sc->sc_async_head); 598 eintrs &= ~EHCI_STS_IAA; 599 } 600 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 601 DPRINTFN(5,("ehci_intr1: %s %s\n", 602 eintrs & EHCI_STS_INT ? "INT" : "", 603 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 604 usb_schedsoftintr(&sc->sc_bus); 605 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 606 } 607 if (eintrs & EHCI_STS_PCD) { 608 ehci_pcd(sc, sc->sc_intrxfer); 609 eintrs &= ~EHCI_STS_PCD; 610 } 611 612 sc->sc_bus.intr_context--; 613 614 if (eintrs != 0) { 615 /* Block unprocessed interrupts. */ 616 sc->sc_eintrs &= ~eintrs; 617 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 618 printf("%s: blocking intrs 0x%x\n", 619 sc->sc_bus.bdev.dv_xname, eintrs); 620 } 621 622 return (1); 623 } 624 625 void 626 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 627 { 628 u_char *p; 629 int i, m; 630 631 if (xfer == NULL) { 632 /* Just ignore the change. */ 633 return; 634 } 635 636 p = KERNADDR(&xfer->dmabuf, 0); 637 m = min(sc->sc_noport, xfer->length * 8 - 1); 638 memset(p, 0, xfer->length); 639 for (i = 1; i <= m; i++) { 640 /* Pick out CHANGE bits from the status reg. */ 641 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 642 p[i/8] |= 1 << (i%8); 643 } 644 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 645 xfer->actlen = xfer->length; 646 xfer->status = USBD_NORMAL_COMPLETION; 647 648 usb_transfer_complete(xfer); 649 } 650 651 void 652 ehci_softintr(void *v) 653 { 654 ehci_softc_t *sc = v; 655 struct ehci_xfer *ex, *nextex; 656 657 DPRINTFN(10,("%s: ehci_softintr (%d)\n", sc->sc_bus.bdev.dv_xname, 658 sc->sc_bus.intr_context)); 659 660 if (sc->sc_bus.dying) 661 return; 662 663 sc->sc_bus.intr_context++; 664 665 /* 666 * The only explanation I can think of for why EHCI is as brain dead 667 * as UHCI interrupt-wise is that Intel was involved in both. 668 * An interrupt just tells us that something is done, we have no 669 * clue what, so we need to scan through all active transfers. :-( 670 */ 671 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 672 nextex = TAILQ_NEXT(ex, inext); 673 ehci_check_intr(sc, ex); 674 } 675 676 /* Schedule a callout to catch any dropped transactions. */ 677 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 678 !TAILQ_EMPTY(&sc->sc_intrhead)) { 679 timeout_add_sec(&sc->sc_tmo_intrlist, 1); 680 } 681 682 if (sc->sc_softwake) { 683 sc->sc_softwake = 0; 684 wakeup(&sc->sc_softwake); 685 } 686 687 sc->sc_bus.intr_context--; 688 } 689 690 /* Check for an interrupt. */ 691 void 692 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 693 { 694 int attr; 695 696 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 697 698 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 699 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 700 ehci_check_itd_intr(sc, ex); 701 else 702 ehci_check_qh_intr(sc, ex); 703 704 return; 705 } 706 707 void 708 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 709 { 710 ehci_soft_qtd_t *sqtd, *lsqtd; 711 __uint32_t status; 712 713 if (ex->sqtdstart == NULL) { 714 printf("ehci_check_qh_intr: not valid sqtd\n"); 715 return; 716 } 717 718 lsqtd = ex->sqtdend; 719 #ifdef DIAGNOSTIC 720 if (lsqtd == NULL) { 721 printf("ehci_check_qh_intr: lsqtd==0\n"); 722 return; 723 } 724 #endif 725 /* 726 * If the last TD is still active we need to check whether there 727 * is a an error somewhere in the middle, or whether there was a 728 * short packet (SPD and not ACTIVE). 729 */ 730 usb_syncmem(&lsqtd->dma, 731 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 732 sizeof(lsqtd->qtd.qtd_status), 733 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 734 if (letoh32(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 735 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 736 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 737 usb_syncmem(&sqtd->dma, 738 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 739 sizeof(sqtd->qtd.qtd_status), 740 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 741 status = letoh32(sqtd->qtd.qtd_status); 742 usb_syncmem(&sqtd->dma, 743 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 744 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 745 /* If there's an active QTD the xfer isn't done. */ 746 if (status & EHCI_QTD_ACTIVE) 747 break; 748 /* Any kind of error makes the xfer done. */ 749 if (status & EHCI_QTD_HALTED) 750 goto done; 751 /* We want short packets, and it is short: it's done */ 752 if (EHCI_QTD_GET_BYTES(status) != 0) 753 goto done; 754 } 755 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 756 ex, ex->sqtdstart)); 757 usb_syncmem(&lsqtd->dma, 758 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 759 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 760 return; 761 } 762 done: 763 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 764 timeout_del(&ex->xfer.timeout_handle); 765 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task); 766 ehci_idone(ex); 767 } 768 769 void 770 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 771 ehci_soft_itd_t *itd; 772 int i; 773 774 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 775 return; 776 777 if (ex->itdstart == NULL) { 778 printf("ehci_check_itd_intr: not valid itd\n"); 779 return; 780 } 781 782 itd = ex->itdend; 783 #ifdef DIAGNOSTIC 784 if (itd == NULL) { 785 printf("ehci_check_itd_intr: itdend == 0\n"); 786 return; 787 } 788 #endif 789 790 /* 791 * check no active transfers in last itd, meaning we're finished 792 */ 793 794 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 795 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 796 BUS_DMASYNC_POSTREAD); 797 798 for (i = 0; i < 8; i++) { 799 if (letoh32(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 800 break; 801 } 802 803 if (i == 8) { 804 goto done; /* All 8 descriptors inactive, it's done */ 805 } 806 807 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 808 ex->itdstart)); 809 return; 810 done: 811 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 812 timeout_del(&ex->xfer.timeout_handle); 813 ehci_idone(ex); 814 } 815 816 void 817 ehci_idone(struct ehci_xfer *ex) 818 { 819 usbd_xfer_handle xfer = &ex->xfer; 820 #ifdef EHCI_DEBUG 821 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 822 #endif 823 ehci_soft_qtd_t *sqtd, *lsqtd; 824 u_int32_t status = 0, nstatus = 0; 825 int actlen, cerr; 826 827 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 828 #ifdef DIAGNOSTIC 829 { 830 int s = splhigh(); 831 if (ex->isdone) { 832 splx(s); 833 #ifdef EHCI_DEBUG 834 printf("ehci_idone: ex is done!\n "); 835 ehci_dump_exfer(ex); 836 #else 837 printf("ehci_idone: ex=%p is done!\n", ex); 838 #endif 839 return; 840 } 841 ex->isdone = 1; 842 splx(s); 843 } 844 #endif 845 if (xfer->status == USBD_CANCELLED || 846 xfer->status == USBD_TIMEOUT) { 847 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 848 return; 849 } 850 851 #ifdef EHCI_DEBUG 852 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 853 if (ehcidebug > 10) 854 ehci_dump_sqtds(ex->sqtdstart); 855 #endif 856 857 /* The transfer is done, compute actual length and status. */ 858 859 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 860 == UE_ISOCHRONOUS) { 861 /* Isoc transfer */ 862 struct ehci_soft_itd *itd; 863 int i, nframes, len, uframes; 864 865 nframes = 0; 866 actlen = 0; 867 868 switch (xfer->pipe->endpoint->edesc->bInterval) { 869 case 0: 870 panic("ehci: isoc xfer suddenly has 0 bInterval, " 871 "invalid"); 872 case 1: 873 uframes = 1; 874 break; 875 case 2: 876 uframes = 2; 877 break; 878 case 3: 879 uframes = 4; 880 break; 881 default: 882 uframes = 8; 883 break; 884 } 885 886 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 887 usb_syncmem(&itd->dma, 888 itd->offs + offsetof(ehci_itd_t, itd_ctl), 889 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 890 BUS_DMASYNC_POSTREAD); 891 892 for (i = 0; i < 8; i += uframes) { 893 /* XXX - driver didn't fill in the frame full 894 * of uframes. This leads to scheduling 895 * inefficiencies, but working around 896 * this doubles complexity of tracking 897 * an xfer. 898 */ 899 if (nframes >= xfer->nframes) 900 break; 901 902 status = letoh32(itd->itd.itd_ctl[i]); 903 len = EHCI_ITD_GET_LEN(status); 904 if (EHCI_ITD_GET_STATUS(status) != 0) 905 len = 0; /*No valid data on error*/ 906 907 xfer->frlengths[nframes++] = len; 908 actlen += len; 909 } 910 911 if (nframes >= xfer->nframes) 912 break; 913 } 914 915 xfer->actlen = actlen; 916 xfer->status = USBD_NORMAL_COMPLETION; 917 918 goto end; 919 } 920 921 /* Continue processing xfers using queue heads */ 922 923 lsqtd = ex->sqtdend; 924 actlen = 0; 925 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; 926 sqtd = sqtd->nextqtd) { 927 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 928 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 929 nstatus = letoh32(sqtd->qtd.qtd_status); 930 if (nstatus & EHCI_QTD_ACTIVE) 931 break; 932 933 status = nstatus; 934 /* halt is ok if descriptor is last, and complete */ 935 if (sqtd->qtd.qtd_next == EHCI_NULL && 936 EHCI_QTD_GET_BYTES(status) == 0) 937 status &= ~EHCI_QTD_HALTED; 938 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 939 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 940 } 941 942 cerr = EHCI_QTD_GET_CERR(status); 943 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 944 "status=0x%x\n", xfer->length, actlen, cerr, status)); 945 xfer->actlen = actlen; 946 if ((status & EHCI_QTD_HALTED) != 0) { 947 #ifdef EHCI_DEBUG 948 char sbuf[128]; 949 950 bitmask_snprintf((u_int32_t)status, 951 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 952 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 953 954 DPRINTFN(2, 955 ("ehci_idone: error, addr=%d, endpt=0x%02x, " 956 "status 0x%s\n", 957 xfer->pipe->device->address, 958 xfer->pipe->endpoint->edesc->bEndpointAddress, 959 sbuf)); 960 if (ehcidebug > 2) { 961 ehci_dump_sqh(epipe->sqh); 962 ehci_dump_sqtds(ex->sqtdstart); 963 } 964 #endif 965 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0) 966 xfer->status = USBD_STALLED; 967 else 968 xfer->status = USBD_IOERROR; /* more info XXX */ 969 } else 970 xfer->status = USBD_NORMAL_COMPLETION; 971 end: 972 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 973 * during this call, before methods->done is called: dma sync required 974 * beforehand? */ 975 usb_transfer_complete(xfer); 976 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 977 } 978 979 /* 980 * Wait here until controller claims to have an interrupt. 981 * Then call ehci_intr and return. Use timeout to avoid waiting 982 * too long. 983 */ 984 void 985 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 986 { 987 int timo; 988 u_int32_t intrs; 989 990 xfer->status = USBD_IN_PROGRESS; 991 for (timo = xfer->timeout; timo >= 0; timo--) { 992 usb_delay_ms(&sc->sc_bus, 1); 993 if (sc->sc_bus.dying) 994 break; 995 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 996 sc->sc_eintrs; 997 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 998 #ifdef EHCI_DEBUG 999 if (ehcidebug > 15) 1000 ehci_dump_regs(sc); 1001 #endif 1002 if (intrs) { 1003 ehci_intr1(sc); 1004 if (xfer->status != USBD_IN_PROGRESS) 1005 return; 1006 } 1007 } 1008 1009 /* Timeout */ 1010 DPRINTF(("ehci_waitintr: timeout\n")); 1011 xfer->status = USBD_TIMEOUT; 1012 usb_transfer_complete(xfer); 1013 /* XXX should free TD */ 1014 } 1015 1016 void 1017 ehci_poll(struct usbd_bus *bus) 1018 { 1019 ehci_softc_t *sc = (ehci_softc_t *)bus; 1020 #ifdef EHCI_DEBUG 1021 static int last; 1022 int new; 1023 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1024 if (new != last) { 1025 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1026 last = new; 1027 } 1028 #endif 1029 1030 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1031 ehci_intr1(sc); 1032 } 1033 1034 int 1035 ehci_detach(struct ehci_softc *sc, int flags) 1036 { 1037 int rv = 0; 1038 1039 if (sc->sc_child != NULL) 1040 rv = config_detach(sc->sc_child, flags); 1041 1042 if (rv != 0) 1043 return (rv); 1044 1045 timeout_del(&sc->sc_tmo_intrlist); 1046 1047 if (sc->sc_shutdownhook != NULL) 1048 shutdownhook_disestablish(sc->sc_shutdownhook); 1049 1050 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1051 1052 /* XXX free other data structures XXX */ 1053 1054 return (rv); 1055 } 1056 1057 1058 int 1059 ehci_activate(struct device *self, int act) 1060 { 1061 struct ehci_softc *sc = (struct ehci_softc *)self; 1062 u_int32_t cmd, hcr; 1063 int i, rv = 0; 1064 1065 switch (act) { 1066 case DVACT_QUIESCE: 1067 rv = config_activate_children(self, act); 1068 break; 1069 case DVACT_SUSPEND: 1070 sc->sc_bus.use_polling++; 1071 1072 for (i = 1; i <= sc->sc_noport; i++) { 1073 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1074 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE) 1075 EOWRITE4(sc, EHCI_PORTSC(i), 1076 cmd | EHCI_PS_SUSP); 1077 } 1078 1079 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1080 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1081 EOWRITE4(sc, EHCI_USBCMD, cmd); 1082 1083 for (i = 0; i < 100; i++) { 1084 hcr = EOREAD4(sc, EHCI_USBSTS) & 1085 (EHCI_STS_ASS | EHCI_STS_PSS); 1086 if (hcr == 0) 1087 break; 1088 1089 usb_delay_ms(&sc->sc_bus, 1); 1090 } 1091 if (hcr != 0) 1092 printf("%s: reset timeout\n", 1093 sc->sc_bus.bdev.dv_xname); 1094 1095 cmd &= ~EHCI_CMD_RS; 1096 EOWRITE4(sc, EHCI_USBCMD, cmd); 1097 1098 for (i = 0; i < 100; i++) { 1099 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1100 if (hcr == EHCI_STS_HCH) 1101 break; 1102 1103 usb_delay_ms(&sc->sc_bus, 1); 1104 } 1105 if (hcr != EHCI_STS_HCH) 1106 printf("%s: config timeout\n", 1107 sc->sc_bus.bdev.dv_xname); 1108 1109 sc->sc_bus.use_polling--; 1110 break; 1111 case DVACT_RESUME: 1112 sc->sc_bus.use_polling++; 1113 1114 /* restore things in case the bios sucks */ 1115 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1116 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1117 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1118 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1119 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1120 1121 hcr = 0; 1122 for (i = 1; i <= sc->sc_noport; i++) { 1123 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1124 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP) { 1125 EOWRITE4(sc, EHCI_PORTSC(i), 1126 cmd | EHCI_PS_FPR); 1127 hcr = 1; 1128 } 1129 } 1130 1131 if (hcr) { 1132 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1133 for (i = 1; i <= sc->sc_noport; i++) { 1134 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1135 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == 1136 EHCI_PS_SUSP) 1137 EOWRITE4(sc, EHCI_PORTSC(i), 1138 cmd & ~EHCI_PS_FPR); 1139 } 1140 } 1141 1142 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1143 1144 /* Take over port ownership */ 1145 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 1146 1147 for (i = 0; i < 100; i++) { 1148 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1149 if (hcr != EHCI_STS_HCH) 1150 break; 1151 1152 usb_delay_ms(&sc->sc_bus, 1); 1153 } 1154 if (hcr == EHCI_STS_HCH) 1155 printf("%s: config timeout\n", 1156 sc->sc_bus.bdev.dv_xname); 1157 1158 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1159 1160 sc->sc_bus.use_polling--; 1161 rv = config_activate_children(self, act); 1162 break; 1163 case DVACT_DEACTIVATE: 1164 if (sc->sc_child != NULL) 1165 rv = config_deactivate(sc->sc_child); 1166 sc->sc_bus.dying = 1; 1167 break; 1168 } 1169 return (rv); 1170 } 1171 1172 /* 1173 * Shut down the controller when the system is going down. 1174 */ 1175 void 1176 ehci_shutdown(void *v) 1177 { 1178 ehci_softc_t *sc = v; 1179 1180 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1181 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1182 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1183 } 1184 1185 usbd_status 1186 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1187 { 1188 struct ehci_softc *sc = (struct ehci_softc *)bus; 1189 usbd_status err; 1190 1191 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1192 #ifdef EHCI_DEBUG 1193 if (err) 1194 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1195 #endif 1196 return (err); 1197 } 1198 1199 void 1200 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1201 { 1202 struct ehci_softc *sc = (struct ehci_softc *)bus; 1203 1204 usb_freemem(&sc->sc_bus, dma); 1205 } 1206 1207 usbd_xfer_handle 1208 ehci_allocx(struct usbd_bus *bus) 1209 { 1210 struct ehci_softc *sc = (struct ehci_softc *)bus; 1211 usbd_xfer_handle xfer; 1212 1213 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1214 if (xfer != NULL) { 1215 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1216 #ifdef DIAGNOSTIC 1217 if (xfer->busy_free != XFER_FREE) 1218 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", 1219 xfer, xfer->busy_free); 1220 #endif 1221 } else 1222 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1223 1224 if (xfer != NULL) { 1225 memset(xfer, 0, sizeof(struct ehci_xfer)); 1226 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task, 1227 xfer, USB_TASK_TYPE_ABORT); 1228 EXFER(xfer)->ehci_xfer_flags = 0; 1229 #ifdef DIAGNOSTIC 1230 EXFER(xfer)->isdone = 1; 1231 xfer->busy_free = XFER_BUSY; 1232 #endif 1233 } 1234 return (xfer); 1235 } 1236 1237 void 1238 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1239 { 1240 struct ehci_softc *sc = (struct ehci_softc *)bus; 1241 1242 #ifdef DIAGNOSTIC 1243 if (xfer->busy_free != XFER_BUSY) { 1244 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1245 xfer->busy_free); 1246 return; 1247 } 1248 xfer->busy_free = XFER_FREE; 1249 if (!EXFER(xfer)->isdone) { 1250 printf("ehci_freex: !isdone\n"); 1251 return; 1252 } 1253 #endif 1254 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1255 } 1256 1257 void 1258 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1259 { 1260 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1261 1262 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1263 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1264 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 1265 if (ehcidebug) 1266 usbd_dump_pipe(pipe); 1267 #endif 1268 #ifdef DIAGNOSTIC 1269 if ((epipe->sqh->qh.qh_qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) != 0) 1270 panic("ehci_device_clear_toggle: queue active"); 1271 #endif 1272 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1273 } 1274 1275 void 1276 ehci_noop(usbd_pipe_handle pipe) 1277 { 1278 } 1279 1280 #ifdef EHCI_DEBUG 1281 void 1282 ehci_dump_regs(ehci_softc_t *sc) 1283 { 1284 int i; 1285 1286 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1287 EOREAD4(sc, EHCI_USBCMD), 1288 EOREAD4(sc, EHCI_USBSTS), 1289 EOREAD4(sc, EHCI_USBINTR)); 1290 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1291 EOREAD4(sc, EHCI_FRINDEX), 1292 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1293 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1294 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1295 for (i = 1; i <= sc->sc_noport; i++) 1296 printf("port %d status=0x%08x\n", i, 1297 EOREAD4(sc, EHCI_PORTSC(i))); 1298 } 1299 1300 /* 1301 * Unused function - this is meant to be called from a kernel 1302 * debugger. 1303 */ 1304 void 1305 ehci_dump(void) 1306 { 1307 ehci_dump_regs(theehci); 1308 } 1309 1310 void 1311 ehci_dump_link(ehci_link_t link, int type) 1312 { 1313 link = letoh32(link); 1314 printf("0x%08x", link); 1315 if (link & EHCI_LINK_TERMINATE) 1316 printf("<T>"); 1317 else { 1318 printf("<"); 1319 if (type) { 1320 switch (EHCI_LINK_TYPE(link)) { 1321 case EHCI_LINK_ITD: 1322 printf("ITD"); 1323 break; 1324 case EHCI_LINK_QH: 1325 printf("QH"); 1326 break; 1327 case EHCI_LINK_SITD: 1328 printf("SITD"); 1329 break; 1330 case EHCI_LINK_FSTN: 1331 printf("FSTN"); 1332 break; 1333 } 1334 } 1335 printf(">"); 1336 } 1337 } 1338 1339 void 1340 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1341 { 1342 int i; 1343 u_int32_t stop; 1344 1345 stop = 0; 1346 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1347 ehci_dump_sqtd(sqtd); 1348 usb_syncmem(&sqtd->dma, 1349 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1350 sizeof(sqtd->qtd), 1351 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1352 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1353 usb_syncmem(&sqtd->dma, 1354 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1355 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1356 } 1357 if (!stop) 1358 printf("dump aborted, too many TDs\n"); 1359 } 1360 1361 void 1362 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1363 { 1364 usb_syncmem(&sqtd->dma, sqtd->offs, 1365 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1366 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1367 ehci_dump_qtd(&sqtd->qtd); 1368 usb_syncmem(&sqtd->dma, sqtd->offs, 1369 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1370 } 1371 1372 void 1373 ehci_dump_qtd(ehci_qtd_t *qtd) 1374 { 1375 u_int32_t s; 1376 char sbuf[128]; 1377 1378 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1379 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1380 printf("\n"); 1381 s = letoh32(qtd->qtd_status); 1382 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED" 1383 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING", 1384 sbuf, sizeof(sbuf)); 1385 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1386 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1387 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1388 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1389 EHCI_QTD_GET_PID(s), sbuf); 1390 for (s = 0; s < 5; s++) 1391 printf(" buffer[%d]=0x%08x\n", s, letoh32(qtd->qtd_buffer[s])); 1392 } 1393 1394 void 1395 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1396 { 1397 ehci_qh_t *qh = &sqh->qh; 1398 u_int32_t endp, endphub; 1399 1400 usb_syncmem(&sqh->dma, sqh->offs, 1401 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1402 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1403 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1404 endp = letoh32(qh->qh_endp); 1405 printf(" endp=0x%08x\n", endp); 1406 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1407 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1408 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1409 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1410 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1411 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1412 EHCI_QH_GET_NRL(endp)); 1413 endphub = letoh32(qh->qh_endphub); 1414 printf(" endphub=0x%08x\n", endphub); 1415 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1416 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1417 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1418 EHCI_QH_GET_MULT(endphub)); 1419 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1420 printf("Overlay qTD:\n"); 1421 ehci_dump_qtd(&qh->qh_qtd); 1422 usb_syncmem(&sqh->dma, sqh->offs, 1423 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1424 } 1425 1426 #if notyet 1427 void 1428 ehci_dump_itd(struct ehci_soft_itd *itd) 1429 { 1430 ehci_isoc_trans_t t; 1431 ehci_isoc_bufr_ptr_t b, b2, b3; 1432 int i; 1433 1434 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1435 1436 for (i = 0; i < 8;i++) { 1437 t = letoh32(itd->itd.itd_ctl[i]); 1438 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1439 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1440 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1441 EHCI_ITD_GET_OFFS(t)); 1442 } 1443 printf("ITDbufr: "); 1444 for (i = 0; i < 7; i++) 1445 printf("%X,", EHCI_ITD_GET_BPTR(letoh32(itd->itd.itd_bufr[i]))); 1446 1447 b = letoh32(itd->itd.itd_bufr[0]); 1448 b2 = letoh32(itd->itd.itd_bufr[1]); 1449 b3 = letoh32(itd->itd.itd_bufr[2]); 1450 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1451 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1452 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1453 } 1454 1455 void 1456 ehci_dump_sitd(struct ehci_soft_itd *itd) 1457 { 1458 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1459 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1460 itd->xfer_next, itd->physaddr, itd->slot); 1461 } 1462 #endif 1463 1464 #ifdef DIAGNOSTIC 1465 void 1466 ehci_dump_exfer(struct ehci_xfer *ex) 1467 { 1468 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p " 1469 "isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, 1470 ex->itdend, ex->isdone); 1471 } 1472 #endif 1473 1474 #endif /* EHCI_DEBUG */ 1475 1476 usbd_status 1477 ehci_open(usbd_pipe_handle pipe) 1478 { 1479 usbd_device_handle dev = pipe->device; 1480 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1481 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1482 u_int8_t addr = dev->address; 1483 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1484 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1485 ehci_soft_qh_t *sqh; 1486 usbd_status err; 1487 int s; 1488 int ival, speed, naks; 1489 int hshubaddr, hshubport; 1490 1491 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1492 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1493 1494 if (sc->sc_bus.dying) 1495 return (USBD_IOERROR); 1496 1497 if (dev->myhsport) { 1498 hshubaddr = dev->myhsport->parent->address; 1499 hshubport = dev->myhsport->portno; 1500 } else { 1501 hshubaddr = 0; 1502 hshubport = 0; 1503 } 1504 1505 if (addr == sc->sc_addr) { 1506 switch (ed->bEndpointAddress) { 1507 case USB_CONTROL_ENDPOINT: 1508 pipe->methods = &ehci_root_ctrl_methods; 1509 break; 1510 case UE_DIR_IN | EHCI_INTR_ENDPT: 1511 pipe->methods = &ehci_root_intr_methods; 1512 break; 1513 default: 1514 return (USBD_INVAL); 1515 } 1516 return (USBD_NORMAL_COMPLETION); 1517 } 1518 1519 /* XXX All this stuff is only valid for async. */ 1520 switch (dev->speed) { 1521 case USB_SPEED_LOW: 1522 speed = EHCI_QH_SPEED_LOW; 1523 break; 1524 case USB_SPEED_FULL: 1525 speed = EHCI_QH_SPEED_FULL; 1526 break; 1527 case USB_SPEED_HIGH: 1528 speed = EHCI_QH_SPEED_HIGH; 1529 break; 1530 default: 1531 panic("ehci_open: bad device speed %d", dev->speed); 1532 } 1533 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1534 printf("%s: Error opening low/full speed isoc endpoint.\n" 1535 "A low/full speed device is attached to a USB2 hub, and " 1536 "transaction translations are not yet supported.\n" 1537 "Reattach the device to the root hub instead.\n", 1538 sc->sc_bus.bdev.dv_xname); 1539 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1540 hshubaddr, hshubport)); 1541 return (USBD_INVAL); 1542 } 1543 1544 naks = 8; /* XXX */ 1545 1546 /* Allocate sqh for everything, save isoc xfers */ 1547 if (xfertype != UE_ISOCHRONOUS) { 1548 sqh = ehci_alloc_sqh(sc); 1549 if (sqh == NULL) 1550 return (USBD_NOMEM); 1551 /* qh_link filled when the QH is added */ 1552 sqh->qh.qh_endp = htole32( 1553 EHCI_QH_SET_ADDR(addr) | 1554 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1555 EHCI_QH_SET_EPS(speed) | 1556 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1557 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1558 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1559 EHCI_QH_CTL : 0) | 1560 EHCI_QH_SET_NRL(naks) 1561 ); 1562 sqh->qh.qh_endphub = htole32( 1563 EHCI_QH_SET_MULT(1) | 1564 EHCI_QH_SET_HUBA(hshubaddr) | 1565 EHCI_QH_SET_PORT(hshubport) | 1566 EHCI_QH_SET_CMASK(0x1c) | /* XXX */ 1567 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1568 ); 1569 sqh->qh.qh_curqtd = EHCI_NULL; 1570 /* Fill the overlay qTD */ 1571 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1572 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1573 sqh->qh.qh_qtd.qtd_status = 1574 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1575 1576 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1577 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1578 epipe->sqh = sqh; 1579 } else { 1580 sqh = NULL; 1581 } /*xfertype == UE_ISOC*/ 1582 1583 switch (xfertype) { 1584 case UE_CONTROL: 1585 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1586 0, &epipe->u.ctl.reqdma); 1587 #ifdef EHCI_DEBUG 1588 if (err) 1589 printf("ehci_open: usb_allocmem()=%d\n", err); 1590 #endif 1591 if (err) 1592 goto bad; 1593 pipe->methods = &ehci_device_ctrl_methods; 1594 s = splusb(); 1595 ehci_add_qh(sqh, sc->sc_async_head); 1596 splx(s); 1597 break; 1598 case UE_BULK: 1599 pipe->methods = &ehci_device_bulk_methods; 1600 s = splusb(); 1601 ehci_add_qh(sqh, sc->sc_async_head); 1602 splx(s); 1603 break; 1604 case UE_INTERRUPT: 1605 pipe->methods = &ehci_device_intr_methods; 1606 ival = pipe->interval; 1607 if (ival == USBD_DEFAULT_INTERVAL) 1608 ival = ed->bInterval; 1609 s = splusb(); 1610 err = ehci_device_setintr(sc, sqh, ival); 1611 splx(s); 1612 return (err); 1613 case UE_ISOCHRONOUS: 1614 pipe->methods = &ehci_device_isoc_methods; 1615 if (ed->bInterval == 0 || ed->bInterval > 16) { 1616 printf("ehci: opening pipe with invalid bInterval\n"); 1617 err = USBD_INVAL; 1618 goto bad; 1619 } 1620 if (UGETW(ed->wMaxPacketSize) == 0) { 1621 printf("ehci: zero length endpoint open request\n"); 1622 err = USBD_INVAL; 1623 goto bad; 1624 } 1625 epipe->u.isoc.next_frame = 0; 1626 epipe->u.isoc.cur_xfers = 0; 1627 break; 1628 default: 1629 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1630 return (USBD_INVAL); 1631 } 1632 return (USBD_NORMAL_COMPLETION); 1633 1634 bad: 1635 if (sqh != NULL) 1636 ehci_free_sqh(sc, sqh); 1637 return (err); 1638 } 1639 1640 /* 1641 * Add an ED to the schedule. Called at splusb(). 1642 * If in the async schedule, it will always have a next. 1643 * If in the intr schedule it may not. 1644 */ 1645 void 1646 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1647 { 1648 SPLUSBCHECK; 1649 1650 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1651 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1652 sqh->next = head->next; 1653 sqh->prev = head; 1654 sqh->qh.qh_link = head->qh.qh_link; 1655 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1656 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1657 head->next = sqh; 1658 if (sqh->next) 1659 sqh->next->prev = sqh; 1660 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1661 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1662 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1663 1664 #ifdef EHCI_DEBUG 1665 if (ehcidebug > 5) { 1666 printf("ehci_add_qh:\n"); 1667 ehci_dump_sqh(sqh); 1668 } 1669 #endif 1670 } 1671 1672 /* 1673 * Remove an ED from the schedule. Called at splusb(). 1674 * Will always have a 'next' if it's in the async list as it's circular. 1675 */ 1676 void 1677 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1678 { 1679 SPLUSBCHECK; 1680 /* XXX */ 1681 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1682 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1683 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1684 sqh->prev->next = sqh->next; 1685 if (sqh->next) 1686 sqh->next->prev = sqh->prev; 1687 usb_syncmem(&sqh->prev->dma, 1688 sqh->prev->offs + offsetof(ehci_qh_t, qh_link), 1689 sizeof(sqh->prev->qh.qh_link), BUS_DMASYNC_PREWRITE); 1690 1691 ehci_sync_hc(sc); 1692 } 1693 1694 void 1695 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1696 { 1697 int i; 1698 u_int32_t status; 1699 1700 /* Save toggle bit and ping status. */ 1701 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1702 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1703 status = sqh->qh.qh_qtd.qtd_status & 1704 htole32(EHCI_QTD_TOGGLE_MASK | 1705 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1706 /* Set HALTED to make hw leave it alone. */ 1707 sqh->qh.qh_qtd.qtd_status = 1708 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1709 usb_syncmem(&sqh->dma, 1710 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1711 sizeof(sqh->qh.qh_qtd.qtd_status), 1712 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1713 sqh->qh.qh_curqtd = 0; 1714 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1715 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1716 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1717 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1718 sqh->sqtd = sqtd; 1719 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1720 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1721 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1722 sqh->qh.qh_qtd.qtd_status = status; 1723 usb_syncmem(&sqh->dma, 1724 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1725 sizeof(sqh->qh.qh_qtd.qtd_status), 1726 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1727 } 1728 1729 /* 1730 * Ensure that the HC has released all references to the QH. We do this 1731 * by asking for a Async Advance Doorbell interrupt and then we wait for 1732 * the interrupt. 1733 * To make this easier we first obtain exclusive use of the doorbell. 1734 */ 1735 void 1736 ehci_sync_hc(ehci_softc_t *sc) 1737 { 1738 int s, error; 1739 int tries = 0; 1740 1741 if (sc->sc_bus.dying) { 1742 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1743 return; 1744 } 1745 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1746 /* get doorbell */ 1747 rw_enter_write(&sc->sc_doorbell_lock); 1748 s = splhardusb(); 1749 do { 1750 /* ask for doorbell */ 1751 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | 1752 EHCI_CMD_IAAD); 1753 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1754 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1755 /* bell wait */ 1756 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz / 2); 1757 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1758 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1759 } while (error && ++tries < 10); 1760 splx(s); 1761 /* release doorbell */ 1762 rw_exit_write(&sc->sc_doorbell_lock); 1763 #ifdef DIAGNOSTIC 1764 if (error) 1765 printf("ehci_sync_hc: tsleep() = %d\n", error); 1766 #endif 1767 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1768 } 1769 1770 /*Call at splusb*/ 1771 void 1772 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1773 { 1774 struct ehci_soft_itd *itd, *prev; 1775 1776 prev = NULL; 1777 1778 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1779 panic("ehci isoc xfer being freed, but with no itd chain"); 1780 1781 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1782 prev = itd->u.frame_list.prev; 1783 /* Unlink itd from hardware chain, or frame array */ 1784 if (prev == NULL) { /* We're at the table head */ 1785 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1786 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1787 usb_syncmem(&sc->sc_fldma, 1788 sizeof(ehci_link_t) * itd->slot, 1789 sizeof(ehci_link_t), 1790 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1791 1792 if (itd->u.frame_list.next != NULL) 1793 itd->u.frame_list.next->u.frame_list.prev = 1794 NULL; 1795 } else { 1796 /* XXX this part is untested... */ 1797 prev->itd.itd_next = itd->itd.itd_next; 1798 usb_syncmem(&itd->dma, 1799 itd->offs + offsetof(ehci_itd_t, itd_next), 1800 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1801 1802 prev->u.frame_list.next = itd->u.frame_list.next; 1803 if (itd->u.frame_list.next != NULL) 1804 itd->u.frame_list.next->u.frame_list.prev = 1805 prev; 1806 } 1807 } 1808 1809 prev = NULL; 1810 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1811 if (prev != NULL) 1812 ehci_free_itd(sc, prev); 1813 prev = itd; 1814 } 1815 if (prev) 1816 ehci_free_itd(sc, prev); 1817 exfer->itdstart = NULL; 1818 exfer->itdend = NULL; 1819 } 1820 1821 /***********/ 1822 1823 /* 1824 * Data structures and routines to emulate the root hub. 1825 */ 1826 usb_device_descriptor_t ehci_devd = { 1827 USB_DEVICE_DESCRIPTOR_SIZE, 1828 UDESC_DEVICE, /* type */ 1829 {0x00, 0x02}, /* USB version */ 1830 UDCLASS_HUB, /* class */ 1831 UDSUBCLASS_HUB, /* subclass */ 1832 UDPROTO_HSHUBSTT, /* protocol */ 1833 64, /* max packet */ 1834 {0},{0},{0x00,0x01}, /* device id */ 1835 1,2,0, /* string indicies */ 1836 1 /* # of configurations */ 1837 }; 1838 1839 usb_device_qualifier_t ehci_odevd = { 1840 USB_DEVICE_DESCRIPTOR_SIZE, 1841 UDESC_DEVICE_QUALIFIER, /* type */ 1842 {0x00, 0x02}, /* USB version */ 1843 UDCLASS_HUB, /* class */ 1844 UDSUBCLASS_HUB, /* subclass */ 1845 UDPROTO_FSHUB, /* protocol */ 1846 64, /* max packet */ 1847 1, /* # of configurations */ 1848 0 1849 }; 1850 1851 usb_config_descriptor_t ehci_confd = { 1852 USB_CONFIG_DESCRIPTOR_SIZE, 1853 UDESC_CONFIG, 1854 {USB_CONFIG_DESCRIPTOR_SIZE + 1855 USB_INTERFACE_DESCRIPTOR_SIZE + 1856 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1857 1, 1858 1, 1859 0, 1860 UC_SELF_POWERED, 1861 0 /* max power */ 1862 }; 1863 1864 usb_interface_descriptor_t ehci_ifcd = { 1865 USB_INTERFACE_DESCRIPTOR_SIZE, 1866 UDESC_INTERFACE, 1867 0, 1868 0, 1869 1, 1870 UICLASS_HUB, 1871 UISUBCLASS_HUB, 1872 UIPROTO_HSHUBSTT, 1873 0 1874 }; 1875 1876 usb_endpoint_descriptor_t ehci_endpd = { 1877 USB_ENDPOINT_DESCRIPTOR_SIZE, 1878 UDESC_ENDPOINT, 1879 UE_DIR_IN | EHCI_INTR_ENDPT, 1880 UE_INTERRUPT, 1881 {8, 0}, /* max packet */ 1882 255 1883 }; 1884 1885 usb_hub_descriptor_t ehci_hubd = { 1886 USB_HUB_DESCRIPTOR_SIZE, 1887 UDESC_HUB, 1888 0, 1889 {0,0}, 1890 0, 1891 0, 1892 {0}, 1893 }; 1894 1895 int 1896 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 1897 { 1898 int i; 1899 1900 if (l == 0) 1901 return (0); 1902 p->bLength = 2 * strlen(s) + 2; 1903 if (l == 1) 1904 return (1); 1905 p->bDescriptorType = UDESC_STRING; 1906 l -= 2; 1907 for (i = 0; s[i] && l > 1; i++, l -= 2) 1908 USETW2(p->bString[i], 0, s[i]); 1909 return (2*i+2); 1910 } 1911 1912 /* 1913 * Simulate a hardware hub by handling all the necessary requests. 1914 */ 1915 usbd_status 1916 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1917 { 1918 usbd_status err; 1919 1920 /* Insert last in queue. */ 1921 err = usb_insert_transfer(xfer); 1922 if (err) 1923 return (err); 1924 1925 /* Pipe isn't running, start first */ 1926 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1927 } 1928 1929 usbd_status 1930 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1931 { 1932 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1933 usb_device_request_t *req; 1934 void *buf = NULL; 1935 int port, i; 1936 int s, len, value, index, l, totlen = 0; 1937 usb_port_status_t ps; 1938 usb_hub_descriptor_t hubd; 1939 usbd_status err; 1940 u_int32_t v; 1941 1942 if (sc->sc_bus.dying) 1943 return (USBD_IOERROR); 1944 1945 #ifdef DIAGNOSTIC 1946 if (!(xfer->rqflags & URQ_REQUEST)) 1947 /* XXX panic */ 1948 return (USBD_INVAL); 1949 #endif 1950 req = &xfer->request; 1951 1952 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1953 req->bmRequestType, req->bRequest)); 1954 1955 len = UGETW(req->wLength); 1956 value = UGETW(req->wValue); 1957 index = UGETW(req->wIndex); 1958 1959 if (len != 0) 1960 buf = KERNADDR(&xfer->dmabuf, 0); 1961 1962 #define C(x,y) ((x) | ((y) << 8)) 1963 switch(C(req->bRequest, req->bmRequestType)) { 1964 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1965 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1966 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1967 /* 1968 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1969 * for the integrated root hub. 1970 */ 1971 break; 1972 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1973 if (len > 0) { 1974 *(u_int8_t *)buf = sc->sc_conf; 1975 totlen = 1; 1976 } 1977 break; 1978 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1979 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1980 switch(value >> 8) { 1981 case UDESC_DEVICE: 1982 if ((value & 0xff) != 0) { 1983 err = USBD_IOERROR; 1984 goto ret; 1985 } 1986 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1987 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1988 memcpy(buf, &ehci_devd, l); 1989 break; 1990 /* 1991 * We can't really operate at another speed, but the spec says 1992 * we need this descriptor. 1993 */ 1994 case UDESC_DEVICE_QUALIFIER: 1995 if ((value & 0xff) != 0) { 1996 err = USBD_IOERROR; 1997 goto ret; 1998 } 1999 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2000 memcpy(buf, &ehci_odevd, l); 2001 break; 2002 /* 2003 * We can't really operate at another speed, but the spec says 2004 * we need this descriptor. 2005 */ 2006 case UDESC_OTHER_SPEED_CONFIGURATION: 2007 case UDESC_CONFIG: 2008 if ((value & 0xff) != 0) { 2009 err = USBD_IOERROR; 2010 goto ret; 2011 } 2012 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2013 memcpy(buf, &ehci_confd, l); 2014 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2015 value >> 8; 2016 buf = (char *)buf + l; 2017 len -= l; 2018 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2019 totlen += l; 2020 memcpy(buf, &ehci_ifcd, l); 2021 buf = (char *)buf + l; 2022 len -= l; 2023 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2024 totlen += l; 2025 memcpy(buf, &ehci_endpd, l); 2026 break; 2027 case UDESC_STRING: 2028 if (len == 0) 2029 break; 2030 *(u_int8_t *)buf = 0; 2031 totlen = 1; 2032 switch (value & 0xff) { 2033 case 0: /* Language table */ 2034 totlen = ehci_str(buf, len, "\001"); 2035 break; 2036 case 1: /* Vendor */ 2037 totlen = ehci_str(buf, len, sc->sc_vendor); 2038 break; 2039 case 2: /* Product */ 2040 totlen = ehci_str(buf, len, "EHCI root hub"); 2041 break; 2042 } 2043 break; 2044 default: 2045 err = USBD_IOERROR; 2046 goto ret; 2047 } 2048 break; 2049 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2050 if (len > 0) { 2051 *(u_int8_t *)buf = 0; 2052 totlen = 1; 2053 } 2054 break; 2055 case C(UR_GET_STATUS, UT_READ_DEVICE): 2056 if (len > 1) { 2057 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2058 totlen = 2; 2059 } 2060 break; 2061 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2062 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2063 if (len > 1) { 2064 USETW(((usb_status_t *)buf)->wStatus, 0); 2065 totlen = 2; 2066 } 2067 break; 2068 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2069 if (value >= USB_MAX_DEVICES) { 2070 err = USBD_IOERROR; 2071 goto ret; 2072 } 2073 sc->sc_addr = value; 2074 break; 2075 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2076 if (value != 0 && value != 1) { 2077 err = USBD_IOERROR; 2078 goto ret; 2079 } 2080 sc->sc_conf = value; 2081 break; 2082 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2083 break; 2084 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2085 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2086 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2087 err = USBD_IOERROR; 2088 goto ret; 2089 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2090 break; 2091 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2092 break; 2093 /* Hub requests */ 2094 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2095 break; 2096 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2097 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2098 "port=%d feature=%d\n", index, value)); 2099 if (index < 1 || index > sc->sc_noport) { 2100 err = USBD_IOERROR; 2101 goto ret; 2102 } 2103 port = EHCI_PORTSC(index); 2104 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2105 switch(value) { 2106 case UHF_PORT_ENABLE: 2107 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2108 break; 2109 case UHF_PORT_SUSPEND: 2110 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 2111 break; 2112 case UHF_PORT_POWER: 2113 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2114 break; 2115 case UHF_PORT_TEST: 2116 DPRINTFN(2,("ehci_root_ctrl_start: " 2117 "clear port test %d\n", index)); 2118 break; 2119 case UHF_PORT_INDICATOR: 2120 DPRINTFN(2,("ehci_root_ctrl_start: " 2121 "clear port index %d\n", index)); 2122 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2123 break; 2124 case UHF_C_PORT_CONNECTION: 2125 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2126 break; 2127 case UHF_C_PORT_ENABLE: 2128 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2129 break; 2130 case UHF_C_PORT_SUSPEND: 2131 /* how? */ 2132 break; 2133 case UHF_C_PORT_OVER_CURRENT: 2134 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2135 break; 2136 case UHF_C_PORT_RESET: 2137 sc->sc_isreset = 0; 2138 break; 2139 default: 2140 err = USBD_IOERROR; 2141 goto ret; 2142 } 2143 break; 2144 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2145 if ((value & 0xff) != 0) { 2146 err = USBD_IOERROR; 2147 goto ret; 2148 } 2149 hubd = ehci_hubd; 2150 hubd.bNbrPorts = sc->sc_noport; 2151 v = EOREAD4(sc, EHCI_HCSPARAMS); 2152 USETW(hubd.wHubCharacteristics, 2153 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2154 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2155 ? UHD_PORT_IND : 0); 2156 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2157 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2158 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2159 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2160 l = min(len, hubd.bDescLength); 2161 totlen = l; 2162 memcpy(buf, &hubd, l); 2163 break; 2164 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2165 if (len != 4) { 2166 err = USBD_IOERROR; 2167 goto ret; 2168 } 2169 memset(buf, 0, len); /* ? XXX */ 2170 totlen = len; 2171 break; 2172 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2173 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2174 index)); 2175 if (index < 1 || index > sc->sc_noport) { 2176 err = USBD_IOERROR; 2177 goto ret; 2178 } 2179 if (len != 4) { 2180 err = USBD_IOERROR; 2181 goto ret; 2182 } 2183 v = EOREAD4(sc, EHCI_PORTSC(index)); 2184 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2185 i = UPS_HIGH_SPEED; 2186 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2187 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2188 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2189 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2190 if (v & EHCI_PS_PR) i |= UPS_RESET; 2191 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2192 USETW(ps.wPortStatus, i); 2193 i = 0; 2194 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2195 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2196 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2197 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2198 USETW(ps.wPortChange, i); 2199 l = min(len, sizeof(ps)); 2200 memcpy(buf, &ps, l); 2201 totlen = l; 2202 break; 2203 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2204 err = USBD_IOERROR; 2205 goto ret; 2206 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2207 break; 2208 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2209 if (index < 1 || index > sc->sc_noport) { 2210 err = USBD_IOERROR; 2211 goto ret; 2212 } 2213 port = EHCI_PORTSC(index); 2214 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2215 switch(value) { 2216 case UHF_PORT_ENABLE: 2217 EOWRITE4(sc, port, v | EHCI_PS_PE); 2218 break; 2219 case UHF_PORT_SUSPEND: 2220 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2221 break; 2222 case UHF_PORT_DISOWN_TO_1_1: 2223 /* enter to Port Reset State */ 2224 v &= ~EHCI_PS_PE; 2225 EOWRITE4(sc, port, v | EHCI_PS_PR); 2226 ehci_disown(sc, index, 0); 2227 break; 2228 case UHF_PORT_RESET: 2229 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2230 index)); 2231 if (EHCI_PS_IS_LOWSPEED(v)) { 2232 /* Low speed device, give up ownership. */ 2233 ehci_disown(sc, index, 1); 2234 break; 2235 } 2236 /* Start reset sequence. */ 2237 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2238 EOWRITE4(sc, port, v | EHCI_PS_PR); 2239 /* Wait for reset to complete. */ 2240 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2241 if (sc->sc_bus.dying) { 2242 err = USBD_IOERROR; 2243 goto ret; 2244 } 2245 /* Terminate reset sequence. */ 2246 v = EOREAD4(sc, port); 2247 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2248 /* Wait for HC to complete reset. */ 2249 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2250 if (sc->sc_bus.dying) { 2251 err = USBD_IOERROR; 2252 goto ret; 2253 } 2254 v = EOREAD4(sc, port); 2255 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2256 if (v & EHCI_PS_PR) { 2257 printf("%s: port reset timeout\n", 2258 sc->sc_bus.bdev.dv_xname); 2259 err = USBD_IOERROR; 2260 goto ret; 2261 } 2262 if (!(v & EHCI_PS_PE)) { 2263 /* Not a high speed device, give up ownership.*/ 2264 ehci_disown(sc, index, 0); 2265 break; 2266 } 2267 sc->sc_isreset = 1; 2268 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2269 index, v)); 2270 break; 2271 case UHF_PORT_POWER: 2272 DPRINTFN(2,("ehci_root_ctrl_start: " 2273 "set port power %d\n", index)); 2274 EOWRITE4(sc, port, v | EHCI_PS_PP); 2275 break; 2276 case UHF_PORT_TEST: 2277 DPRINTFN(2,("ehci_root_ctrl_start: " 2278 "set port test %d\n", index)); 2279 break; 2280 case UHF_PORT_INDICATOR: 2281 DPRINTFN(2,("ehci_root_ctrl_start: " 2282 "set port ind %d\n", index)); 2283 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2284 break; 2285 default: 2286 err = USBD_IOERROR; 2287 goto ret; 2288 } 2289 break; 2290 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2291 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2292 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2293 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2294 break; 2295 default: 2296 err = USBD_IOERROR; 2297 goto ret; 2298 } 2299 xfer->actlen = totlen; 2300 err = USBD_NORMAL_COMPLETION; 2301 ret: 2302 xfer->status = err; 2303 s = splusb(); 2304 usb_transfer_complete(xfer); 2305 splx(s); 2306 return (USBD_IN_PROGRESS); 2307 } 2308 2309 void 2310 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2311 { 2312 int port; 2313 u_int32_t v; 2314 2315 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2316 2317 port = EHCI_PORTSC(index); 2318 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2319 EOWRITE4(sc, port, v | EHCI_PS_PO); 2320 } 2321 2322 /* Abort a root control request. */ 2323 void 2324 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2325 { 2326 /* Nothing to do, all transfers are synchronous. */ 2327 } 2328 2329 /* Close the root pipe. */ 2330 void 2331 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2332 { 2333 DPRINTF(("ehci_root_ctrl_close\n")); 2334 /* Nothing to do. */ 2335 } 2336 2337 void 2338 ehci_root_intr_done(usbd_xfer_handle xfer) 2339 { 2340 } 2341 2342 usbd_status 2343 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2344 { 2345 usbd_status err; 2346 2347 /* Insert last in queue. */ 2348 err = usb_insert_transfer(xfer); 2349 if (err) 2350 return (err); 2351 2352 /* Pipe isn't running, start first */ 2353 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2354 } 2355 2356 usbd_status 2357 ehci_root_intr_start(usbd_xfer_handle xfer) 2358 { 2359 usbd_pipe_handle pipe = xfer->pipe; 2360 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2361 2362 if (sc->sc_bus.dying) 2363 return (USBD_IOERROR); 2364 2365 sc->sc_intrxfer = xfer; 2366 2367 return (USBD_IN_PROGRESS); 2368 } 2369 2370 /* Abort a root interrupt request. */ 2371 void 2372 ehci_root_intr_abort(usbd_xfer_handle xfer) 2373 { 2374 int s; 2375 2376 if (xfer->pipe->intrxfer == xfer) { 2377 DPRINTF(("ehci_root_intr_abort: remove\n")); 2378 xfer->pipe->intrxfer = NULL; 2379 } 2380 xfer->status = USBD_CANCELLED; 2381 s = splusb(); 2382 usb_transfer_complete(xfer); 2383 splx(s); 2384 } 2385 2386 /* Close the root pipe. */ 2387 void 2388 ehci_root_intr_close(usbd_pipe_handle pipe) 2389 { 2390 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2391 2392 DPRINTF(("ehci_root_intr_close\n")); 2393 2394 sc->sc_intrxfer = NULL; 2395 } 2396 2397 void 2398 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2399 { 2400 } 2401 2402 /************************/ 2403 2404 ehci_soft_qh_t * 2405 ehci_alloc_sqh(ehci_softc_t *sc) 2406 { 2407 ehci_soft_qh_t *sqh; 2408 usbd_status err; 2409 int i, offs; 2410 usb_dma_t dma; 2411 2412 if (sc->sc_freeqhs == NULL) { 2413 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2414 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2415 EHCI_PAGE_SIZE, &dma); 2416 #ifdef EHCI_DEBUG 2417 if (err) 2418 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2419 #endif 2420 if (err) 2421 return (NULL); 2422 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2423 offs = i * EHCI_SQH_SIZE; 2424 sqh = KERNADDR(&dma, offs); 2425 sqh->physaddr = DMAADDR(&dma, offs); 2426 sqh->dma = dma; 2427 sqh->offs = offs; 2428 sqh->next = sc->sc_freeqhs; 2429 sc->sc_freeqhs = sqh; 2430 } 2431 } 2432 sqh = sc->sc_freeqhs; 2433 sc->sc_freeqhs = sqh->next; 2434 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2435 sqh->next = NULL; 2436 sqh->prev = NULL; 2437 return (sqh); 2438 } 2439 2440 void 2441 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2442 { 2443 sqh->next = sc->sc_freeqhs; 2444 sc->sc_freeqhs = sqh; 2445 } 2446 2447 ehci_soft_qtd_t * 2448 ehci_alloc_sqtd(ehci_softc_t *sc) 2449 { 2450 ehci_soft_qtd_t *sqtd; 2451 usbd_status err; 2452 int i, offs; 2453 usb_dma_t dma; 2454 int s; 2455 2456 if (sc->sc_freeqtds == NULL) { 2457 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2458 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2459 EHCI_PAGE_SIZE, &dma); 2460 #ifdef EHCI_DEBUG 2461 if (err) 2462 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2463 #endif 2464 if (err) 2465 return (NULL); 2466 s = splusb(); 2467 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2468 offs = i * EHCI_SQTD_SIZE; 2469 sqtd = KERNADDR(&dma, offs); 2470 sqtd->physaddr = DMAADDR(&dma, offs); 2471 sqtd->dma = dma; 2472 sqtd->offs = offs; 2473 sqtd->nextqtd = sc->sc_freeqtds; 2474 sc->sc_freeqtds = sqtd; 2475 } 2476 splx(s); 2477 } 2478 2479 s = splusb(); 2480 sqtd = sc->sc_freeqtds; 2481 sc->sc_freeqtds = sqtd->nextqtd; 2482 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2483 sqtd->nextqtd = NULL; 2484 sqtd->xfer = NULL; 2485 splx(s); 2486 2487 return (sqtd); 2488 } 2489 2490 void 2491 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2492 { 2493 int s; 2494 2495 s = splusb(); 2496 sqtd->nextqtd = sc->sc_freeqtds; 2497 sc->sc_freeqtds = sqtd; 2498 splx(s); 2499 } 2500 2501 usbd_status 2502 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, u_int alen, 2503 int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2504 { 2505 ehci_soft_qtd_t *next, *cur; 2506 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2507 u_int32_t qtdstatus; 2508 u_int len, curlen; 2509 int mps, i, iscontrol, forceshort; 2510 usb_dma_t *dma = &xfer->dmabuf; 2511 2512 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2513 2514 len = alen; 2515 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2516 UE_CONTROL; 2517 2518 dataphys = DMAADDR(dma, 0); 2519 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2520 qtdstatus = EHCI_QTD_ACTIVE | 2521 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2522 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */ 2523 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2524 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2525 len % mps == 0; 2526 /* 2527 * The control transfer data stage always starts with a toggle of 1. 2528 * For other transfers we let the hardware track the toggle state. 2529 */ 2530 if (iscontrol) 2531 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2532 2533 cur = ehci_alloc_sqtd(sc); 2534 *sp = cur; 2535 if (cur == NULL) 2536 goto nomem; 2537 2538 usb_syncmem(dma, 0, alen, 2539 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2540 for (;;) { 2541 dataphyspage = EHCI_PAGE(dataphys); 2542 /* The EHCI hardware can handle at most 5 pages. */ 2543 if (dataphyslastpage - dataphyspage < 2544 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2545 /* we can handle it in this QTD */ 2546 curlen = len; 2547 } else { 2548 /* must use multiple TDs, fill as much as possible. */ 2549 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2550 EHCI_PAGE_OFFSET(dataphys); 2551 #ifdef DIAGNOSTIC 2552 if (curlen > len) { 2553 printf("ehci_alloc_sqtd_chain: curlen=%u " 2554 "len=%u offs=0x%x\n", curlen, len, 2555 EHCI_PAGE_OFFSET(dataphys)); 2556 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2557 dataphyslastpage, dataphyspage, dataphys); 2558 curlen = len; 2559 } 2560 #endif 2561 /* the length must be a multiple of the max size */ 2562 curlen -= curlen % mps; 2563 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2564 "curlen=%u\n", curlen)); 2565 #ifdef DIAGNOSTIC 2566 if (curlen == 0) 2567 panic("ehci_alloc_std: curlen == 0"); 2568 #endif 2569 } 2570 2571 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2572 "dataphyslastpage=0x%08x len=%u curlen=%u\n", 2573 dataphys, dataphyslastpage, len, curlen)); 2574 len -= curlen; 2575 2576 /* 2577 * Allocate another transfer if there's more data left, 2578 * or if force last short transfer flag is set and we're 2579 * allocating a multiple of the max packet size. 2580 */ 2581 if (len != 0 || forceshort) { 2582 next = ehci_alloc_sqtd(sc); 2583 if (next == NULL) 2584 goto nomem; 2585 nextphys = htole32(next->physaddr); 2586 } else { 2587 next = NULL; 2588 nextphys = EHCI_NULL; 2589 } 2590 2591 for (i = 0; i * EHCI_PAGE_SIZE < 2592 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2593 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2594 if (i != 0) /* use offset only in first buffer */ 2595 a = EHCI_PAGE(a); 2596 #ifdef DIAGNOSTIC 2597 if (i >= EHCI_QTD_NBUFFERS) { 2598 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2599 goto nomem; 2600 } 2601 #endif 2602 cur->qtd.qtd_buffer[i] = htole32(a); 2603 cur->qtd.qtd_buffer_hi[i] = 0; 2604 } 2605 cur->nextqtd = next; 2606 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2607 cur->qtd.qtd_status = htole32(qtdstatus | 2608 EHCI_QTD_SET_BYTES(curlen)); 2609 cur->xfer = xfer; 2610 cur->len = curlen; 2611 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2612 dataphys, dataphys + curlen)); 2613 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%u\n", curlen)); 2614 if (iscontrol) { 2615 /* 2616 * adjust the toggle based on the number of packets 2617 * in this qtd 2618 */ 2619 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2620 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2621 } 2622 if (len == 0) { 2623 if (! forceshort) 2624 break; 2625 forceshort = 0; 2626 } 2627 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2628 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2629 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2630 dataphys += curlen; 2631 cur = next; 2632 } 2633 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2634 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2635 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2636 *ep = cur; 2637 2638 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2639 *sp, *ep)); 2640 2641 return (USBD_NORMAL_COMPLETION); 2642 2643 nomem: 2644 /* XXX free chain */ 2645 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2646 return (USBD_NOMEM); 2647 } 2648 2649 void 2650 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2651 ehci_soft_qtd_t *sqtdend) 2652 { 2653 ehci_soft_qtd_t *p; 2654 int i; 2655 2656 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2657 sqtd, sqtdend)); 2658 2659 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2660 p = sqtd->nextqtd; 2661 ehci_free_sqtd(sc, sqtd); 2662 } 2663 } 2664 2665 ehci_soft_itd_t * 2666 ehci_alloc_itd(ehci_softc_t *sc) 2667 { 2668 struct ehci_soft_itd *itd, *freeitd; 2669 usbd_status err; 2670 int i, s, offs, frindex, previndex; 2671 usb_dma_t dma; 2672 2673 s = splusb(); 2674 2675 /* Find an itd that wasn't freed this frame or last frame. This can 2676 * discard itds that were freed before frindex wrapped around 2677 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2678 * interrupt and fiddling with list when that happens */ 2679 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2680 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2681 2682 freeitd = NULL; 2683 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2684 if (itd == NULL) 2685 break; 2686 if (itd->slot != frindex && itd->slot != previndex) { 2687 freeitd = itd; 2688 break; 2689 } 2690 } 2691 2692 if (freeitd == NULL) { 2693 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2694 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2695 EHCI_PAGE_SIZE, &dma); 2696 2697 if (err) { 2698 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2699 return (NULL); 2700 } 2701 2702 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2703 offs = i * EHCI_ITD_SIZE; 2704 itd = KERNADDR(&dma, offs); 2705 itd->physaddr = DMAADDR(&dma, offs); 2706 itd->dma = dma; 2707 itd->offs = offs; 2708 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2709 } 2710 freeitd = LIST_FIRST(&sc->sc_freeitds); 2711 } 2712 2713 itd = freeitd; 2714 LIST_REMOVE(itd, u.free_list); 2715 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2716 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2717 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2718 BUS_DMASYNC_PREREAD); 2719 2720 itd->u.frame_list.next = NULL; 2721 itd->u.frame_list.prev = NULL; 2722 itd->xfer_next = NULL; 2723 itd->slot = 0; 2724 splx(s); 2725 2726 return (itd); 2727 } 2728 2729 void 2730 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2731 { 2732 int s; 2733 2734 s = splusb(); 2735 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2736 splx(s); 2737 } 2738 2739 /****************/ 2740 2741 /* 2742 * Close a reqular pipe. 2743 * Assumes that there are no pending transactions. 2744 */ 2745 void 2746 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2747 { 2748 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2749 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2750 ehci_soft_qh_t *sqh = epipe->sqh; 2751 int s; 2752 2753 s = splusb(); 2754 ehci_rem_qh(sc, sqh, head); 2755 splx(s); 2756 pipe->endpoint->savedtoggle = 2757 EHCI_QTD_GET_TOGGLE(letoh32(sqh->qh.qh_qtd.qtd_status)); 2758 ehci_free_sqh(sc, epipe->sqh); 2759 } 2760 2761 /* 2762 * Abort a device request. 2763 * If this routine is called at splusb() it guarantees that the request 2764 * will be removed from the hardware scheduling and that the callback 2765 * for it will be called with USBD_CANCELLED status. 2766 * It's impossible to guarantee that the requested transfer will not 2767 * have happened since the hardware runs concurrently. 2768 * If the transaction has already happened we rely on the ordinary 2769 * interrupt processing to process it. 2770 */ 2771 void 2772 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2773 { 2774 #define exfer EXFER(xfer) 2775 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2776 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2777 ehci_soft_qh_t *sqh = epipe->sqh; 2778 ehci_soft_qtd_t *sqtd, *snext, **psqtd; 2779 ehci_physaddr_t cur, us, next; 2780 int s; 2781 int hit; 2782 ehci_soft_qh_t *psqh; 2783 2784 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2785 2786 if (sc->sc_bus.dying) { 2787 /* If we're dying, just do the software part. */ 2788 s = splusb(); 2789 xfer->status = status; /* make software ignore it */ 2790 timeout_del(&xfer->timeout_handle); 2791 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2792 usb_transfer_complete(xfer); 2793 splx(s); 2794 return; 2795 } 2796 2797 if (xfer->device->bus->intr_context) 2798 panic("ehci_abort_xfer: not in process context"); 2799 2800 /* 2801 * If an abort is already in progress then just wait for it to 2802 * complete and return. 2803 */ 2804 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2805 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2806 /* No need to wait if we're aborting from a timeout. */ 2807 if (status == USBD_TIMEOUT) 2808 return; 2809 /* Override the status which might be USBD_TIMEOUT. */ 2810 xfer->status = status; 2811 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2812 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2813 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 2814 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciaw", 0); 2815 return; 2816 } 2817 2818 /* 2819 * Step 1: Make interrupt routine and timeouts ignore xfer. 2820 */ 2821 s = splusb(); 2822 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2823 xfer->status = status; /* make software ignore it */ 2824 timeout_del(&xfer->timeout_handle); 2825 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2826 splx(s); 2827 2828 /* 2829 * Step 2: Wait until we know hardware has finished any possible 2830 * use of the xfer. We do this by removing the entire 2831 * queue from the async schedule and waiting for the doorbell. 2832 * Nothing else should be touching the queue now. 2833 */ 2834 psqh = sqh->prev; 2835 ehci_rem_qh(sc, sqh, psqh); 2836 2837 /* 2838 * Step 3: Deactivate all of the qTDs that we will be removing, 2839 * otherwise the queue head may go active again. The EHCI spec 2840 * suggests we should perform the deactivation before removing the 2841 * queue head from the schedule, however the VT6202 (at least) only 2842 * behaves correctly when we deactivate them afterwards. 2843 */ 2844 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2845 usb_syncmem(&sqtd->dma, 2846 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2847 sizeof(sqtd->qtd.qtd_status), 2848 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2849 sqtd->qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2850 usb_syncmem(&sqtd->dma, 2851 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2852 sizeof(sqtd->qtd.qtd_status), 2853 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2854 if (sqtd == exfer->sqtdend) 2855 break; 2856 } 2857 ehci_sync_hc(sc); 2858 2859 /* 2860 * Step 4: make sure the soft interrupt routine 2861 * has run. This should remove any completed items off the queue. 2862 * The hardware has no reference to completed items (TDs). 2863 * It's safe to remove them at any time. 2864 * use of the xfer. Also make sure the soft interrupt routine 2865 * has run. 2866 */ 2867 s = splusb(); 2868 sc->sc_softwake = 1; 2869 usb_schedsoftintr(&sc->sc_bus); 2870 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2871 2872 /* 2873 * Step 5: Remove any vestiges of the xfer from the hardware. 2874 * The complication here is that the hardware may have executed 2875 * into or even beyond the xfer we're trying to abort. 2876 * So as we're scanning the TDs of this xfer we check if 2877 * the hardware points to any of them. 2878 * 2879 * first we need to see if there are any transfers 2880 * on this queue before the xfer we are aborting.. we need 2881 * to update any pointers that point to us to point past 2882 * the aborting xfer. (If there is something past us). 2883 * Hardware and software. 2884 */ 2885 usb_syncmem(&sqh->dma, 2886 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2887 sizeof(sqh->qh.qh_curqtd), 2888 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2889 cur = EHCI_LINK_ADDR(letoh32(sqh->qh.qh_curqtd)); 2890 hit = 0; 2891 2892 /* If they initially point here. */ 2893 us = exfer->sqtdstart->physaddr; 2894 2895 /* We will change them to point here */ 2896 snext = exfer->sqtdend->nextqtd; 2897 next = snext ? snext->physaddr : EHCI_NULL; 2898 2899 /* 2900 * Now loop through any qTDs before us and keep track of the pointer 2901 * that points to us for the end. 2902 */ 2903 psqtd = &sqh->sqtd; 2904 sqtd = sqh->sqtd; 2905 while (sqtd && sqtd != exfer->sqtdstart) { 2906 hit |= (cur == sqtd->physaddr); 2907 if (EHCI_LINK_ADDR(letoh32(sqtd->qtd.qtd_next)) == us) 2908 sqtd->qtd.qtd_next = next; 2909 if (EHCI_LINK_ADDR(letoh32(sqtd->qtd.qtd_altnext)) == us) 2910 sqtd->qtd.qtd_altnext = next; 2911 psqtd = &sqtd->nextqtd; 2912 sqtd = sqtd->nextqtd; 2913 } 2914 /* make the software pointer bypass us too */ 2915 *psqtd = exfer->sqtdend->nextqtd; 2916 2917 /* 2918 * If we already saw the active one then we are pretty much done. 2919 * We've done all the relinking we need to do. 2920 */ 2921 if (!hit) { 2922 2923 /* 2924 * Now reinitialise the QH to point to the next qTD 2925 * (if there is one). We only need to do this if 2926 * it was previously pointing to us. 2927 * XXX Not quite sure what to do about the data toggle. 2928 */ 2929 sqtd = exfer->sqtdstart; 2930 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2931 if (cur == sqtd->physaddr) { 2932 hit++; 2933 } 2934 if (sqtd == exfer->sqtdend) 2935 break; 2936 } 2937 /* 2938 * Only need to alter the QH if it was pointing at a qTD 2939 * that we are removing. 2940 */ 2941 if (hit) { 2942 if (snext) { 2943 ehci_set_qh_qtd(sqh, snext); 2944 } else { 2945 2946 sqh->qh.qh_curqtd = 0; /* unlink qTDs */ 2947 sqh->qh.qh_qtd.qtd_status = 0; 2948 sqh->qh.qh_qtd.qtd_next = 2949 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2950 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2951 } 2952 } 2953 } 2954 ehci_add_qh(sqh, psqh); 2955 2956 /* 2957 * Step 6: Execute callback. 2958 */ 2959 #ifdef DIAGNOSTIC 2960 exfer->isdone = 1; 2961 #endif 2962 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2963 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 2964 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 2965 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 2966 wakeup(&exfer->ehci_xfer_flags); 2967 } 2968 usb_transfer_complete(xfer); 2969 2970 splx(s); 2971 #undef exfer 2972 } 2973 2974 void 2975 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 2976 { 2977 ehci_isoc_trans_t trans_status; 2978 struct ehci_pipe *epipe; 2979 struct ehci_xfer *exfer; 2980 ehci_softc_t *sc; 2981 struct ehci_soft_itd *itd; 2982 int s, i, wake; 2983 2984 epipe = (struct ehci_pipe *) xfer->pipe; 2985 exfer = EXFER(xfer); 2986 sc = (ehci_softc_t *)epipe->pipe.device->bus; 2987 2988 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 2989 2990 if (sc->sc_bus.dying) { 2991 s = splusb(); 2992 xfer->status = status; 2993 timeout_del(&xfer->timeout_handle); 2994 usb_transfer_complete(xfer); 2995 splx(s); 2996 return; 2997 } 2998 2999 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 3000 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3001 3002 #ifdef DIAGNOSTIC 3003 if (status == USBD_TIMEOUT) 3004 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3005 #endif 3006 3007 xfer->status = status; 3008 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3009 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 3010 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 3011 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciiaw", 0); 3012 return; 3013 } 3014 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 3015 3016 xfer->status = status; 3017 timeout_del(&xfer->timeout_handle); 3018 3019 s = splusb(); 3020 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3021 for (i = 0; i < 8; i++) { 3022 trans_status = letoh32(itd->itd.itd_ctl[i]); 3023 trans_status &= ~EHCI_ITD_ACTIVE; 3024 itd->itd.itd_ctl[i] = htole32(trans_status); 3025 } 3026 } 3027 splx(s); 3028 3029 s = splusb(); 3030 sc->sc_softwake = 1; 3031 usb_schedsoftintr(&sc->sc_bus); 3032 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3033 splx(s); 3034 3035 #ifdef DIAGNOSTIC 3036 exfer->isdone = 1; 3037 #endif 3038 wake = exfer->ehci_xfer_flags & EHCI_XFER_ABORTING; 3039 exfer->ehci_xfer_flags &= ~(EHCI_XFER_ABORTING | EHCI_XFER_ABORTWAIT); 3040 usb_transfer_complete(xfer); 3041 if (wake) 3042 wakeup(&exfer->ehci_xfer_flags); 3043 3044 return; 3045 } 3046 3047 void 3048 ehci_timeout(void *addr) 3049 { 3050 struct ehci_xfer *exfer = addr; 3051 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3052 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 3053 3054 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3055 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 3056 if (ehcidebug > 1) 3057 usbd_dump_pipe(exfer->xfer.pipe); 3058 #endif 3059 3060 if (sc->sc_bus.dying) { 3061 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3062 return; 3063 } 3064 3065 /* Execute the abort in a process context. */ 3066 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task); 3067 } 3068 3069 void 3070 ehci_timeout_task(void *addr) 3071 { 3072 usbd_xfer_handle xfer = addr; 3073 int s; 3074 3075 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3076 3077 s = splusb(); 3078 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3079 splx(s); 3080 } 3081 3082 /* 3083 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3084 * qTD status, or miss signalling occasionally under heavy load. If the host 3085 * machine is too fast, we we can miss transaction completion - when we scan 3086 * the active list the transaction still seems to be active. This generally 3087 * exhibits itself as a umass stall that never recovers. 3088 * 3089 * We work around this behaviour by setting up this callback after any softintr 3090 * that completes with transactions still pending, giving us another chance to 3091 * check for completion after the writeback has taken place. 3092 */ 3093 void 3094 ehci_intrlist_timeout(void *arg) 3095 { 3096 ehci_softc_t *sc = arg; 3097 int s; 3098 3099 if (sc->sc_bus.dying) 3100 return; 3101 3102 s = splusb(); 3103 DPRINTFN(1, ("ehci_intrlist_timeout\n")); 3104 usb_schedsoftintr(&sc->sc_bus); 3105 splx(s); 3106 } 3107 3108 /************************/ 3109 3110 usbd_status 3111 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3112 { 3113 usbd_status err; 3114 3115 /* Insert last in queue. */ 3116 err = usb_insert_transfer(xfer); 3117 if (err) 3118 return (err); 3119 3120 /* Pipe isn't running, start first */ 3121 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3122 } 3123 3124 usbd_status 3125 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3126 { 3127 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3128 usbd_status err; 3129 3130 if (sc->sc_bus.dying) 3131 return (USBD_IOERROR); 3132 3133 #ifdef DIAGNOSTIC 3134 if (!(xfer->rqflags & URQ_REQUEST)) { 3135 /* XXX panic */ 3136 printf("ehci_device_ctrl_transfer: not a request\n"); 3137 return (USBD_INVAL); 3138 } 3139 #endif 3140 3141 err = ehci_device_request(xfer); 3142 if (err) 3143 return (err); 3144 3145 if (sc->sc_bus.use_polling) 3146 ehci_waitintr(sc, xfer); 3147 return (USBD_IN_PROGRESS); 3148 } 3149 3150 void 3151 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3152 { 3153 struct ehci_xfer *ex = EXFER(xfer); 3154 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3155 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 3156 3157 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3158 3159 #ifdef DIAGNOSTIC 3160 if (!(xfer->rqflags & URQ_REQUEST)) { 3161 panic("ehci_ctrl_done: not a request"); 3162 } 3163 #endif 3164 3165 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3166 ehci_del_intr_list(sc, ex); /* remove from active list */ 3167 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3168 } 3169 3170 DPRINTFN(5, ("ehci_ctrl_done: length=%u\n", xfer->actlen)); 3171 } 3172 3173 /* Abort a device control request. */ 3174 void 3175 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3176 { 3177 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3178 ehci_abort_xfer(xfer, USBD_CANCELLED); 3179 } 3180 3181 /* Close a device control pipe. */ 3182 void 3183 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3184 { 3185 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3186 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3187 3188 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3189 ehci_close_pipe(pipe, sc->sc_async_head); 3190 } 3191 3192 usbd_status 3193 ehci_device_request(usbd_xfer_handle xfer) 3194 { 3195 #define exfer EXFER(xfer) 3196 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3197 usb_device_request_t *req = &xfer->request; 3198 usbd_device_handle dev = epipe->pipe.device; 3199 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3200 int addr = dev->address; 3201 ehci_soft_qtd_t *setup, *stat, *next; 3202 ehci_soft_qh_t *sqh; 3203 int isread; 3204 u_int len; 3205 usbd_status err; 3206 int s; 3207 3208 isread = req->bmRequestType & UT_READ; 3209 len = UGETW(req->wLength); 3210 3211 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3212 "wValue=0x%04x, wIndex=0x%04x len=%u, addr=%d, endpt=%d\n", 3213 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3214 UGETW(req->wIndex), len, addr, 3215 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3216 3217 setup = ehci_alloc_sqtd(sc); 3218 if (setup == NULL) { 3219 err = USBD_NOMEM; 3220 goto bad1; 3221 } 3222 stat = ehci_alloc_sqtd(sc); 3223 if (stat == NULL) { 3224 err = USBD_NOMEM; 3225 goto bad2; 3226 } 3227 3228 sqh = epipe->sqh; 3229 epipe->u.ctl.length = len; 3230 3231 /* Update device address and length since they may have changed 3232 during the setup of the control pipe in usbd_new_device(). */ 3233 /* XXX This only needs to be done once, but it's too early in open. */ 3234 /* XXXX Should not touch ED here! */ 3235 sqh->qh.qh_endp = 3236 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3237 htole32( 3238 EHCI_QH_SET_ADDR(addr) | 3239 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3240 ); 3241 3242 /* Set up data transaction */ 3243 if (len != 0) { 3244 ehci_soft_qtd_t *end; 3245 3246 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3247 &next, &end); 3248 if (err) 3249 goto bad3; 3250 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3251 end->nextqtd = stat; 3252 end->qtd.qtd_next = 3253 end->qtd.qtd_altnext = htole32(stat->physaddr); 3254 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3255 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3256 } else { 3257 next = stat; 3258 } 3259 3260 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3261 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3262 3263 /* Clear toggle */ 3264 setup->qtd.qtd_status = htole32( 3265 EHCI_QTD_ACTIVE | 3266 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3267 EHCI_QTD_SET_CERR(3) | 3268 EHCI_QTD_SET_TOGGLE(0) | 3269 EHCI_QTD_SET_BYTES(sizeof(*req))); 3270 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3271 setup->qtd.qtd_buffer_hi[0] = 0; 3272 setup->nextqtd = next; 3273 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3274 setup->xfer = xfer; 3275 setup->len = sizeof(*req); 3276 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3277 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3278 3279 stat->qtd.qtd_status = htole32( 3280 EHCI_QTD_ACTIVE | 3281 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3282 EHCI_QTD_SET_CERR(3) | 3283 EHCI_QTD_SET_TOGGLE(1) | 3284 EHCI_QTD_IOC); 3285 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3286 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3287 stat->nextqtd = NULL; 3288 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3289 stat->xfer = xfer; 3290 stat->len = 0; 3291 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3292 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3293 3294 #ifdef EHCI_DEBUG 3295 if (ehcidebug > 5) { 3296 DPRINTF(("ehci_device_request:\n")); 3297 ehci_dump_sqh(sqh); 3298 ehci_dump_sqtds(setup); 3299 } 3300 #endif 3301 3302 exfer->sqtdstart = setup; 3303 exfer->sqtdend = stat; 3304 #ifdef DIAGNOSTIC 3305 if (!exfer->isdone) { 3306 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3307 } 3308 exfer->isdone = 0; 3309 #endif 3310 3311 /* Insert qTD in QH list. */ 3312 s = splusb(); 3313 ehci_set_qh_qtd(sqh, setup); 3314 if (xfer->timeout && !sc->sc_bus.use_polling) { 3315 timeout_del(&xfer->timeout_handle); 3316 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3317 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3318 } 3319 ehci_add_intr_list(sc, exfer); 3320 xfer->status = USBD_IN_PROGRESS; 3321 splx(s); 3322 3323 #ifdef EHCI_DEBUG 3324 if (ehcidebug > 10) { 3325 DPRINTF(("ehci_device_request: status=%x\n", 3326 EOREAD4(sc, EHCI_USBSTS))); 3327 delay(10000); 3328 ehci_dump_regs(sc); 3329 ehci_dump_sqh(sc->sc_async_head); 3330 ehci_dump_sqh(sqh); 3331 ehci_dump_sqtds(setup); 3332 } 3333 #endif 3334 3335 return (USBD_NORMAL_COMPLETION); 3336 3337 bad3: 3338 ehci_free_sqtd(sc, stat); 3339 bad2: 3340 ehci_free_sqtd(sc, setup); 3341 bad1: 3342 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3343 xfer->status = err; 3344 usb_transfer_complete(xfer); 3345 return (err); 3346 #undef exfer 3347 } 3348 3349 /************************/ 3350 3351 usbd_status 3352 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3353 { 3354 usbd_status err; 3355 3356 /* Insert last in queue. */ 3357 err = usb_insert_transfer(xfer); 3358 if (err) 3359 return (err); 3360 3361 /* Pipe isn't running, start first */ 3362 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3363 } 3364 3365 usbd_status 3366 ehci_device_bulk_start(usbd_xfer_handle xfer) 3367 { 3368 #define exfer EXFER(xfer) 3369 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3370 usbd_device_handle dev = epipe->pipe.device; 3371 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3372 ehci_soft_qtd_t *data, *dataend; 3373 ehci_soft_qh_t *sqh; 3374 usbd_status err; 3375 u_int len; 3376 int isread, endpt; 3377 int s; 3378 3379 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%u flags=%d\n", 3380 xfer, xfer->length, xfer->flags)); 3381 3382 if (sc->sc_bus.dying) 3383 return (USBD_IOERROR); 3384 3385 #ifdef DIAGNOSTIC 3386 if (xfer->rqflags & URQ_REQUEST) 3387 panic("ehci_device_bulk_start: a request"); 3388 #endif 3389 3390 len = xfer->length; 3391 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3392 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3393 sqh = epipe->sqh; 3394 3395 epipe->u.bulk.length = len; 3396 3397 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3398 &dataend); 3399 if (err) { 3400 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n")); 3401 xfer->status = err; 3402 usb_transfer_complete(xfer); 3403 return (err); 3404 } 3405 3406 #ifdef EHCI_DEBUG 3407 if (ehcidebug > 5) { 3408 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3409 ehci_dump_sqh(sqh); 3410 ehci_dump_sqtds(data); 3411 } 3412 #endif 3413 3414 /* Set up interrupt info. */ 3415 exfer->sqtdstart = data; 3416 exfer->sqtdend = dataend; 3417 #ifdef DIAGNOSTIC 3418 if (!exfer->isdone) { 3419 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3420 } 3421 exfer->isdone = 0; 3422 #endif 3423 3424 s = splusb(); 3425 ehci_set_qh_qtd(sqh, data); 3426 if (xfer->timeout && !sc->sc_bus.use_polling) { 3427 timeout_del(&xfer->timeout_handle); 3428 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3429 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3430 } 3431 ehci_add_intr_list(sc, exfer); 3432 xfer->status = USBD_IN_PROGRESS; 3433 splx(s); 3434 3435 #ifdef EHCI_DEBUG 3436 if (ehcidebug > 10) { 3437 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3438 delay(10000); 3439 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3440 ehci_dump_regs(sc); 3441 #if 0 3442 printf("async_head:\n"); 3443 ehci_dump_sqh(sc->sc_async_head); 3444 #endif 3445 printf("sqh:\n"); 3446 ehci_dump_sqh(sqh); 3447 ehci_dump_sqtds(data); 3448 } 3449 #endif 3450 3451 if (sc->sc_bus.use_polling) 3452 ehci_waitintr(sc, xfer); 3453 3454 return (USBD_IN_PROGRESS); 3455 #undef exfer 3456 } 3457 3458 void 3459 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3460 { 3461 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3462 ehci_abort_xfer(xfer, USBD_CANCELLED); 3463 } 3464 3465 /* 3466 * Close a device bulk pipe. 3467 */ 3468 void 3469 ehci_device_bulk_close(usbd_pipe_handle pipe) 3470 { 3471 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3472 3473 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3474 ehci_close_pipe(pipe, sc->sc_async_head); 3475 } 3476 3477 void 3478 ehci_device_bulk_done(usbd_xfer_handle xfer) 3479 { 3480 struct ehci_xfer *ex = EXFER(xfer); 3481 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3482 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3483 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3484 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3485 3486 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3487 xfer, xfer->actlen)); 3488 3489 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3490 ehci_del_intr_list(sc, ex); /* remove from active list */ 3491 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3492 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3493 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3494 } 3495 3496 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3497 } 3498 3499 /************************/ 3500 3501 usbd_status 3502 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3503 { 3504 struct ehci_soft_islot *isp; 3505 int islot, lev; 3506 3507 /* Find a poll rate that is large enough. */ 3508 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3509 if (EHCI_ILEV_IVAL(lev) <= ival) 3510 break; 3511 3512 /* Pick an interrupt slot at the right level. */ 3513 /* XXX could do better than picking at random */ 3514 if (cold) { 3515 /* XXX prevent panics at boot by not using arc4random */ 3516 sc->sc_rand = (sc->sc_rand + 192) % sc->sc_flsize; 3517 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3518 } else 3519 islot = EHCI_IQHIDX(lev, arc4random()); 3520 3521 sqh->islot = islot; 3522 isp = &sc->sc_islots[islot]; 3523 ehci_add_qh(sqh, isp->sqh); 3524 3525 return (USBD_NORMAL_COMPLETION); 3526 } 3527 3528 usbd_status 3529 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3530 { 3531 usbd_status err; 3532 3533 /* Insert last in queue. */ 3534 err = usb_insert_transfer(xfer); 3535 if (err) 3536 return (err); 3537 3538 /* 3539 * Pipe isn't running (otherwise err would be USBD_INPROG), 3540 * so start it first. 3541 */ 3542 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3543 } 3544 3545 usbd_status 3546 ehci_device_intr_start(usbd_xfer_handle xfer) 3547 { 3548 #define exfer EXFER(xfer) 3549 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3550 usbd_device_handle dev = xfer->pipe->device; 3551 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3552 ehci_soft_qtd_t *data, *dataend; 3553 ehci_soft_qh_t *sqh; 3554 usbd_status err; 3555 u_int len; 3556 int isread, endpt; 3557 int s; 3558 3559 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%u flags=%d\n", 3560 xfer, xfer->length, xfer->flags)); 3561 3562 if (sc->sc_bus.dying) 3563 return (USBD_IOERROR); 3564 3565 #ifdef DIAGNOSTIC 3566 if (xfer->rqflags & URQ_REQUEST) 3567 panic("ehci_device_intr_start: a request"); 3568 #endif 3569 3570 len = xfer->length; 3571 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3572 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3573 sqh = epipe->sqh; 3574 3575 epipe->u.intr.length = len; 3576 3577 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3578 &dataend); 3579 if (err) { 3580 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3581 xfer->status = err; 3582 usb_transfer_complete(xfer); 3583 return (err); 3584 } 3585 3586 #ifdef EHCI_DEBUG 3587 if (ehcidebug > 5) { 3588 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3589 ehci_dump_sqh(sqh); 3590 ehci_dump_sqtds(data); 3591 } 3592 #endif 3593 3594 /* Set up interrupt info. */ 3595 exfer->sqtdstart = data; 3596 exfer->sqtdend = dataend; 3597 #ifdef DIAGNOSTIC 3598 if (!exfer->isdone) 3599 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3600 exfer->isdone = 0; 3601 #endif 3602 3603 s = splusb(); 3604 ehci_set_qh_qtd(sqh, data); 3605 if (xfer->timeout && !sc->sc_bus.use_polling) { 3606 timeout_del(&xfer->timeout_handle); 3607 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3608 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3609 } 3610 ehci_add_intr_list(sc, exfer); 3611 xfer->status = USBD_IN_PROGRESS; 3612 splx(s); 3613 3614 #ifdef EHCI_DEBUG 3615 if (ehcidebug > 10) { 3616 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3617 delay(10000); 3618 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3619 ehci_dump_regs(sc); 3620 printf("sqh:\n"); 3621 ehci_dump_sqh(sqh); 3622 ehci_dump_sqtds(data); 3623 } 3624 #endif 3625 3626 if (sc->sc_bus.use_polling) 3627 ehci_waitintr(sc, xfer); 3628 3629 return (USBD_IN_PROGRESS); 3630 #undef exfer 3631 } 3632 3633 void 3634 ehci_device_intr_abort(usbd_xfer_handle xfer) 3635 { 3636 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3637 if (xfer->pipe->intrxfer == xfer) { 3638 DPRINTFN(1, ("ehci_device_intr_abort: remove\n")); 3639 xfer->pipe->intrxfer = NULL; 3640 } 3641 /* 3642 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3643 * async doorbell. That's dependant on the async list, wheras 3644 * intr xfers are periodic, should not use this? 3645 */ 3646 ehci_abort_xfer(xfer, USBD_CANCELLED); 3647 } 3648 3649 void 3650 ehci_device_intr_close(usbd_pipe_handle pipe) 3651 { 3652 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3653 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3654 struct ehci_soft_islot *isp; 3655 3656 isp = &sc->sc_islots[epipe->sqh->islot]; 3657 ehci_close_pipe(pipe, isp->sqh); 3658 } 3659 3660 void 3661 ehci_device_intr_done(usbd_xfer_handle xfer) 3662 { 3663 #define exfer EXFER(xfer) 3664 struct ehci_xfer *ex = EXFER(xfer); 3665 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3666 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3667 ehci_soft_qtd_t *data, *dataend; 3668 ehci_soft_qh_t *sqh; 3669 usbd_status err; 3670 u_int len; 3671 int isread, endpt, s; 3672 3673 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3674 xfer, xfer->actlen)); 3675 3676 if (xfer->pipe->repeat) { 3677 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3678 3679 len = epipe->u.intr.length; 3680 xfer->length = len; 3681 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3682 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3683 usb_syncmem(&xfer->dmabuf, 0, len, 3684 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3685 sqh = epipe->sqh; 3686 3687 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3688 &data, &dataend); 3689 if (err) { 3690 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3691 xfer->status = err; 3692 return; 3693 } 3694 3695 /* Set up interrupt info. */ 3696 exfer->sqtdstart = data; 3697 exfer->sqtdend = dataend; 3698 #ifdef DIAGNOSTIC 3699 if (!exfer->isdone) { 3700 printf("ehci_device_intr_done: not done, ex=%p\n", 3701 exfer); 3702 } 3703 exfer->isdone = 0; 3704 #endif 3705 3706 s = splusb(); 3707 ehci_set_qh_qtd(sqh, data); 3708 if (xfer->timeout && !sc->sc_bus.use_polling) { 3709 timeout_del(&xfer->timeout_handle); 3710 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3711 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3712 } 3713 splx(s); 3714 3715 xfer->status = USBD_IN_PROGRESS; 3716 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3717 ehci_del_intr_list(sc, ex); /* remove from active list */ 3718 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3719 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3720 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3721 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3722 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3723 } 3724 #undef exfer 3725 } 3726 3727 /************************/ 3728 3729 usbd_status 3730 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3731 { 3732 usbd_status err; 3733 3734 err = usb_insert_transfer(xfer); 3735 if (err && err != USBD_IN_PROGRESS) 3736 return (err); 3737 3738 return (ehci_device_isoc_start(xfer)); 3739 } 3740 3741 usbd_status 3742 ehci_device_isoc_start(usbd_xfer_handle xfer) 3743 { 3744 struct ehci_pipe *epipe; 3745 ehci_softc_t *sc; 3746 struct ehci_xfer *exfer; 3747 ehci_soft_itd_t *itd, *prev, *start, *stop; 3748 usb_dma_t *dma_buf; 3749 int i, j, k, frames, uframes, ufrperframe; 3750 int s, trans_count, offs, total_length; 3751 int frindex; 3752 3753 start = NULL; 3754 prev = NULL; 3755 itd = NULL; 3756 trans_count = 0; 3757 total_length = 0; 3758 exfer = (struct ehci_xfer *) xfer; 3759 sc = (ehci_softc_t *)xfer->pipe->device->bus; 3760 epipe = (struct ehci_pipe *)xfer->pipe; 3761 3762 /* 3763 * To allow continuous transfers, above we start all transfers 3764 * immediately. However, we're still going to get usbd_start_next call 3765 * this when another xfer completes. So, check if this is already 3766 * in progress or not 3767 */ 3768 3769 if (exfer->itdstart != NULL) 3770 return (USBD_IN_PROGRESS); 3771 3772 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %u flags %d\n", 3773 xfer, xfer->length, xfer->flags)); 3774 3775 if (sc->sc_bus.dying) 3776 return (USBD_IOERROR); 3777 3778 /* 3779 * To avoid complication, don't allow a request right now that'll span 3780 * the entire frame table. To within 4 frames, to allow some leeway 3781 * on either side of where the hc currently is. 3782 */ 3783 if ((1 << (epipe->pipe.endpoint->edesc->bInterval - 1)) * 3784 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3785 printf("ehci: isoc descriptor requested that spans the entire " 3786 "frametable, too many frames\n"); 3787 return (USBD_INVAL); 3788 } 3789 3790 #ifdef DIAGNOSTIC 3791 if (xfer->rqflags & URQ_REQUEST) 3792 panic("ehci_device_isoc_start: request"); 3793 3794 if (!exfer->isdone) 3795 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3796 exfer->isdone = 0; 3797 #endif 3798 3799 /* 3800 * Step 1: Allocate and initialize itds, how many do we need? 3801 * One per transfer if interval >= 8 microframes, fewer if we use 3802 * multiple microframes per frame. 3803 */ 3804 3805 i = epipe->pipe.endpoint->edesc->bInterval; 3806 if (i > 16 || i == 0) { 3807 /* Spec page 271 says intervals > 16 are invalid */ 3808 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3809 return (USBD_INVAL); 3810 } 3811 3812 switch (i) { 3813 case 1: 3814 ufrperframe = 8; 3815 break; 3816 case 2: 3817 ufrperframe = 4; 3818 break; 3819 case 3: 3820 ufrperframe = 2; 3821 break; 3822 default: 3823 ufrperframe = 1; 3824 break; 3825 } 3826 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3827 uframes = 8 / ufrperframe; 3828 3829 if (frames == 0) { 3830 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3831 return (USBD_INVAL); 3832 } 3833 3834 dma_buf = &xfer->dmabuf; 3835 offs = 0; 3836 3837 for (i = 0; i < frames; i++) { 3838 int froffs = offs; 3839 itd = ehci_alloc_itd(sc); 3840 3841 if (prev != NULL) { 3842 prev->itd.itd_next = 3843 htole32(itd->physaddr | EHCI_LINK_ITD); 3844 prev->xfer_next = itd; 3845 } else { 3846 start = itd; 3847 } 3848 3849 /* 3850 * Step 1.5, initialize uframes 3851 */ 3852 for (j = 0; j < 8; j += uframes) { 3853 /* Calculate which page in the list this starts in */ 3854 int addr = DMAADDR(dma_buf, froffs); 3855 addr = EHCI_PAGE_OFFSET(addr); 3856 addr += (offs - froffs); 3857 addr = EHCI_PAGE(addr); 3858 addr /= EHCI_PAGE_SIZE; 3859 3860 /* This gets the initial offset into the first page, 3861 * looks how far further along the current uframe 3862 * offset is. Works out how many pages that is. 3863 */ 3864 3865 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3866 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3867 EHCI_ITD_SET_PG(addr) | 3868 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf, 3869 offs)))); 3870 3871 total_length += xfer->frlengths[trans_count]; 3872 offs += xfer->frlengths[trans_count]; 3873 trans_count++; 3874 3875 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3876 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3877 break; 3878 } 3879 } 3880 3881 /* Step 1.75, set buffer pointers. To simplify matters, all 3882 * pointers are filled out for the next 7 hardware pages in 3883 * the dma block, so no need to worry what pages to cover 3884 * and what to not. 3885 */ 3886 3887 for (j=0; j < 7; j++) { 3888 /* 3889 * Don't try to lookup a page that's past the end 3890 * of buffer 3891 */ 3892 int page_offs = EHCI_PAGE(froffs + 3893 (EHCI_PAGE_SIZE * j)); 3894 3895 if (page_offs >= dma_buf->block->size) 3896 break; 3897 3898 long long page = DMAADDR(dma_buf, page_offs); 3899 page = EHCI_PAGE(page); 3900 itd->itd.itd_bufr[j] = 3901 htole32(EHCI_ITD_SET_BPTR(page)); 3902 itd->itd.itd_bufr_hi[j] = 3903 htole32(page >> 32); 3904 } 3905 3906 /* 3907 * Other special values 3908 */ 3909 3910 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3911 itd->itd.itd_bufr[0] |= 3912 htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3913 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3914 3915 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3916 ? 1 : 0; 3917 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3918 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3919 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3920 3921 /* FIXME: handle invalid trans */ 3922 itd->itd.itd_bufr[2] |= 3923 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3924 prev = itd; 3925 } /* End of frame */ 3926 3927 stop = itd; 3928 stop->xfer_next = NULL; 3929 exfer->isoc_len = total_length; 3930 3931 /* 3932 * Part 2: Transfer descriptors have now been set up, now they must 3933 * be scheduled into the period frame list. Erk. Not wanting to 3934 * complicate matters, transfer is denied if the transfer spans 3935 * more than the period frame list. 3936 */ 3937 3938 s = splusb(); 3939 3940 /* Start inserting frames */ 3941 if (epipe->u.isoc.cur_xfers > 0) { 3942 frindex = epipe->u.isoc.next_frame; 3943 } else { 3944 frindex = EOREAD4(sc, EHCI_FRINDEX); 3945 frindex = frindex >> 3; /* Erase microframe index */ 3946 frindex += 2; 3947 } 3948 3949 if (frindex >= sc->sc_flsize) 3950 frindex &= (sc->sc_flsize - 1); 3951 3952 /* Whats the frame interval? */ 3953 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 3954 if (i / 8 == 0) 3955 i = 1; 3956 else 3957 i /= 8; 3958 3959 itd = start; 3960 for (j = 0; j < frames; j++) { 3961 if (itd == NULL) 3962 panic("ehci: unexpectedly ran out of isoc itds, " 3963 "isoc_start"); 3964 3965 itd->itd.itd_next = sc->sc_flist[frindex]; 3966 if (itd->itd.itd_next == 0) 3967 /* FIXME: frindex table gets initialized to NULL 3968 * or EHCI_NULL? */ 3969 itd->itd.itd_next = htole32(EHCI_NULL); 3970 3971 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 3972 itd->u.frame_list.next = sc->sc_softitds[frindex]; 3973 sc->sc_softitds[frindex] = itd; 3974 if (itd->u.frame_list.next != NULL) 3975 itd->u.frame_list.next->u.frame_list.prev = itd; 3976 itd->slot = frindex; 3977 itd->u.frame_list.prev = NULL; 3978 3979 frindex += i; 3980 if (frindex >= sc->sc_flsize) 3981 frindex -= sc->sc_flsize; 3982 3983 itd = itd->xfer_next; 3984 } 3985 3986 epipe->u.isoc.cur_xfers++; 3987 epipe->u.isoc.next_frame = frindex; 3988 3989 exfer->itdstart = start; 3990 exfer->itdend = stop; 3991 exfer->sqtdstart = NULL; 3992 exfer->sqtdstart = NULL; 3993 3994 ehci_add_intr_list(sc, exfer); 3995 xfer->status = USBD_IN_PROGRESS; 3996 xfer->done = 0; 3997 splx(s); 3998 3999 if (sc->sc_bus.use_polling) { 4000 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4001 ehci_waitintr(sc, xfer); 4002 } 4003 4004 return (USBD_IN_PROGRESS); 4005 } 4006 4007 void 4008 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4009 { 4010 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4011 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4012 } 4013 4014 void 4015 ehci_device_isoc_close(usbd_pipe_handle pipe) 4016 { 4017 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4018 } 4019 4020 void 4021 ehci_device_isoc_done(usbd_xfer_handle xfer) 4022 { 4023 struct ehci_xfer *exfer; 4024 ehci_softc_t *sc; 4025 struct ehci_pipe *epipe; 4026 int s; 4027 4028 exfer = EXFER(xfer); 4029 sc = (ehci_softc_t *)xfer->pipe->device->bus; 4030 epipe = (struct ehci_pipe *) xfer->pipe; 4031 4032 s = splusb(); 4033 epipe->u.isoc.cur_xfers--; 4034 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4035 ehci_del_intr_list(sc, exfer); 4036 ehci_rem_free_itd_chain(sc, exfer); 4037 } 4038 splx(s); 4039 } 4040