1 /* $OpenBSD: if_athn_usb.h,v 1.12 2020/11/30 16:09:33 krw Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2018 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* Maximum number of STAs firmware can handle. */ 21 #define AR_USB_MAX_STA 8 22 23 #define AR_USB_DEFAULT_NF (-95) 24 25 /* USB requests. */ 26 #define AR_FW_DOWNLOAD 0x30 27 #define AR_FW_DOWNLOAD_COMP 0x31 28 29 /* USB endpoints addresses. */ 30 #define AR_PIPE_TX_DATA (UE_DIR_OUT | 1) 31 #define AR_PIPE_RX_DATA (UE_DIR_IN | 2) 32 #define AR_PIPE_RX_INTR (UE_DIR_IN | 3) 33 #define AR_PIPE_TX_INTR (UE_DIR_OUT | 4) 34 35 /* Wireless module interface commands. */ 36 #define AR_WMI_CMD_ECHO 0x001 37 #define AR_WMI_CMD_ACCESS_MEMORY 0x002 38 #define AR_WMI_GET_FW_VERSION 0x003 39 #define AR_WMI_CMD_DISABLE_INTR 0x004 40 #define AR_WMI_CMD_ENABLE_INTR 0x005 41 #define AR_WMI_CMD_ATH_INIT 0x006 42 #define AR_WMI_CMD_ABORT_TXQ 0x007 43 #define AR_WMI_CMD_STOP_TX_DMA 0x008 44 #define AR_WMI_CMD_ABORT_TX_DMA 0x009 45 #define AR_WMI_CMD_DRAIN_TXQ 0x00a 46 #define AR_WMI_CMD_DRAIN_TXQ_ALL 0x00b 47 #define AR_WMI_CMD_START_RECV 0x00c 48 #define AR_WMI_CMD_STOP_RECV 0x00d 49 #define AR_WMI_CMD_FLUSH_RECV 0x00e 50 #define AR_WMI_CMD_SET_MODE 0x00f 51 #define AR_WMI_CMD_NODE_CREATE 0x010 52 #define AR_WMI_CMD_NODE_REMOVE 0x011 53 #define AR_WMI_CMD_VAP_REMOVE 0x012 54 #define AR_WMI_CMD_VAP_CREATE 0x013 55 #define AR_WMI_CMD_REG_READ 0x014 56 #define AR_WMI_CMD_REG_WRITE 0x015 57 #define AR_WMI_CMD_RC_STATE_CHANGE 0x016 58 #define AR_WMI_CMD_RC_RATE_UPDATE 0x017 59 #define AR_WMI_CMD_TARGET_IC_UPDATE 0x018 60 #define AR_WMI_CMD_TX_AGGR_ENABLE 0x019 61 #define AR_WMI_CMD_TGT_DETACH 0x020 62 #define AR_WMI_CMD_NODE_UPDATE 0x021 63 #define AR_WMI_CMD_INT_STATS 0x022 64 #define AR_WMI_CMD_TX_STATS 0x023 65 #define AR_WMI_CMD_RX_STATS 0x024 66 #define AR_WMI_CMD_BITRATE_MASK 0x025 67 #define AR_WMI_CMD_REG_RMW 0x026 68 69 /* Wireless module interface events. */ 70 #define AR_WMI_EVT_TGT_RDY 0x001 71 #define AR_WMI_EVT_SWBA 0x002 72 #define AR_WMI_EVT_FATAL 0x003 73 #define AR_WMI_EVT_TXTO 0x004 74 #define AR_WMI_EVT_BMISS 0x005 75 #define AR_WMI_EVT_DELBA 0x006 76 #define AR_WMI_EVT_TXSTATUS 0x007 77 78 /* Structure for service AR_SVC_WMI_CONTROL. */ 79 struct ar_wmi_cmd_hdr { 80 uint16_t cmd_id; 81 #define AR_WMI_EVT_FLAG 0x1000 82 83 uint16_t seq_no; 84 } __packed; 85 86 /* Values for AR_WMI_CMD_SET_MODE. */ 87 #define AR_HTC_MODE_11NA 0 88 #define AR_HTC_MODE_11NG 1 89 90 #define AR_MAX_WRITE_COUNT 32 91 /* Structure for command AR_WMI_CMD_REG_WRITE. */ 92 struct ar_wmi_cmd_reg_write { 93 uint32_t addr; 94 uint32_t val; 95 } __packed; 96 97 /* Structure for command AR_WMI_CMD_NODE_{CREATE,REMOVE}. */ 98 struct ar_htc_target_sta { 99 uint8_t macaddr[IEEE80211_ADDR_LEN]; 100 uint8_t bssid[IEEE80211_ADDR_LEN]; 101 uint8_t sta_index; 102 uint8_t vif_index; 103 uint8_t is_vif_sta; 104 uint16_t flags; 105 #define AR_HTC_STA_AUTH 0x0001 106 #define AR_HTC_STA_QOS 0x0002 107 #define AR_HTC_STA_ERP 0x0004 108 #define AR_HTC_STA_HT 0x0008 109 110 uint16_t htcap; 111 uint16_t maxampdu; 112 uint8_t pad; 113 114 /* Internal state. */ 115 uint16_t txseqmgmt; 116 uint16_t iv16; 117 uint32_t iv32; 118 void *ni_vap; 119 } __packed; 120 121 /* Structures for command AR_WMI_CMD_RC_RATE_UPDATE. */ 122 #define AR_HTC_RATE_MAX 30 123 struct ar_htc_rateset { 124 uint8_t rs_nrates; 125 uint8_t rs_rates[AR_HTC_RATE_MAX]; 126 } __packed; 127 128 struct ar_htc_target_rate { 129 uint8_t sta_index; 130 uint8_t isnew; 131 uint8_t pad[2]; 132 uint32_t capflags; 133 #define AR_RC_DS_FLAG 0x00000001 134 #define AR_RC_40_FLAG 0x00000002 135 #define AR_RC_SGI_FLAG 0x00000004 136 #define AR_RC_HT_FLAG 0x00000008 137 #define AR_RC_STBC_FLAG 0x00000030 /* 2 bits */ 138 #define AR_RC_WEP_TKIP_FLAG 0x00000100 139 140 struct ar_htc_rateset lg_rates; 141 struct ar_htc_rateset ht_rates; 142 } __packed; 143 144 /* Structure for command AR_WMI_CMD_TX_AGGR_ENABLE. */ 145 struct ar_htc_target_aggr { 146 uint8_t sta_index; 147 uint8_t tidno; 148 uint8_t aggr_enable; 149 uint8_t padding; 150 } __packed; 151 152 /* Structure for command AR_WMI_CMD_VAP_CREATE. */ 153 struct ar_htc_target_vif { 154 uint8_t index; 155 uint32_t opmode; 156 #define AR_HTC_M_IBSS 0 157 #define AR_HTC_M_STA 1 158 #define AR_HTC_M_WDS 2 159 #define AR_HTC_M_AHDEMO 3 160 #define AR_HTC_M_HOSTAP 6 161 #define AR_HTC_M_MONITOR 8 162 uint8_t myaddr[IEEE80211_ADDR_LEN]; 163 uint8_t ath_cap; 164 uint16_t rtsthreshold; 165 uint8_t pad; 166 167 /* Internal state. */ 168 int8_t nodeindex; 169 void *iv_bss; 170 } __packed; 171 172 /* Structure for command AM_WMI_CMD_TARGET_IC_UPDATE. */ 173 struct ar_htc_cap_target { 174 uint32_t ampdu_limit; 175 uint8_t ampdu_subframes; 176 uint8_t enable_coex; 177 uint8_t txchainmask; 178 uint8_t pad; 179 } __packed; 180 181 struct ar_wmi_evt_txstatus { 182 uint8_t cookie; 183 184 /* 185 * Legacy rates are indicated as rate array indices. 186 * HT rates are indicated as MCS indices. 187 */ 188 uint8_t rate; 189 #define AR_HTC_TXSTAT_RATE 0x0f 190 #define AR_HTC_TXSTAT_EPID 0xf0 191 #define AR_HTC_TXSTAT_EPID_SHIFT 4 192 193 uint8_t flags; 194 #define AR_HTC_TXSTAT_ACK 0x01 195 #define AR_HTC_TXSTAT_FILT 0x02 196 #define AR_HTC_TXSTAT_RTC_CTS 0x04 197 #define AR_HTC_TXSTAT_MCS 0x08 198 #define AR_HTC_TXSTAT_CW40 0x10 199 #define AR_HTC_TXSTAT_SGI 0x20 200 } __packed; 201 202 /* Structure for event AR_WMI_EVT_TXSTATUS. */ 203 #define AR_HTC_MAX_TX_STATUS 12 204 struct ar_wmi_evt_txstatus_list { 205 uint8_t count; 206 struct ar_wmi_evt_txstatus ts[AR_HTC_MAX_TX_STATUS]; 207 } __packed; 208 209 /* HTC header. */ 210 struct ar_htc_frame_hdr { 211 uint8_t endpoint_id; 212 uint8_t flags; 213 #define AR_HTC_FLAG_NEED_CREDIT_UPDATE 0x01 214 #define AR_HTC_FLAG_TRAILER 0x02 215 #define AR_HTC_FLAG_CREDIT_REDISTRIBUTION 0x03 216 217 uint16_t payload_len; 218 uint8_t control[4]; 219 } __packed; 220 221 /* Structure for HTC enpoint id 0. */ 222 struct ar_htc_msg_hdr { 223 uint16_t msg_id; 224 #define AR_HTC_MSG_READY 0x0001 225 #define AR_HTC_MSG_CONN_SVC 0x0002 226 #define AR_HTC_MSG_CONN_SVC_RSP 0x0003 227 #define AR_HTC_MSG_SETUP_COMPLETE 0x0004 228 #define AR_HTC_MSG_CONF_PIPE 0x0005 229 #define AR_HTC_MSG_CONF_PIPE_RSP 0x0006 230 } __packed; 231 232 /* Structure for services AR_SVC_WMI_DATA_{VO,VI,BE,BK}. */ 233 struct ar_tx_frame { 234 uint8_t data_type; 235 #define AR_HTC_AMPDU 1 236 #define AR_HTC_NORMAL 2 237 238 uint8_t node_idx; 239 uint8_t vif_idx; 240 uint8_t tid; 241 uint32_t flags; 242 #define AR_HTC_TX_CTSONLY 0x00000001 243 #define AR_HTC_TX_RTSCTS 0x00000002 244 #define AR_HTC_TX_USE_MIN_RATE 0x00000100 245 246 uint8_t key_type; 247 uint8_t key_idx; 248 uint8_t cookie; 249 uint8_t pad; 250 } __packed; 251 252 /* Structure for service AR_SVC_WMI_MGMT. */ 253 struct ar_tx_mgmt { 254 uint8_t node_idx; 255 uint8_t vif_idx; 256 uint8_t tid; 257 uint8_t flags; 258 uint8_t key_type; 259 uint8_t key_idx; 260 uint8_t cookie; 261 uint8_t pad; 262 } __packed; 263 264 /* Structure for service AR_SVC_WMI_BEACON. */ 265 struct ar_tx_bcn { 266 uint8_t len_changed; 267 uint8_t vif_idx; 268 uint16_t rev; 269 } __packed; 270 271 /* Structure for message AR_HTC_MSG_READY. */ 272 struct ar_htc_msg_ready { 273 uint16_t credits; 274 uint16_t credits_size; 275 uint8_t max_endpoints; 276 uint8_t reserved; 277 } __packed; 278 279 /* Structure for message AR_HTC_MSG_CONF_PIPE. */ 280 struct ar_htc_msg_config_pipe { 281 uint8_t pipe_id; 282 uint8_t credits; 283 } __packed; 284 285 /* Structure for message AR_HTC_MSG_CONN_SVC. */ 286 struct ar_htc_msg_conn_svc { 287 uint16_t svc_id; 288 uint16_t conn_flags; 289 uint8_t dl_pipeid; 290 uint8_t ul_pipeid; 291 uint8_t svc_meta_len; 292 uint8_t reserved; 293 } __packed; 294 295 /* Structure for message AR_HTC_MSG_CONN_SVC_RSP. */ 296 struct ar_htc_msg_conn_svc_rsp { 297 uint16_t svc_id; 298 uint8_t status; 299 #define AR_HTC_SVC_SUCCESS 0 300 #define AR_HTC_SVC_NOT_FOUND 1 301 #define AR_HTC_SVC_FAILED 2 302 #define AR_HTC_SVC_NO_RESOURCES 3 303 #define AR_HTC_SVC_NO_MORE_EP 4 304 305 uint8_t endpoint_id; 306 uint16_t max_msg_len; 307 uint8_t svc_meta_len; 308 uint8_t reserved; 309 } __packed; 310 311 #define AR_SVC(grp, idx) ((grp) << 8 | (idx)) 312 #define AR_SVC_IDX(svc) ((svc) & 0xff) 313 /* Service groups. */ 314 #define AR_SVC_GRP_RSVD 0 315 #define AR_SVC_GRP_WMI 1 316 /* Service identifiers for WMI group. */ 317 #define AR_SVC_WMI_CONTROL AR_SVC(AR_SVC_GRP_WMI, 0) 318 #define AR_SVC_WMI_BEACON AR_SVC(AR_SVC_GRP_WMI, 1) 319 #define AR_SVC_WMI_CAB AR_SVC(AR_SVC_GRP_WMI, 2) 320 #define AR_SVC_WMI_UAPSD AR_SVC(AR_SVC_GRP_WMI, 3) 321 #define AR_SVC_WMI_MGMT AR_SVC(AR_SVC_GRP_WMI, 4) 322 #define AR_SVC_WMI_DATA_VO AR_SVC(AR_SVC_GRP_WMI, 5) 323 #define AR_SVC_WMI_DATA_VI AR_SVC(AR_SVC_GRP_WMI, 6) 324 #define AR_SVC_WMI_DATA_BE AR_SVC(AR_SVC_GRP_WMI, 7) 325 #define AR_SVC_WMI_DATA_BK AR_SVC(AR_SVC_GRP_WMI, 8) 326 327 struct ar_stream_hdr { 328 uint16_t len; 329 uint16_t tag; 330 #define AR_USB_RX_STREAM_TAG 0x4e00 331 #define AR_USB_TX_STREAM_TAG 0x697e 332 } __packed __attribute__((aligned(4))); 333 334 #define AR_MAX_CHAINS 3 335 336 /* Rx descriptor. */ 337 struct ar_rx_status { 338 uint64_t rs_tstamp; 339 uint16_t rs_datalen; 340 uint8_t rs_status; 341 #define AR_RXS_RXERR_CRC 0x01 342 #define AR_RXS_RXERR_PHY 0x02 343 #define AR_RXS_RXERR_FIFO 0x04 344 #define AR_RXS_RXERR_DECRYPT 0x08 345 #define AR_RXS_RXERR_MIC 0x10 346 uint8_t rs_phyerr; 347 int8_t rs_rssi; 348 int8_t rs_rssi_ctl[AR_MAX_CHAINS]; 349 int8_t rs_rssi_ext[AR_MAX_CHAINS]; 350 uint8_t rs_keyix; 351 uint8_t rs_rate; 352 uint8_t rs_antenna; 353 uint8_t rs_more; 354 uint8_t rs_isaggr; 355 uint8_t rs_moreaggr; 356 uint8_t rs_num_delims; 357 uint8_t rs_flags; 358 #define AR_RXS_FLAG_GI 0x04 359 #define AR_RXS_FLAG_2040 0x08 360 361 uint8_t rs_dummy; 362 uint32_t rs_evm[AR_MAX_CHAINS]; 363 } __packed __attribute__((aligned(4))); 364 365 366 /* 367 * Driver definitions. 368 */ 369 #define ATHN_USB_RX_LIST_COUNT 1 370 #define ATHN_USB_TX_LIST_COUNT (8 + 1) /* NB: +1 for beacons. */ 371 372 #define ATHN_USB_HOST_CMD_RING_COUNT 32 373 374 #define ATHN_USB_RXBUFSZ (8 * 1024) /* XXX Linux 16K */ 375 #define ATHN_USB_TXBUFSZ \ 376 ((sizeof(struct ar_stream_hdr) + \ 377 sizeof(struct ar_htc_frame_hdr) + \ 378 sizeof(struct ar_tx_frame) + \ 379 IEEE80211_MAX_LEN + 3) & ~3) 380 #define ATHN_USB_TXCMDSZ 512 381 382 #define ATHN_USB_TX_TIMEOUT 5000 /* ms */ 383 #define ATHN_USB_CMD_TIMEOUT 1000 /* ms */ 384 385 struct athn_usb_softc; 386 387 struct athn_usb_rx_stream { 388 struct mbuf *m; 389 int moff; 390 int left; 391 }; 392 393 struct athn_usb_rx_data { 394 struct athn_usb_softc *sc; 395 struct usbd_xfer *xfer; 396 uint8_t *buf; 397 }; 398 399 struct athn_usb_tx_data { 400 struct athn_usb_softc *sc; 401 struct usbd_xfer *xfer; 402 uint8_t *buf; 403 TAILQ_ENTRY(athn_usb_tx_data) next; 404 }; 405 406 struct athn_usb_host_cmd { 407 void (*cb)(struct athn_usb_softc *, void *); 408 uint8_t data[256]; 409 }; 410 411 struct athn_usb_cmd_newstate { 412 enum ieee80211_state state; 413 int arg; 414 }; 415 416 struct athn_usb_cmd_key { 417 struct ieee80211_node *ni; 418 struct ieee80211_key *key; 419 }; 420 421 struct athn_usb_aggr_cmd { 422 uint8_t sta_index; 423 uint8_t tid; 424 }; 425 426 struct athn_usb_host_cmd_ring { 427 struct athn_usb_host_cmd cmd[ATHN_USB_HOST_CMD_RING_COUNT]; 428 int cur; 429 int next; 430 int queued; 431 }; 432 433 struct athn_usb_softc { 434 struct athn_softc sc_sc; 435 #define usb_dev sc_sc.sc_dev 436 int sc_athn_attached; 437 438 /* USB specific goo. */ 439 struct usbd_device *sc_udev; 440 struct usbd_interface *sc_iface; 441 struct usb_task sc_task; 442 443 u_int flags; 444 #define ATHN_USB_FLAG_AR7010 0x01 445 446 struct athn_usb_rx_stream rx_stream; 447 448 struct usbd_pipe *tx_data_pipe; 449 struct usbd_pipe *rx_data_pipe; 450 struct usbd_pipe *rx_intr_pipe; 451 struct usbd_pipe *tx_intr_pipe; 452 uint8_t *ibuf; 453 size_t ibuflen; 454 455 struct ar_wmi_cmd_reg_write wbuf[AR_MAX_WRITE_COUNT]; 456 int wcount; 457 458 uint16_t wmi_seq_no; 459 uint16_t wait_cmd_id; 460 uint16_t wait_msg_id; 461 void *obuf; 462 struct ar_htc_msg_conn_svc_rsp *msg_conn_svc_rsp; 463 464 struct athn_usb_host_cmd_ring cmdq; 465 struct athn_usb_rx_data rx_data[ATHN_USB_RX_LIST_COUNT]; 466 struct athn_usb_tx_data tx_data[ATHN_USB_TX_LIST_COUNT]; 467 TAILQ_HEAD(, athn_usb_tx_data) tx_free_list; 468 struct athn_usb_tx_data tx_cmd; 469 struct athn_usb_tx_data *tx_bcn; 470 471 uint8_t ep_ctrl; 472 uint8_t ep_bcn; 473 uint8_t ep_cab; 474 uint8_t ep_uapsd; 475 uint8_t ep_mgmt; 476 uint8_t ep_data[EDCA_NUM_AC]; 477 478 /* 479 * Firmware cannot handle more than 8 STAs. 480 * We use a bitmask to keep track of available slots in the firmware's 481 * node array. A 1 bit at index N, as determined by ffs(3), means the 482 * slot at this index is available. 483 */ 484 uint8_t free_node_slots; 485 486 void (*sc_node_free)(struct ieee80211com *, 487 struct ieee80211_node *); 488 int sc_key_tasks; 489 }; 490