1 /* $OpenBSD: if_auereg.h,v 1.13 2007/06/10 10:15:35 mbalmer Exp $ */ 2 /* $NetBSD: if_auereg.h,v 1.16 2001/10/10 02:14:17 augustss Exp $ */ 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/usb/if_auereg.h,v 1.2 2000/01/08 06:52:36 wpaul Exp $ 35 */ 36 37 /* 38 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet 39 * chip. The Pegasus uses a total of four USB endpoints: the control 40 * endpoint (0), a bulk read endpoint for receiving packets (1), 41 * a bulk write endpoint for sending packets (2) and an interrupt 42 * endpoint for passing RX and TX status (3). Endpoint 0 is used 43 * to read and write the ethernet module's registers. All registers 44 * are 8 bits wide. 45 * 46 * Packet transfer is done in 64 byte chunks. The last chunk in a 47 * transfer is denoted by having a length less that 64 bytes. For 48 * the RX case, the data includes an optional RX status word. 49 */ 50 51 #define AUE_UR_READREG 0xF0 52 #define AUE_UR_WRITEREG 0xF1 53 54 #define AUE_CONFIG_NO 1 55 #define AUE_IFACE_IDX 0 56 57 /* 58 * Note that while the ADMtek technically has four 59 * endpoints, the control endpoint (endpoint 0) is 60 * regarded as special by the USB code and drivers 61 * don't have direct access to it. (We access it 62 * using usbd_do_request() when reading/writing 63 * registers.) Consequently, our endpoint indexes 64 * don't match those in the ADMtek Pegasus manual: 65 * we consider the RX data endpoint to be index 0 66 * and work up from there. 67 */ 68 #define AUE_ENDPT_RX 0x0 69 #define AUE_ENDPT_TX 0x1 70 #define AUE_ENDPT_INTR 0x2 71 #define AUE_ENDPT_MAX 0x3 72 73 #define AUE_CTL0 0x00 74 #define AUE_CTL1 0x01 75 #define AUE_CTL2 0x02 76 #define AUE_MAR0 0x08 77 #define AUE_MAR1 0x09 78 #define AUE_MAR2 0x0A 79 #define AUE_MAR3 0x0B 80 #define AUE_MAR4 0x0C 81 #define AUE_MAR5 0x0D 82 #define AUE_MAR6 0x0E 83 #define AUE_MAR7 0x0F 84 #define AUE_MAR AUE_MAR0 85 #define AUE_PAR0 0x10 86 #define AUE_PAR1 0x11 87 #define AUE_PAR2 0x12 88 #define AUE_PAR3 0x13 89 #define AUE_PAR4 0x14 90 #define AUE_PAR5 0x15 91 #define AUE_PAR AUE_PAR0 92 #define AUE_PAUSE0 0x18 93 #define AUE_PAUSE1 0x19 94 #define AUE_PAUSE AUE_PAUSE0 95 #define AUE_RX_FLOWCTL_CNT 0x1A 96 #define AUE_RX_FLOWCTL_FIFO 0x1B 97 #define AUE_REG_1D 0x1D 98 #define AUE_EE_REG 0x20 99 #define AUE_EE_DATA0 0x21 100 #define AUE_EE_DATA1 0x22 101 #define AUE_EE_DATA AUE_EE_DATA0 102 #define AUE_EE_CTL 0x23 103 #define AUE_PHY_ADDR 0x25 104 #define AUE_PHY_DATA0 0x26 105 #define AUE_PHY_DATA1 0x27 106 #define AUE_PHY_DATA AUE_PHY_DATA0 107 #define AUE_PHY_CTL 0x28 108 #define AUE_USB_STS 0x2A 109 #define AUE_TXSTAT0 0x2B 110 #define AUE_TXSTAT1 0x2C 111 #define AUE_TXSTAT AUE_TXSTAT0 112 #define AUE_RXSTAT 0x2D 113 #define AUE_PKTLOST0 0x2E 114 #define AUE_PKTLOST1 0x2F 115 #define AUE_PKTLOST AUE_PKTLOST0 116 117 #define AUE_REG_7B 0x7B 118 #define AUE_GPIO0 0x7E 119 #define AUE_GPIO1 0x7F 120 #define AUE_REG_81 0x81 121 122 #define AUE_CTL0_INCLUDE_RXCRC 0x01 123 #define AUE_CTL0_ALLMULTI 0x02 124 #define AUE_CTL0_STOP_BACKOFF 0x04 125 #define AUE_CTL0_RXSTAT_APPEND 0x08 126 #define AUE_CTL0_WAKEON_ENB 0x10 127 #define AUE_CTL0_RXPAUSE_ENB 0x20 128 #define AUE_CTL0_RX_ENB 0x40 129 #define AUE_CTL0_TX_ENB 0x80 130 131 #define AUE_CTL1_HOMELAN 0x04 132 #define AUE_CTL1_RESETMAC 0x08 133 #define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */ 134 #define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */ 135 #define AUE_CTL1_DELAYHOME 0x40 136 137 #define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */ 138 #define AUE_CTL2_RX_BADFRAMES 0x02 139 #define AUE_CTL2_RX_PROMISC 0x04 140 #define AUE_CTL2_LOOPBACK 0x08 141 #define AUE_CTL2_EEPROMWR_ENB 0x10 142 #define AUE_CTL2_EEPROM_LOAD 0x20 143 144 #define AUE_EECTL_WRITE 0x01 145 #define AUE_EECTL_READ 0x02 146 #define AUE_EECTL_DONE 0x04 147 148 #define AUE_PHYCTL_PHYREG 0x1F 149 #define AUE_PHYCTL_WRITE 0x20 150 #define AUE_PHYCTL_READ 0x40 151 #define AUE_PHYCTL_DONE 0x80 152 153 #define AUE_USBSTS_SUSPEND 0x01 154 #define AUE_USBSTS_RESUME 0x02 155 156 #define AUE_TXSTAT0_JABTIMO 0x04 157 #define AUE_TXSTAT0_CARLOSS 0x08 158 #define AUE_TXSTAT0_NOCARRIER 0x10 159 #define AUE_TXSTAT0_LATECOLL 0x20 160 #define AUE_TXSTAT0_EXCESSCOLL 0x40 161 #define AUE_TXSTAT0_UNDERRUN 0x80 162 163 #define AUE_TXSTAT1_PKTCNT 0x0F 164 #define AUE_TXSTAT1_FIFO_EMPTY 0x40 165 #define AUE_TXSTAT1_FIFO_FULL 0x80 166 167 #define AUE_RXSTAT_OVERRUN 0x01 168 #define AUE_RXSTAT_PAUSE 0x02 169 170 #define AUE_GPIO_IN0 0x01 171 #define AUE_GPIO_OUT0 0x02 172 #define AUE_GPIO_SEL0 0x04 173 #define AUE_GPIO_IN1 0x08 174 #define AUE_GPIO_OUT1 0x10 175 #define AUE_GPIO_SEL1 0x20 176 177 struct aue_intrpkt { 178 u_int8_t aue_txstat0; 179 u_int8_t aue_txstat1; 180 u_int8_t aue_rxstat; 181 u_int8_t aue_rxlostpkt0; 182 u_int8_t aue_rxlostpkt1; 183 u_int8_t aue_wakeupstat; 184 u_int8_t aue_rsvd; 185 u_int8_t _pad; 186 }; 187 #define AUE_INTR_PKTLEN 8 188 189 struct aue_rxpkt { 190 uWord aue_pktlen; 191 uByte aue_rxstat; 192 }; 193 194 #define AUE_RXSTAT_MCAST 0x01 195 #define AUE_RXSTAT_GIANT 0x02 196 #define AUE_RXSTAT_RUNT 0x04 197 #define AUE_RXSTAT_CRCERR 0x08 198 #define AUE_RXSTAT_DRIBBLE 0x10 199 #define AUE_RXSTAT_MASK 0x1E 200 201 202 /*************** The rest belongs in if_auevar.h *************/ 203 204 #define AUE_TX_LIST_CNT 1 205 #define AUE_RX_LIST_CNT 1 206 207 struct aue_softc; 208 209 struct aue_chain { 210 struct aue_softc *aue_sc; 211 usbd_xfer_handle aue_xfer; 212 char *aue_buf; 213 struct mbuf *aue_mbuf; 214 int aue_idx; 215 }; 216 217 struct aue_cdata { 218 struct aue_chain aue_tx_chain[AUE_TX_LIST_CNT]; 219 struct aue_chain aue_rx_chain[AUE_RX_LIST_CNT]; 220 struct aue_intrpkt aue_ibuf; 221 int aue_tx_prod; 222 int aue_tx_cons; 223 int aue_tx_cnt; 224 int aue_rx_prod; 225 }; 226 227 struct aue_softc { 228 struct device aue_dev; 229 230 struct arpcom arpcom; 231 struct mii_data aue_mii; 232 #define GET_IFP(sc) (&(sc)->arpcom.ac_if) 233 #define GET_MII(sc) (&(sc)->aue_mii) 234 235 struct timeout aue_stat_ch; 236 237 usbd_device_handle aue_udev; 238 usbd_interface_handle aue_iface; 239 u_int16_t aue_vendor; 240 u_int16_t aue_product; 241 int aue_ed[AUE_ENDPT_MAX]; 242 usbd_pipe_handle aue_ep[AUE_ENDPT_MAX]; 243 u_int8_t aue_link; 244 int aue_if_flags; 245 struct aue_cdata aue_cdata; 246 247 u_int16_t aue_flags; 248 249 int aue_refcnt; 250 char aue_dying; 251 char aue_attached; 252 u_int aue_rx_errs; 253 u_int aue_intr_errs; 254 struct timeval aue_rx_notice; 255 256 struct usb_task aue_tick_task; 257 struct usb_task aue_stop_task; 258 259 struct rwlock aue_mii_lock; 260 261 void *sc_sdhook; 262 }; 263 264 #define AUE_TIMEOUT 1000 265 #define AUE_BUFSZ 1536 266 #define AUE_MIN_FRAMELEN 60 267 #define AUE_TX_TIMEOUT 10000 /* ms */ 268 #define AUE_INTR_INTERVAL 100 /* ms */ 269