1 /* $OpenBSD: if_otus.c,v 1.70 2021/11/22 10:17:14 mglocker Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for Atheros AR9001U chipset. 21 */ 22 23 #include "bpfilter.h" 24 25 #include <sys/param.h> 26 #include <sys/sockio.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/timeout.h> 32 #include <sys/conf.h> 33 #include <sys/device.h> 34 #include <sys/endian.h> 35 36 #include <machine/intr.h> 37 38 #if NBPFILTER > 0 39 #include <net/bpf.h> 40 #endif 41 #include <net/if.h> 42 #include <net/if_dl.h> 43 #include <net/if_media.h> 44 45 #include <netinet/in.h> 46 #include <netinet/if_ether.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_amrr.h> 50 #include <net80211/ieee80211_radiotap.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 #include <dev/usb/usbdi_util.h> 55 #include <dev/usb/usbdevs.h> 56 57 #include <dev/usb/if_otusreg.h> 58 59 #ifdef OTUS_DEBUG 60 #define DPRINTF(x) do { if (otus_debug) printf x; } while (0) 61 #define DPRINTFN(n, x) do { if (otus_debug >= (n)) printf x; } while (0) 62 int otus_debug = 1; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n, x) 66 #endif 67 68 static const struct usb_devno otus_devs[] = { 69 { USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_WN7512 }, 70 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_3CRUSBN275 }, 71 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_TG121N }, 72 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_AR9170 }, 73 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN612 }, 74 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN821NV2 }, 75 { USB_VENDOR_AVM, USB_PRODUCT_AVM_FRITZWLAN }, 76 { USB_VENDOR_CACE, USB_PRODUCT_CACE_AIRPCAPNX }, 77 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA130D1 }, 78 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A1 }, 79 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A2 }, 80 { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_WNGDNUS2 }, 81 { USB_VENDOR_NEC, USB_PRODUCT_NEC_WL300NUG }, 82 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WN111V2 }, 83 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000 }, 84 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNDA3100 }, 85 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GW_US300 }, 86 { USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_O8494 }, 87 { USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_WNC0600 }, 88 { USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB81 }, 89 { USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB82 }, 90 { USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ZD1221 }, 91 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_NWD271N } 92 }; 93 94 int otus_match(struct device *, void *, void *); 95 void otus_attach(struct device *, struct device *, void *); 96 int otus_detach(struct device *, int); 97 void otus_attachhook(struct device *); 98 void otus_get_chanlist(struct otus_softc *); 99 int otus_load_firmware(struct otus_softc *, const char *, 100 uint32_t); 101 int otus_open_pipes(struct otus_softc *); 102 void otus_close_pipes(struct otus_softc *); 103 int otus_alloc_tx_cmd(struct otus_softc *); 104 void otus_free_tx_cmd(struct otus_softc *); 105 int otus_alloc_tx_data_list(struct otus_softc *); 106 void otus_free_tx_data_list(struct otus_softc *); 107 int otus_alloc_rx_data_list(struct otus_softc *); 108 void otus_free_rx_data_list(struct otus_softc *); 109 void otus_next_scan(void *); 110 void otus_task(void *); 111 void otus_do_async(struct otus_softc *, 112 void (*)(struct otus_softc *, void *), void *, int); 113 int otus_newstate(struct ieee80211com *, enum ieee80211_state, 114 int); 115 void otus_newstate_cb(struct otus_softc *, void *); 116 int otus_cmd(struct otus_softc *, uint8_t, const void *, int, 117 void *); 118 void otus_write(struct otus_softc *, uint32_t, uint32_t); 119 int otus_write_barrier(struct otus_softc *); 120 struct ieee80211_node *otus_node_alloc(struct ieee80211com *); 121 int otus_media_change(struct ifnet *); 122 int otus_read_eeprom(struct otus_softc *); 123 void otus_newassoc(struct ieee80211com *, struct ieee80211_node *, 124 int); 125 void otus_intr(struct usbd_xfer *, void *, usbd_status); 126 void otus_cmd_rxeof(struct otus_softc *, uint8_t *, int); 127 void otus_sub_rxeof(struct otus_softc *, uint8_t *, int, 128 struct mbuf_list *); 129 void otus_rxeof(struct usbd_xfer *, void *, usbd_status); 130 void otus_txeof(struct usbd_xfer *, void *, usbd_status); 131 int otus_tx(struct otus_softc *, struct mbuf *, 132 struct ieee80211_node *); 133 void otus_start(struct ifnet *); 134 void otus_watchdog(struct ifnet *); 135 int otus_ioctl(struct ifnet *, u_long, caddr_t); 136 int otus_set_multi(struct otus_softc *); 137 void otus_updateedca(struct ieee80211com *); 138 void otus_updateedca_cb(struct otus_softc *, void *); 139 void otus_updateslot(struct ieee80211com *); 140 void otus_updateslot_cb(struct otus_softc *, void *); 141 int otus_init_mac(struct otus_softc *); 142 uint32_t otus_phy_get_def(struct otus_softc *, uint32_t); 143 int otus_set_board_values(struct otus_softc *, 144 struct ieee80211_channel *); 145 int otus_program_phy(struct otus_softc *, 146 struct ieee80211_channel *); 147 int otus_set_rf_bank4(struct otus_softc *, 148 struct ieee80211_channel *); 149 void otus_get_delta_slope(uint32_t, uint32_t *, uint32_t *); 150 int otus_set_chan(struct otus_softc *, struct ieee80211_channel *, 151 int); 152 int otus_set_key(struct ieee80211com *, struct ieee80211_node *, 153 struct ieee80211_key *); 154 void otus_set_key_cb(struct otus_softc *, void *); 155 void otus_delete_key(struct ieee80211com *, struct ieee80211_node *, 156 struct ieee80211_key *); 157 void otus_delete_key_cb(struct otus_softc *, void *); 158 void otus_calibrate_to(void *); 159 int otus_set_bssid(struct otus_softc *, const uint8_t *); 160 int otus_set_macaddr(struct otus_softc *, const uint8_t *); 161 void otus_led_newstate_type1(struct otus_softc *); 162 void otus_led_newstate_type2(struct otus_softc *); 163 void otus_led_newstate_type3(struct otus_softc *); 164 int otus_init(struct ifnet *); 165 void otus_stop(struct ifnet *); 166 167 struct cfdriver otus_cd = { 168 NULL, "otus", DV_IFNET 169 }; 170 171 const struct cfattach otus_ca = { 172 sizeof (struct otus_softc), otus_match, otus_attach, otus_detach 173 }; 174 175 int 176 otus_match(struct device *parent, void *match, void *aux) 177 { 178 struct usb_attach_arg *uaa = aux; 179 180 if (uaa->iface == NULL || uaa->configno != 1) 181 return UMATCH_NONE; 182 183 return (usb_lookup(otus_devs, uaa->vendor, uaa->product) != NULL) ? 184 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 185 } 186 187 void 188 otus_attach(struct device *parent, struct device *self, void *aux) 189 { 190 struct otus_softc *sc = (struct otus_softc *)self; 191 struct usb_attach_arg *uaa = aux; 192 int error; 193 194 sc->sc_udev = uaa->device; 195 196 usb_init_task(&sc->sc_task, otus_task, sc, USB_TASK_TYPE_GENERIC); 197 timeout_set(&sc->scan_to, otus_next_scan, sc); 198 timeout_set(&sc->calib_to, otus_calibrate_to, sc); 199 200 sc->amrr.amrr_min_success_threshold = 1; 201 sc->amrr.amrr_max_success_threshold = 10; 202 203 /* Get the first interface handle. */ 204 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 205 if (error != 0) { 206 printf("%s: could not get interface handle\n", 207 sc->sc_dev.dv_xname); 208 return; 209 } 210 211 if ((error = otus_open_pipes(sc)) != 0) { 212 printf("%s: could not open pipes\n", sc->sc_dev.dv_xname); 213 return; 214 } 215 216 config_mountroot(self, otus_attachhook); 217 } 218 219 int 220 otus_detach(struct device *self, int flags) 221 { 222 struct otus_softc *sc = (struct otus_softc *)self; 223 struct ifnet *ifp = &sc->sc_ic.ic_if; 224 int s; 225 226 s = splusb(); 227 228 if (timeout_initialized(&sc->scan_to)) 229 timeout_del(&sc->scan_to); 230 if (timeout_initialized(&sc->calib_to)) 231 timeout_del(&sc->calib_to); 232 233 /* Wait for all queued asynchronous commands to complete. */ 234 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 235 236 usbd_ref_wait(sc->sc_udev); 237 238 if (ifp->if_softc != NULL) { 239 ifp->if_flags &= ~IFF_RUNNING; 240 ifq_clr_oactive(&ifp->if_snd); 241 ieee80211_ifdetach(ifp); 242 if_detach(ifp); 243 } 244 245 otus_close_pipes(sc); 246 247 splx(s); 248 249 return 0; 250 } 251 252 void 253 otus_attachhook(struct device *self) 254 { 255 struct otus_softc *sc = (struct otus_softc *)self; 256 struct ieee80211com *ic = &sc->sc_ic; 257 struct ifnet *ifp = &ic->ic_if; 258 usb_device_request_t req; 259 uint32_t in, out; 260 int error; 261 262 error = otus_load_firmware(sc, "otus-init", AR_FW_INIT_ADDR); 263 if (error != 0) { 264 printf("%s: could not load %s firmware\n", 265 sc->sc_dev.dv_xname, "init"); 266 return; 267 } 268 269 usbd_delay_ms(sc->sc_udev, 1000); 270 271 error = otus_load_firmware(sc, "otus-main", AR_FW_MAIN_ADDR); 272 if (error != 0) { 273 printf("%s: could not load %s firmware\n", 274 sc->sc_dev.dv_xname, "main"); 275 return; 276 } 277 278 /* Tell device that firmware transfer is complete. */ 279 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 280 req.bRequest = AR_FW_DOWNLOAD_COMPLETE; 281 USETW(req.wValue, 0); 282 USETW(req.wIndex, 0); 283 USETW(req.wLength, 0); 284 if (usbd_do_request(sc->sc_udev, &req, NULL) != 0) { 285 printf("%s: firmware initialization failed\n", 286 sc->sc_dev.dv_xname); 287 return; 288 } 289 290 /* Send an ECHO command to check that everything is settled. */ 291 in = 0xbadc0ffe; 292 if (otus_cmd(sc, AR_CMD_ECHO, &in, sizeof in, &out) != 0) { 293 printf("%s: echo command failed\n", sc->sc_dev.dv_xname); 294 return; 295 } 296 if (in != out) { 297 printf("%s: echo reply mismatch: 0x%08x!=0x%08x\n", 298 sc->sc_dev.dv_xname, in, out); 299 return; 300 } 301 302 /* Read entire EEPROM. */ 303 if (otus_read_eeprom(sc) != 0) { 304 printf("%s: could not read EEPROM\n", sc->sc_dev.dv_xname); 305 return; 306 } 307 308 sc->txmask = sc->eeprom.baseEepHeader.txMask; 309 sc->rxmask = sc->eeprom.baseEepHeader.rxMask; 310 sc->capflags = sc->eeprom.baseEepHeader.opCapFlags; 311 IEEE80211_ADDR_COPY(ic->ic_myaddr, sc->eeprom.baseEepHeader.macAddr); 312 sc->sc_led_newstate = otus_led_newstate_type3; /* XXX */ 313 314 printf("%s: MAC/BBP AR9170, RF AR%X, MIMO %dT%dR, address %s\n", 315 sc->sc_dev.dv_xname, (sc->capflags & AR5416_OPFLAGS_11A) ? 316 0x9104 : ((sc->txmask == 0x5) ? 0x9102 : 0x9101), 317 (sc->txmask == 0x5) ? 2 : 1, (sc->rxmask == 0x5) ? 2 : 1, 318 ether_sprintf(ic->ic_myaddr)); 319 320 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 321 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 322 ic->ic_state = IEEE80211_S_INIT; 323 324 /* Set device capabilities. */ 325 ic->ic_caps = 326 IEEE80211_C_MONITOR | /* monitor mode supported */ 327 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 328 IEEE80211_C_SHSLOT | /* short slot time supported */ 329 IEEE80211_C_WEP | /* WEP */ 330 IEEE80211_C_RSN; /* WPA/RSN */ 331 332 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 333 /* Set supported .11b and .11g rates. */ 334 ic->ic_sup_rates[IEEE80211_MODE_11B] = 335 ieee80211_std_rateset_11b; 336 ic->ic_sup_rates[IEEE80211_MODE_11G] = 337 ieee80211_std_rateset_11g; 338 } 339 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 340 /* Set supported .11a rates. */ 341 ic->ic_sup_rates[IEEE80211_MODE_11A] = 342 ieee80211_std_rateset_11a; 343 } 344 345 /* Build the list of supported channels. */ 346 otus_get_chanlist(sc); 347 348 ifp->if_softc = sc; 349 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 350 ifp->if_ioctl = otus_ioctl; 351 ifp->if_start = otus_start; 352 ifp->if_watchdog = otus_watchdog; 353 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 354 355 if_attach(ifp); 356 ieee80211_ifattach(ifp); 357 ic->ic_node_alloc = otus_node_alloc; 358 ic->ic_newassoc = otus_newassoc; 359 ic->ic_updateslot = otus_updateslot; 360 ic->ic_updateedca = otus_updateedca; 361 #ifdef notyet 362 ic->ic_set_key = otus_set_key; 363 ic->ic_delete_key = otus_delete_key; 364 #endif 365 /* Override state transition machine. */ 366 sc->sc_newstate = ic->ic_newstate; 367 ic->ic_newstate = otus_newstate; 368 ieee80211_media_init(ifp, otus_media_change, ieee80211_media_status); 369 370 #if NBPFILTER > 0 371 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 372 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 373 374 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 375 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 376 sc->sc_rxtap.wr_ihdr.it_present = htole32(OTUS_RX_RADIOTAP_PRESENT); 377 378 sc->sc_txtap_len = sizeof sc->sc_txtapu; 379 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 380 sc->sc_txtap.wt_ihdr.it_present = htole32(OTUS_TX_RADIOTAP_PRESENT); 381 #endif 382 } 383 384 void 385 otus_get_chanlist(struct otus_softc *sc) 386 { 387 struct ieee80211com *ic = &sc->sc_ic; 388 uint16_t domain; 389 uint8_t chan; 390 int i; 391 392 /* XXX regulatory domain. */ 393 domain = letoh16(sc->eeprom.baseEepHeader.regDmn[0]); 394 DPRINTF(("regdomain=0x%04x\n", domain)); 395 396 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 397 for (i = 0; i < 14; i++) { 398 chan = ar_chans[i]; 399 ic->ic_channels[chan].ic_freq = 400 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 401 ic->ic_channels[chan].ic_flags = 402 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 403 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 404 } 405 } 406 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 407 for (i = 14; i < nitems(ar_chans); i++) { 408 chan = ar_chans[i]; 409 ic->ic_channels[chan].ic_freq = 410 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 411 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 412 } 413 } 414 } 415 416 int 417 otus_load_firmware(struct otus_softc *sc, const char *name, uint32_t addr) 418 { 419 usb_device_request_t req; 420 size_t fwsize, size; 421 u_char *fw, *ptr; 422 int mlen, error; 423 424 /* Read firmware image from the filesystem. */ 425 if ((error = loadfirmware(name, &fw, &fwsize)) != 0) { 426 printf("%s: failed loadfirmware of file %s (error %d)\n", 427 sc->sc_dev.dv_xname, name, error); 428 return error; 429 } 430 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 431 req.bRequest = AR_FW_DOWNLOAD; 432 USETW(req.wIndex, 0); 433 434 ptr = fw; 435 size = fwsize; 436 addr >>= 8; 437 while (size > 0) { 438 mlen = MIN(size, 4096); 439 440 USETW(req.wValue, addr); 441 USETW(req.wLength, mlen); 442 if (usbd_do_request(sc->sc_udev, &req, ptr) != 0) { 443 error = EIO; 444 break; 445 } 446 addr += mlen >> 8; 447 ptr += mlen; 448 size -= mlen; 449 } 450 free(fw, M_DEVBUF, fwsize); 451 return error; 452 } 453 454 int 455 otus_open_pipes(struct otus_softc *sc) 456 { 457 usb_endpoint_descriptor_t *ed; 458 int i, isize, error; 459 460 error = usbd_open_pipe(sc->sc_iface, AR_EPT_BULK_RX_NO, 0, 461 &sc->data_rx_pipe); 462 if (error != 0) { 463 printf("%s: could not open Rx bulk pipe\n", 464 sc->sc_dev.dv_xname); 465 goto fail; 466 } 467 468 ed = usbd_get_endpoint_descriptor(sc->sc_iface, AR_EPT_INTR_RX_NO); 469 if (ed == NULL) { 470 printf("%s: could not retrieve Rx intr pipe descriptor\n", 471 sc->sc_dev.dv_xname); 472 goto fail; 473 } 474 isize = UGETW(ed->wMaxPacketSize); 475 if (isize == 0) { 476 printf("%s: invalid Rx intr pipe descriptor\n", 477 sc->sc_dev.dv_xname); 478 goto fail; 479 } 480 sc->ibuf = malloc(isize, M_USBDEV, M_NOWAIT); 481 if (sc->ibuf == NULL) { 482 printf("%s: could not allocate Rx intr buffer\n", 483 sc->sc_dev.dv_xname); 484 goto fail; 485 } 486 sc->ibuflen = isize; 487 error = usbd_open_pipe_intr(sc->sc_iface, AR_EPT_INTR_RX_NO, 488 USBD_SHORT_XFER_OK, &sc->cmd_rx_pipe, sc, sc->ibuf, isize, 489 otus_intr, USBD_DEFAULT_INTERVAL); 490 if (error != 0) { 491 printf("%s: could not open Rx intr pipe\n", 492 sc->sc_dev.dv_xname); 493 goto fail; 494 } 495 496 error = usbd_open_pipe(sc->sc_iface, AR_EPT_BULK_TX_NO, 0, 497 &sc->data_tx_pipe); 498 if (error != 0) { 499 printf("%s: could not open Tx bulk pipe\n", 500 sc->sc_dev.dv_xname); 501 goto fail; 502 } 503 504 error = usbd_open_pipe(sc->sc_iface, AR_EPT_INTR_TX_NO, 0, 505 &sc->cmd_tx_pipe); 506 if (error != 0) { 507 printf("%s: could not open Tx intr pipe\n", 508 sc->sc_dev.dv_xname); 509 goto fail; 510 } 511 512 if (otus_alloc_tx_cmd(sc) != 0) { 513 printf("%s: could not allocate command xfer\n", 514 sc->sc_dev.dv_xname); 515 goto fail; 516 } 517 518 if (otus_alloc_tx_data_list(sc) != 0) { 519 printf("%s: could not allocate Tx xfers\n", 520 sc->sc_dev.dv_xname); 521 goto fail; 522 } 523 524 if (otus_alloc_rx_data_list(sc) != 0) { 525 printf("%s: could not allocate Rx xfers\n", 526 sc->sc_dev.dv_xname); 527 goto fail; 528 } 529 530 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) { 531 struct otus_rx_data *data = &sc->rx_data[i]; 532 533 usbd_setup_xfer(data->xfer, sc->data_rx_pipe, data, data->buf, 534 OTUS_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 535 USBD_NO_TIMEOUT, otus_rxeof); 536 error = usbd_transfer(data->xfer); 537 if (error != USBD_IN_PROGRESS && error != 0) { 538 printf("%s: could not queue Rx xfer\n", 539 sc->sc_dev.dv_xname); 540 goto fail; 541 } 542 } 543 return 0; 544 545 fail: otus_close_pipes(sc); 546 return error; 547 } 548 549 void 550 otus_close_pipes(struct otus_softc *sc) 551 { 552 otus_free_tx_cmd(sc); 553 otus_free_tx_data_list(sc); 554 otus_free_rx_data_list(sc); 555 556 if (sc->data_rx_pipe != NULL) 557 usbd_close_pipe(sc->data_rx_pipe); 558 if (sc->cmd_rx_pipe != NULL) 559 usbd_close_pipe(sc->cmd_rx_pipe); 560 if (sc->ibuf != NULL) 561 free(sc->ibuf, M_USBDEV, sc->ibuflen); 562 if (sc->data_tx_pipe != NULL) 563 usbd_close_pipe(sc->data_tx_pipe); 564 if (sc->cmd_tx_pipe != NULL) 565 usbd_close_pipe(sc->cmd_tx_pipe); 566 } 567 568 int 569 otus_alloc_tx_cmd(struct otus_softc *sc) 570 { 571 struct otus_tx_cmd *cmd = &sc->tx_cmd; 572 573 cmd->xfer = usbd_alloc_xfer(sc->sc_udev); 574 if (cmd->xfer == NULL) { 575 printf("%s: could not allocate xfer\n", 576 sc->sc_dev.dv_xname); 577 return ENOMEM; 578 } 579 cmd->buf = usbd_alloc_buffer(cmd->xfer, OTUS_MAX_TXCMDSZ); 580 if (cmd->buf == NULL) { 581 printf("%s: could not allocate xfer buffer\n", 582 sc->sc_dev.dv_xname); 583 usbd_free_xfer(cmd->xfer); 584 cmd->xfer = NULL; 585 return ENOMEM; 586 } 587 return 0; 588 } 589 590 void 591 otus_free_tx_cmd(struct otus_softc *sc) 592 { 593 /* Make sure no transfers are pending. */ 594 usbd_abort_pipe(sc->cmd_tx_pipe); 595 596 if (sc->tx_cmd.xfer != NULL) 597 usbd_free_xfer(sc->tx_cmd.xfer); 598 } 599 600 int 601 otus_alloc_tx_data_list(struct otus_softc *sc) 602 { 603 struct otus_tx_data *data; 604 int i, error; 605 606 for (i = 0; i < OTUS_TX_DATA_LIST_COUNT; i++) { 607 data = &sc->tx_data[i]; 608 609 data->sc = sc; /* Backpointer for callbacks. */ 610 611 data->xfer = usbd_alloc_xfer(sc->sc_udev); 612 if (data->xfer == NULL) { 613 printf("%s: could not allocate xfer\n", 614 sc->sc_dev.dv_xname); 615 error = ENOMEM; 616 goto fail; 617 } 618 data->buf = usbd_alloc_buffer(data->xfer, OTUS_TXBUFSZ); 619 if (data->buf == NULL) { 620 printf("%s: could not allocate xfer buffer\n", 621 sc->sc_dev.dv_xname); 622 error = ENOMEM; 623 goto fail; 624 } 625 } 626 return 0; 627 628 fail: otus_free_tx_data_list(sc); 629 return error; 630 } 631 632 void 633 otus_free_tx_data_list(struct otus_softc *sc) 634 { 635 int i; 636 637 /* Make sure no transfers are pending. */ 638 usbd_abort_pipe(sc->data_tx_pipe); 639 640 for (i = 0; i < OTUS_TX_DATA_LIST_COUNT; i++) 641 if (sc->tx_data[i].xfer != NULL) 642 usbd_free_xfer(sc->tx_data[i].xfer); 643 } 644 645 int 646 otus_alloc_rx_data_list(struct otus_softc *sc) 647 { 648 struct otus_rx_data *data; 649 int i, error; 650 651 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) { 652 data = &sc->rx_data[i]; 653 654 data->sc = sc; /* Backpointer for callbacks. */ 655 656 data->xfer = usbd_alloc_xfer(sc->sc_udev); 657 if (data->xfer == NULL) { 658 printf("%s: could not allocate xfer\n", 659 sc->sc_dev.dv_xname); 660 error = ENOMEM; 661 goto fail; 662 } 663 data->buf = usbd_alloc_buffer(data->xfer, OTUS_RXBUFSZ); 664 if (data->buf == NULL) { 665 printf("%s: could not allocate xfer buffer\n", 666 sc->sc_dev.dv_xname); 667 error = ENOMEM; 668 goto fail; 669 } 670 } 671 return 0; 672 673 fail: otus_free_rx_data_list(sc); 674 return error; 675 } 676 677 void 678 otus_free_rx_data_list(struct otus_softc *sc) 679 { 680 int i; 681 682 /* Make sure no transfers are pending. */ 683 usbd_abort_pipe(sc->data_rx_pipe); 684 685 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) 686 if (sc->rx_data[i].xfer != NULL) 687 usbd_free_xfer(sc->rx_data[i].xfer); 688 } 689 690 void 691 otus_next_scan(void *arg) 692 { 693 struct otus_softc *sc = arg; 694 struct ieee80211com *ic = &sc->sc_ic; 695 struct ifnet *ifp = &ic->ic_if; 696 697 if (usbd_is_dying(sc->sc_udev)) 698 return; 699 700 usbd_ref_incr(sc->sc_udev); 701 702 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN && 703 (ifp->if_flags & IFF_RUNNING)) 704 ieee80211_next_scan(&sc->sc_ic.ic_if); 705 706 usbd_ref_decr(sc->sc_udev); 707 } 708 709 void 710 otus_task(void *arg) 711 { 712 struct otus_softc *sc = arg; 713 struct otus_host_cmd_ring *ring = &sc->cmdq; 714 struct otus_host_cmd *cmd; 715 int s; 716 717 /* Process host commands. */ 718 s = splusb(); 719 while (ring->next != ring->cur) { 720 cmd = &ring->cmd[ring->next]; 721 splx(s); 722 /* Callback. */ 723 cmd->cb(sc, cmd->data); 724 s = splusb(); 725 ring->queued--; 726 ring->next = (ring->next + 1) % OTUS_HOST_CMD_RING_COUNT; 727 } 728 splx(s); 729 } 730 731 void 732 otus_do_async(struct otus_softc *sc, void (*cb)(struct otus_softc *, void *), 733 void *arg, int len) 734 { 735 struct otus_host_cmd_ring *ring = &sc->cmdq; 736 struct otus_host_cmd *cmd; 737 int s; 738 739 s = splusb(); 740 cmd = &ring->cmd[ring->cur]; 741 cmd->cb = cb; 742 KASSERT(len <= sizeof (cmd->data)); 743 memcpy(cmd->data, arg, len); 744 ring->cur = (ring->cur + 1) % OTUS_HOST_CMD_RING_COUNT; 745 746 /* If there is no pending command already, schedule a task. */ 747 if (++ring->queued == 1) 748 usb_add_task(sc->sc_udev, &sc->sc_task); 749 splx(s); 750 } 751 752 int 753 otus_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 754 { 755 struct otus_softc *sc = ic->ic_softc; 756 struct otus_cmd_newstate cmd; 757 758 /* Do it in a process context. */ 759 cmd.state = nstate; 760 cmd.arg = arg; 761 otus_do_async(sc, otus_newstate_cb, &cmd, sizeof cmd); 762 return 0; 763 } 764 765 void 766 otus_newstate_cb(struct otus_softc *sc, void *arg) 767 { 768 struct otus_cmd_newstate *cmd = arg; 769 struct ieee80211com *ic = &sc->sc_ic; 770 struct ieee80211_node *ni; 771 int s; 772 773 s = splnet(); 774 775 switch (cmd->state) { 776 case IEEE80211_S_INIT: 777 break; 778 779 case IEEE80211_S_SCAN: 780 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 0); 781 if (!usbd_is_dying(sc->sc_udev)) 782 timeout_add_msec(&sc->scan_to, 200); 783 break; 784 785 case IEEE80211_S_AUTH: 786 case IEEE80211_S_ASSOC: 787 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 0); 788 break; 789 790 case IEEE80211_S_RUN: 791 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 1); 792 793 ni = ic->ic_bss; 794 795 if (ic->ic_opmode == IEEE80211_M_STA) { 796 otus_updateslot(ic); 797 otus_set_bssid(sc, ni->ni_bssid); 798 799 /* Fake a join to init the Tx rate. */ 800 otus_newassoc(ic, ni, 1); 801 802 /* Start calibration timer. */ 803 if (!usbd_is_dying(sc->sc_udev)) 804 timeout_add_sec(&sc->calib_to, 1); 805 } 806 break; 807 } 808 809 sc->sc_led_newstate(sc); 810 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 811 812 splx(s); 813 } 814 815 int 816 otus_cmd(struct otus_softc *sc, uint8_t code, const void *idata, int ilen, 817 void *odata) 818 { 819 struct otus_tx_cmd *cmd = &sc->tx_cmd; 820 struct ar_cmd_hdr *hdr; 821 int s, xferlen, error; 822 823 /* Always bulk-out a multiple of 4 bytes. */ 824 xferlen = (sizeof (*hdr) + ilen + 3) & ~3; 825 826 hdr = (struct ar_cmd_hdr *)cmd->buf; 827 hdr->code = code; 828 hdr->len = ilen; 829 hdr->token = ++cmd->token; /* Don't care about endianness. */ 830 memcpy((uint8_t *)&hdr[1], idata, ilen); 831 832 DPRINTFN(2, ("sending command code=0x%02x len=%d token=%d\n", 833 code, ilen, hdr->token)); 834 835 s = splusb(); 836 cmd->odata = odata; 837 cmd->done = 0; 838 839 usbd_setup_xfer(cmd->xfer, sc->cmd_tx_pipe, cmd, cmd->buf, xferlen, 840 USBD_FORCE_SHORT_XFER | USBD_NO_COPY | USBD_SYNCHRONOUS, 841 OTUS_CMD_TIMEOUT, NULL); 842 error = usbd_transfer(cmd->xfer); 843 if (error != 0) { 844 splx(s); 845 printf("%s: could not send command 0x%x (error=%s)\n", 846 sc->sc_dev.dv_xname, code, usbd_errstr(error)); 847 return EIO; 848 } 849 if (!cmd->done) 850 error = tsleep_nsec(cmd, PCATCH, "otuscmd", SEC_TO_NSEC(1)); 851 cmd->odata = NULL; /* In case answer is received too late. */ 852 splx(s); 853 if (error != 0) { 854 printf("%s: timeout waiting for command 0x%02x reply\n", 855 sc->sc_dev.dv_xname, code); 856 } 857 return error; 858 } 859 860 void 861 otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val) 862 { 863 sc->write_buf[sc->write_idx].reg = htole32(reg); 864 sc->write_buf[sc->write_idx].val = htole32(val); 865 866 if (++sc->write_idx > AR_MAX_WRITE_IDX) 867 (void)otus_write_barrier(sc); 868 } 869 870 int 871 otus_write_barrier(struct otus_softc *sc) 872 { 873 int error; 874 875 if (sc->write_idx == 0) 876 return 0; /* Nothing to flush. */ 877 878 error = otus_cmd(sc, AR_CMD_WREG, sc->write_buf, 879 sizeof (sc->write_buf[0]) * sc->write_idx, NULL); 880 sc->write_idx = 0; 881 return error; 882 } 883 884 struct ieee80211_node * 885 otus_node_alloc(struct ieee80211com *ic) 886 { 887 return malloc(sizeof (struct otus_node), M_USBDEV, M_NOWAIT | M_ZERO); 888 } 889 890 int 891 otus_media_change(struct ifnet *ifp) 892 { 893 struct otus_softc *sc = ifp->if_softc; 894 struct ieee80211com *ic = &sc->sc_ic; 895 uint8_t rate, ridx; 896 int error; 897 898 error = ieee80211_media_change(ifp); 899 if (error != ENETRESET) 900 return error; 901 902 if (ic->ic_fixed_rate != -1) { 903 rate = ic->ic_sup_rates[ic->ic_curmode]. 904 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 905 for (ridx = 0; ridx <= OTUS_RIDX_MAX; ridx++) 906 if (otus_rates[ridx].rate == rate) 907 break; 908 sc->fixed_ridx = ridx; 909 } 910 911 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 912 error = otus_init(ifp); 913 914 return error; 915 } 916 917 int 918 otus_read_eeprom(struct otus_softc *sc) 919 { 920 uint32_t regs[8], reg; 921 uint8_t *eep; 922 int i, j, error; 923 924 /* Read EEPROM by blocks of 32 bytes. */ 925 eep = (uint8_t *)&sc->eeprom; 926 reg = AR_EEPROM_OFFSET; 927 for (i = 0; i < sizeof (sc->eeprom) / 32; i++) { 928 for (j = 0; j < 8; j++, reg += 4) 929 regs[j] = htole32(reg); 930 error = otus_cmd(sc, AR_CMD_RREG, regs, sizeof regs, eep); 931 if (error != 0) 932 break; 933 eep += 32; 934 } 935 return error; 936 } 937 938 void 939 otus_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 940 { 941 struct otus_softc *sc = ic->ic_softc; 942 struct otus_node *on = (void *)ni; 943 struct ieee80211_rateset *rs = &ni->ni_rates; 944 uint8_t rate; 945 int ridx, i; 946 947 DPRINTF(("new assoc isnew=%d addr=%s\n", 948 isnew, ether_sprintf(ni->ni_macaddr))); 949 950 ieee80211_amrr_node_init(&sc->amrr, &on->amn); 951 /* Start at lowest available bit-rate, AMRR will raise. */ 952 ni->ni_txrate = 0; 953 954 for (i = 0; i < rs->rs_nrates; i++) { 955 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 956 /* Convert 802.11 rate to hardware rate index. */ 957 for (ridx = 0; ridx <= OTUS_RIDX_MAX; ridx++) 958 if (otus_rates[ridx].rate == rate) 959 break; 960 on->ridx[i] = ridx; 961 DPRINTF(("rate=0x%02x ridx=%d\n", 962 rs->rs_rates[i], on->ridx[i])); 963 } 964 } 965 966 /* ARGSUSED */ 967 void 968 otus_intr(struct usbd_xfer *xfer, void *priv, usbd_status status) 969 { 970 #if 0 971 struct otus_softc *sc = priv; 972 int len; 973 974 /* 975 * The Rx intr pipe is unused with current firmware. Notifications 976 * and replies to commands are sent through the Rx bulk pipe instead 977 * (with a magic PLCP header.) 978 */ 979 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 980 DPRINTF(("intr status=%d\n", status)); 981 if (status == USBD_STALLED) 982 usbd_clear_endpoint_stall_async(sc->cmd_rx_pipe); 983 return; 984 } 985 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 986 987 otus_cmd_rxeof(sc, sc->ibuf, len); 988 #endif 989 } 990 991 void 992 otus_cmd_rxeof(struct otus_softc *sc, uint8_t *buf, int len) 993 { 994 struct ieee80211com *ic = &sc->sc_ic; 995 struct otus_tx_cmd *cmd; 996 struct ar_cmd_hdr *hdr; 997 int s; 998 999 if (__predict_false(len < sizeof (*hdr))) { 1000 DPRINTF(("cmd too small %d\n", len)); 1001 return; 1002 } 1003 hdr = (struct ar_cmd_hdr *)buf; 1004 if (__predict_false(sizeof (*hdr) + hdr->len > len || 1005 sizeof (*hdr) + hdr->len > 64)) { 1006 DPRINTF(("cmd too large %d\n", hdr->len)); 1007 return; 1008 } 1009 1010 if ((hdr->code & 0xc0) != 0xc0) { 1011 DPRINTFN(2, ("received reply code=0x%02x len=%d token=%d\n", 1012 hdr->code, hdr->len, hdr->token)); 1013 cmd = &sc->tx_cmd; 1014 if (__predict_false(hdr->token != cmd->token)) 1015 return; 1016 /* Copy answer into caller's supplied buffer. */ 1017 if (cmd->odata != NULL) 1018 memcpy(cmd->odata, &hdr[1], hdr->len); 1019 cmd->done = 1; 1020 wakeup(cmd); 1021 return; 1022 } 1023 1024 /* Received unsolicited notification. */ 1025 DPRINTF(("received notification code=0x%02x len=%d\n", 1026 hdr->code, hdr->len)); 1027 switch (hdr->code & 0x3f) { 1028 case AR_EVT_BEACON: 1029 break; 1030 case AR_EVT_TX_COMP: 1031 { 1032 struct ar_evt_tx_comp *tx = (struct ar_evt_tx_comp *)&hdr[1]; 1033 struct ieee80211_node *ni; 1034 struct otus_node *on; 1035 1036 DPRINTF(("tx completed %s status=%d phy=0x%x\n", 1037 ether_sprintf(tx->macaddr), letoh16(tx->status), 1038 letoh32(tx->phy))); 1039 s = splnet(); 1040 #ifdef notyet 1041 #ifndef IEEE80211_STA_ONLY 1042 if (ic->ic_opmode != IEEE80211_M_STA) { 1043 ni = ieee80211_find_node(ic, tx->macaddr); 1044 if (__predict_false(ni == NULL)) { 1045 splx(s); 1046 break; 1047 } 1048 } else 1049 #endif 1050 #endif 1051 ni = ic->ic_bss; 1052 /* Update rate control statistics. */ 1053 on = (void *)ni; 1054 /* NB: we do not set the TX_MAC_RATE_PROBING flag. */ 1055 if (__predict_true(tx->status != 0)) 1056 on->amn.amn_retrycnt++; 1057 splx(s); 1058 break; 1059 } 1060 case AR_EVT_TBTT: 1061 break; 1062 } 1063 } 1064 1065 void 1066 otus_sub_rxeof(struct otus_softc *sc, uint8_t *buf, int len, 1067 struct mbuf_list *ml) 1068 { 1069 struct ieee80211com *ic = &sc->sc_ic; 1070 struct ifnet *ifp = &ic->ic_if; 1071 struct ieee80211_rxinfo rxi; 1072 struct ieee80211_node *ni; 1073 struct ar_rx_tail *tail; 1074 struct ieee80211_frame *wh; 1075 struct mbuf *m; 1076 uint8_t *plcp; 1077 int s, mlen, align; 1078 1079 if (__predict_false(len < AR_PLCP_HDR_LEN)) { 1080 DPRINTF(("sub-xfer too short %d\n", len)); 1081 return; 1082 } 1083 plcp = buf; 1084 1085 /* All bits in the PLCP header are set to 1 for non-MPDU. */ 1086 if (memcmp(plcp, AR_PLCP_HDR_INTR, AR_PLCP_HDR_LEN) == 0) { 1087 otus_cmd_rxeof(sc, plcp + AR_PLCP_HDR_LEN, 1088 len - AR_PLCP_HDR_LEN); 1089 return; 1090 } 1091 1092 /* Received MPDU. */ 1093 if (__predict_false(len < AR_PLCP_HDR_LEN + sizeof (*tail))) { 1094 DPRINTF(("MPDU too short %d\n", len)); 1095 ifp->if_ierrors++; 1096 return; 1097 } 1098 tail = (struct ar_rx_tail *)(plcp + len - sizeof (*tail)); 1099 1100 /* Discard error frames. */ 1101 if (__predict_false(tail->error != 0)) { 1102 DPRINTF(("error frame 0x%02x\n", tail->error)); 1103 if (tail->error & AR_RX_ERROR_FCS) { 1104 DPRINTFN(3, ("bad FCS\n")); 1105 } else if (tail->error & AR_RX_ERROR_MMIC) { 1106 /* Report Michael MIC failures to net80211. */ 1107 ic->ic_stats.is_rx_locmicfail++; 1108 ieee80211_michael_mic_failure(ic, 0); 1109 } 1110 ifp->if_ierrors++; 1111 return; 1112 } 1113 /* Compute MPDU's length. */ 1114 mlen = len - AR_PLCP_HDR_LEN - sizeof (*tail); 1115 /* Make sure there's room for an 802.11 header + FCS. */ 1116 if (__predict_false(mlen < IEEE80211_MIN_LEN)) { 1117 ifp->if_ierrors++; 1118 return; 1119 } 1120 mlen -= IEEE80211_CRC_LEN; /* strip 802.11 FCS */ 1121 if (mlen > MCLBYTES) { 1122 DPRINTF(("frame too large: %d\n", mlen)); 1123 ifp->if_ierrors++; 1124 return; 1125 } 1126 1127 wh = (struct ieee80211_frame *)(plcp + AR_PLCP_HDR_LEN); 1128 /* Provide a 32-bit aligned protocol header to the stack. */ 1129 align = (ieee80211_has_qos(wh) ^ ieee80211_has_addr4(wh)) ? 2 : 0; 1130 1131 MGETHDR(m, M_DONTWAIT, MT_DATA); 1132 if (__predict_false(m == NULL)) { 1133 ifp->if_ierrors++; 1134 return; 1135 } 1136 if (align + mlen > MHLEN) { 1137 MCLGET(m, M_DONTWAIT); 1138 if (__predict_false(!(m->m_flags & M_EXT))) { 1139 ifp->if_ierrors++; 1140 m_freem(m); 1141 return; 1142 } 1143 } 1144 /* Finalize mbuf. */ 1145 m->m_data += align; 1146 memcpy(mtod(m, caddr_t), wh, mlen); 1147 m->m_pkthdr.len = m->m_len = mlen; 1148 1149 #if NBPFILTER > 0 1150 if (__predict_false(sc->sc_drvbpf != NULL)) { 1151 struct otus_rx_radiotap_header *tap = &sc->sc_rxtap; 1152 struct mbuf mb; 1153 1154 tap->wr_flags = 0; 1155 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1156 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1157 tap->wr_antsignal = tail->rssi; 1158 tap->wr_rate = 2; /* In case it can't be found below. */ 1159 switch (tail->status & AR_RX_STATUS_MT_MASK) { 1160 case AR_RX_STATUS_MT_CCK: 1161 switch (plcp[0]) { 1162 case 10: tap->wr_rate = 2; break; 1163 case 20: tap->wr_rate = 4; break; 1164 case 55: tap->wr_rate = 11; break; 1165 case 110: tap->wr_rate = 22; break; 1166 } 1167 if (tail->status & AR_RX_STATUS_SHPREAMBLE) 1168 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1169 break; 1170 case AR_RX_STATUS_MT_OFDM: 1171 switch (plcp[0] & 0xf) { 1172 case 0xb: tap->wr_rate = 12; break; 1173 case 0xf: tap->wr_rate = 18; break; 1174 case 0xa: tap->wr_rate = 24; break; 1175 case 0xe: tap->wr_rate = 36; break; 1176 case 0x9: tap->wr_rate = 48; break; 1177 case 0xd: tap->wr_rate = 72; break; 1178 case 0x8: tap->wr_rate = 96; break; 1179 case 0xc: tap->wr_rate = 108; break; 1180 } 1181 break; 1182 } 1183 mb.m_data = (caddr_t)tap; 1184 mb.m_len = sc->sc_rxtap_len; 1185 mb.m_next = m; 1186 mb.m_nextpkt = NULL; 1187 mb.m_type = 0; 1188 mb.m_flags = 0; 1189 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1190 } 1191 #endif 1192 1193 s = splnet(); 1194 ni = ieee80211_find_rxnode(ic, wh); 1195 rxi.rxi_flags = 0; 1196 rxi.rxi_rssi = tail->rssi; 1197 rxi.rxi_tstamp = 0; /* unused */ 1198 ieee80211_inputm(ifp, m, ni, &rxi, ml); 1199 1200 /* Node is no longer needed. */ 1201 ieee80211_release_node(ic, ni); 1202 splx(s); 1203 } 1204 1205 void 1206 otus_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1207 { 1208 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1209 struct otus_rx_data *data = priv; 1210 struct otus_softc *sc = data->sc; 1211 caddr_t buf = data->buf; 1212 struct ar_rx_head *head; 1213 uint16_t hlen; 1214 int len; 1215 1216 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1217 DPRINTF(("RX status=%d\n", status)); 1218 if (status == USBD_STALLED) 1219 usbd_clear_endpoint_stall_async(sc->data_rx_pipe); 1220 if (status != USBD_CANCELLED) 1221 goto resubmit; 1222 return; 1223 } 1224 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1225 1226 while (len >= sizeof (*head)) { 1227 head = (struct ar_rx_head *)buf; 1228 if (__predict_false(head->tag != htole16(AR_RX_HEAD_TAG))) { 1229 DPRINTF(("tag not valid 0x%x\n", letoh16(head->tag))); 1230 break; 1231 } 1232 hlen = letoh16(head->len); 1233 if (__predict_false(sizeof (*head) + hlen > len)) { 1234 DPRINTF(("xfer too short %d/%d\n", len, hlen)); 1235 break; 1236 } 1237 /* Process sub-xfer. */ 1238 otus_sub_rxeof(sc, (uint8_t *)&head[1], hlen, &ml); 1239 1240 /* Next sub-xfer is aligned on a 32-bit boundary. */ 1241 hlen = (sizeof (*head) + hlen + 3) & ~3; 1242 buf += hlen; 1243 len -= hlen; 1244 } 1245 if_input(&sc->sc_ic.ic_if, &ml); 1246 1247 resubmit: 1248 usbd_setup_xfer(xfer, sc->data_rx_pipe, data, data->buf, OTUS_RXBUFSZ, 1249 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, otus_rxeof); 1250 (void)usbd_transfer(data->xfer); 1251 } 1252 1253 void 1254 otus_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1255 { 1256 struct otus_tx_data *data = priv; 1257 struct otus_softc *sc = data->sc; 1258 struct ieee80211com *ic = &sc->sc_ic; 1259 struct ifnet *ifp = &ic->ic_if; 1260 int s; 1261 1262 s = splnet(); 1263 sc->tx_queued--; 1264 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1265 DPRINTF(("TX status=%d\n", status)); 1266 if (status == USBD_STALLED) 1267 usbd_clear_endpoint_stall_async(sc->data_tx_pipe); 1268 ifp->if_oerrors++; 1269 splx(s); 1270 return; 1271 } 1272 sc->sc_tx_timer = 0; 1273 ifq_clr_oactive(&ifp->if_snd); 1274 otus_start(ifp); 1275 splx(s); 1276 } 1277 1278 int 1279 otus_tx(struct otus_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1280 { 1281 struct ieee80211com *ic = &sc->sc_ic; 1282 struct otus_node *on = (void *)ni; 1283 struct otus_tx_data *data; 1284 struct ieee80211_frame *wh; 1285 struct ieee80211_key *k; 1286 struct ar_tx_head *head; 1287 uint32_t phyctl; 1288 uint16_t macctl, qos; 1289 uint8_t tid, qid; 1290 int error, ridx, hasqos, xferlen; 1291 1292 wh = mtod(m, struct ieee80211_frame *); 1293 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1294 k = ieee80211_get_txkey(ic, wh, ni); 1295 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1296 return ENOBUFS; 1297 wh = mtod(m, struct ieee80211_frame *); 1298 } 1299 1300 if ((hasqos = ieee80211_has_qos(wh))) { 1301 qos = ieee80211_get_qos(wh); 1302 tid = qos & IEEE80211_QOS_TID; 1303 qid = ieee80211_up_to_ac(ic, tid); 1304 } else { 1305 qos = 0; 1306 qid = EDCA_AC_BE; 1307 } 1308 1309 /* Pickup a rate index. */ 1310 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1311 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA) 1312 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1313 OTUS_RIDX_OFDM6 : OTUS_RIDX_CCK1; 1314 else if (ic->ic_fixed_rate != -1) 1315 ridx = sc->fixed_ridx; 1316 else 1317 ridx = on->ridx[ni->ni_txrate]; 1318 1319 phyctl = 0; 1320 macctl = AR_TX_MAC_BACKOFF | AR_TX_MAC_HW_DUR | AR_TX_MAC_QID(qid); 1321 1322 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1323 (hasqos && ((qos & IEEE80211_QOS_ACK_POLICY_MASK) == 1324 IEEE80211_QOS_ACK_POLICY_NOACK))) 1325 macctl |= AR_TX_MAC_NOACK; 1326 1327 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1328 if (m->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold) 1329 macctl |= AR_TX_MAC_RTS; 1330 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1331 ridx >= OTUS_RIDX_OFDM6) { 1332 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1333 macctl |= AR_TX_MAC_CTS; 1334 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1335 macctl |= AR_TX_MAC_RTS; 1336 } 1337 } 1338 1339 phyctl |= AR_TX_PHY_MCS(otus_rates[ridx].mcs); 1340 if (ridx >= OTUS_RIDX_OFDM6) { 1341 phyctl |= AR_TX_PHY_MT_OFDM; 1342 if (ridx <= OTUS_RIDX_OFDM24) 1343 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 1344 else 1345 phyctl |= AR_TX_PHY_ANTMSK(1); 1346 } else { /* CCK */ 1347 phyctl |= AR_TX_PHY_MT_CCK; 1348 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 1349 } 1350 1351 /* Update rate control stats for frames that are ACK'ed. */ 1352 if (!(macctl & AR_TX_MAC_NOACK)) 1353 ((struct otus_node *)ni)->amn.amn_txcnt++; 1354 1355 data = &sc->tx_data[sc->tx_cur]; 1356 /* Fill Tx descriptor. */ 1357 head = (struct ar_tx_head *)data->buf; 1358 head->len = htole16(m->m_pkthdr.len + IEEE80211_CRC_LEN); 1359 head->macctl = htole16(macctl); 1360 head->phyctl = htole32(phyctl); 1361 1362 #if NBPFILTER > 0 1363 if (__predict_false(sc->sc_drvbpf != NULL)) { 1364 struct otus_tx_radiotap_header *tap = &sc->sc_txtap; 1365 struct mbuf mb; 1366 1367 tap->wt_flags = 0; 1368 tap->wt_rate = otus_rates[ridx].rate; 1369 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1370 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1371 1372 mb.m_data = (caddr_t)tap; 1373 mb.m_len = sc->sc_txtap_len; 1374 mb.m_next = m; 1375 mb.m_nextpkt = NULL; 1376 mb.m_type = 0; 1377 mb.m_flags = 0; 1378 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1379 } 1380 #endif 1381 1382 xferlen = sizeof (*head) + m->m_pkthdr.len; 1383 m_copydata(m, 0, m->m_pkthdr.len, &head[1]); 1384 m_freem(m); 1385 1386 DPRINTFN(5, ("tx queued=%d len=%d mac=0x%04x phy=0x%08x rate=%d\n", 1387 sc->tx_queued, head->len, head->macctl, head->phyctl, 1388 otus_rates[ridx].rate)); 1389 usbd_setup_xfer(data->xfer, sc->data_tx_pipe, data, data->buf, xferlen, 1390 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, OTUS_TX_TIMEOUT, otus_txeof); 1391 error = usbd_transfer(data->xfer); 1392 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) 1393 return error; 1394 1395 ieee80211_release_node(ic, ni); 1396 1397 sc->tx_queued++; 1398 sc->tx_cur = (sc->tx_cur + 1) % OTUS_TX_DATA_LIST_COUNT; 1399 1400 return 0; 1401 } 1402 1403 void 1404 otus_start(struct ifnet *ifp) 1405 { 1406 struct otus_softc *sc = ifp->if_softc; 1407 struct ieee80211com *ic = &sc->sc_ic; 1408 struct ieee80211_node *ni; 1409 struct mbuf *m; 1410 1411 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1412 return; 1413 1414 for (;;) { 1415 if (sc->tx_queued >= OTUS_TX_DATA_LIST_COUNT) { 1416 ifq_set_oactive(&ifp->if_snd); 1417 break; 1418 } 1419 /* Send pending management frames first. */ 1420 m = mq_dequeue(&ic->ic_mgtq); 1421 if (m != NULL) { 1422 ni = m->m_pkthdr.ph_cookie; 1423 goto sendit; 1424 } 1425 if (ic->ic_state != IEEE80211_S_RUN) 1426 break; 1427 1428 /* Encapsulate and send data frames. */ 1429 m = ifq_dequeue(&ifp->if_snd); 1430 if (m == NULL) 1431 break; 1432 #if NBPFILTER > 0 1433 if (ifp->if_bpf != NULL) 1434 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1435 #endif 1436 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1437 continue; 1438 sendit: 1439 #if NBPFILTER > 0 1440 if (ic->ic_rawbpf != NULL) 1441 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1442 #endif 1443 if (otus_tx(sc, m, ni) != 0) { 1444 ieee80211_release_node(ic, ni); 1445 ifp->if_oerrors++; 1446 continue; 1447 } 1448 1449 sc->sc_tx_timer = 5; 1450 ifp->if_timer = 1; 1451 } 1452 } 1453 1454 void 1455 otus_watchdog(struct ifnet *ifp) 1456 { 1457 struct otus_softc *sc = ifp->if_softc; 1458 1459 ifp->if_timer = 0; 1460 1461 if (sc->sc_tx_timer > 0) { 1462 if (--sc->sc_tx_timer == 0) { 1463 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1464 /* otus_init(ifp); XXX needs a process context! */ 1465 ifp->if_oerrors++; 1466 return; 1467 } 1468 ifp->if_timer = 1; 1469 } 1470 ieee80211_watchdog(ifp); 1471 } 1472 1473 int 1474 otus_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1475 { 1476 struct otus_softc *sc = ifp->if_softc; 1477 struct ieee80211com *ic = &sc->sc_ic; 1478 int s, error = 0; 1479 1480 if (usbd_is_dying(sc->sc_udev)) 1481 return ENXIO; 1482 1483 usbd_ref_incr(sc->sc_udev); 1484 1485 s = splnet(); 1486 1487 switch (cmd) { 1488 case SIOCSIFADDR: 1489 ifp->if_flags |= IFF_UP; 1490 /* FALLTHROUGH */ 1491 case SIOCSIFFLAGS: 1492 if (ifp->if_flags & IFF_UP) { 1493 if ((ifp->if_flags & IFF_RUNNING) && 1494 ((ifp->if_flags ^ sc->sc_if_flags) & 1495 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1496 otus_set_multi(sc); 1497 } else if (!(ifp->if_flags & IFF_RUNNING)) 1498 otus_init(ifp); 1499 1500 } else if (ifp->if_flags & IFF_RUNNING) 1501 otus_stop(ifp); 1502 1503 sc->sc_if_flags = ifp->if_flags; 1504 break; 1505 case SIOCS80211CHANNEL: 1506 error = ieee80211_ioctl(ifp, cmd, data); 1507 if (error == ENETRESET && 1508 ic->ic_opmode == IEEE80211_M_MONITOR) { 1509 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1510 (IFF_UP | IFF_RUNNING)) 1511 otus_set_chan(sc, ic->ic_ibss_chan, 0); 1512 error = 0; 1513 } 1514 break; 1515 default: 1516 error = ieee80211_ioctl(ifp, cmd, data); 1517 } 1518 1519 if (error == ENETRESET) { 1520 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1521 (IFF_UP | IFF_RUNNING)) 1522 otus_init(ifp); 1523 error = 0; 1524 } 1525 1526 splx(s); 1527 1528 usbd_ref_decr(sc->sc_udev); 1529 1530 return error; 1531 } 1532 1533 int 1534 otus_set_multi(struct otus_softc *sc) 1535 { 1536 struct arpcom *ac = &sc->sc_ic.ic_ac; 1537 struct ifnet *ifp = &ac->ac_if; 1538 struct ether_multi *enm; 1539 struct ether_multistep step; 1540 uint32_t lo, hi; 1541 uint8_t bit; 1542 1543 if (ac->ac_multirangecnt > 0) 1544 ifp->if_flags |= IFF_ALLMULTI; 1545 1546 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1547 lo = hi = 0xffffffff; 1548 goto done; 1549 } 1550 lo = hi = 0; 1551 ETHER_FIRST_MULTI(step, ac, enm); 1552 while (enm != NULL) { 1553 bit = enm->enm_addrlo[5] >> 2; 1554 if (bit < 32) 1555 lo |= 1 << bit; 1556 else 1557 hi |= 1 << (bit - 32); 1558 ETHER_NEXT_MULTI(step, enm); 1559 } 1560 done: 1561 hi |= 1U << 31; /* Make sure the broadcast bit is set. */ 1562 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, lo); 1563 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hi); 1564 return otus_write_barrier(sc); 1565 } 1566 1567 void 1568 otus_updateedca(struct ieee80211com *ic) 1569 { 1570 /* Do it in a process context. */ 1571 otus_do_async(ic->ic_softc, otus_updateedca_cb, NULL, 0); 1572 } 1573 1574 /* ARGSUSED */ 1575 void 1576 otus_updateedca_cb(struct otus_softc *sc, void *arg) 1577 { 1578 #define EXP2(val) ((1 << (val)) - 1) 1579 #define AIFS(val) ((val) * 9 + 10) 1580 struct ieee80211com *ic = &sc->sc_ic; 1581 const struct ieee80211_edca_ac_params *edca; 1582 int s; 1583 1584 s = splnet(); 1585 1586 edca = (ic->ic_flags & IEEE80211_F_QOS) ? 1587 ic->ic_edca_ac : otus_edca_def; 1588 1589 /* Set CWmin/CWmax values. */ 1590 otus_write(sc, AR_MAC_REG_AC0_CW, 1591 EXP2(edca[EDCA_AC_BE].ac_ecwmax) << 16 | 1592 EXP2(edca[EDCA_AC_BE].ac_ecwmin)); 1593 otus_write(sc, AR_MAC_REG_AC1_CW, 1594 EXP2(edca[EDCA_AC_BK].ac_ecwmax) << 16 | 1595 EXP2(edca[EDCA_AC_BK].ac_ecwmin)); 1596 otus_write(sc, AR_MAC_REG_AC2_CW, 1597 EXP2(edca[EDCA_AC_VI].ac_ecwmax) << 16 | 1598 EXP2(edca[EDCA_AC_VI].ac_ecwmin)); 1599 otus_write(sc, AR_MAC_REG_AC3_CW, 1600 EXP2(edca[EDCA_AC_VO].ac_ecwmax) << 16 | 1601 EXP2(edca[EDCA_AC_VO].ac_ecwmin)); 1602 otus_write(sc, AR_MAC_REG_AC4_CW, /* Special TXQ. */ 1603 EXP2(edca[EDCA_AC_VO].ac_ecwmax) << 16 | 1604 EXP2(edca[EDCA_AC_VO].ac_ecwmin)); 1605 1606 /* Set AIFSN values. */ 1607 otus_write(sc, AR_MAC_REG_AC1_AC0_AIFS, 1608 AIFS(edca[EDCA_AC_VI].ac_aifsn) << 24 | 1609 AIFS(edca[EDCA_AC_BK].ac_aifsn) << 12 | 1610 AIFS(edca[EDCA_AC_BE].ac_aifsn)); 1611 otus_write(sc, AR_MAC_REG_AC3_AC2_AIFS, 1612 AIFS(edca[EDCA_AC_VO].ac_aifsn) << 16 | /* Special TXQ. */ 1613 AIFS(edca[EDCA_AC_VO].ac_aifsn) << 4 | 1614 AIFS(edca[EDCA_AC_VI].ac_aifsn) >> 8); 1615 1616 /* Set TXOP limit. */ 1617 otus_write(sc, AR_MAC_REG_AC1_AC0_TXOP, 1618 edca[EDCA_AC_BK].ac_txoplimit << 16 | 1619 edca[EDCA_AC_BE].ac_txoplimit); 1620 otus_write(sc, AR_MAC_REG_AC3_AC2_TXOP, 1621 edca[EDCA_AC_VO].ac_txoplimit << 16 | 1622 edca[EDCA_AC_VI].ac_txoplimit); 1623 1624 splx(s); 1625 1626 (void)otus_write_barrier(sc); 1627 #undef AIFS 1628 #undef EXP2 1629 } 1630 1631 void 1632 otus_updateslot(struct ieee80211com *ic) 1633 { 1634 /* Do it in a process context. */ 1635 otus_do_async(ic->ic_softc, otus_updateslot_cb, NULL, 0); 1636 } 1637 1638 /* ARGSUSED */ 1639 void 1640 otus_updateslot_cb(struct otus_softc *sc, void *arg) 1641 { 1642 uint32_t slottime; 1643 1644 slottime = (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 1645 IEEE80211_DUR_DS_SHSLOT: IEEE80211_DUR_DS_SLOT; 1646 otus_write(sc, AR_MAC_REG_SLOT_TIME, slottime << 10); 1647 (void)otus_write_barrier(sc); 1648 } 1649 1650 int 1651 otus_init_mac(struct otus_softc *sc) 1652 { 1653 int error; 1654 1655 otus_write(sc, AR_MAC_REG_ACK_EXTENSION, 0x40); 1656 otus_write(sc, AR_MAC_REG_RETRY_MAX, 0); 1657 otus_write(sc, AR_MAC_REG_SNIFFER, 0x2000000); 1658 otus_write(sc, AR_MAC_REG_RX_THRESHOLD, 0xc1f80); 1659 otus_write(sc, AR_MAC_REG_RX_PE_DELAY, 0x70); 1660 otus_write(sc, AR_MAC_REG_EIFS_AND_SIFS, 0xa144000); 1661 otus_write(sc, AR_MAC_REG_SLOT_TIME, 9 << 10); 1662 otus_write(sc, 0x1c3b2c, 0x19000000); 1663 /* NAV protects ACK only (in TXOP). */ 1664 otus_write(sc, 0x1c3b38, 0x201); 1665 /* Set beacon Tx power to 0x7. */ 1666 otus_write(sc, AR_MAC_REG_BCN_HT1, 0x8000170); 1667 otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105); 1668 otus_write(sc, 0x1c3b9c, 0x10000a); 1669 /* Filter any control frames, BAR is bit 24. */ 1670 otus_write(sc, 0x1c368c, 0x0500ffff); 1671 otus_write(sc, 0x1c3c40, 0x1); 1672 otus_write(sc, AR_MAC_REG_BASIC_RATE, 0x150f); 1673 otus_write(sc, AR_MAC_REG_MANDATORY_RATE, 0x150f); 1674 otus_write(sc, AR_MAC_REG_RTS_CTS_RATE, 0x10b01bb); 1675 otus_write(sc, 0x1c3694, 0x4003c1e); 1676 /* Enable LED0 and LED1. */ 1677 otus_write(sc, 0x1d0100, 0x3); 1678 otus_write(sc, 0x1d0104, 0x3); 1679 /* Switch MAC to OTUS interface. */ 1680 otus_write(sc, 0x1c3600, 0x3); 1681 otus_write(sc, 0x1c3c50, 0xffff); 1682 otus_write(sc, 0x1c3680, 0xf00008); 1683 /* Disable Rx timeout (workaround). */ 1684 otus_write(sc, 0x1c362c, 0); 1685 1686 /* Set USB Rx stream mode maximum frame number to 2. */ 1687 otus_write(sc, 0x1e1110, 0x4); 1688 /* Set USB Rx stream mode timeout to 10us. */ 1689 otus_write(sc, 0x1e1114, 0x80); 1690 1691 /* Set clock frequency to 88/80MHz. */ 1692 otus_write(sc, 0x1d4008, 0x73); 1693 /* Set WLAN DMA interrupt mode: generate intr per packet. */ 1694 otus_write(sc, 0x1c3d7c, 0x110011); 1695 otus_write(sc, 0x1c3bb0, 0x4); 1696 otus_write(sc, AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141e0f48); 1697 1698 /* Disable HW decryption for now. */ 1699 otus_write(sc, 0x1c3678, 0x78); 1700 1701 if ((error = otus_write_barrier(sc)) != 0) 1702 return error; 1703 1704 /* Set default EDCA parameters. */ 1705 otus_updateedca_cb(sc, NULL); 1706 1707 return 0; 1708 } 1709 1710 /* 1711 * Return default value for PHY register based on current operating mode. 1712 */ 1713 uint32_t 1714 otus_phy_get_def(struct otus_softc *sc, uint32_t reg) 1715 { 1716 int i; 1717 1718 for (i = 0; i < nitems(ar5416_phy_regs); i++) 1719 if (AR_PHY(ar5416_phy_regs[i]) == reg) 1720 return sc->phy_vals[i]; 1721 return 0; /* Register not found. */ 1722 } 1723 1724 /* 1725 * Update PHY's programming based on vendor-specific data stored in EEPROM. 1726 * This is for FEM-type devices only. 1727 */ 1728 int 1729 otus_set_board_values(struct otus_softc *sc, struct ieee80211_channel *c) 1730 { 1731 const struct ModalEepHeader *eep; 1732 uint32_t tmp, offset; 1733 1734 if (IEEE80211_IS_CHAN_5GHZ(c)) 1735 eep = &sc->eeprom.modalHeader[0]; 1736 else 1737 eep = &sc->eeprom.modalHeader[1]; 1738 1739 /* Offset of chain 2. */ 1740 offset = 2 * 0x1000; 1741 1742 tmp = letoh32(eep->antCtrlCommon); 1743 otus_write(sc, AR_PHY_SWITCH_COM, tmp); 1744 1745 tmp = letoh32(eep->antCtrlChain[0]); 1746 otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp); 1747 1748 tmp = letoh32(eep->antCtrlChain[1]); 1749 otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp); 1750 1751 if (1 /* sc->sc_sco == AR_SCO_SCN */) { 1752 tmp = otus_phy_get_def(sc, AR_PHY_SETTLING); 1753 tmp &= ~(0x7f << 7); 1754 tmp |= (eep->switchSettling & 0x7f) << 7; 1755 otus_write(sc, AR_PHY_SETTLING, tmp); 1756 } 1757 1758 tmp = otus_phy_get_def(sc, AR_PHY_DESIRED_SZ); 1759 tmp &= ~0xffff; 1760 tmp |= eep->pgaDesiredSize << 8 | eep->adcDesiredSize; 1761 otus_write(sc, AR_PHY_DESIRED_SZ, tmp); 1762 1763 tmp = eep->txEndToXpaOff << 24 | eep->txEndToXpaOff << 16 | 1764 eep->txFrameToXpaOn << 8 | eep->txFrameToXpaOn; 1765 otus_write(sc, AR_PHY_RF_CTL4, tmp); 1766 1767 tmp = otus_phy_get_def(sc, AR_PHY_RF_CTL3); 1768 tmp &= ~(0xff << 16); 1769 tmp |= eep->txEndToRxOn << 16; 1770 otus_write(sc, AR_PHY_RF_CTL3, tmp); 1771 1772 tmp = otus_phy_get_def(sc, AR_PHY_CCA); 1773 tmp &= ~(0x7f << 12); 1774 tmp |= (eep->thresh62 & 0x7f) << 12; 1775 otus_write(sc, AR_PHY_CCA, tmp); 1776 1777 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN); 1778 tmp &= ~(0x3f << 12); 1779 tmp |= (eep->txRxAttenCh[0] & 0x3f) << 12; 1780 otus_write(sc, AR_PHY_RXGAIN, tmp); 1781 1782 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN + offset); 1783 tmp &= ~(0x3f << 12); 1784 tmp |= (eep->txRxAttenCh[1] & 0x3f) << 12; 1785 otus_write(sc, AR_PHY_RXGAIN + offset, tmp); 1786 1787 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ); 1788 tmp &= ~(0x3f << 18); 1789 tmp |= (eep->rxTxMarginCh[0] & 0x3f) << 18; 1790 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1791 tmp &= ~(0xf << 10); 1792 tmp |= (eep->bswMargin[0] & 0xf) << 10; 1793 } 1794 otus_write(sc, AR_PHY_GAIN_2GHZ, tmp); 1795 1796 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ + offset); 1797 tmp &= ~(0x3f << 18); 1798 tmp |= (eep->rxTxMarginCh[1] & 0x3f) << 18; 1799 otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp); 1800 1801 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4); 1802 tmp &= ~(0x3f << 5 | 0x1f); 1803 tmp |= (eep->iqCalICh[0] & 0x3f) << 5 | (eep->iqCalQCh[0] & 0x1f); 1804 otus_write(sc, AR_PHY_TIMING_CTRL4, tmp); 1805 1806 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset); 1807 tmp &= ~(0x3f << 5 | 0x1f); 1808 tmp |= (eep->iqCalICh[1] & 0x3f) << 5 | (eep->iqCalQCh[1] & 0x1f); 1809 otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp); 1810 1811 tmp = otus_phy_get_def(sc, AR_PHY_TPCRG1); 1812 tmp &= ~(0xf << 16); 1813 tmp |= (eep->xpd & 0xf) << 16; 1814 otus_write(sc, AR_PHY_TPCRG1, tmp); 1815 1816 return otus_write_barrier(sc); 1817 } 1818 1819 int 1820 otus_program_phy(struct otus_softc *sc, struct ieee80211_channel *c) 1821 { 1822 const uint32_t *vals; 1823 int error, i; 1824 1825 /* Select PHY programming based on band and bandwidth. */ 1826 if (IEEE80211_IS_CHAN_2GHZ(c)) 1827 vals = ar5416_phy_vals_2ghz_20mhz; 1828 else 1829 vals = ar5416_phy_vals_5ghz_20mhz; 1830 for (i = 0; i < nitems(ar5416_phy_regs); i++) 1831 otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]); 1832 sc->phy_vals = vals; 1833 1834 if (sc->eeprom.baseEepHeader.deviceType == 0x80) /* FEM */ 1835 if ((error = otus_set_board_values(sc, c)) != 0) 1836 return error; 1837 1838 /* Initial Tx power settings. */ 1839 otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f); 1840 otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f); 1841 otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f); 1842 otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f); 1843 otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f); 1844 otus_write(sc, AR_PHY_POWER_TX_RATE5, 0x3f3f3f3f); 1845 otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f); 1846 otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f); 1847 otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f); 1848 otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f); 1849 1850 if (IEEE80211_IS_CHAN_2GHZ(c)) 1851 otus_write(sc, 0x1d4014, 0x5163); 1852 else 1853 otus_write(sc, 0x1d4014, 0x5143); 1854 1855 return otus_write_barrier(sc); 1856 } 1857 1858 static __inline uint8_t 1859 otus_reverse_bits(uint8_t v) 1860 { 1861 v = ((v >> 1) & 0x55) | ((v & 0x55) << 1); 1862 v = ((v >> 2) & 0x33) | ((v & 0x33) << 2); 1863 v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4); 1864 return v; 1865 } 1866 1867 int 1868 otus_set_rf_bank4(struct otus_softc *sc, struct ieee80211_channel *c) 1869 { 1870 uint8_t chansel, d0, d1; 1871 uint16_t data; 1872 int error; 1873 1874 d0 = 0; 1875 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1876 chansel = (c->ic_freq - 4800) / 5; 1877 if (chansel & 1) 1878 d0 |= AR_BANK4_AMODE_REFSEL(2); 1879 else 1880 d0 |= AR_BANK4_AMODE_REFSEL(1); 1881 } else { 1882 d0 |= AR_BANK4_AMODE_REFSEL(2); 1883 if (c->ic_freq == 2484) { /* CH 14 */ 1884 d0 |= AR_BANK4_BMODE_LF_SYNTH_FREQ; 1885 chansel = 10 + (c->ic_freq - 2274) / 5; 1886 } else 1887 chansel = 16 + (c->ic_freq - 2272) / 5; 1888 chansel <<= 2; 1889 } 1890 d0 |= AR_BANK4_ADDR(1) | AR_BANK4_CHUP; 1891 d1 = otus_reverse_bits(chansel); 1892 1893 /* Write bits 0-4 of d0 and d1. */ 1894 data = (d1 & 0x1f) << 5 | (d0 & 0x1f); 1895 otus_write(sc, AR_PHY(44), data); 1896 /* Write bits 5-7 of d0 and d1. */ 1897 data = (d1 >> 5) << 5 | (d0 >> 5); 1898 otus_write(sc, AR_PHY(58), data); 1899 1900 if ((error = otus_write_barrier(sc)) == 0) 1901 usbd_delay_ms(sc->sc_udev, 10); 1902 return error; 1903 } 1904 1905 void 1906 otus_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1907 { 1908 #define COEFF_SCALE_SHIFT 24 1909 uint32_t exp, man; 1910 1911 /* exponent = 14 - floor(log2(coeff)) */ 1912 for (exp = 31; exp > 0; exp--) 1913 if (coeff & (1 << exp)) 1914 break; 1915 KASSERT(exp != 0); 1916 exp = 14 - (exp - COEFF_SCALE_SHIFT); 1917 1918 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1919 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1920 1921 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1922 *exponent = exp - 16; 1923 #undef COEFF_SCALE_SHIFT 1924 } 1925 1926 int 1927 otus_set_chan(struct otus_softc *sc, struct ieee80211_channel *c, int assoc) 1928 { 1929 struct ieee80211com *ic = &sc->sc_ic; 1930 struct ar_cmd_frequency cmd; 1931 struct ar_rsp_frequency rsp; 1932 const uint32_t *vals; 1933 uint32_t coeff, exp, man, tmp; 1934 uint8_t code; 1935 int error, chan, i; 1936 1937 chan = ieee80211_chan2ieee(ic, c); 1938 DPRINTF(("setting channel %d (%dMHz)\n", chan, c->ic_freq)); 1939 1940 tmp = IEEE80211_IS_CHAN_2GHZ(c) ? 0x105 : 0x104; 1941 otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp); 1942 if ((error = otus_write_barrier(sc)) != 0) 1943 return error; 1944 1945 /* Disable BB Heavy Clip. */ 1946 otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200); 1947 if ((error = otus_write_barrier(sc)) != 0) 1948 return error; 1949 1950 /* XXX Is that FREQ_START ? */ 1951 error = otus_cmd(sc, AR_CMD_FREQ_STRAT, NULL, 0, NULL); 1952 if (error != 0) 1953 return error; 1954 1955 /* Reprogram PHY and RF on channel band or bandwidth changes. */ 1956 if (sc->bb_reset || c->ic_flags != sc->sc_curchan->ic_flags) { 1957 DPRINTF(("band switch\n")); 1958 1959 /* Cold/Warm reset BB/ADDA. */ 1960 otus_write(sc, 0x1d4004, sc->bb_reset ? 0x800 : 0x400); 1961 if ((error = otus_write_barrier(sc)) != 0) 1962 return error; 1963 otus_write(sc, 0x1d4004, 0); 1964 if ((error = otus_write_barrier(sc)) != 0) 1965 return error; 1966 sc->bb_reset = 0; 1967 1968 if ((error = otus_program_phy(sc, c)) != 0) { 1969 printf("%s: could not program PHY\n", 1970 sc->sc_dev.dv_xname); 1971 return error; 1972 } 1973 1974 /* Select RF programming based on band. */ 1975 if (IEEE80211_IS_CHAN_5GHZ(c)) 1976 vals = ar5416_banks_vals_5ghz; 1977 else 1978 vals = ar5416_banks_vals_2ghz; 1979 for (i = 0; i < nitems(ar5416_banks_regs); i++) 1980 otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]); 1981 if ((error = otus_write_barrier(sc)) != 0) { 1982 printf("%s: could not program RF\n", 1983 sc->sc_dev.dv_xname); 1984 return error; 1985 } 1986 code = AR_CMD_RF_INIT; 1987 } else { 1988 code = AR_CMD_FREQUENCY; 1989 } 1990 1991 if ((error = otus_set_rf_bank4(sc, c)) != 0) 1992 return error; 1993 1994 tmp = (sc->txmask == 0x5) ? 0x340 : 0x240; 1995 otus_write(sc, AR_PHY_TURBO, tmp); 1996 if ((error = otus_write_barrier(sc)) != 0) 1997 return error; 1998 1999 /* Send firmware command to set channel. */ 2000 cmd.freq = htole32((uint32_t)c->ic_freq * 1000); 2001 cmd.dynht2040 = htole32(0); 2002 cmd.htena = htole32(1); 2003 /* Set Delta Slope (exponent and mantissa). */ 2004 coeff = (100 << 24) / c->ic_freq; 2005 otus_get_delta_slope(coeff, &exp, &man); 2006 cmd.dsc_exp = htole32(exp); 2007 cmd.dsc_man = htole32(man); 2008 DPRINTF(("ds coeff=%u exp=%u man=%u\n", coeff, exp, man)); 2009 /* For Short GI, coeff is 9/10 that of normal coeff. */ 2010 coeff = (9 * coeff) / 10; 2011 otus_get_delta_slope(coeff, &exp, &man); 2012 cmd.dsc_shgi_exp = htole32(exp); 2013 cmd.dsc_shgi_man = htole32(man); 2014 DPRINTF(("ds shgi coeff=%u exp=%u man=%u\n", coeff, exp, man)); 2015 /* Set wait time for AGC and noise calibration (100 or 200ms). */ 2016 cmd.check_loop_count = assoc ? htole32(2000) : htole32(1000); 2017 DPRINTF(("%s\n", (code == AR_CMD_RF_INIT) ? "RF_INIT" : "FREQUENCY")); 2018 error = otus_cmd(sc, code, &cmd, sizeof cmd, &rsp); 2019 if (error != 0) 2020 return error; 2021 if ((rsp.status & htole32(AR_CAL_ERR_AGC | AR_CAL_ERR_NF_VAL)) != 0) { 2022 DPRINTF(("status=0x%x\n", letoh32(rsp.status))); 2023 /* Force cold reset on next channel. */ 2024 sc->bb_reset = 1; 2025 } 2026 #ifdef OTUS_DEBUG 2027 if (otus_debug) { 2028 printf("calibration status=0x%x\n", letoh32(rsp.status)); 2029 for (i = 0; i < 2; i++) { /* 2 Rx chains */ 2030 /* Sign-extend 9-bit NF values. */ 2031 printf("noisefloor chain %d=%d\n", i, 2032 (((int32_t)letoh32(rsp.nf[i])) << 4) >> 23); 2033 printf("noisefloor ext chain %d=%d\n", i, 2034 ((int32_t)letoh32(rsp.nf_ext[i])) >> 23); 2035 } 2036 } 2037 #endif 2038 sc->sc_curchan = c; 2039 return 0; 2040 } 2041 2042 #ifdef notyet 2043 int 2044 otus_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2045 struct ieee80211_key *k) 2046 { 2047 struct otus_softc *sc = ic->ic_softc; 2048 struct otus_cmd_key cmd; 2049 2050 /* Defer setting of WEP keys until interface is brought up. */ 2051 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2052 (IFF_UP | IFF_RUNNING)) 2053 return 0; 2054 2055 /* Do it in a process context. */ 2056 cmd.key = *k; 2057 cmd.ni = *ni; 2058 otus_do_async(sc, otus_set_key_cb, &cmd, sizeof cmd); 2059 sc->sc_key_tasks++ 2060 return EBUSY; 2061 } 2062 2063 void 2064 otus_set_key_cb(struct otus_softc *sc, void *arg) 2065 { 2066 struct otus_cmd_key *cmd = arg; 2067 struct ieee80211_key *k = &cmd->key; 2068 struct ar_cmd_ekey key; 2069 uint16_t cipher; 2070 int error; 2071 2072 sc->sc_keys_tasks--; 2073 2074 memset(&key, 0, sizeof key); 2075 if (k->k_flags & IEEE80211_KEY_GROUP) { 2076 key.uid = htole16(k->k_id); 2077 IEEE80211_ADDR_COPY(key.macaddr, sc->sc_ic.ic_myaddr); 2078 key.macaddr[0] |= 0x80; 2079 } else { 2080 key.uid = htole16(OTUS_UID(cmd->associd)); 2081 IEEE80211_ADDR_COPY(key.macaddr, ni->ni_macaddr); 2082 } 2083 key.kix = htole16(0); 2084 /* Map net80211 cipher to hardware. */ 2085 switch (k->k_cipher) { 2086 case IEEE80211_CIPHER_WEP40: 2087 cipher = AR_CIPHER_WEP64; 2088 break; 2089 case IEEE80211_CIPHER_WEP104: 2090 cipher = AR_CIPHER_WEP128; 2091 break; 2092 case IEEE80211_CIPHER_TKIP: 2093 cipher = AR_CIPHER_TKIP; 2094 break; 2095 case IEEE80211_CIPHER_CCMP: 2096 cipher = AR_CIPHER_AES; 2097 break; 2098 default: 2099 IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH, 2100 IEEE80211_REASON_AUTH_LEAVE); 2101 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2102 return; 2103 } 2104 key.cipher = htole16(cipher); 2105 memcpy(key.key, k->k_key, MIN(k->k_len, 16)); 2106 error = otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL); 2107 if (error != 0 || k->k_cipher != IEEE80211_CIPHER_TKIP) { 2108 IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH, 2109 IEEE80211_REASON_AUTH_LEAVE); 2110 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2111 return; 2112 } 2113 2114 /* TKIP: set Tx/Rx MIC Key. */ 2115 key.kix = htole16(1); 2116 memcpy(key.key, k->k_key + 16, 16); 2117 (void)otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL); 2118 2119 if (sc->sc_key_tasks == 0) { 2120 DPRINTF(("marking port %s valid\n", 2121 ether_sprintf(cmd->ni->ni_macaddr))); 2122 cmd->ni->ni_port_valid = 1; 2123 ieee80211_set_link_state(ic, LINK_STATE_UP); 2124 } 2125 } 2126 2127 void 2128 otus_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2129 struct ieee80211_key *k) 2130 { 2131 struct otus_softc *sc = ic->ic_softc; 2132 struct otus_cmd_key cmd; 2133 2134 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 2135 ic->ic_state != IEEE80211_S_RUN) 2136 return; /* Nothing to do. */ 2137 2138 /* Do it in a process context. */ 2139 cmd.key = *k; 2140 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2141 otus_do_async(sc, otus_delete_key_cb, &cmd, sizeof cmd); 2142 } 2143 2144 void 2145 otus_delete_key_cb(struct otus_softc *sc, void *arg) 2146 { 2147 struct otus_cmd_key *cmd = arg; 2148 struct ieee80211_key *k = &cmd->key; 2149 uint32_t uid; 2150 2151 if (k->k_flags & IEEE80211_KEY_GROUP) 2152 uid = htole32(k->k_id); 2153 else 2154 uid = htole32(OTUS_UID(cmd->associd)); 2155 (void)otus_cmd(sc, AR_CMD_DKEY, &uid, sizeof uid, NULL); 2156 } 2157 #endif 2158 2159 void 2160 otus_calibrate_to(void *arg) 2161 { 2162 struct otus_softc *sc = arg; 2163 struct ieee80211com *ic = &sc->sc_ic; 2164 struct ieee80211_node *ni; 2165 int s; 2166 2167 if (usbd_is_dying(sc->sc_udev)) 2168 return; 2169 2170 usbd_ref_incr(sc->sc_udev); 2171 2172 s = splnet(); 2173 ni = ic->ic_bss; 2174 ieee80211_amrr_choose(&sc->amrr, ni, &((struct otus_node *)ni)->amn); 2175 splx(s); 2176 2177 if (!usbd_is_dying(sc->sc_udev)) 2178 timeout_add_sec(&sc->calib_to, 1); 2179 2180 usbd_ref_decr(sc->sc_udev); 2181 } 2182 2183 int 2184 otus_set_bssid(struct otus_softc *sc, const uint8_t *bssid) 2185 { 2186 otus_write(sc, AR_MAC_REG_BSSID_L, 2187 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2188 otus_write(sc, AR_MAC_REG_BSSID_H, 2189 bssid[4] | bssid[5] << 8); 2190 return otus_write_barrier(sc); 2191 } 2192 2193 int 2194 otus_set_macaddr(struct otus_softc *sc, const uint8_t *addr) 2195 { 2196 otus_write(sc, AR_MAC_REG_MAC_ADDR_L, 2197 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2198 otus_write(sc, AR_MAC_REG_MAC_ADDR_H, 2199 addr[4] | addr[5] << 8); 2200 return otus_write_barrier(sc); 2201 } 2202 2203 /* Default single-LED. */ 2204 void 2205 otus_led_newstate_type1(struct otus_softc *sc) 2206 { 2207 /* TBD */ 2208 } 2209 2210 /* NETGEAR, dual-LED. */ 2211 void 2212 otus_led_newstate_type2(struct otus_softc *sc) 2213 { 2214 /* TBD */ 2215 } 2216 2217 /* NETGEAR, single-LED/3 colors (blue, red, purple.) */ 2218 void 2219 otus_led_newstate_type3(struct otus_softc *sc) 2220 { 2221 struct ieee80211com *ic = &sc->sc_ic; 2222 uint32_t state = sc->led_state; 2223 2224 if (ic->ic_state == IEEE80211_S_INIT) { 2225 state = 0; /* LED off. */ 2226 } else if (ic->ic_state == IEEE80211_S_RUN) { 2227 /* Associated, LED always on. */ 2228 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 2229 state = AR_LED0_ON; /* 2GHz=>Red. */ 2230 else 2231 state = AR_LED1_ON; /* 5GHz=>Blue. */ 2232 } else { 2233 /* Scanning, blink LED. */ 2234 state ^= AR_LED0_ON | AR_LED1_ON; 2235 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 2236 state &= ~AR_LED1_ON; 2237 else 2238 state &= ~AR_LED0_ON; 2239 } 2240 if (state != sc->led_state) { 2241 otus_write(sc, 0x1d0104, state); 2242 if (otus_write_barrier(sc) == 0) 2243 sc->led_state = state; 2244 } 2245 } 2246 2247 int 2248 otus_init(struct ifnet *ifp) 2249 { 2250 struct otus_softc *sc = ifp->if_softc; 2251 struct ieee80211com *ic = &sc->sc_ic; 2252 int error; 2253 2254 /* Init host command ring. */ 2255 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2256 2257 if ((error = otus_init_mac(sc)) != 0) { 2258 printf("%s: could not initialize MAC\n", sc->sc_dev.dv_xname); 2259 return error; 2260 } 2261 2262 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2263 (void)otus_set_macaddr(sc, ic->ic_myaddr); 2264 2265 switch (ic->ic_opmode) { 2266 #ifdef notyet 2267 #ifndef IEEE80211_STA_ONLY 2268 case IEEE80211_M_HOSTAP: 2269 otus_write(sc, 0x1c3700, 0x0f0000a1); 2270 otus_write(sc, 0x1c3c40, 0x1); 2271 break; 2272 case IEEE80211_M_IBSS: 2273 otus_write(sc, 0x1c3700, 0x0f000000); 2274 otus_write(sc, 0x1c3c40, 0x1); 2275 break; 2276 #endif 2277 #endif 2278 case IEEE80211_M_STA: 2279 otus_write(sc, 0x1c3700, 0x0f000002); 2280 otus_write(sc, 0x1c3c40, 0x1); 2281 break; 2282 default: 2283 break; 2284 } 2285 otus_write(sc, AR_MAC_REG_SNIFFER, 2286 (ic->ic_opmode == IEEE80211_M_MONITOR) ? 0x2000001 : 0x2000000); 2287 (void)otus_write_barrier(sc); 2288 2289 sc->bb_reset = 1; /* Force cold reset. */ 2290 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2291 if ((error = otus_set_chan(sc, ic->ic_ibss_chan, 0)) != 0) { 2292 printf("%s: could not set channel\n", sc->sc_dev.dv_xname); 2293 return error; 2294 } 2295 2296 /* Start Rx. */ 2297 otus_write(sc, AR_MAC_REG_DMA_TRIGGER, AR_DMA_TRIGGER_RXQ); 2298 (void)otus_write_barrier(sc); 2299 2300 ifp->if_flags |= IFF_RUNNING; 2301 ifq_clr_oactive(&ifp->if_snd); 2302 2303 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2304 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2305 else 2306 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2307 2308 return 0; 2309 } 2310 2311 void 2312 otus_stop(struct ifnet *ifp) 2313 { 2314 struct otus_softc *sc = ifp->if_softc; 2315 struct ieee80211com *ic = &sc->sc_ic; 2316 int s; 2317 2318 sc->sc_tx_timer = 0; 2319 ifp->if_timer = 0; 2320 ifp->if_flags &= ~IFF_RUNNING; 2321 ifq_clr_oactive(&ifp->if_snd); 2322 2323 timeout_del(&sc->scan_to); 2324 timeout_del(&sc->calib_to); 2325 2326 s = splusb(); 2327 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2328 /* Wait for all queued asynchronous commands to complete. */ 2329 usb_wait_task(sc->sc_udev, &sc->sc_task); 2330 splx(s); 2331 2332 /* Stop Rx. */ 2333 otus_write(sc, AR_MAC_REG_DMA_TRIGGER, 0); 2334 (void)otus_write_barrier(sc); 2335 2336 sc->tx_queued = 0; 2337 } 2338