1 /* $OpenBSD: if_ralreg.h,v 1.12 2006/11/13 20:06:38 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define RAL_RX_DESC_SIZE (sizeof (struct ural_rx_desc)) 21 #define RAL_TX_DESC_SIZE (sizeof (struct ural_tx_desc)) 22 23 #define RAL_CONFIG_NO 1 24 #define RAL_IFACE_INDEX 0 25 26 #define RAL_WRITE_MAC 0x02 27 #define RAL_READ_MAC 0x03 28 #define RAL_WRITE_MULTI_MAC 0x06 29 #define RAL_READ_MULTI_MAC 0x07 30 #define RAL_READ_EEPROM 0x09 31 32 /* 33 * MAC registers. 34 */ 35 #define RAL_MAC_CSR0 0x0400 /* ASIC Version */ 36 #define RAL_MAC_CSR1 0x0402 /* System control */ 37 #define RAL_MAC_CSR2 0x0404 /* MAC addr0 */ 38 #define RAL_MAC_CSR3 0x0406 /* MAC addr1 */ 39 #define RAL_MAC_CSR4 0x0408 /* MAC addr2 */ 40 #define RAL_MAC_CSR5 0x040a /* BSSID0 */ 41 #define RAL_MAC_CSR6 0x040c /* BSSID1 */ 42 #define RAL_MAC_CSR7 0x040e /* BSSID2 */ 43 #define RAL_MAC_CSR8 0x0410 /* Max frame length */ 44 #define RAL_MAC_CSR9 0x0412 /* Timer control */ 45 #define RAL_MAC_CSR10 0x0414 /* Slot time */ 46 #define RAL_MAC_CSR11 0x0416 /* IFS */ 47 #define RAL_MAC_CSR12 0x0418 /* EIFS */ 48 #define RAL_MAC_CSR13 0x041a /* Power mode0 */ 49 #define RAL_MAC_CSR14 0x041c /* Power mode1 */ 50 #define RAL_MAC_CSR15 0x041e /* Power saving transition0 */ 51 #define RAL_MAC_CSR16 0x0420 /* Power saving transition1 */ 52 #define RAL_MAC_CSR17 0x0422 /* Power state control */ 53 #define RAL_MAC_CSR18 0x0424 /* Auto wake-up control */ 54 #define RAL_MAC_CSR19 0x0426 /* GPIO control */ 55 #define RAL_MAC_CSR20 0x0428 /* LED control0 */ 56 #define RAL_MAC_CSR22 0x042c /* XXX not documented */ 57 58 /* 59 * Tx/Rx Registers. 60 */ 61 #define RAL_TXRX_CSR0 0x0440 /* Security control */ 62 #define RAL_TXRX_CSR2 0x0444 /* Rx control */ 63 #define RAL_TXRX_CSR5 0x044a /* CCK Tx BBP ID0 */ 64 #define RAL_TXRX_CSR6 0x044c /* CCK Tx BBP ID1 */ 65 #define RAL_TXRX_CSR7 0x044e /* OFDM Tx BBP ID0 */ 66 #define RAL_TXRX_CSR8 0x0450 /* OFDM Tx BBP ID1 */ 67 #define RAL_TXRX_CSR10 0x0454 /* Auto responder control */ 68 #define RAL_TXRX_CSR11 0x0456 /* Auto responder basic rate */ 69 #define RAL_TXRX_CSR18 0x0464 /* Beacon interval */ 70 #define RAL_TXRX_CSR19 0x0466 /* Beacon/sync control */ 71 #define RAL_TXRX_CSR20 0x0468 /* Beacon alignment */ 72 #define RAL_TXRX_CSR21 0x046a /* XXX not documented */ 73 74 /* 75 * Security registers. 76 */ 77 #define RAL_SEC_CSR0 0x0480 /* Shared key 0, word 0 */ 78 79 /* 80 * PHY registers. 81 */ 82 #define RAL_PHY_CSR2 0x04c4 /* Tx MAC configuration */ 83 #define RAL_PHY_CSR4 0x04c8 /* Interface configuration */ 84 #define RAL_PHY_CSR5 0x04ca /* BBP Pre-Tx CCK */ 85 #define RAL_PHY_CSR6 0x04cc /* BBP Pre-Tx OFDM */ 86 #define RAL_PHY_CSR7 0x04ce /* BBP serial control */ 87 #define RAL_PHY_CSR8 0x04d0 /* BBP serial status */ 88 #define RAL_PHY_CSR9 0x04d2 /* RF serial control0 */ 89 #define RAL_PHY_CSR10 0x04d4 /* RF serial control1 */ 90 91 /* 92 * Statistics registers. 93 */ 94 #define RAL_STA_CSR0 0x04e0 /* FCS error */ 95 96 97 #define RAL_DISABLE_RX (1 << 0) 98 #define RAL_DROP_CRC_ERROR (1 << 1) 99 #define RAL_DROP_PHY_ERROR (1 << 2) 100 #define RAL_DROP_CTL (1 << 3) 101 #define RAL_DROP_NOT_TO_ME (1 << 4) 102 #define RAL_DROP_TODS (1 << 5) 103 #define RAL_DROP_VERSION_ERROR (1 << 6) 104 #define RAL_DROP_MULTICAST (1 << 9) 105 #define RAL_DROP_BROADCAST (1 << 10) 106 107 #define RAL_SHORT_PREAMBLE (1 << 2) 108 109 #define RAL_RESET_ASIC (1 << 0) 110 #define RAL_RESET_BBP (1 << 1) 111 #define RAL_HOST_READY (1 << 2) 112 113 #define RAL_ENABLE_TSF (1 << 0) 114 #define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) 115 #define RAL_ENABLE_TBCN (1 << 3) 116 #define RAL_ENABLE_BEACON_GENERATOR (1 << 4) 117 118 #define RAL_RF_AWAKE (3 << 7) 119 #define RAL_BBP_AWAKE (3 << 5) 120 121 #define RAL_BBP_WRITE (1 << 15) 122 #define RAL_BBP_BUSY (1 << 0) 123 124 #define RAL_RF1_AUTOTUNE 0x08000 125 #define RAL_RF3_AUTOTUNE 0x00040 126 127 #define RAL_RF_2522 0x00 128 #define RAL_RF_2523 0x01 129 #define RAL_RF_2524 0x02 130 #define RAL_RF_2525 0x03 131 #define RAL_RF_2525E 0x04 132 #define RAL_RF_2526 0x05 133 /* dual-band RF */ 134 #define RAL_RF_5222 0x10 135 136 #define RAL_BBP_VERSION 0 137 #define RAL_BBP_TX 2 138 #define RAL_BBP_RX 14 139 140 #define RAL_BBP_ANTA 0x00 141 #define RAL_BBP_DIVERSITY 0x01 142 #define RAL_BBP_ANTB 0x02 143 #define RAL_BBP_ANTMASK 0x03 144 #define RAL_BBP_FLIPIQ 0x04 145 146 #define RAL_JAPAN_FILTER 0x08 147 148 struct ural_tx_desc { 149 uint32_t flags; 150 #define RAL_TX_RETRY(x) ((x) << 4) 151 #define RAL_TX_MORE_FRAG (1 << 8) 152 #define RAL_TX_NEED_ACK (1 << 9) 153 #define RAL_TX_TIMESTAMP (1 << 10) 154 #define RAL_TX_OFDM (1 << 11) 155 #define RAL_TX_NEWSEQ (1 << 12) 156 157 #define RAL_TX_IFS_MASK 0x00006000 158 #define RAL_TX_IFS_BACKOFF (0 << 13) 159 #define RAL_TX_IFS_SIFS (1 << 13) 160 #define RAL_TX_IFS_NEWBACKOFF (2 << 13) 161 #define RAL_TX_IFS_NONE (3 << 13) 162 163 uint16_t wme; 164 #define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) 165 #define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) 166 #define RAL_AIFSN(x) (((x) & 0x3) << 6) 167 #define RAL_IVOFFSET(x) (((x) & 0x3f)) 168 169 uint16_t reserved; 170 uint8_t plcp_signal; 171 uint8_t plcp_service; 172 #define RAL_PLCP_LENGEXT 0x80 173 174 uint8_t plcp_length_lo; 175 uint8_t plcp_length_hi; 176 uint32_t iv; 177 uint32_t eiv; 178 } __packed; 179 180 struct ural_rx_desc { 181 uint32_t flags; 182 #define RAL_RX_CRC_ERROR (1 << 5) 183 #define RAL_RX_OFDM (1 << 6) 184 #define RAL_RX_PHY_ERROR (1 << 7) 185 186 uint8_t rate; 187 uint8_t rssi; 188 uint16_t reserved; 189 190 uint32_t iv; 191 uint32_t eiv; 192 } __packed; 193 194 #define RAL_RF_LOBUSY (1 << 15) 195 #define RAL_RF_BUSY (1 << 31) 196 #define RAL_RF_20BIT (20 << 24) 197 198 #define RAL_RF1 0 199 #define RAL_RF2 2 200 #define RAL_RF3 1 201 #define RAL_RF4 3 202 203 #define RAL_EEPROM_MACBBP 0x0000 204 #define RAL_EEPROM_ADDRESS 0x0004 205 #define RAL_EEPROM_TXPOWER 0x003c 206 #define RAL_EEPROM_CONFIG0 0x0016 207 #define RAL_EEPROM_BBP_BASE 0x001c 208 209 /* 210 * Default values for MAC registers; values taken from the reference driver. 211 */ 212 #define RAL_DEF_MAC \ 213 { RAL_TXRX_CSR5, 0x8c8d }, \ 214 { RAL_TXRX_CSR6, 0x8b8a }, \ 215 { RAL_TXRX_CSR7, 0x8687 }, \ 216 { RAL_TXRX_CSR8, 0x0085 }, \ 217 { RAL_MAC_CSR13, 0x1111 }, \ 218 { RAL_MAC_CSR14, 0x1e11 }, \ 219 { RAL_TXRX_CSR21, 0xe78f }, \ 220 { RAL_MAC_CSR9, 0xff1d }, \ 221 { RAL_MAC_CSR11, 0x0002 }, \ 222 { RAL_MAC_CSR22, 0x0053 }, \ 223 { RAL_MAC_CSR15, 0x0000 }, \ 224 { RAL_MAC_CSR8, 0x0780 }, \ 225 { RAL_TXRX_CSR19, 0x0000 }, \ 226 { RAL_TXRX_CSR18, 0x005a }, \ 227 { RAL_PHY_CSR2, 0x0000 }, \ 228 { RAL_TXRX_CSR0, 0x1ec0 }, \ 229 { RAL_PHY_CSR4, 0x000f } 230 231 /* 232 * Default values for BBP registers; values taken from the reference driver. 233 */ 234 #define RAL_DEF_BBP \ 235 { 3, 0x02 }, \ 236 { 4, 0x19 }, \ 237 { 14, 0x1c }, \ 238 { 15, 0x30 }, \ 239 { 16, 0xac }, \ 240 { 17, 0x48 }, \ 241 { 18, 0x18 }, \ 242 { 19, 0xff }, \ 243 { 20, 0x1e }, \ 244 { 21, 0x08 }, \ 245 { 22, 0x08 }, \ 246 { 23, 0x08 }, \ 247 { 24, 0x80 }, \ 248 { 25, 0x50 }, \ 249 { 26, 0x08 }, \ 250 { 27, 0x23 }, \ 251 { 30, 0x10 }, \ 252 { 31, 0x2b }, \ 253 { 32, 0xb9 }, \ 254 { 34, 0x12 }, \ 255 { 35, 0x50 }, \ 256 { 39, 0xc4 }, \ 257 { 40, 0x02 }, \ 258 { 41, 0x60 }, \ 259 { 53, 0x10 }, \ 260 { 54, 0x18 }, \ 261 { 56, 0x08 }, \ 262 { 57, 0x10 }, \ 263 { 58, 0x08 }, \ 264 { 61, 0x60 }, \ 265 { 62, 0x10 }, \ 266 { 75, 0xff } 267 268 /* 269 * Default values for RF register R2 indexed by channel numbers. 270 */ 271 #define RAL_RF2522_R2 \ 272 { \ 273 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, \ 274 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e \ 275 } 276 277 #define RAL_RF2523_R2 \ 278 { \ 279 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \ 280 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \ 281 } 282 283 #define RAL_RF2524_R2 \ 284 { \ 285 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \ 286 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \ 287 } 288 289 #define RAL_RF2525_R2 \ 290 { \ 291 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, \ 292 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 \ 293 } 294 295 #define RAL_RF2525_HI_R2 \ 296 { \ 297 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, \ 298 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e \ 299 } 300 301 #define RAL_RF2525E_R2 \ 302 { \ 303 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, \ 304 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b \ 305 } 306 307 #define RAL_RF2526_HI_R2 \ 308 { \ 309 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, \ 310 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 \ 311 } 312 313 #define RAL_RF2526_R2 \ 314 { \ 315 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, \ 316 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d \ 317 } 318