1 /* $OpenBSD: if_rsu.c,v 1.22 2014/07/13 15:52:49 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for Realtek RTL8188SU/RTL8191SU/RTL8192SU. 21 */ 22 23 #include "bpfilter.h" 24 25 #include <sys/param.h> 26 #include <sys/sockio.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/timeout.h> 32 #include <sys/conf.h> 33 #include <sys/device.h> 34 35 #include <machine/bus.h> 36 #include <machine/endian.h> 37 #include <machine/intr.h> 38 39 #if NBPFILTER > 0 40 #include <net/bpf.h> 41 #endif 42 #include <net/if.h> 43 #include <net/if_arp.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 #include <net/if_types.h> 47 48 #include <netinet/in.h> 49 #include <netinet/if_ether.h> 50 51 #include <net80211/ieee80211_var.h> 52 #include <net80211/ieee80211_radiotap.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include <dev/usb/usbdevs.h> 58 59 #include <dev/usb/if_rsureg.h> 60 61 #ifdef RSU_DEBUG 62 #define DPRINTF(x) do { if (rsu_debug) printf x; } while (0) 63 #define DPRINTFN(n, x) do { if (rsu_debug >= (n)) printf x; } while (0) 64 int rsu_debug = 4; 65 #else 66 #define DPRINTF(x) 67 #define DPRINTFN(n, x) 68 #endif 69 70 /* 71 * NB: When updating this list of devices, beware to also update the list 72 * of devices that have HT support disabled below, if applicable. 73 */ 74 static const struct usb_devno rsu_devs[] = { 75 { USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_RTL8192SU }, 76 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_USBN10 }, 77 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192SU_1 }, 78 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_1 }, 79 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_2 }, 80 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_3 }, 81 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_4 }, 82 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_5 }, 83 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_1 }, 84 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_2 }, 85 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_3 }, 86 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_1 }, 87 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_2 }, 88 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_3 }, 89 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192SU }, 90 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA131A1 }, 91 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_RTL8192SU_1 }, 92 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_RTL8192SU_2 }, 93 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_1 }, 94 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_2 }, 95 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_3 }, 96 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWGUN54 }, 97 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUM300 }, 98 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192SU_1 }, 99 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192SU_2 }, 100 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GWUSNANO }, 101 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8171 }, 102 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8172 }, 103 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8173 }, 104 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8174 }, 105 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192SU }, 106 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8712 }, 107 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8713 }, 108 { USB_VENDOR_SENAO, USB_PRODUCT_SENAO_RTL8192SU_1 }, 109 { USB_VENDOR_SENAO, USB_PRODUCT_SENAO_RTL8192SU_2 }, 110 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_WL349V1 }, 111 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_WL353 }, 112 { USB_VENDOR_SWEEX2, USB_PRODUCT_SWEEX2_LW154 } 113 }; 114 115 #ifndef IEEE80211_NO_HT 116 /* List of devices that have HT support disabled. */ 117 static const struct usb_devno rsu_devs_noht[] = { 118 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192SU_1 }, 119 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_4 } 120 }; 121 #endif 122 123 int rsu_match(struct device *, void *, void *); 124 void rsu_attach(struct device *, struct device *, void *); 125 int rsu_detach(struct device *, int); 126 int rsu_open_pipes(struct rsu_softc *); 127 void rsu_close_pipes(struct rsu_softc *); 128 int rsu_alloc_rx_list(struct rsu_softc *); 129 void rsu_free_rx_list(struct rsu_softc *); 130 int rsu_alloc_tx_list(struct rsu_softc *); 131 void rsu_free_tx_list(struct rsu_softc *); 132 void rsu_task(void *); 133 void rsu_do_async(struct rsu_softc *, 134 void (*)(struct rsu_softc *, void *), void *, int); 135 void rsu_wait_async(struct rsu_softc *); 136 int rsu_write_region_1(struct rsu_softc *, uint16_t, uint8_t *, 137 int); 138 void rsu_write_1(struct rsu_softc *, uint16_t, uint8_t); 139 void rsu_write_2(struct rsu_softc *, uint16_t, uint16_t); 140 void rsu_write_4(struct rsu_softc *, uint16_t, uint32_t); 141 int rsu_read_region_1(struct rsu_softc *, uint16_t, uint8_t *, 142 int); 143 uint8_t rsu_read_1(struct rsu_softc *, uint16_t); 144 uint16_t rsu_read_2(struct rsu_softc *, uint16_t); 145 uint32_t rsu_read_4(struct rsu_softc *, uint16_t); 146 int rsu_fw_iocmd(struct rsu_softc *, uint32_t); 147 uint8_t rsu_efuse_read_1(struct rsu_softc *, uint16_t); 148 int rsu_read_rom(struct rsu_softc *); 149 int rsu_fw_cmd(struct rsu_softc *, uint8_t, void *, int); 150 int rsu_media_change(struct ifnet *); 151 void rsu_calib_to(void *); 152 void rsu_calib_cb(struct rsu_softc *, void *); 153 int rsu_newstate(struct ieee80211com *, enum ieee80211_state, int); 154 void rsu_newstate_cb(struct rsu_softc *, void *); 155 int rsu_set_key(struct ieee80211com *, struct ieee80211_node *, 156 struct ieee80211_key *); 157 void rsu_set_key_cb(struct rsu_softc *, void *); 158 void rsu_delete_key(struct ieee80211com *, struct ieee80211_node *, 159 struct ieee80211_key *); 160 void rsu_delete_key_cb(struct rsu_softc *, void *); 161 int rsu_site_survey(struct rsu_softc *); 162 int rsu_join_bss(struct rsu_softc *, struct ieee80211_node *); 163 int rsu_disconnect(struct rsu_softc *); 164 void rsu_event_survey(struct rsu_softc *, uint8_t *, int); 165 void rsu_event_join_bss(struct rsu_softc *, uint8_t *, int); 166 void rsu_rx_event(struct rsu_softc *, uint8_t, uint8_t *, int); 167 void rsu_rx_multi_event(struct rsu_softc *, uint8_t *, int); 168 int8_t rsu_get_rssi(struct rsu_softc *, int, void *); 169 void rsu_rx_frame(struct rsu_softc *, uint8_t *, int); 170 void rsu_rx_multi_frame(struct rsu_softc *, uint8_t *, int); 171 void rsu_rxeof(struct usbd_xfer *, void *, usbd_status); 172 void rsu_txeof(struct usbd_xfer *, void *, usbd_status); 173 int rsu_tx(struct rsu_softc *, struct mbuf *, 174 struct ieee80211_node *); 175 int rsu_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 176 int, int, int); 177 void rsu_start(struct ifnet *); 178 void rsu_watchdog(struct ifnet *); 179 int rsu_ioctl(struct ifnet *, u_long, caddr_t); 180 void rsu_power_on_acut(struct rsu_softc *); 181 void rsu_power_on_bcut(struct rsu_softc *); 182 void rsu_power_off(struct rsu_softc *); 183 int rsu_fw_loadsection(struct rsu_softc *, uint8_t *, int); 184 int rsu_load_firmware(struct rsu_softc *); 185 int rsu_init(struct ifnet *); 186 void rsu_stop(struct ifnet *); 187 188 struct cfdriver rsu_cd = { 189 NULL, "rsu", DV_IFNET 190 }; 191 192 const struct cfattach rsu_ca = { 193 sizeof(struct rsu_softc), rsu_match, rsu_attach, rsu_detach, 194 }; 195 196 int 197 rsu_match(struct device *parent, void *match, void *aux) 198 { 199 struct usb_attach_arg *uaa = aux; 200 201 if (uaa->iface != NULL) 202 return (UMATCH_NONE); 203 204 return ((usb_lookup(rsu_devs, uaa->vendor, uaa->product) != NULL) ? 205 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 206 } 207 208 void 209 rsu_attach(struct device *parent, struct device *self, void *aux) 210 { 211 struct rsu_softc *sc = (struct rsu_softc *)self; 212 struct usb_attach_arg *uaa = aux; 213 struct ieee80211com *ic = &sc->sc_ic; 214 struct ifnet *ifp = &ic->ic_if; 215 int i, error; 216 217 sc->sc_udev = uaa->device; 218 219 usb_init_task(&sc->sc_task, rsu_task, sc, USB_TASK_TYPE_GENERIC); 220 timeout_set(&sc->calib_to, rsu_calib_to, sc); 221 222 if (usbd_set_config_no(sc->sc_udev, 1, 0) != 0) { 223 printf("%s: could not set configuration no\n", 224 sc->sc_dev.dv_xname); 225 return; 226 } 227 228 /* Get the first interface handle. */ 229 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 230 if (error != 0) { 231 printf("%s: could not get interface handle\n", 232 sc->sc_dev.dv_xname); 233 return; 234 } 235 236 /* Read chip revision. */ 237 sc->cut = MS(rsu_read_4(sc, R92S_PMC_FSM), R92S_PMC_FSM_CUT); 238 if (sc->cut != 3) 239 sc->cut = (sc->cut >> 1) + 1; 240 241 error = rsu_read_rom(sc); 242 if (error != 0) { 243 printf("%s: could not read ROM\n", sc->sc_dev.dv_xname); 244 return; 245 } 246 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->rom[0x12]); 247 248 printf("%s: MAC/BB RTL8712 cut %d, address %s\n", 249 sc->sc_dev.dv_xname, sc->cut, ether_sprintf(ic->ic_myaddr)); 250 251 if (rsu_open_pipes(sc) != 0) 252 return; 253 254 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 255 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 256 ic->ic_state = IEEE80211_S_INIT; 257 258 /* Set device capabilities. */ 259 ic->ic_caps = 260 IEEE80211_C_SCANALL | /* Hardware scan. */ 261 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 262 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 263 IEEE80211_C_WEP | /* WEP. */ 264 IEEE80211_C_RSN; /* WPA/RSN. */ 265 #ifndef IEEE80211_NO_HT 266 /* Check if HT support is present. */ 267 if (usb_lookup(rsu_devs_noht, uaa->vendor, uaa->product) == NULL) { 268 /* Set HT capabilities. */ 269 ic->ic_htcaps = 270 IEEE80211_HTCAP_CBW20_40 | 271 IEEE80211_HTCAP_DSSSCCK40; 272 /* Set supported HT rates. */ 273 for (i = 0; i < 2; i++) 274 ic->ic_sup_mcs[i] = 0xff; 275 } 276 #endif 277 278 /* Set supported .11b and .11g rates. */ 279 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 280 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 281 282 /* Set supported .11b and .11g channels (1 through 14). */ 283 for (i = 1; i <= 14; i++) { 284 ic->ic_channels[i].ic_freq = 285 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 286 ic->ic_channels[i].ic_flags = 287 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 288 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 289 } 290 291 ifp->if_softc = sc; 292 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 293 ifp->if_ioctl = rsu_ioctl; 294 ifp->if_start = rsu_start; 295 ifp->if_watchdog = rsu_watchdog; 296 IFQ_SET_READY(&ifp->if_snd); 297 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 298 299 if_attach(ifp); 300 ieee80211_ifattach(ifp); 301 #ifdef notyet 302 ic->ic_set_key = rsu_set_key; 303 ic->ic_delete_key = rsu_delete_key; 304 #endif 305 /* Override state transition machine. */ 306 sc->sc_newstate = ic->ic_newstate; 307 ic->ic_newstate = rsu_newstate; 308 ic->ic_send_mgmt = rsu_send_mgmt; 309 ieee80211_media_init(ifp, rsu_media_change, ieee80211_media_status); 310 311 #if NBPFILTER > 0 312 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 313 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 314 315 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 316 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 317 sc->sc_rxtap.wr_ihdr.it_present = htole32(RSU_RX_RADIOTAP_PRESENT); 318 319 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 320 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 321 sc->sc_txtap.wt_ihdr.it_present = htole32(RSU_TX_RADIOTAP_PRESENT); 322 #endif 323 } 324 325 int 326 rsu_detach(struct device *self, int flags) 327 { 328 struct rsu_softc *sc = (struct rsu_softc *)self; 329 struct ifnet *ifp = &sc->sc_ic.ic_if; 330 int s; 331 332 s = splusb(); 333 334 if (timeout_initialized(&sc->calib_to)) 335 timeout_del(&sc->calib_to); 336 337 /* Wait for all async commands to complete. */ 338 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 339 340 usbd_ref_wait(sc->sc_udev); 341 342 if (ifp->if_softc != NULL) { 343 ieee80211_ifdetach(ifp); 344 if_detach(ifp); 345 } 346 347 /* Abort and close Tx/Rx pipes. */ 348 rsu_close_pipes(sc); 349 350 /* Free Tx/Rx buffers. */ 351 rsu_free_tx_list(sc); 352 rsu_free_rx_list(sc); 353 splx(s); 354 355 return (0); 356 } 357 358 int 359 rsu_open_pipes(struct rsu_softc *sc) 360 { 361 usb_interface_descriptor_t *id; 362 int i, error; 363 364 /* 365 * Determine the number of Tx/Rx endpoints (there are chips with 366 * 4, 6 or 11 endpoints). 367 */ 368 id = usbd_get_interface_descriptor(sc->sc_iface); 369 sc->npipes = id->bNumEndpoints; 370 if (sc->npipes == 4) 371 sc->qid2idx = rsu_qid2idx_4ep; 372 else if (sc->npipes == 6) 373 sc->qid2idx = rsu_qid2idx_6ep; 374 else /* Assume npipes==11; will fail below otherwise. */ 375 sc->qid2idx = rsu_qid2idx_11ep; 376 DPRINTF(("%d endpoints configuration\n", sc->npipes)); 377 378 /* Open all pipes. */ 379 for (i = 0; i < MIN(sc->npipes, nitems(r92s_epaddr)); i++) { 380 error = usbd_open_pipe(sc->sc_iface, r92s_epaddr[i], 0, 381 &sc->pipe[i]); 382 if (error != 0) { 383 printf("%s: could not open bulk pipe 0x%02x\n", 384 sc->sc_dev.dv_xname, r92s_epaddr[i]); 385 break; 386 } 387 } 388 if (error != 0) 389 rsu_close_pipes(sc); 390 return (error); 391 } 392 393 void 394 rsu_close_pipes(struct rsu_softc *sc) 395 { 396 int i; 397 398 /* Close all pipes. */ 399 for (i = 0; i < sc->npipes; i++) { 400 if (sc->pipe[i] == NULL) 401 continue; 402 usbd_abort_pipe(sc->pipe[i]); 403 usbd_close_pipe(sc->pipe[i]); 404 } 405 } 406 407 int 408 rsu_alloc_rx_list(struct rsu_softc *sc) 409 { 410 struct rsu_rx_data *data; 411 int i, error = 0; 412 413 for (i = 0; i < RSU_RX_LIST_COUNT; i++) { 414 data = &sc->rx_data[i]; 415 416 data->sc = sc; /* Backpointer for callbacks. */ 417 418 data->xfer = usbd_alloc_xfer(sc->sc_udev); 419 if (data->xfer == NULL) { 420 printf("%s: could not allocate xfer\n", 421 sc->sc_dev.dv_xname); 422 error = ENOMEM; 423 break; 424 } 425 data->buf = usbd_alloc_buffer(data->xfer, RSU_RXBUFSZ); 426 if (data->buf == NULL) { 427 printf("%s: could not allocate xfer buffer\n", 428 sc->sc_dev.dv_xname); 429 error = ENOMEM; 430 break; 431 } 432 } 433 if (error != 0) 434 rsu_free_rx_list(sc); 435 return (error); 436 } 437 438 void 439 rsu_free_rx_list(struct rsu_softc *sc) 440 { 441 int i; 442 443 /* NB: Caller must abort pipe first. */ 444 for (i = 0; i < RSU_RX_LIST_COUNT; i++) { 445 if (sc->rx_data[i].xfer != NULL) 446 usbd_free_xfer(sc->rx_data[i].xfer); 447 sc->rx_data[i].xfer = NULL; 448 } 449 } 450 451 int 452 rsu_alloc_tx_list(struct rsu_softc *sc) 453 { 454 struct rsu_tx_data *data; 455 int i, error = 0; 456 457 TAILQ_INIT(&sc->tx_free_list); 458 for (i = 0; i < RSU_TX_LIST_COUNT; i++) { 459 data = &sc->tx_data[i]; 460 461 data->sc = sc; /* Backpointer for callbacks. */ 462 463 data->xfer = usbd_alloc_xfer(sc->sc_udev); 464 if (data->xfer == NULL) { 465 printf("%s: could not allocate xfer\n", 466 sc->sc_dev.dv_xname); 467 error = ENOMEM; 468 break; 469 } 470 data->buf = usbd_alloc_buffer(data->xfer, RSU_TXBUFSZ); 471 if (data->buf == NULL) { 472 printf("%s: could not allocate xfer buffer\n", 473 sc->sc_dev.dv_xname); 474 error = ENOMEM; 475 break; 476 } 477 /* Append this Tx buffer to our free list. */ 478 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 479 } 480 if (error != 0) 481 rsu_free_tx_list(sc); 482 return (error); 483 } 484 485 void 486 rsu_free_tx_list(struct rsu_softc *sc) 487 { 488 int i; 489 490 /* NB: Caller must abort pipe first. */ 491 for (i = 0; i < RSU_TX_LIST_COUNT; i++) { 492 if (sc->tx_data[i].xfer != NULL) 493 usbd_free_xfer(sc->tx_data[i].xfer); 494 sc->tx_data[i].xfer = NULL; 495 } 496 } 497 498 void 499 rsu_task(void *arg) 500 { 501 struct rsu_softc *sc = arg; 502 struct rsu_host_cmd_ring *ring = &sc->cmdq; 503 struct rsu_host_cmd *cmd; 504 int s; 505 506 /* Process host commands. */ 507 s = splusb(); 508 while (ring->next != ring->cur) { 509 cmd = &ring->cmd[ring->next]; 510 splx(s); 511 /* Invoke callback. */ 512 cmd->cb(sc, cmd->data); 513 s = splusb(); 514 ring->queued--; 515 ring->next = (ring->next + 1) % RSU_HOST_CMD_RING_COUNT; 516 } 517 splx(s); 518 } 519 520 void 521 rsu_do_async(struct rsu_softc *sc, 522 void (*cb)(struct rsu_softc *, void *), void *arg, int len) 523 { 524 struct rsu_host_cmd_ring *ring = &sc->cmdq; 525 struct rsu_host_cmd *cmd; 526 int s; 527 528 s = splusb(); 529 cmd = &ring->cmd[ring->cur]; 530 cmd->cb = cb; 531 KASSERT(len <= sizeof(cmd->data)); 532 memcpy(cmd->data, arg, len); 533 ring->cur = (ring->cur + 1) % RSU_HOST_CMD_RING_COUNT; 534 535 /* If there is no pending command already, schedule a task. */ 536 if (++ring->queued == 1) 537 usb_add_task(sc->sc_udev, &sc->sc_task); 538 splx(s); 539 } 540 541 void 542 rsu_wait_async(struct rsu_softc *sc) 543 { 544 /* Wait for all queued asynchronous commands to complete. */ 545 usb_wait_task(sc->sc_udev, &sc->sc_task); 546 } 547 548 int 549 rsu_write_region_1(struct rsu_softc *sc, uint16_t addr, uint8_t *buf, 550 int len) 551 { 552 usb_device_request_t req; 553 554 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 555 req.bRequest = R92S_REQ_REGS; 556 USETW(req.wValue, addr); 557 USETW(req.wIndex, 0); 558 USETW(req.wLength, len); 559 return (usbd_do_request(sc->sc_udev, &req, buf)); 560 } 561 562 void 563 rsu_write_1(struct rsu_softc *sc, uint16_t addr, uint8_t val) 564 { 565 rsu_write_region_1(sc, addr, &val, 1); 566 } 567 568 void 569 rsu_write_2(struct rsu_softc *sc, uint16_t addr, uint16_t val) 570 { 571 val = htole16(val); 572 rsu_write_region_1(sc, addr, (uint8_t *)&val, 2); 573 } 574 575 void 576 rsu_write_4(struct rsu_softc *sc, uint16_t addr, uint32_t val) 577 { 578 val = htole32(val); 579 rsu_write_region_1(sc, addr, (uint8_t *)&val, 4); 580 } 581 582 int 583 rsu_read_region_1(struct rsu_softc *sc, uint16_t addr, uint8_t *buf, 584 int len) 585 { 586 usb_device_request_t req; 587 588 req.bmRequestType = UT_READ_VENDOR_DEVICE; 589 req.bRequest = R92S_REQ_REGS; 590 USETW(req.wValue, addr); 591 USETW(req.wIndex, 0); 592 USETW(req.wLength, len); 593 return (usbd_do_request(sc->sc_udev, &req, buf)); 594 } 595 596 uint8_t 597 rsu_read_1(struct rsu_softc *sc, uint16_t addr) 598 { 599 uint8_t val; 600 601 if (rsu_read_region_1(sc, addr, &val, 1) != 0) 602 return (0xff); 603 return (val); 604 } 605 606 uint16_t 607 rsu_read_2(struct rsu_softc *sc, uint16_t addr) 608 { 609 uint16_t val; 610 611 if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 612 return (0xffff); 613 return (letoh16(val)); 614 } 615 616 uint32_t 617 rsu_read_4(struct rsu_softc *sc, uint16_t addr) 618 { 619 uint32_t val; 620 621 if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 622 return (0xffffffff); 623 return (letoh32(val)); 624 } 625 626 int 627 rsu_fw_iocmd(struct rsu_softc *sc, uint32_t iocmd) 628 { 629 int ntries; 630 631 rsu_write_4(sc, R92S_IOCMD_CTRL, iocmd); 632 DELAY(100); 633 for (ntries = 0; ntries < 50; ntries++) { 634 if (rsu_read_4(sc, R92S_IOCMD_CTRL) == 0) 635 return (0); 636 DELAY(10); 637 } 638 return (ETIMEDOUT); 639 } 640 641 uint8_t 642 rsu_efuse_read_1(struct rsu_softc *sc, uint16_t addr) 643 { 644 uint32_t reg; 645 int ntries; 646 647 reg = rsu_read_4(sc, R92S_EFUSE_CTRL); 648 reg = RW(reg, R92S_EFUSE_CTRL_ADDR, addr); 649 reg &= ~R92S_EFUSE_CTRL_VALID; 650 rsu_write_4(sc, R92S_EFUSE_CTRL, reg); 651 /* Wait for read operation to complete. */ 652 for (ntries = 0; ntries < 100; ntries++) { 653 reg = rsu_read_4(sc, R92S_EFUSE_CTRL); 654 if (reg & R92S_EFUSE_CTRL_VALID) 655 return (MS(reg, R92S_EFUSE_CTRL_DATA)); 656 DELAY(5); 657 } 658 printf("%s: could not read efuse byte at address 0x%x\n", 659 sc->sc_dev.dv_xname, addr); 660 return (0xff); 661 } 662 663 int 664 rsu_read_rom(struct rsu_softc *sc) 665 { 666 uint8_t *rom = sc->rom; 667 uint16_t addr = 0; 668 uint32_t reg; 669 uint8_t off, msk; 670 int i; 671 672 /* Make sure that ROM type is eFuse and that autoload succeeded. */ 673 reg = rsu_read_1(sc, R92S_EE_9346CR); 674 if ((reg & (R92S_9356SEL | R92S_EEPROM_EN)) != R92S_EEPROM_EN) 675 return (EIO); 676 677 /* Turn on 2.5V to prevent eFuse leakage. */ 678 reg = rsu_read_1(sc, R92S_EFUSE_TEST + 3); 679 rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg | 0x80); 680 DELAY(1000); 681 rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg & ~0x80); 682 683 /* Read full ROM image. */ 684 memset(&sc->rom, 0xff, sizeof(sc->rom)); 685 while (addr < 512) { 686 reg = rsu_efuse_read_1(sc, addr); 687 if (reg == 0xff) 688 break; 689 addr++; 690 off = reg >> 4; 691 msk = reg & 0xf; 692 for (i = 0; i < 4; i++) { 693 if (msk & (1 << i)) 694 continue; 695 rom[off * 8 + i * 2 + 0] = 696 rsu_efuse_read_1(sc, addr); 697 addr++; 698 rom[off * 8 + i * 2 + 1] = 699 rsu_efuse_read_1(sc, addr); 700 addr++; 701 } 702 } 703 #ifdef RSU_DEBUG 704 if (rsu_debug >= 5) { 705 /* Dump ROM content. */ 706 printf("\n"); 707 for (i = 0; i < sizeof(sc->rom); i++) 708 printf("%02x:", rom[i]); 709 printf("\n"); 710 } 711 #endif 712 return (0); 713 } 714 715 int 716 rsu_fw_cmd(struct rsu_softc *sc, uint8_t code, void *buf, int len) 717 { 718 struct rsu_tx_data *data; 719 struct r92s_tx_desc *txd; 720 struct r92s_fw_cmd_hdr *cmd; 721 struct usbd_pipe *pipe; 722 int cmdsz, xferlen; 723 724 data = sc->fwcmd_data; 725 726 /* Round-up command length to a multiple of 8 bytes. */ 727 cmdsz = (len + 7) & ~7; 728 729 xferlen = sizeof(*txd) + sizeof(*cmd) + cmdsz; 730 KASSERT(xferlen <= RSU_TXBUFSZ); 731 memset(data->buf, 0, xferlen); 732 733 /* Setup Tx descriptor. */ 734 txd = (struct r92s_tx_desc *)data->buf; 735 txd->txdw0 = htole32( 736 SM(R92S_TXDW0_OFFSET, sizeof(*txd)) | 737 SM(R92S_TXDW0_PKTLEN, sizeof(*cmd) + cmdsz) | 738 R92S_TXDW0_OWN | R92S_TXDW0_FSG | R92S_TXDW0_LSG); 739 txd->txdw1 = htole32(SM(R92S_TXDW1_QSEL, R92S_TXDW1_QSEL_H2C)); 740 741 /* Setup command header. */ 742 cmd = (struct r92s_fw_cmd_hdr *)&txd[1]; 743 cmd->len = htole16(cmdsz); 744 cmd->code = code; 745 cmd->seq = sc->cmd_seq; 746 sc->cmd_seq = (sc->cmd_seq + 1) & 0x7f; 747 748 /* Copy command payload. */ 749 memcpy(&cmd[1], buf, len); 750 751 DPRINTFN(2, ("Tx cmd code=%d len=%d\n", code, cmdsz)); 752 pipe = sc->pipe[sc->qid2idx[RSU_QID_H2C]]; 753 usbd_setup_xfer(data->xfer, pipe, NULL, data->buf, xferlen, 754 USBD_SHORT_XFER_OK | USBD_NO_COPY | USBD_SYNCHRONOUS, 755 RSU_CMD_TIMEOUT, NULL); 756 return (usbd_transfer(data->xfer)); 757 } 758 759 int 760 rsu_media_change(struct ifnet *ifp) 761 { 762 int error; 763 764 error = ieee80211_media_change(ifp); 765 if (error != ENETRESET) 766 return (error); 767 768 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 769 (IFF_UP | IFF_RUNNING)) { 770 rsu_stop(ifp); 771 rsu_init(ifp); 772 } 773 return (0); 774 } 775 776 void 777 rsu_calib_to(void *arg) 778 { 779 struct rsu_softc *sc = arg; 780 781 if (usbd_is_dying(sc->sc_udev)) 782 return; 783 784 usbd_ref_incr(sc->sc_udev); 785 786 /* Do it in a process context. */ 787 rsu_do_async(sc, rsu_calib_cb, NULL, 0); 788 789 usbd_ref_decr(sc->sc_udev); 790 } 791 792 /* ARGSUSED */ 793 void 794 rsu_calib_cb(struct rsu_softc *sc, void *arg) 795 { 796 uint32_t reg; 797 798 #ifdef notyet 799 /* Read WPS PBC status. */ 800 rsu_write_1(sc, R92S_MAC_PINMUX_CTRL, 801 R92S_GPIOMUX_EN | SM(R92S_GPIOSEL_GPIO, R92S_GPIOSEL_GPIO_JTAG)); 802 rsu_write_1(sc, R92S_GPIO_IO_SEL, 803 rsu_read_1(sc, R92S_GPIO_IO_SEL) & ~R92S_GPIO_WPS); 804 reg = rsu_read_1(sc, R92S_GPIO_CTRL); 805 if (reg != 0xff && (reg & R92S_GPIO_WPS)) 806 DPRINTF(("WPS PBC is pushed\n")); 807 #endif 808 /* Read current signal level. */ 809 if (rsu_fw_iocmd(sc, 0xf4000001) == 0) { 810 reg = rsu_read_4(sc, R92S_IOCMD_DATA); 811 DPRINTFN(8, ("RSSI=%d%%\n", reg >> 4)); 812 } 813 814 if (!usbd_is_dying(sc->sc_udev)) 815 timeout_add_sec(&sc->calib_to, 2); 816 } 817 818 int 819 rsu_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 820 { 821 struct rsu_softc *sc = ic->ic_softc; 822 struct rsu_cmd_newstate cmd; 823 824 /* Do it in a process context. */ 825 cmd.state = nstate; 826 cmd.arg = arg; 827 rsu_do_async(sc, rsu_newstate_cb, &cmd, sizeof(cmd)); 828 return (0); 829 } 830 831 void 832 rsu_newstate_cb(struct rsu_softc *sc, void *arg) 833 { 834 struct rsu_cmd_newstate *cmd = arg; 835 struct ieee80211com *ic = &sc->sc_ic; 836 enum ieee80211_state ostate; 837 int error, s; 838 839 s = splnet(); 840 ostate = ic->ic_state; 841 DPRINTF(("newstate %d -> %d\n", ostate, cmd->state)); 842 843 if (ostate == IEEE80211_S_RUN) { 844 /* Stop calibration. */ 845 timeout_del(&sc->calib_to); 846 /* Disassociate from our current BSS. */ 847 (void)rsu_disconnect(sc); 848 } 849 switch (cmd->state) { 850 case IEEE80211_S_INIT: 851 break; 852 case IEEE80211_S_SCAN: 853 error = rsu_site_survey(sc); 854 if (error != 0) { 855 printf("%s: could not send site survey command\n", 856 sc->sc_dev.dv_xname); 857 } 858 ic->ic_state = cmd->state; 859 splx(s); 860 return; 861 case IEEE80211_S_AUTH: 862 error = rsu_join_bss(sc, ic->ic_bss); 863 if (error != 0) { 864 printf("%s: could not send join command\n", 865 sc->sc_dev.dv_xname); 866 ieee80211_begin_scan(&ic->ic_if); 867 splx(s); 868 return; 869 } 870 ic->ic_state = cmd->state; 871 splx(s); 872 return; 873 case IEEE80211_S_ASSOC: 874 ic->ic_state = cmd->state; 875 splx(s); 876 return; 877 case IEEE80211_S_RUN: 878 /* Indicate highest supported rate. */ 879 ic->ic_bss->ni_txrate = ic->ic_bss->ni_rates.rs_nrates - 1; 880 881 /* Start periodic calibration. */ 882 if (!usbd_is_dying(sc->sc_udev)) 883 timeout_add_sec(&sc->calib_to, 2); 884 break; 885 } 886 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 887 splx(s); 888 } 889 890 int 891 rsu_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 892 struct ieee80211_key *k) 893 { 894 struct rsu_softc *sc = ic->ic_softc; 895 struct rsu_cmd_key cmd; 896 897 /* Defer setting of WEP keys until interface is brought up. */ 898 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 899 (IFF_UP | IFF_RUNNING)) 900 return (0); 901 902 /* Do it in a process context. */ 903 cmd.key = *k; 904 rsu_do_async(sc, rsu_set_key_cb, &cmd, sizeof(cmd)); 905 return (0); 906 } 907 908 void 909 rsu_set_key_cb(struct rsu_softc *sc, void *arg) 910 { 911 struct rsu_cmd_key *cmd = arg; 912 struct ieee80211_key *k = &cmd->key; 913 struct r92s_fw_cmd_set_key key; 914 915 memset(&key, 0, sizeof(key)); 916 /* Map net80211 cipher to HW crypto algorithm. */ 917 switch (k->k_cipher) { 918 case IEEE80211_CIPHER_WEP40: 919 key.algo = R92S_KEY_ALGO_WEP40; 920 break; 921 case IEEE80211_CIPHER_WEP104: 922 key.algo = R92S_KEY_ALGO_WEP104; 923 break; 924 case IEEE80211_CIPHER_TKIP: 925 key.algo = R92S_KEY_ALGO_TKIP; 926 break; 927 case IEEE80211_CIPHER_CCMP: 928 key.algo = R92S_KEY_ALGO_AES; 929 break; 930 default: 931 return; 932 } 933 key.id = k->k_id; 934 key.grpkey = (k->k_flags & IEEE80211_KEY_GROUP) != 0; 935 memcpy(key.key, k->k_key, MIN(k->k_len, sizeof(key.key))); 936 (void)rsu_fw_cmd(sc, R92S_CMD_SET_KEY, &key, sizeof(key)); 937 } 938 939 /* ARGSUSED */ 940 void 941 rsu_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 942 struct ieee80211_key *k) 943 { 944 struct rsu_softc *sc = ic->ic_softc; 945 struct rsu_cmd_key cmd; 946 947 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 948 ic->ic_state != IEEE80211_S_RUN) 949 return; /* Nothing to do. */ 950 951 /* Do it in a process context. */ 952 cmd.key = *k; 953 rsu_do_async(sc, rsu_delete_key_cb, &cmd, sizeof(cmd)); 954 } 955 956 void 957 rsu_delete_key_cb(struct rsu_softc *sc, void *arg) 958 { 959 struct rsu_cmd_key *cmd = arg; 960 struct ieee80211_key *k = &cmd->key; 961 struct r92s_fw_cmd_set_key key; 962 963 memset(&key, 0, sizeof(key)); 964 key.id = k->k_id; 965 (void)rsu_fw_cmd(sc, R92S_CMD_SET_KEY, &key, sizeof(key)); 966 } 967 968 int 969 rsu_site_survey(struct rsu_softc *sc) 970 { 971 struct ieee80211com *ic = &sc->sc_ic; 972 struct r92s_fw_cmd_sitesurvey cmd; 973 974 memset(&cmd, 0, sizeof(cmd)); 975 if ((ic->ic_flags & IEEE80211_F_ASCAN) || sc->scan_pass == 1) 976 cmd.active = htole32(1); 977 cmd.limit = htole32(48); 978 if (sc->scan_pass == 1) { 979 /* Do a directed scan for second pass. */ 980 cmd.ssidlen = htole32(ic->ic_des_esslen); 981 memcpy(cmd.ssid, ic->ic_des_essid, ic->ic_des_esslen); 982 } 983 DPRINTF(("sending site survey command, pass=%d\n", sc->scan_pass)); 984 return (rsu_fw_cmd(sc, R92S_CMD_SITE_SURVEY, &cmd, sizeof(cmd))); 985 } 986 987 int 988 rsu_join_bss(struct rsu_softc *sc, struct ieee80211_node *ni) 989 { 990 struct ieee80211com *ic = &sc->sc_ic; 991 struct ndis_wlan_bssid_ex *bss; 992 struct ndis_802_11_fixed_ies *fixed; 993 struct r92s_fw_cmd_auth auth; 994 uint8_t buf[sizeof(*bss) + 128], *frm; 995 uint8_t opmode; 996 int error; 997 998 /* Let the FW decide the opmode based on the capinfo field. */ 999 opmode = NDIS802_11AUTOUNKNOWN; 1000 DPRINTF(("setting operating mode to %d\n", opmode)); 1001 error = rsu_fw_cmd(sc, R92S_CMD_SET_OPMODE, &opmode, sizeof(opmode)); 1002 if (error != 0) 1003 return (error); 1004 1005 memset(&auth, 0, sizeof(auth)); 1006 if (ic->ic_flags & IEEE80211_F_RSNON) { 1007 auth.mode = R92S_AUTHMODE_WPA; 1008 auth.dot1x = ieee80211_is_8021x_akm(ni->ni_rsnakms); 1009 } else 1010 auth.mode = R92S_AUTHMODE_OPEN; 1011 DPRINTF(("setting auth mode to %d\n", auth.mode)); 1012 error = rsu_fw_cmd(sc, R92S_CMD_SET_AUTH, &auth, sizeof(auth)); 1013 if (error != 0) 1014 return (error); 1015 1016 memset(buf, 0, sizeof(buf)); 1017 bss = (struct ndis_wlan_bssid_ex *)buf; 1018 IEEE80211_ADDR_COPY(bss->macaddr, ni->ni_bssid); 1019 bss->ssid.ssidlen = htole32(ni->ni_esslen); 1020 memcpy(bss->ssid.ssid, ni->ni_essid, ni->ni_esslen); 1021 if (ic->ic_flags & (IEEE80211_F_WEPON | IEEE80211_F_RSNON)) 1022 bss->privacy = htole32(1); 1023 bss->rssi = htole32(ni->ni_rssi); 1024 if (ic->ic_curmode == IEEE80211_MODE_11B) 1025 bss->networktype = htole32(NDIS802_11DS); 1026 else 1027 bss->networktype = htole32(NDIS802_11OFDM24); 1028 bss->config.len = htole32(sizeof(bss->config)); 1029 bss->config.bintval = htole32(ni->ni_intval); 1030 bss->config.dsconfig = htole32(ieee80211_chan2ieee(ic, ni->ni_chan)); 1031 bss->inframode = htole32(NDIS802_11INFRASTRUCTURE); 1032 memcpy(bss->supprates, ni->ni_rates.rs_rates, 1033 ni->ni_rates.rs_nrates); 1034 /* Write the fixed fields of the beacon frame. */ 1035 fixed = (struct ndis_802_11_fixed_ies *)&bss[1]; 1036 memcpy(&fixed->tstamp, ni->ni_tstamp, 8); 1037 fixed->bintval = htole16(ni->ni_intval); 1038 fixed->capabilities = htole16(ni->ni_capinfo); 1039 /* Write IEs to be included in the association request. */ 1040 frm = (uint8_t *)&fixed[1]; 1041 if ((ic->ic_flags & IEEE80211_F_RSNON) && 1042 (ni->ni_rsnprotos & IEEE80211_PROTO_RSN)) 1043 frm = ieee80211_add_rsn(frm, ic, ni); 1044 if (ni->ni_flags & IEEE80211_NODE_QOS) 1045 frm = ieee80211_add_qos_capability(frm, ic); 1046 #ifndef IEEE80211_NO_HT 1047 if (ni->ni_flags & IEEE80211_NODE_HT) 1048 frm = ieee80211_add_htcaps(frm, ic); 1049 #endif 1050 if ((ic->ic_flags & IEEE80211_F_RSNON) && 1051 (ni->ni_rsnprotos & IEEE80211_PROTO_WPA)) 1052 frm = ieee80211_add_wpa(frm, ic, ni); 1053 bss->ieslen = htole32(frm - (uint8_t *)fixed); 1054 bss->len = htole32(((frm - buf) + 3) & ~3); 1055 DPRINTF(("sending join bss command to %s chan %d\n", 1056 ether_sprintf(bss->macaddr), letoh32(bss->config.dsconfig))); 1057 return (rsu_fw_cmd(sc, R92S_CMD_JOIN_BSS, buf, sizeof(buf))); 1058 } 1059 1060 int 1061 rsu_disconnect(struct rsu_softc *sc) 1062 { 1063 uint32_t zero = 0; /* :-) */ 1064 1065 /* Disassociate from our current BSS. */ 1066 DPRINTF(("sending disconnect command\n")); 1067 return (rsu_fw_cmd(sc, R92S_CMD_DISCONNECT, &zero, sizeof(zero))); 1068 } 1069 1070 void 1071 rsu_event_survey(struct rsu_softc *sc, uint8_t *buf, int len) 1072 { 1073 struct ieee80211com *ic = &sc->sc_ic; 1074 struct ifnet *ifp = &ic->ic_if; 1075 struct ieee80211_rxinfo rxi; 1076 struct ieee80211_node *ni; 1077 struct ieee80211_frame *wh; 1078 struct ndis_wlan_bssid_ex *bss; 1079 struct mbuf *m; 1080 int pktlen; 1081 1082 if (__predict_false(len < sizeof(*bss))) 1083 return; 1084 bss = (struct ndis_wlan_bssid_ex *)buf; 1085 if (__predict_false(len < sizeof(*bss) + letoh32(bss->ieslen))) 1086 return; 1087 1088 DPRINTFN(2, ("found BSS %s: len=%d chan=%d inframode=%d " 1089 "networktype=%d privacy=%d\n", 1090 ether_sprintf(bss->macaddr), letoh32(bss->len), 1091 letoh32(bss->config.dsconfig), letoh32(bss->inframode), 1092 letoh32(bss->networktype), letoh32(bss->privacy))); 1093 1094 /* Build a fake beacon frame to let net80211 do all the parsing. */ 1095 pktlen = sizeof(*wh) + letoh32(bss->ieslen); 1096 if (__predict_false(pktlen > MCLBYTES)) 1097 return; 1098 MGETHDR(m, M_DONTWAIT, MT_DATA); 1099 if (__predict_false(m == NULL)) 1100 return; 1101 if (pktlen > MHLEN) { 1102 MCLGET(m, M_DONTWAIT); 1103 if (!(m->m_flags & M_EXT)) { 1104 m_free(m); 1105 return; 1106 } 1107 } 1108 wh = mtod(m, struct ieee80211_frame *); 1109 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 1110 IEEE80211_FC0_SUBTYPE_BEACON; 1111 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1112 *(uint16_t *)wh->i_dur = 0; 1113 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 1114 IEEE80211_ADDR_COPY(wh->i_addr2, bss->macaddr); 1115 IEEE80211_ADDR_COPY(wh->i_addr3, bss->macaddr); 1116 *(uint16_t *)wh->i_seq = 0; 1117 memcpy(&wh[1], (uint8_t *)&bss[1], letoh32(bss->ieslen)); 1118 1119 /* Finalize mbuf. */ 1120 m->m_pkthdr.len = m->m_len = pktlen; 1121 m->m_pkthdr.rcvif = ifp; 1122 1123 ni = ieee80211_find_rxnode(ic, wh); 1124 rxi.rxi_flags = 0; 1125 rxi.rxi_rssi = letoh32(bss->rssi); 1126 rxi.rxi_tstamp = 0; 1127 ieee80211_input(ifp, m, ni, &rxi); 1128 /* Node is no longer needed. */ 1129 ieee80211_release_node(ic, ni); 1130 } 1131 1132 void 1133 rsu_event_join_bss(struct rsu_softc *sc, uint8_t *buf, int len) 1134 { 1135 struct ieee80211com *ic = &sc->sc_ic; 1136 struct ieee80211_node *ni = ic->ic_bss; 1137 struct r92s_event_join_bss *rsp; 1138 int res; 1139 1140 if (__predict_false(len < sizeof(*rsp))) 1141 return; 1142 rsp = (struct r92s_event_join_bss *)buf; 1143 res = (int)letoh32(rsp->join_res); 1144 1145 DPRINTF(("Rx join BSS event len=%d res=%d\n", len, res)); 1146 if (res <= 0) { 1147 ic->ic_stats.is_rx_auth_fail++; 1148 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1149 return; 1150 } 1151 DPRINTF(("associated with %s associd=%d\n", 1152 ether_sprintf(rsp->bss.macaddr), letoh32(rsp->associd))); 1153 1154 ni->ni_associd = letoh32(rsp->associd) | 0xc000; 1155 if (ic->ic_flags & IEEE80211_F_WEPON) 1156 ni->ni_flags |= IEEE80211_NODE_TXRXPROT; 1157 1158 ieee80211_new_state(ic, IEEE80211_S_RUN, 1159 IEEE80211_FC0_SUBTYPE_ASSOC_RESP); 1160 } 1161 1162 void 1163 rsu_rx_event(struct rsu_softc *sc, uint8_t code, uint8_t *buf, int len) 1164 { 1165 struct ieee80211com *ic = &sc->sc_ic; 1166 struct ifnet *ifp = &ic->ic_if; 1167 1168 DPRINTFN(4, ("Rx event code=%d len=%d\n", code, len)); 1169 switch (code) { 1170 case R92S_EVT_SURVEY: 1171 if (ic->ic_state == IEEE80211_S_SCAN) 1172 rsu_event_survey(sc, buf, len); 1173 break; 1174 case R92S_EVT_SURVEY_DONE: 1175 DPRINTF(("site survey pass %d done, found %d BSS\n", 1176 sc->scan_pass, letoh32(*(uint32_t *)buf))); 1177 if (ic->ic_state != IEEE80211_S_SCAN) 1178 break; /* Ignore if not scanning. */ 1179 if (sc->scan_pass == 0 && ic->ic_des_esslen != 0) { 1180 /* Schedule a directed scan for hidden APs. */ 1181 sc->scan_pass = 1; 1182 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1183 break; 1184 } 1185 ieee80211_end_scan(ifp); 1186 sc->scan_pass = 0; 1187 break; 1188 case R92S_EVT_JOIN_BSS: 1189 if (ic->ic_state == IEEE80211_S_AUTH) 1190 rsu_event_join_bss(sc, buf, len); 1191 break; 1192 case R92S_EVT_DEL_STA: 1193 DPRINTF(("disassociated from %s\n", ether_sprintf(buf))); 1194 if (ic->ic_state == IEEE80211_S_RUN && 1195 IEEE80211_ADDR_EQ(ic->ic_bss->ni_bssid, buf)) 1196 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1197 break; 1198 case R92S_EVT_WPS_PBC: 1199 DPRINTF(("WPS PBC pushed.\n")); 1200 break; 1201 case R92S_EVT_FWDBG: 1202 if (ifp->if_flags & IFF_DEBUG) { 1203 buf[60] = '\0'; 1204 printf("FWDBG: %s\n", (char *)buf); 1205 } 1206 break; 1207 } 1208 } 1209 1210 void 1211 rsu_rx_multi_event(struct rsu_softc *sc, uint8_t *buf, int len) 1212 { 1213 struct r92s_fw_cmd_hdr *cmd; 1214 int cmdsz; 1215 1216 DPRINTFN(6, ("Rx events len=%d\n", len)); 1217 1218 /* Skip Rx status. */ 1219 buf += sizeof(struct r92s_rx_stat); 1220 len -= sizeof(struct r92s_rx_stat); 1221 1222 /* Process all events. */ 1223 for (;;) { 1224 /* Check that command header fits. */ 1225 if (__predict_false(len < sizeof(*cmd))) 1226 break; 1227 cmd = (struct r92s_fw_cmd_hdr *)buf; 1228 /* Check that command payload fits. */ 1229 cmdsz = letoh16(cmd->len); 1230 if (__predict_false(len < sizeof(*cmd) + cmdsz)) 1231 break; 1232 1233 /* Process firmware event. */ 1234 rsu_rx_event(sc, cmd->code, (uint8_t *)&cmd[1], cmdsz); 1235 1236 if (!(cmd->seq & R92S_FW_CMD_MORE)) 1237 break; 1238 buf += sizeof(*cmd) + cmdsz; 1239 len -= sizeof(*cmd) + cmdsz; 1240 } 1241 } 1242 1243 int8_t 1244 rsu_get_rssi(struct rsu_softc *sc, int rate, void *physt) 1245 { 1246 static const int8_t cckoff[] = { 14, -2, -20, -40 }; 1247 struct r92s_rx_phystat *phy; 1248 struct r92s_rx_cck *cck; 1249 uint8_t rpt; 1250 int8_t rssi; 1251 1252 if (rate <= 3) { 1253 cck = (struct r92s_rx_cck *)physt; 1254 rpt = (cck->agc_rpt >> 6) & 0x3; 1255 rssi = cck->agc_rpt & 0x3e; 1256 rssi = cckoff[rpt] - rssi; 1257 } else { /* OFDM/HT. */ 1258 phy = (struct r92s_rx_phystat *)physt; 1259 rssi = ((letoh32(phy->phydw1) >> 1) & 0x7f) - 106; 1260 } 1261 return (rssi); 1262 } 1263 1264 void 1265 rsu_rx_frame(struct rsu_softc *sc, uint8_t *buf, int pktlen) 1266 { 1267 struct ieee80211com *ic = &sc->sc_ic; 1268 struct ifnet *ifp = &ic->ic_if; 1269 struct ieee80211_rxinfo rxi; 1270 struct ieee80211_frame *wh; 1271 struct ieee80211_node *ni; 1272 struct r92s_rx_stat *stat; 1273 uint32_t rxdw0, rxdw3; 1274 struct mbuf *m; 1275 uint8_t rate; 1276 int8_t rssi = 0; 1277 int s, infosz; 1278 1279 stat = (struct r92s_rx_stat *)buf; 1280 rxdw0 = letoh32(stat->rxdw0); 1281 rxdw3 = letoh32(stat->rxdw3); 1282 1283 if (__predict_false(rxdw0 & R92S_RXDW0_CRCERR)) { 1284 ifp->if_ierrors++; 1285 return; 1286 } 1287 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1288 ifp->if_ierrors++; 1289 return; 1290 } 1291 1292 rate = MS(rxdw3, R92S_RXDW3_RATE); 1293 infosz = MS(rxdw0, R92S_RXDW0_INFOSZ) * 8; 1294 1295 /* Get RSSI from PHY status descriptor if present. */ 1296 if (infosz != 0) 1297 rssi = rsu_get_rssi(sc, rate, &stat[1]); 1298 1299 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1300 pktlen, rate, infosz, rssi)); 1301 1302 MGETHDR(m, M_DONTWAIT, MT_DATA); 1303 if (__predict_false(m == NULL)) { 1304 ifp->if_ierrors++; 1305 return; 1306 } 1307 if (pktlen > MHLEN) { 1308 MCLGET(m, M_DONTWAIT); 1309 if (__predict_false(!(m->m_flags & M_EXT))) { 1310 ifp->if_ierrors++; 1311 m_freem(m); 1312 return; 1313 } 1314 } 1315 /* Finalize mbuf. */ 1316 m->m_pkthdr.rcvif = ifp; 1317 /* Hardware does Rx TCP checksum offload. */ 1318 if (rxdw3 & R92S_RXDW3_TCPCHKVALID) { 1319 if (__predict_true(rxdw3 & R92S_RXDW3_TCPCHKRPT)) 1320 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 1321 else 1322 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_BAD; 1323 } 1324 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 1325 memcpy(mtod(m, uint8_t *), wh, pktlen); 1326 m->m_pkthdr.len = m->m_len = pktlen; 1327 1328 s = splnet(); 1329 #if NBPFILTER > 0 1330 if (__predict_false(sc->sc_drvbpf != NULL)) { 1331 struct rsu_rx_radiotap_header *tap = &sc->sc_rxtap; 1332 struct mbuf mb; 1333 1334 tap->wr_flags = 0; 1335 /* Map HW rate index to 802.11 rate. */ 1336 tap->wr_flags = 2; 1337 if (!(rxdw3 & R92S_RXDW3_HTC)) { 1338 switch (rate) { 1339 /* CCK. */ 1340 case 0: tap->wr_rate = 2; break; 1341 case 1: tap->wr_rate = 4; break; 1342 case 2: tap->wr_rate = 11; break; 1343 case 3: tap->wr_rate = 22; break; 1344 /* OFDM. */ 1345 case 4: tap->wr_rate = 12; break; 1346 case 5: tap->wr_rate = 18; break; 1347 case 6: tap->wr_rate = 24; break; 1348 case 7: tap->wr_rate = 36; break; 1349 case 8: tap->wr_rate = 48; break; 1350 case 9: tap->wr_rate = 72; break; 1351 case 10: tap->wr_rate = 96; break; 1352 case 11: tap->wr_rate = 108; break; 1353 } 1354 } else if (rate >= 12) { /* MCS0~15. */ 1355 /* Bit 7 set means HT MCS instead of rate. */ 1356 tap->wr_rate = 0x80 | (rate - 12); 1357 } 1358 tap->wr_dbm_antsignal = rssi; 1359 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1360 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1361 1362 mb.m_data = (caddr_t)tap; 1363 mb.m_len = sc->sc_rxtap_len; 1364 mb.m_next = m; 1365 mb.m_nextpkt = NULL; 1366 mb.m_type = 0; 1367 mb.m_flags = 0; 1368 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1369 } 1370 #endif 1371 1372 ni = ieee80211_find_rxnode(ic, wh); 1373 rxi.rxi_flags = 0; 1374 rxi.rxi_rssi = rssi; 1375 rxi.rxi_tstamp = 0; /* Unused. */ 1376 ieee80211_input(ifp, m, ni, &rxi); 1377 /* Node is no longer needed. */ 1378 ieee80211_release_node(ic, ni); 1379 splx(s); 1380 } 1381 1382 void 1383 rsu_rx_multi_frame(struct rsu_softc *sc, uint8_t *buf, int len) 1384 { 1385 struct r92s_rx_stat *stat; 1386 uint32_t rxdw0; 1387 int totlen, pktlen, infosz, npkts; 1388 1389 /* Get the number of encapsulated frames. */ 1390 stat = (struct r92s_rx_stat *)buf; 1391 npkts = MS(letoh32(stat->rxdw2), R92S_RXDW2_PKTCNT); 1392 DPRINTFN(6, ("Rx %d frames in one chunk\n", npkts)); 1393 1394 /* Process all of them. */ 1395 while (npkts-- > 0) { 1396 if (__predict_false(len < sizeof(*stat))) 1397 break; 1398 stat = (struct r92s_rx_stat *)buf; 1399 rxdw0 = letoh32(stat->rxdw0); 1400 1401 pktlen = MS(rxdw0, R92S_RXDW0_PKTLEN); 1402 if (__predict_false(pktlen == 0)) 1403 break; 1404 1405 infosz = MS(rxdw0, R92S_RXDW0_INFOSZ) * 8; 1406 1407 /* Make sure everything fits in xfer. */ 1408 totlen = sizeof(*stat) + infosz + pktlen; 1409 if (__predict_false(totlen > len)) 1410 break; 1411 1412 /* Process 802.11 frame. */ 1413 rsu_rx_frame(sc, buf, pktlen); 1414 1415 /* Next chunk is 128-byte aligned. */ 1416 totlen = (totlen + 127) & ~127; 1417 buf += totlen; 1418 len -= totlen; 1419 } 1420 } 1421 1422 void 1423 rsu_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1424 { 1425 struct rsu_rx_data *data = priv; 1426 struct rsu_softc *sc = data->sc; 1427 struct r92s_rx_stat *stat; 1428 int len; 1429 1430 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1431 DPRINTF(("RX status=%d\n", status)); 1432 if (status == USBD_STALLED) 1433 usbd_clear_endpoint_stall_async(data->pipe); 1434 if (status != USBD_CANCELLED) 1435 goto resubmit; 1436 return; 1437 } 1438 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1439 1440 if (__predict_false(len < sizeof(*stat))) { 1441 DPRINTF(("xfer too short %d\n", len)); 1442 goto resubmit; 1443 } 1444 /* Determine if it is a firmware C2H event or an 802.11 frame. */ 1445 stat = (struct r92s_rx_stat *)data->buf; 1446 if ((letoh32(stat->rxdw1) & 0x1ff) == 0x1ff) 1447 rsu_rx_multi_event(sc, data->buf, len); 1448 else 1449 rsu_rx_multi_frame(sc, data->buf, len); 1450 1451 resubmit: 1452 /* Setup a new transfer. */ 1453 usbd_setup_xfer(xfer, data->pipe, data, data->buf, RSU_RXBUFSZ, 1454 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, rsu_rxeof); 1455 (void)usbd_transfer(xfer); 1456 } 1457 1458 void 1459 rsu_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1460 { 1461 struct rsu_tx_data *data = priv; 1462 struct rsu_softc *sc = data->sc; 1463 struct ifnet *ifp = &sc->sc_ic.ic_if; 1464 int s; 1465 1466 s = splnet(); 1467 /* Put this Tx buffer back to our free list. */ 1468 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1469 1470 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1471 DPRINTF(("TX status=%d\n", status)); 1472 if (status == USBD_STALLED) 1473 usbd_clear_endpoint_stall_async(data->pipe); 1474 ifp->if_oerrors++; 1475 splx(s); 1476 return; 1477 } 1478 sc->sc_tx_timer = 0; 1479 ifp->if_opackets++; 1480 1481 /* We just released a Tx buffer, notify Tx. */ 1482 if (ifp->if_flags & IFF_OACTIVE) { 1483 ifp->if_flags &= ~IFF_OACTIVE; 1484 rsu_start(ifp); 1485 } 1486 splx(s); 1487 } 1488 1489 int 1490 rsu_tx(struct rsu_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1491 { 1492 struct ieee80211com *ic = &sc->sc_ic; 1493 struct ieee80211_frame *wh; 1494 struct ieee80211_key *k = NULL; 1495 struct rsu_tx_data *data; 1496 struct r92s_tx_desc *txd; 1497 struct usbd_pipe *pipe; 1498 uint16_t qos; 1499 uint8_t type, qid, tid = 0; 1500 int hasqos, xferlen, error; 1501 1502 wh = mtod(m, struct ieee80211_frame *); 1503 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1504 1505 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1506 k = ieee80211_get_txkey(ic, wh, ni); 1507 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1508 return (ENOBUFS); 1509 wh = mtod(m, struct ieee80211_frame *); 1510 } 1511 if ((hasqos = ieee80211_has_qos(wh))) { 1512 qos = ieee80211_get_qos(wh); 1513 tid = qos & IEEE80211_QOS_TID; 1514 qid = rsu_ac2qid[ieee80211_up_to_ac(ic, tid)]; 1515 } else 1516 qid = RSU_QID_BE; 1517 1518 /* Get the USB pipe to use for this queue id. */ 1519 pipe = sc->pipe[sc->qid2idx[qid]]; 1520 1521 /* Grab a Tx buffer from our free list. */ 1522 data = TAILQ_FIRST(&sc->tx_free_list); 1523 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1524 1525 /* Fill Tx descriptor. */ 1526 txd = (struct r92s_tx_desc *)data->buf; 1527 memset(txd, 0, sizeof(*txd)); 1528 1529 txd->txdw0 |= htole32( 1530 SM(R92S_TXDW0_PKTLEN, m->m_pkthdr.len) | 1531 SM(R92S_TXDW0_OFFSET, sizeof(*txd)) | 1532 R92S_TXDW0_OWN | R92S_TXDW0_FSG | R92S_TXDW0_LSG); 1533 1534 txd->txdw1 |= htole32( 1535 SM(R92S_TXDW1_MACID, R92S_MACID_BSS) | 1536 SM(R92S_TXDW1_QSEL, R92S_TXDW1_QSEL_BE)); 1537 if (!hasqos) 1538 txd->txdw1 |= htole32(R92S_TXDW1_NONQOS); 1539 #ifdef notyet 1540 if (k != NULL) { 1541 switch (k->k_cipher) { 1542 case IEEE80211_CIPHER_WEP40: 1543 case IEEE80211_CIPHER_WEP104: 1544 cipher = R92S_TXDW1_CIPHER_WEP; 1545 break; 1546 case IEEE80211_CIPHER_TKIP: 1547 cipher = R92S_TXDW1_CIPHER_TKIP; 1548 break; 1549 case IEEE80211_CIPHER_CCMP: 1550 cipher = R92S_TXDW1_CIPHER_AES; 1551 break; 1552 default: 1553 cipher = R92S_TXDW1_CIPHER_NONE; 1554 } 1555 txd->txdw1 |= htole32( 1556 SM(R92S_TXDW1_CIPHER, cipher) | 1557 SM(R92S_TXDW1_KEYIDX, k->k_id)); 1558 } 1559 #endif 1560 txd->txdw2 |= htole32(R92S_TXDW2_BK); 1561 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1562 txd->txdw2 |= htole32(R92S_TXDW2_BMCAST); 1563 /* 1564 * Firmware will use and increment the sequence number for the 1565 * specified TID. 1566 */ 1567 txd->txdw3 |= htole32(SM(R92S_TXDW3_SEQ, tid)); 1568 1569 #if NBPFILTER > 0 1570 if (__predict_false(sc->sc_drvbpf != NULL)) { 1571 struct rsu_tx_radiotap_header *tap = &sc->sc_txtap; 1572 struct mbuf mb; 1573 1574 tap->wt_flags = 0; 1575 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1576 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1577 1578 mb.m_data = (caddr_t)tap; 1579 mb.m_len = sc->sc_txtap_len; 1580 mb.m_next = m; 1581 mb.m_nextpkt = NULL; 1582 mb.m_type = 0; 1583 mb.m_flags = 0; 1584 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1585 } 1586 #endif 1587 1588 xferlen = sizeof(*txd) + m->m_pkthdr.len; 1589 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 1590 m_freem(m); 1591 1592 data->pipe = pipe; 1593 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1594 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RSU_TX_TIMEOUT, 1595 rsu_txeof); 1596 error = usbd_transfer(data->xfer); 1597 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1598 /* Put this Tx buffer back to our free list. */ 1599 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1600 return (error); 1601 } 1602 ieee80211_release_node(ic, ni); 1603 return (0); 1604 } 1605 1606 /* ARGSUSED */ 1607 int 1608 rsu_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1609 int arg1, int arg2) 1610 { 1611 return (EOPNOTSUPP); 1612 } 1613 1614 void 1615 rsu_start(struct ifnet *ifp) 1616 { 1617 struct rsu_softc *sc = ifp->if_softc; 1618 struct ieee80211com *ic = &sc->sc_ic; 1619 struct ieee80211_node *ni; 1620 struct mbuf *m; 1621 1622 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1623 return; 1624 1625 for (;;) { 1626 if (TAILQ_EMPTY(&sc->tx_free_list)) { 1627 ifp->if_flags |= IFF_OACTIVE; 1628 break; 1629 } 1630 if (ic->ic_state != IEEE80211_S_RUN) 1631 break; 1632 1633 /* Encapsulate and send data frames. */ 1634 IFQ_DEQUEUE(&ifp->if_snd, m); 1635 if (m == NULL) 1636 break; 1637 #if NBPFILTER > 0 1638 if (ifp->if_bpf != NULL) 1639 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1640 #endif 1641 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1642 continue; 1643 1644 #if NBPFILTER > 0 1645 if (ic->ic_rawbpf != NULL) 1646 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1647 #endif 1648 if (rsu_tx(sc, m, ni) != 0) { 1649 ieee80211_release_node(ic, ni); 1650 ifp->if_oerrors++; 1651 continue; 1652 } 1653 1654 sc->sc_tx_timer = 5; 1655 ifp->if_timer = 1; 1656 } 1657 } 1658 1659 void 1660 rsu_watchdog(struct ifnet *ifp) 1661 { 1662 struct rsu_softc *sc = ifp->if_softc; 1663 1664 ifp->if_timer = 0; 1665 1666 if (sc->sc_tx_timer > 0) { 1667 if (--sc->sc_tx_timer == 0) { 1668 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1669 /* rsu_init(ifp); XXX needs a process context! */ 1670 ifp->if_oerrors++; 1671 return; 1672 } 1673 ifp->if_timer = 1; 1674 } 1675 ieee80211_watchdog(ifp); 1676 } 1677 1678 int 1679 rsu_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1680 { 1681 struct rsu_softc *sc = ifp->if_softc; 1682 struct ieee80211com *ic = &sc->sc_ic; 1683 struct ifaddr *ifa; 1684 struct ifreq *ifr; 1685 int s, error = 0; 1686 1687 if (usbd_is_dying(sc->sc_udev)) 1688 return ENXIO; 1689 1690 usbd_ref_incr(sc->sc_udev); 1691 1692 s = splnet(); 1693 1694 switch (cmd) { 1695 case SIOCSIFADDR: 1696 ifa = (struct ifaddr *)data; 1697 ifp->if_flags |= IFF_UP; 1698 #ifdef INET 1699 if (ifa->ifa_addr->sa_family == AF_INET) 1700 arp_ifinit(&ic->ic_ac, ifa); 1701 #endif 1702 /* FALLTHROUGH */ 1703 case SIOCSIFFLAGS: 1704 if (ifp->if_flags & IFF_UP) { 1705 if (!(ifp->if_flags & IFF_RUNNING)) 1706 rsu_init(ifp); 1707 } else { 1708 if (ifp->if_flags & IFF_RUNNING) 1709 rsu_stop(ifp); 1710 } 1711 break; 1712 case SIOCADDMULTI: 1713 case SIOCDELMULTI: 1714 ifr = (struct ifreq *)data; 1715 error = (cmd == SIOCADDMULTI) ? 1716 ether_addmulti(ifr, &ic->ic_ac) : 1717 ether_delmulti(ifr, &ic->ic_ac); 1718 if (error == ENETRESET) 1719 error = 0; 1720 break; 1721 default: 1722 error = ieee80211_ioctl(ifp, cmd, data); 1723 } 1724 1725 if (error == ENETRESET) { 1726 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1727 (IFF_UP | IFF_RUNNING)) { 1728 rsu_stop(ifp); 1729 rsu_init(ifp); 1730 } 1731 error = 0; 1732 } 1733 splx(s); 1734 1735 usbd_ref_decr(sc->sc_udev); 1736 1737 return (error); 1738 } 1739 1740 /* 1741 * Power on sequence for A-cut adapters. 1742 */ 1743 void 1744 rsu_power_on_acut(struct rsu_softc *sc) 1745 { 1746 uint32_t reg; 1747 1748 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x53); 1749 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x57); 1750 1751 /* Enable AFE macro block's bandgap and Mbias. */ 1752 rsu_write_1(sc, R92S_AFE_MISC, 1753 rsu_read_1(sc, R92S_AFE_MISC) | 1754 R92S_AFE_MISC_BGEN | R92S_AFE_MISC_MBEN); 1755 /* Enable LDOA15 block. */ 1756 rsu_write_1(sc, R92S_LDOA15_CTRL, 1757 rsu_read_1(sc, R92S_LDOA15_CTRL) | R92S_LDA15_EN); 1758 1759 rsu_write_1(sc, R92S_SPS1_CTRL, 1760 rsu_read_1(sc, R92S_SPS1_CTRL) | R92S_SPS1_LDEN); 1761 usbd_delay_ms(sc->sc_udev, 2); 1762 /* Enable switch regulator block. */ 1763 rsu_write_1(sc, R92S_SPS1_CTRL, 1764 rsu_read_1(sc, R92S_SPS1_CTRL) | R92S_SPS1_SWEN); 1765 1766 rsu_write_4(sc, R92S_SPS1_CTRL, 0x00a7b267); 1767 1768 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1769 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) | 0x08); 1770 1771 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1772 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x20); 1773 1774 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1775 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) & ~0x90); 1776 1777 /* Enable AFE clock. */ 1778 rsu_write_1(sc, R92S_AFE_XTAL_CTRL + 1, 1779 rsu_read_1(sc, R92S_AFE_XTAL_CTRL + 1) & ~0x04); 1780 /* Enable AFE PLL macro block. */ 1781 rsu_write_1(sc, R92S_AFE_PLL_CTRL, 1782 rsu_read_1(sc, R92S_AFE_PLL_CTRL) | 0x11); 1783 /* Attach AFE PLL to MACTOP/BB. */ 1784 rsu_write_1(sc, R92S_SYS_ISO_CTRL, 1785 rsu_read_1(sc, R92S_SYS_ISO_CTRL) & ~0x11); 1786 1787 /* Switch to 40MHz clock instead of 80MHz. */ 1788 rsu_write_2(sc, R92S_SYS_CLKR, 1789 rsu_read_2(sc, R92S_SYS_CLKR) & ~R92S_SYS_CLKSEL); 1790 1791 /* Enable MAC clock. */ 1792 rsu_write_2(sc, R92S_SYS_CLKR, 1793 rsu_read_2(sc, R92S_SYS_CLKR) | 1794 R92S_MAC_CLK_EN | R92S_SYS_CLK_EN); 1795 1796 rsu_write_1(sc, R92S_PMC_FSM, 0x02); 1797 1798 /* Enable digital core and IOREG R/W. */ 1799 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1800 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x08); 1801 1802 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1803 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x80); 1804 1805 /* Switch the control path to firmware. */ 1806 reg = rsu_read_2(sc, R92S_SYS_CLKR); 1807 reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL; 1808 rsu_write_2(sc, R92S_SYS_CLKR, reg); 1809 1810 rsu_write_2(sc, R92S_CR, 0x37fc); 1811 1812 /* Fix USB RX FIFO issue. */ 1813 rsu_write_1(sc, 0xfe5c, 1814 rsu_read_1(sc, 0xfe5c) | 0x80); 1815 rsu_write_1(sc, 0x00ab, 1816 rsu_read_1(sc, 0x00ab) | 0xc0); 1817 1818 rsu_write_1(sc, R92S_SYS_CLKR, 1819 rsu_read_1(sc, R92S_SYS_CLKR) & ~R92S_SYS_CPU_CLKSEL); 1820 } 1821 1822 /* 1823 * Power on sequence for B-cut and C-cut adapters. 1824 */ 1825 void 1826 rsu_power_on_bcut(struct rsu_softc *sc) 1827 { 1828 uint32_t reg; 1829 int ntries; 1830 1831 /* Prevent eFuse leakage. */ 1832 rsu_write_1(sc, 0x37, 0xb0); 1833 usbd_delay_ms(sc->sc_udev, 10); 1834 rsu_write_1(sc, 0x37, 0x30); 1835 1836 /* Switch the control path to hardware. */ 1837 reg = rsu_read_2(sc, R92S_SYS_CLKR); 1838 if (reg & R92S_FWHW_SEL) { 1839 rsu_write_2(sc, R92S_SYS_CLKR, 1840 reg & ~(R92S_SWHW_SEL | R92S_FWHW_SEL)); 1841 } 1842 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1843 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) & ~0x8c); 1844 DELAY(1000); 1845 1846 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x53); 1847 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x57); 1848 1849 reg = rsu_read_1(sc, R92S_AFE_MISC); 1850 rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN); 1851 rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN | 1852 R92S_AFE_MISC_MBEN | R92S_AFE_MISC_I32_EN); 1853 1854 /* Enable PLL. */ 1855 rsu_write_1(sc, R92S_LDOA15_CTRL, 1856 rsu_read_1(sc, R92S_LDOA15_CTRL) | R92S_LDA15_EN); 1857 1858 rsu_write_1(sc, R92S_LDOV12D_CTRL, 1859 rsu_read_1(sc, R92S_LDOV12D_CTRL) | R92S_LDV12_EN); 1860 1861 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1862 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) | 0x08); 1863 1864 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1865 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x20); 1866 1867 /* Support 64KB IMEM. */ 1868 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1869 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) & ~0x97); 1870 1871 /* Enable AFE clock. */ 1872 rsu_write_1(sc, R92S_AFE_XTAL_CTRL + 1, 1873 rsu_read_1(sc, R92S_AFE_XTAL_CTRL + 1) & ~0x04); 1874 /* Enable AFE PLL macro block. */ 1875 reg = rsu_read_1(sc, R92S_AFE_PLL_CTRL); 1876 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11); 1877 DELAY(500); 1878 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x51); 1879 DELAY(500); 1880 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11); 1881 DELAY(500); 1882 1883 /* Attach AFE PLL to MACTOP/BB. */ 1884 rsu_write_1(sc, R92S_SYS_ISO_CTRL, 1885 rsu_read_1(sc, R92S_SYS_ISO_CTRL) & ~0x11); 1886 1887 /* Switch to 40MHz clock. */ 1888 rsu_write_1(sc, R92S_SYS_CLKR, 0x00); 1889 /* Disable CPU clock and 80MHz SSC. */ 1890 rsu_write_1(sc, R92S_SYS_CLKR, 1891 rsu_read_1(sc, R92S_SYS_CLKR) | 0xa0); 1892 /* Enable MAC clock. */ 1893 rsu_write_2(sc, R92S_SYS_CLKR, 1894 rsu_read_2(sc, R92S_SYS_CLKR) | 1895 R92S_MAC_CLK_EN | R92S_SYS_CLK_EN); 1896 1897 rsu_write_1(sc, R92S_PMC_FSM, 0x02); 1898 1899 /* Enable digital core and IOREG R/W. */ 1900 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1901 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x08); 1902 1903 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1904 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x80); 1905 1906 /* Switch the control path to firmware. */ 1907 reg = rsu_read_2(sc, R92S_SYS_CLKR); 1908 reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL; 1909 rsu_write_2(sc, R92S_SYS_CLKR, reg); 1910 1911 rsu_write_2(sc, R92S_CR, 0x37fc); 1912 1913 /* Fix USB RX FIFO issue. */ 1914 rsu_write_1(sc, 0xfe5c, 1915 rsu_read_1(sc, 0xfe5c) | 0x80); 1916 1917 rsu_write_1(sc, R92S_SYS_CLKR, 1918 rsu_read_1(sc, R92S_SYS_CLKR) & ~R92S_SYS_CPU_CLKSEL); 1919 1920 rsu_write_1(sc, 0xfe1c, 0x80); 1921 1922 /* Make sure TxDMA is ready to download firmware. */ 1923 for (ntries = 0; ntries < 20; ntries++) { 1924 reg = rsu_read_1(sc, R92S_TCR); 1925 if ((reg & (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT)) == 1926 (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT)) 1927 break; 1928 DELAY(5); 1929 } 1930 if (ntries == 20) { 1931 /* Reset TxDMA. */ 1932 reg = rsu_read_1(sc, R92S_CR); 1933 rsu_write_1(sc, R92S_CR, reg & ~R92S_CR_TXDMA_EN); 1934 DELAY(2); 1935 rsu_write_1(sc, R92S_CR, reg | R92S_CR_TXDMA_EN); 1936 } 1937 } 1938 1939 void 1940 rsu_power_off(struct rsu_softc *sc) 1941 { 1942 /* Turn RF off. */ 1943 rsu_write_1(sc, R92S_RF_CTRL, 0x00); 1944 usbd_delay_ms(sc->sc_udev, 5); 1945 1946 /* Turn MAC off. */ 1947 /* Switch control path. */ 1948 rsu_write_1(sc, R92S_SYS_CLKR + 1, 0x38); 1949 /* Reset MACTOP. */ 1950 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 0x70); 1951 rsu_write_1(sc, R92S_PMC_FSM, 0x06); 1952 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 0, 0xf9); 1953 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 0xe8); 1954 1955 /* Disable AFE PLL. */ 1956 rsu_write_1(sc, R92S_AFE_PLL_CTRL, 0x00); 1957 /* Disable A15V. */ 1958 rsu_write_1(sc, R92S_LDOA15_CTRL, 0x54); 1959 /* Disable eFuse 1.2V. */ 1960 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 0x50); 1961 rsu_write_1(sc, R92S_LDOV12D_CTRL, 0x24); 1962 /* Enable AFE macro block's bandgap and Mbias. */ 1963 rsu_write_1(sc, R92S_AFE_MISC, 0x30); 1964 /* Disable 1.6V LDO. */ 1965 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x56); 1966 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x43); 1967 } 1968 1969 int 1970 rsu_fw_loadsection(struct rsu_softc *sc, uint8_t *buf, int len) 1971 { 1972 struct rsu_tx_data *data; 1973 struct r92s_tx_desc *txd; 1974 struct usbd_pipe *pipe; 1975 int mlen, error; 1976 1977 data = sc->fwcmd_data; 1978 pipe = sc->pipe[sc->qid2idx[RSU_QID_VO]]; 1979 txd = (struct r92s_tx_desc *)data->buf; 1980 while (len > 0) { 1981 memset(txd, 0, sizeof(*txd)); 1982 if (len <= RSU_TXBUFSZ - sizeof(*txd)) { 1983 /* Last chunk. */ 1984 txd->txdw0 |= htole32(R92S_TXDW0_LINIP); 1985 mlen = len; 1986 } else 1987 mlen = RSU_TXBUFSZ - sizeof(*txd); 1988 txd->txdw0 |= htole32(SM(R92S_TXDW0_PKTLEN, mlen)); 1989 memcpy(&txd[1], buf, mlen); 1990 1991 usbd_setup_xfer(data->xfer, pipe, NULL, data->buf, 1992 sizeof(*txd) + mlen, 1993 USBD_SHORT_XFER_OK | USBD_NO_COPY | USBD_SYNCHRONOUS, 1994 RSU_TX_TIMEOUT, NULL); 1995 error = usbd_transfer(data->xfer); 1996 if (error != 0) 1997 return (error); 1998 buf += mlen; 1999 len -= mlen; 2000 } 2001 return (0); 2002 } 2003 2004 int 2005 rsu_load_firmware(struct rsu_softc *sc) 2006 { 2007 struct ieee80211com *ic = &sc->sc_ic; 2008 struct r92s_fw_hdr *hdr; 2009 struct r92s_fw_priv *dmem; 2010 uint8_t *imem, *emem; 2011 int imemsz, ememsz; 2012 u_char *fw; 2013 size_t size; 2014 uint32_t reg; 2015 int ntries, error; 2016 2017 /* Read firmware image from the filesystem. */ 2018 if ((error = loadfirmware("rsu-rtl8712fw", &fw, &size)) != 0) { 2019 printf("%s: failed loadfirmware of file %s (error %d)\n", 2020 sc->sc_dev.dv_xname, "rsu-rtl8712fw", error); 2021 return (error); 2022 } 2023 if (size < sizeof(*hdr)) { 2024 printf("%s: firmware too short\n", sc->sc_dev.dv_xname); 2025 error = EINVAL; 2026 goto fail; 2027 } 2028 hdr = (struct r92s_fw_hdr *)fw; 2029 if (hdr->signature != htole16(0x8712) && 2030 hdr->signature != htole16(0x8192)) { 2031 printf("%s: invalid firmware signature 0x%x\n", 2032 sc->sc_dev.dv_xname, letoh16(hdr->signature)); 2033 error = EINVAL; 2034 goto fail; 2035 } 2036 DPRINTF(("FW V%d %02x-%02x %02x:%02x\n", letoh16(hdr->version), 2037 hdr->month, hdr->day, hdr->hour, hdr->minute)); 2038 2039 /* Make sure that driver and firmware are in sync. */ 2040 if (hdr->privsz != htole32(sizeof(*dmem))) { 2041 printf("%s: unsupported firmware image\n", 2042 sc->sc_dev.dv_xname); 2043 error = EINVAL; 2044 goto fail; 2045 } 2046 /* Get FW sections sizes. */ 2047 imemsz = letoh32(hdr->imemsz); 2048 ememsz = letoh32(hdr->sramsz); 2049 /* Check that all FW sections fit in image. */ 2050 if (size < sizeof(*hdr) + imemsz + ememsz) { 2051 printf("%s: firmware too short\n", sc->sc_dev.dv_xname); 2052 error = EINVAL; 2053 goto fail; 2054 } 2055 imem = (uint8_t *)&hdr[1]; 2056 emem = imem + imemsz; 2057 2058 /* Load IMEM section. */ 2059 error = rsu_fw_loadsection(sc, imem, imemsz); 2060 if (error != 0) { 2061 printf("%s: could not load firmware section %s\n", 2062 sc->sc_dev.dv_xname, "IMEM"); 2063 goto fail; 2064 } 2065 /* Wait for load to complete. */ 2066 for (ntries = 0; ntries < 10; ntries++) { 2067 reg = rsu_read_2(sc, R92S_TCR); 2068 if (reg & R92S_TCR_IMEM_CODE_DONE) 2069 break; 2070 DELAY(10); 2071 } 2072 if (ntries == 10 || !(reg & R92S_TCR_IMEM_CHK_RPT)) { 2073 printf("%s: timeout waiting for %s transfer\n", 2074 sc->sc_dev.dv_xname, "IMEM"); 2075 error = ETIMEDOUT; 2076 goto fail; 2077 } 2078 2079 /* Load EMEM section. */ 2080 error = rsu_fw_loadsection(sc, emem, ememsz); 2081 if (error != 0) { 2082 printf("%s: could not load firmware section %s\n", 2083 sc->sc_dev.dv_xname, "EMEM"); 2084 goto fail; 2085 } 2086 /* Wait for load to complete. */ 2087 for (ntries = 0; ntries < 10; ntries++) { 2088 reg = rsu_read_2(sc, R92S_TCR); 2089 if (reg & R92S_TCR_EMEM_CODE_DONE) 2090 break; 2091 DELAY(10); 2092 } 2093 if (ntries == 10 || !(reg & R92S_TCR_EMEM_CHK_RPT)) { 2094 printf("%s: timeout waiting for %s transfer\n", 2095 sc->sc_dev.dv_xname, "EMEM"); 2096 error = ETIMEDOUT; 2097 goto fail; 2098 } 2099 2100 /* Enable CPU. */ 2101 rsu_write_1(sc, R92S_SYS_CLKR, 2102 rsu_read_1(sc, R92S_SYS_CLKR) | R92S_SYS_CPU_CLKSEL); 2103 if (!(rsu_read_1(sc, R92S_SYS_CLKR) & R92S_SYS_CPU_CLKSEL)) { 2104 printf("%s: could not enable system clock\n", 2105 sc->sc_dev.dv_xname); 2106 error = EIO; 2107 goto fail; 2108 } 2109 rsu_write_2(sc, R92S_SYS_FUNC_EN, 2110 rsu_read_2(sc, R92S_SYS_FUNC_EN) | R92S_FEN_CPUEN); 2111 if (!(rsu_read_2(sc, R92S_SYS_FUNC_EN) & R92S_FEN_CPUEN)) { 2112 printf("%s: could not enable microcontroller\n", 2113 sc->sc_dev.dv_xname); 2114 error = EIO; 2115 goto fail; 2116 } 2117 /* Wait for CPU to initialize. */ 2118 for (ntries = 0; ntries < 100; ntries++) { 2119 if (rsu_read_2(sc, R92S_TCR) & R92S_TCR_IMEM_RDY) 2120 break; 2121 DELAY(1000); 2122 } 2123 if (ntries == 100) { 2124 printf("%s: timeout waiting for microcontroller\n", 2125 sc->sc_dev.dv_xname); 2126 error = ETIMEDOUT; 2127 goto fail; 2128 } 2129 2130 /* Update DMEM section before loading. */ 2131 dmem = &hdr->priv; 2132 memset(dmem, 0, sizeof(*dmem)); 2133 dmem->hci_sel = R92S_HCI_SEL_USB | R92S_HCI_SEL_8172; 2134 dmem->nendpoints = sc->npipes; 2135 dmem->rf_config = 0x12; /* 1T2R */ 2136 dmem->vcs_type = R92S_VCS_TYPE_AUTO; 2137 dmem->vcs_mode = R92S_VCS_MODE_RTS_CTS; 2138 dmem->bw40_en = (ic->ic_htcaps & IEEE80211_HTCAP_CBW20_40) != 0; 2139 dmem->turbo_mode = 1; 2140 /* Load DMEM section. */ 2141 error = rsu_fw_loadsection(sc, (uint8_t *)dmem, sizeof(*dmem)); 2142 if (error != 0) { 2143 printf("%s: could not load firmware section %s\n", 2144 sc->sc_dev.dv_xname, "DMEM"); 2145 goto fail; 2146 } 2147 /* Wait for load to complete. */ 2148 for (ntries = 0; ntries < 100; ntries++) { 2149 if (rsu_read_2(sc, R92S_TCR) & R92S_TCR_DMEM_CODE_DONE) 2150 break; 2151 DELAY(1000); 2152 } 2153 if (ntries == 100) { 2154 printf("%s: timeout waiting for %s transfer\n", 2155 sc->sc_dev.dv_xname, "DMEM"); 2156 error = ETIMEDOUT; 2157 goto fail; 2158 } 2159 /* Wait for firmware readiness. */ 2160 for (ntries = 0; ntries < 60; ntries++) { 2161 if (!(rsu_read_2(sc, R92S_TCR) & R92S_TCR_FWRDY)) 2162 break; 2163 DELAY(1000); 2164 } 2165 if (ntries == 60) { 2166 printf("%s: timeout waiting for firmware readiness\n", 2167 sc->sc_dev.dv_xname); 2168 error = ETIMEDOUT; 2169 goto fail; 2170 } 2171 fail: 2172 free(fw, M_DEVBUF, 0); 2173 return (error); 2174 } 2175 2176 int 2177 rsu_init(struct ifnet *ifp) 2178 { 2179 struct rsu_softc *sc = ifp->if_softc; 2180 struct ieee80211com *ic = &sc->sc_ic; 2181 struct r92s_set_pwr_mode cmd; 2182 struct rsu_rx_data *data; 2183 int i, error; 2184 2185 /* Init host async commands ring. */ 2186 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2187 2188 /* Allocate Tx/Rx buffers. */ 2189 error = rsu_alloc_rx_list(sc); 2190 if (error != 0) { 2191 printf("%s: could not allocate Rx buffers\n", 2192 sc->sc_dev.dv_xname); 2193 goto fail; 2194 } 2195 error = rsu_alloc_tx_list(sc); 2196 if (error != 0) { 2197 printf("%s: could not allocate Tx buffers\n", 2198 sc->sc_dev.dv_xname); 2199 goto fail; 2200 } 2201 /* Reserve one Tx buffer for firmware commands. */ 2202 sc->fwcmd_data = TAILQ_FIRST(&sc->tx_free_list); 2203 TAILQ_REMOVE(&sc->tx_free_list, sc->fwcmd_data, next); 2204 2205 /* Power on adapter. */ 2206 if (sc->cut == 1) 2207 rsu_power_on_acut(sc); 2208 else 2209 rsu_power_on_bcut(sc); 2210 /* Load firmware. */ 2211 error = rsu_load_firmware(sc); 2212 if (error != 0) 2213 goto fail; 2214 2215 /* Enable Rx TCP checksum offload. */ 2216 rsu_write_4(sc, R92S_RCR, 2217 rsu_read_4(sc, R92S_RCR) | 0x04000000); 2218 /* Append PHY status. */ 2219 rsu_write_4(sc, R92S_RCR, 2220 rsu_read_4(sc, R92S_RCR) | 0x02000000); 2221 2222 rsu_write_4(sc, R92S_CR, 2223 rsu_read_4(sc, R92S_CR) & ~0xff000000); 2224 2225 /* Use 128 bytes pages. */ 2226 rsu_write_1(sc, 0x00b5, 2227 rsu_read_1(sc, 0x00b5) | 0x01); 2228 /* Enable USB Rx aggregation. */ 2229 rsu_write_1(sc, 0x00bd, 2230 rsu_read_1(sc, 0x00bd) | 0x80); 2231 /* Set USB Rx aggregation threshold. */ 2232 rsu_write_1(sc, 0x00d9, 0x01); 2233 /* Set USB Rx aggregation timeout (1.7ms/4). */ 2234 rsu_write_1(sc, 0xfe5b, 0x04); 2235 /* Fix USB Rx FIFO issue. */ 2236 rsu_write_1(sc, 0xfe5c, 2237 rsu_read_1(sc, 0xfe5c) | 0x80); 2238 2239 /* Set MAC address. */ 2240 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2241 rsu_write_region_1(sc, R92S_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 2242 2243 /* Queue Rx xfers (XXX C2H pipe for 11-pipe configurations?) */ 2244 for (i = 0; i < RSU_RX_LIST_COUNT; i++) { 2245 data = &sc->rx_data[i]; 2246 2247 data->pipe = sc->pipe[sc->qid2idx[RSU_QID_RXOFF]]; 2248 usbd_setup_xfer(data->xfer, data->pipe, data, data->buf, 2249 RSU_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2250 USBD_NO_TIMEOUT, rsu_rxeof); 2251 error = usbd_transfer(data->xfer); 2252 if (error != 0 && error != USBD_IN_PROGRESS) 2253 goto fail; 2254 } 2255 2256 /* NB: it really takes that long for firmware to boot. */ 2257 usbd_delay_ms(sc->sc_udev, 1500); 2258 2259 DPRINTF(("setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 2260 error = rsu_fw_cmd(sc, R92S_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2261 IEEE80211_ADDR_LEN); 2262 if (error != 0) { 2263 printf("%s: could not set MAC address\n", sc->sc_dev.dv_xname); 2264 goto fail; 2265 } 2266 2267 rsu_write_1(sc, R92S_USB_HRPWM, 2268 R92S_USB_HRPWM_PS_ST_ACTIVE | R92S_USB_HRPWM_PS_ALL_ON); 2269 2270 memset(&cmd, 0, sizeof(cmd)); 2271 cmd.mode = R92S_PS_MODE_ACTIVE; 2272 DPRINTF(("setting ps mode to %d\n", cmd.mode)); 2273 error = rsu_fw_cmd(sc, R92S_CMD_SET_PWR_MODE, &cmd, sizeof(cmd)); 2274 if (error != 0) { 2275 printf("%s: could not set PS mode\n", sc->sc_dev.dv_xname); 2276 goto fail; 2277 } 2278 2279 if (ic->ic_htcaps & IEEE80211_HTCAP_CBW20_40) { 2280 /* Enable 40MHz mode. */ 2281 error = rsu_fw_iocmd(sc, 2282 SM(R92S_IOCMD_CLASS, 0xf4) | 2283 SM(R92S_IOCMD_INDEX, 0x00) | 2284 SM(R92S_IOCMD_VALUE, 0x0007)); 2285 if (error != 0) { 2286 printf("%s: could not enable 40MHz mode\n", 2287 sc->sc_dev.dv_xname); 2288 goto fail; 2289 } 2290 } 2291 2292 /* Set default channel. */ 2293 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2294 2295 /* We're ready to go. */ 2296 ifp->if_flags &= ~IFF_OACTIVE; 2297 ifp->if_flags |= IFF_RUNNING; 2298 2299 #ifdef notyet 2300 if (ic->ic_flags & IEEE80211_F_WEPON) { 2301 /* Install WEP keys. */ 2302 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2303 rsu_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2304 rsu_wait_async(sc); 2305 } 2306 #endif 2307 2308 sc->scan_pass = 0; 2309 ieee80211_begin_scan(ifp); 2310 return (0); 2311 fail: 2312 rsu_stop(ifp); 2313 return (error); 2314 } 2315 2316 void 2317 rsu_stop(struct ifnet *ifp) 2318 { 2319 struct rsu_softc *sc = ifp->if_softc; 2320 struct ieee80211com *ic = &sc->sc_ic; 2321 int i, s; 2322 2323 sc->sc_tx_timer = 0; 2324 ifp->if_timer = 0; 2325 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2326 2327 /* In case we were scanning, release the scan "lock". */ 2328 ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; 2329 2330 s = splusb(); 2331 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2332 /* Wait for all async commands to complete. */ 2333 rsu_wait_async(sc); 2334 splx(s); 2335 2336 timeout_del(&sc->calib_to); 2337 2338 /* Power off adapter. */ 2339 rsu_power_off(sc); 2340 2341 /* Abort Tx/Rx. */ 2342 for (i = 0; i < sc->npipes; i++) 2343 usbd_abort_pipe(sc->pipe[i]); 2344 2345 /* Free Tx/Rx buffers. */ 2346 rsu_free_tx_list(sc); 2347 rsu_free_rx_list(sc); 2348 } 2349