1 /* $OpenBSD: if_urtwn.c,v 1.85 2019/11/16 14:08:31 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU/ 23 * RTL8192EU. 24 */ 25 26 #include "bpfilter.h" 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_amrr.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdi_util.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/r92creg.h> 63 #include <dev/ic/rtwnvar.h> 64 65 /* Maximum number of output pipes is 3. */ 66 #define R92C_MAX_EPOUT 3 67 68 #define R92C_HQ_NPAGES 12 69 #define R92C_LQ_NPAGES 2 70 #define R92C_NQ_NPAGES 2 71 #define R92C_TXPKTBUF_COUNT 256 72 #define R92C_TX_PAGE_COUNT 248 73 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 74 #define R92C_MAX_RX_DMA_SIZE 0x2800 75 76 #define R88E_HQ_NPAGES 0 77 #define R88E_LQ_NPAGES 9 78 #define R88E_NQ_NPAGES 0 79 #define R88E_TXPKTBUF_COUNT 177 80 #define R88E_TX_PAGE_COUNT 168 81 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 82 #define R88E_MAX_RX_DMA_SIZE 0x2400 83 84 #define R92E_HQ_NPAGES 16 85 #define R92E_LQ_NPAGES 16 86 #define R92E_NQ_NPAGES 16 87 #define R92E_TX_PAGE_COUNT 248 88 #define R92E_TX_PAGE_BOUNDARY (R92E_TX_PAGE_COUNT + 1) 89 #define R92E_MAX_RX_DMA_SIZE 0x3fc0 90 91 #define R92C_TXDESC_SUMSIZE 32 92 #define R92C_TXDESC_SUMOFFSET 14 93 94 /* USB Requests. */ 95 #define R92C_REQ_REGS 0x05 96 97 /* 98 * Driver definitions. 99 */ 100 #define URTWN_RX_LIST_COUNT 1 101 #define URTWN_TX_LIST_COUNT 8 102 #define URTWN_HOST_CMD_RING_COUNT 32 103 104 #define URTWN_RXBUFSZ (16 * 1024) 105 #define URTWN_TXBUFSZ (sizeof(struct r92e_tx_desc_usb) + IEEE80211_MAX_LEN) 106 107 #define URTWN_RIDX_COUNT 28 108 109 #define URTWN_TX_TIMEOUT 5000 /* ms */ 110 111 #define URTWN_LED_LINK 0 112 #define URTWN_LED_DATA 1 113 114 struct urtwn_rx_radiotap_header { 115 struct ieee80211_radiotap_header wr_ihdr; 116 uint8_t wr_flags; 117 uint8_t wr_rate; 118 uint16_t wr_chan_freq; 119 uint16_t wr_chan_flags; 120 uint8_t wr_dbm_antsignal; 121 } __packed; 122 123 #define URTWN_RX_RADIOTAP_PRESENT \ 124 (1 << IEEE80211_RADIOTAP_FLAGS | \ 125 1 << IEEE80211_RADIOTAP_RATE | \ 126 1 << IEEE80211_RADIOTAP_CHANNEL | \ 127 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 128 129 struct urtwn_tx_radiotap_header { 130 struct ieee80211_radiotap_header wt_ihdr; 131 uint8_t wt_flags; 132 uint16_t wt_chan_freq; 133 uint16_t wt_chan_flags; 134 } __packed; 135 136 #define URTWN_TX_RADIOTAP_PRESENT \ 137 (1 << IEEE80211_RADIOTAP_FLAGS | \ 138 1 << IEEE80211_RADIOTAP_CHANNEL) 139 140 struct urtwn_softc; 141 142 struct urtwn_rx_data { 143 struct urtwn_softc *sc; 144 struct usbd_xfer *xfer; 145 uint8_t *buf; 146 }; 147 148 struct urtwn_tx_data { 149 struct urtwn_softc *sc; 150 struct usbd_pipe *pipe; 151 struct usbd_xfer *xfer; 152 uint8_t *buf; 153 TAILQ_ENTRY(urtwn_tx_data) next; 154 }; 155 156 struct urtwn_host_cmd { 157 void (*cb)(struct urtwn_softc *, void *); 158 uint8_t data[256]; 159 }; 160 161 struct urtwn_cmd_newstate { 162 enum ieee80211_state state; 163 int arg; 164 }; 165 166 struct urtwn_cmd_key { 167 struct ieee80211_key key; 168 struct ieee80211_node *ni; 169 }; 170 171 struct urtwn_host_cmd_ring { 172 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; 173 int cur; 174 int next; 175 int queued; 176 }; 177 178 struct urtwn_softc { 179 struct device sc_dev; 180 struct rtwn_softc sc_sc; 181 182 struct usbd_device *sc_udev; 183 struct usbd_interface *sc_iface; 184 struct usb_task sc_task; 185 186 struct timeout scan_to; 187 struct timeout calib_to; 188 189 int ntx; 190 struct usbd_pipe *rx_pipe; 191 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT]; 192 int ac2idx[EDCA_NUM_AC]; 193 194 struct urtwn_host_cmd_ring cmdq; 195 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; 196 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; 197 TAILQ_HEAD(, urtwn_tx_data) tx_free_list; 198 199 struct ieee80211_amrr amrr; 200 struct ieee80211_amrr_node amn; 201 202 #if NBPFILTER > 0 203 caddr_t sc_drvbpf; 204 205 union { 206 struct urtwn_rx_radiotap_header th; 207 uint8_t pad[64]; 208 } sc_rxtapu; 209 #define sc_rxtap sc_rxtapu.th 210 int sc_rxtap_len; 211 212 union { 213 struct urtwn_tx_radiotap_header th; 214 uint8_t pad[64]; 215 } sc_txtapu; 216 #define sc_txtap sc_txtapu.th 217 int sc_txtap_len; 218 #endif 219 }; 220 221 #ifdef URTWN_DEBUG 222 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0) 223 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0) 224 int urtwn_debug = 4; 225 #else 226 #define DPRINTF(x) 227 #define DPRINTFN(n, x) 228 #endif 229 230 /* 231 * Various supported device vendors/products. 232 */ 233 #define URTWN_DEV(v, p, f) \ 234 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, (f) | RTWN_CHIP_USB } 235 #define URTWN_DEV_8192CU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92C | RTWN_CHIP_88C) 236 #define URTWN_DEV_8188EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_88E) 237 #define URTWN_DEV_8192EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92E) 238 static const struct urtwn_type { 239 struct usb_devno dev; 240 uint32_t chip; 241 } urtwn_devs[] = { 242 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 243 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 244 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_2), 245 URTWN_DEV_8192CU(ABOCOM, RTL8192CU), 246 URTWN_DEV_8192CU(ASUS, RTL8192CU), 247 URTWN_DEV_8192CU(ASUS, RTL8192CU_2), 248 URTWN_DEV_8192CU(ASUS, RTL8192CU_3), 249 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_1), 250 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_2), 251 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CU), 252 URTWN_DEV_8192CU(BELKIN, F7D2102), 253 URTWN_DEV_8192CU(BELKIN, F9L1004V1), 254 URTWN_DEV_8192CU(BELKIN, RTL8188CU), 255 URTWN_DEV_8192CU(BELKIN, RTL8188CUS), 256 URTWN_DEV_8192CU(BELKIN, RTL8192CU), 257 URTWN_DEV_8192CU(BELKIN, RTL8192CU_1), 258 URTWN_DEV_8192CU(BELKIN, RTL8192CU_2), 259 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_1), 260 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_2), 261 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_3), 262 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_4), 263 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_5), 264 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_6), 265 URTWN_DEV_8192CU(COMPARE, RTL8192CU), 266 URTWN_DEV_8192CU(COREGA, RTL8192CU), 267 URTWN_DEV_8192CU(DLINK, DWA131B), 268 URTWN_DEV_8192CU(DLINK, RTL8188CU), 269 URTWN_DEV_8192CU(DLINK, RTL8192CU_1), 270 URTWN_DEV_8192CU(DLINK, RTL8192CU_2), 271 URTWN_DEV_8192CU(DLINK, RTL8192CU_3), 272 URTWN_DEV_8192CU(DLINK, RTL8192CU_4), 273 URTWN_DEV_8192CU(EDIMAX, EW7811UN), 274 URTWN_DEV_8192CU(EDIMAX, RTL8192CU), 275 URTWN_DEV_8192CU(FEIXUN, RTL8188CU), 276 URTWN_DEV_8192CU(FEIXUN, RTL8192CU), 277 URTWN_DEV_8192CU(GUILLEMOT, HWNUP150), 278 URTWN_DEV_8192CU(GUILLEMOT, RTL8192CU), 279 URTWN_DEV_8192CU(HAWKING, RTL8192CU), 280 URTWN_DEV_8192CU(HAWKING, RTL8192CU_2), 281 URTWN_DEV_8192CU(HP3, RTL8188CU), 282 URTWN_DEV_8192CU(IODATA, WNG150UM), 283 URTWN_DEV_8192CU(IODATA, RTL8192CU), 284 URTWN_DEV_8192CU(NETGEAR, N300MA), 285 URTWN_DEV_8192CU(NETGEAR, WNA1000M), 286 URTWN_DEV_8192CU(NETGEAR, WNA1000Mv2), 287 URTWN_DEV_8192CU(NETGEAR, RTL8192CU), 288 URTWN_DEV_8192CU(NETGEAR4, RTL8188CU), 289 URTWN_DEV_8192CU(NETWEEN, RTL8192CU), 290 URTWN_DEV_8192CU(NOVATECH, RTL8188CU), 291 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_1), 292 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_2), 293 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_3), 294 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_4), 295 URTWN_DEV_8192CU(PLANEX2, RTL8188CUS), 296 URTWN_DEV_8192CU(PLANEX2, RTL8192CU), 297 URTWN_DEV_8192CU(REALTEK, RTL8188CE_0), 298 URTWN_DEV_8192CU(REALTEK, RTL8188CE_1), 299 URTWN_DEV_8192CU(REALTEK, RTL8188CTV), 300 URTWN_DEV_8192CU(REALTEK, RTL8188CU_0), 301 URTWN_DEV_8192CU(REALTEK, RTL8188CU_1), 302 URTWN_DEV_8192CU(REALTEK, RTL8188CU_2), 303 URTWN_DEV_8192CU(REALTEK, RTL8188CU_3), 304 URTWN_DEV_8192CU(REALTEK, RTL8188CU_4), 305 URTWN_DEV_8192CU(REALTEK, RTL8188CU_5), 306 URTWN_DEV_8192CU(REALTEK, RTL8188CU_COMBO), 307 URTWN_DEV_8192CU(REALTEK, RTL8188CUS), 308 URTWN_DEV_8192CU(REALTEK, RTL8188RU), 309 URTWN_DEV_8192CU(REALTEK, RTL8188RU_2), 310 URTWN_DEV_8192CU(REALTEK, RTL8188RU_3), 311 URTWN_DEV_8192CU(REALTEK, RTL8191CU), 312 URTWN_DEV_8192CU(REALTEK, RTL8192CE), 313 URTWN_DEV_8192CU(REALTEK, RTL8192CE_VAU), 314 URTWN_DEV_8192CU(REALTEK, RTL8192CU), 315 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU), 316 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU_2), 317 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU), 318 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU_2), 319 URTWN_DEV_8192CU(SITECOMEU, WLA2100V2), 320 URTWN_DEV_8192CU(TPLINK, RTL8192CU), 321 URTWN_DEV_8192CU(TRENDNET, RTL8188CU), 322 URTWN_DEV_8192CU(TRENDNET, RTL8192CU), 323 URTWN_DEV_8192CU(ZYXEL, RTL8192CU), 324 /* URTWN_RTL8188E */ 325 URTWN_DEV_8188EU(ABOCOM, RTL8188EU), 326 URTWN_DEV_8188EU(DLINK, DWA123D1), 327 URTWN_DEV_8188EU(DLINK, DWA125D1), 328 URTWN_DEV_8188EU(ELECOM, WDC150SU2M), 329 URTWN_DEV_8188EU(REALTEK, RTL8188ETV), 330 URTWN_DEV_8188EU(REALTEK, RTL8188EU), 331 URTWN_DEV_8188EU(TPLINK, RTL8188EUS), 332 /* URTWN_RTL8192EU */ 333 URTWN_DEV_8192EU(DLINK, DWA131E1), 334 URTWN_DEV_8192EU(REALTEK, RTL8192EU), 335 URTWN_DEV_8192EU(TPLINK, RTL8192EU) 336 }; 337 338 #define urtwn_lookup(v, p) \ 339 ((const struct urtwn_type *)usb_lookup(urtwn_devs, v, p)) 340 341 int urtwn_match(struct device *, void *, void *); 342 void urtwn_attach(struct device *, struct device *, void *); 343 int urtwn_detach(struct device *, int); 344 int urtwn_open_pipes(struct urtwn_softc *); 345 void urtwn_close_pipes(struct urtwn_softc *); 346 int urtwn_alloc_rx_list(struct urtwn_softc *); 347 void urtwn_free_rx_list(struct urtwn_softc *); 348 int urtwn_alloc_tx_list(struct urtwn_softc *); 349 void urtwn_free_tx_list(struct urtwn_softc *); 350 void urtwn_task(void *); 351 void urtwn_do_async(struct urtwn_softc *, 352 void (*)(struct urtwn_softc *, void *), void *, int); 353 void urtwn_wait_async(void *); 354 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 355 int); 356 void urtwn_write_1(void *, uint16_t, uint8_t); 357 void urtwn_write_2(void *, uint16_t, uint16_t); 358 void urtwn_write_4(void *, uint16_t, uint32_t); 359 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 360 int); 361 uint8_t urtwn_read_1(void *, uint16_t); 362 uint16_t urtwn_read_2(void *, uint16_t); 363 uint32_t urtwn_read_4(void *, uint16_t); 364 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 365 void urtwn_calib_to(void *); 366 void urtwn_calib_cb(struct urtwn_softc *, void *); 367 void urtwn_scan_to(void *); 368 void urtwn_next_scan(void *); 369 void urtwn_cancel_scan(void *); 370 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 371 int); 372 void urtwn_newstate_cb(struct urtwn_softc *, void *); 373 void urtwn_updateslot(struct ieee80211com *); 374 void urtwn_updateslot_cb(struct urtwn_softc *, void *); 375 void urtwn_updateedca(struct ieee80211com *); 376 void urtwn_updateedca_cb(struct urtwn_softc *, void *); 377 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *, 378 struct ieee80211_key *); 379 void urtwn_set_key_cb(struct urtwn_softc *, void *); 380 void urtwn_delete_key(struct ieee80211com *, 381 struct ieee80211_node *, struct ieee80211_key *); 382 void urtwn_delete_key_cb(struct urtwn_softc *, void *); 383 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 384 struct mbuf_list *); 385 void urtwn_rxeof(struct usbd_xfer *, void *, 386 usbd_status); 387 void urtwn_txeof(struct usbd_xfer *, void *, 388 usbd_status); 389 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *); 390 int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 391 int urtwn_power_on(void *); 392 int urtwn_alloc_buffers(void *); 393 int urtwn_r92c_power_on(struct urtwn_softc *); 394 int urtwn_r92e_power_on(struct urtwn_softc *); 395 int urtwn_r88e_power_on(struct urtwn_softc *); 396 int urtwn_llt_init(struct urtwn_softc *, int); 397 int urtwn_fw_loadpage(void *, int, uint8_t *, int); 398 int urtwn_load_firmware(void *, u_char **, size_t *); 399 int urtwn_dma_init(void *); 400 void urtwn_aggr_init(void *); 401 void urtwn_mac_init(void *); 402 void urtwn_bb_init(void *); 403 void urtwn_burstlen_init(struct urtwn_softc *); 404 int urtwn_init(void *); 405 void urtwn_stop(void *); 406 int urtwn_is_oactive(void *); 407 void urtwn_next_calib(void *); 408 void urtwn_cancel_calib(void *); 409 410 /* Aliases. */ 411 #define urtwn_bb_write urtwn_write_4 412 #define urtwn_bb_read urtwn_read_4 413 414 struct cfdriver urtwn_cd = { 415 NULL, "urtwn", DV_IFNET 416 }; 417 418 const struct cfattach urtwn_ca = { 419 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach 420 }; 421 422 int 423 urtwn_match(struct device *parent, void *match, void *aux) 424 { 425 struct usb_attach_arg *uaa = aux; 426 427 if (uaa->iface == NULL || uaa->configno != 1) 428 return (UMATCH_NONE); 429 430 return ((urtwn_lookup(uaa->vendor, uaa->product) != NULL) ? 431 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 432 } 433 434 void 435 urtwn_attach(struct device *parent, struct device *self, void *aux) 436 { 437 struct urtwn_softc *sc = (struct urtwn_softc *)self; 438 struct usb_attach_arg *uaa = aux; 439 struct ifnet *ifp; 440 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 441 442 sc->sc_udev = uaa->device; 443 sc->sc_iface = uaa->iface; 444 445 sc->sc_sc.chip = urtwn_lookup(uaa->vendor, uaa->product)->chip; 446 447 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC); 448 timeout_set(&sc->scan_to, urtwn_scan_to, sc); 449 timeout_set(&sc->calib_to, urtwn_calib_to, sc); 450 if (urtwn_open_pipes(sc) != 0) 451 return; 452 453 sc->amrr.amrr_min_success_threshold = 1; 454 sc->amrr.amrr_max_success_threshold = 10; 455 456 /* Attach the bus-agnostic driver. */ 457 sc->sc_sc.sc_ops.cookie = sc; 458 sc->sc_sc.sc_ops.write_1 = urtwn_write_1; 459 sc->sc_sc.sc_ops.write_2 = urtwn_write_2; 460 sc->sc_sc.sc_ops.write_4 = urtwn_write_4; 461 sc->sc_sc.sc_ops.read_1 = urtwn_read_1; 462 sc->sc_sc.sc_ops.read_2 = urtwn_read_2; 463 sc->sc_sc.sc_ops.read_4 = urtwn_read_4; 464 sc->sc_sc.sc_ops.tx = urtwn_tx; 465 sc->sc_sc.sc_ops.power_on = urtwn_power_on; 466 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init; 467 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage; 468 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware; 469 sc->sc_sc.sc_ops.aggr_init = urtwn_aggr_init; 470 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init; 471 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init; 472 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers; 473 sc->sc_sc.sc_ops.init = urtwn_init; 474 sc->sc_sc.sc_ops.stop = urtwn_stop; 475 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive; 476 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib; 477 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib; 478 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan; 479 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan; 480 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async; 481 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc) != 0) { 482 urtwn_close_pipes(sc); 483 return; 484 } 485 486 /* ifp is now valid */ 487 ifp = &sc->sc_sc.sc_ic.ic_if; 488 ifp->if_ioctl = urtwn_ioctl; 489 490 ic->ic_updateslot = urtwn_updateslot; 491 ic->ic_updateedca = urtwn_updateedca; 492 #ifdef notyet 493 ic->ic_set_key = urtwn_set_key; 494 ic->ic_delete_key = urtwn_delete_key; 495 #endif 496 /* Override state transition machine. */ 497 ic->ic_newstate = urtwn_newstate; 498 499 #if NBPFILTER > 0 500 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 501 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 502 503 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 504 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 505 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 506 507 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 508 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 509 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 510 #endif 511 } 512 513 int 514 urtwn_detach(struct device *self, int flags) 515 { 516 struct urtwn_softc *sc = (struct urtwn_softc *)self; 517 int s; 518 519 s = splusb(); 520 521 if (timeout_initialized(&sc->scan_to)) 522 timeout_del(&sc->scan_to); 523 if (timeout_initialized(&sc->calib_to)) 524 timeout_del(&sc->calib_to); 525 526 /* Wait for all async commands to complete. */ 527 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 528 529 usbd_ref_wait(sc->sc_udev); 530 531 rtwn_detach(&sc->sc_sc, flags); 532 533 /* Abort and close Tx/Rx pipes. */ 534 urtwn_close_pipes(sc); 535 536 /* Free Tx/Rx buffers. */ 537 urtwn_free_tx_list(sc); 538 urtwn_free_rx_list(sc); 539 splx(s); 540 541 return (0); 542 } 543 544 int 545 urtwn_open_pipes(struct urtwn_softc *sc) 546 { 547 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 548 uint8_t epaddr[R92C_MAX_EPOUT] = { 0, 0, 0 }; 549 uint8_t rx_no; 550 usb_interface_descriptor_t *id; 551 usb_endpoint_descriptor_t *ed; 552 int i, error, nrx = 0; 553 554 /* Find all bulk endpoints. */ 555 id = usbd_get_interface_descriptor(sc->sc_iface); 556 for (i = 0; i < id->bNumEndpoints; i++) { 557 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 558 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 559 continue; 560 561 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 562 rx_no = ed->bEndpointAddress; 563 nrx++; 564 } else { 565 if (sc->ntx < R92C_MAX_EPOUT) 566 epaddr[sc->ntx] = ed->bEndpointAddress; 567 sc->ntx++; 568 } 569 } 570 if (nrx == 0) { 571 printf("%s: %d: invalid number of Rx bulk pipes\n", 572 sc->sc_dev.dv_xname, nrx); 573 return (EIO); 574 } 575 DPRINTF(("found %d bulk-out pipes\n", sc->ntx)); 576 if (sc->ntx == 0 || sc->ntx > R92C_MAX_EPOUT) { 577 printf("%s: %d: invalid number of Tx bulk pipes\n", 578 sc->sc_dev.dv_xname, sc->ntx); 579 return (EIO); 580 } 581 582 /* Open bulk-in pipe. */ 583 error = usbd_open_pipe(sc->sc_iface, rx_no, 0, &sc->rx_pipe); 584 if (error != 0) { 585 printf("%s: could not open Rx bulk pipe\n", 586 sc->sc_dev.dv_xname); 587 goto fail; 588 } 589 590 /* Open bulk-out pipes (up to 3). */ 591 for (i = 0; i < sc->ntx; i++) { 592 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, 593 &sc->tx_pipe[i]); 594 if (error != 0) { 595 printf("%s: could not open Tx bulk pipe 0x%02x\n", 596 sc->sc_dev.dv_xname, epaddr[i]); 597 goto fail; 598 } 599 } 600 601 /* Map 802.11 access categories to USB pipes. */ 602 sc->ac2idx[EDCA_AC_BK] = 603 sc->ac2idx[EDCA_AC_BE] = (sc->ntx == 3) ? 2 : ((sc->ntx == 2) ? 1 : 0); 604 sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0; 605 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */ 606 607 if (error != 0) 608 fail: urtwn_close_pipes(sc); 609 return (error); 610 } 611 612 void 613 urtwn_close_pipes(struct urtwn_softc *sc) 614 { 615 int i; 616 617 /* Close Rx pipe. */ 618 if (sc->rx_pipe != NULL) { 619 usbd_abort_pipe(sc->rx_pipe); 620 usbd_close_pipe(sc->rx_pipe); 621 } 622 /* Close Tx pipes. */ 623 for (i = 0; i < R92C_MAX_EPOUT; i++) { 624 if (sc->tx_pipe[i] == NULL) 625 continue; 626 usbd_abort_pipe(sc->tx_pipe[i]); 627 usbd_close_pipe(sc->tx_pipe[i]); 628 } 629 } 630 631 int 632 urtwn_alloc_rx_list(struct urtwn_softc *sc) 633 { 634 struct urtwn_rx_data *data; 635 int i, error = 0; 636 637 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 638 data = &sc->rx_data[i]; 639 640 data->sc = sc; /* Backpointer for callbacks. */ 641 642 data->xfer = usbd_alloc_xfer(sc->sc_udev); 643 if (data->xfer == NULL) { 644 printf("%s: could not allocate xfer\n", 645 sc->sc_dev.dv_xname); 646 error = ENOMEM; 647 break; 648 } 649 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 650 if (data->buf == NULL) { 651 printf("%s: could not allocate xfer buffer\n", 652 sc->sc_dev.dv_xname); 653 error = ENOMEM; 654 break; 655 } 656 } 657 if (error != 0) 658 urtwn_free_rx_list(sc); 659 return (error); 660 } 661 662 void 663 urtwn_free_rx_list(struct urtwn_softc *sc) 664 { 665 int i; 666 667 /* NB: Caller must abort pipe first. */ 668 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 669 if (sc->rx_data[i].xfer != NULL) 670 usbd_free_xfer(sc->rx_data[i].xfer); 671 sc->rx_data[i].xfer = NULL; 672 } 673 } 674 675 int 676 urtwn_alloc_tx_list(struct urtwn_softc *sc) 677 { 678 struct urtwn_tx_data *data; 679 int i, error = 0; 680 681 TAILQ_INIT(&sc->tx_free_list); 682 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 683 data = &sc->tx_data[i]; 684 685 data->sc = sc; /* Backpointer for callbacks. */ 686 687 data->xfer = usbd_alloc_xfer(sc->sc_udev); 688 if (data->xfer == NULL) { 689 printf("%s: could not allocate xfer\n", 690 sc->sc_dev.dv_xname); 691 error = ENOMEM; 692 break; 693 } 694 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 695 if (data->buf == NULL) { 696 printf("%s: could not allocate xfer buffer\n", 697 sc->sc_dev.dv_xname); 698 error = ENOMEM; 699 break; 700 } 701 /* Append this Tx buffer to our free list. */ 702 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 703 } 704 if (error != 0) 705 urtwn_free_tx_list(sc); 706 return (error); 707 } 708 709 void 710 urtwn_free_tx_list(struct urtwn_softc *sc) 711 { 712 int i; 713 714 /* NB: Caller must abort pipe first. */ 715 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 716 if (sc->tx_data[i].xfer != NULL) 717 usbd_free_xfer(sc->tx_data[i].xfer); 718 sc->tx_data[i].xfer = NULL; 719 } 720 } 721 722 void 723 urtwn_task(void *arg) 724 { 725 struct urtwn_softc *sc = arg; 726 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 727 struct urtwn_host_cmd *cmd; 728 int s; 729 730 /* Process host commands. */ 731 s = splusb(); 732 while (ring->next != ring->cur) { 733 cmd = &ring->cmd[ring->next]; 734 splx(s); 735 /* Invoke callback. */ 736 cmd->cb(sc, cmd->data); 737 s = splusb(); 738 ring->queued--; 739 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 740 } 741 splx(s); 742 } 743 744 void 745 urtwn_do_async(struct urtwn_softc *sc, 746 void (*cb)(struct urtwn_softc *, void *), void *arg, int len) 747 { 748 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 749 struct urtwn_host_cmd *cmd; 750 int s; 751 752 s = splusb(); 753 cmd = &ring->cmd[ring->cur]; 754 cmd->cb = cb; 755 KASSERT(len <= sizeof(cmd->data)); 756 memcpy(cmd->data, arg, len); 757 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 758 759 /* If there is no pending command already, schedule a task. */ 760 if (++ring->queued == 1) 761 usb_add_task(sc->sc_udev, &sc->sc_task); 762 splx(s); 763 } 764 765 void 766 urtwn_wait_async(void *cookie) 767 { 768 struct urtwn_softc *sc = cookie; 769 int s; 770 771 s = splusb(); 772 /* Wait for all queued asynchronous commands to complete. */ 773 usb_wait_task(sc->sc_udev, &sc->sc_task); 774 splx(s); 775 } 776 777 int 778 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 779 int len) 780 { 781 usb_device_request_t req; 782 783 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 784 req.bRequest = R92C_REQ_REGS; 785 USETW(req.wValue, addr); 786 USETW(req.wIndex, 0); 787 USETW(req.wLength, len); 788 return (usbd_do_request(sc->sc_udev, &req, buf)); 789 } 790 791 void 792 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val) 793 { 794 struct urtwn_softc *sc = cookie; 795 796 urtwn_write_region_1(sc, addr, &val, 1); 797 } 798 799 void 800 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val) 801 { 802 struct urtwn_softc *sc = cookie; 803 804 val = htole16(val); 805 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 806 } 807 808 void 809 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val) 810 { 811 struct urtwn_softc *sc = cookie; 812 813 val = htole32(val); 814 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 815 } 816 817 int 818 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 819 int len) 820 { 821 usb_device_request_t req; 822 823 req.bmRequestType = UT_READ_VENDOR_DEVICE; 824 req.bRequest = R92C_REQ_REGS; 825 USETW(req.wValue, addr); 826 USETW(req.wIndex, 0); 827 USETW(req.wLength, len); 828 return (usbd_do_request(sc->sc_udev, &req, buf)); 829 } 830 831 uint8_t 832 urtwn_read_1(void *cookie, uint16_t addr) 833 { 834 struct urtwn_softc *sc = cookie; 835 uint8_t val; 836 837 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 838 return (0xff); 839 return (val); 840 } 841 842 uint16_t 843 urtwn_read_2(void *cookie, uint16_t addr) 844 { 845 struct urtwn_softc *sc = cookie; 846 uint16_t val; 847 848 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 849 return (0xffff); 850 return (letoh16(val)); 851 } 852 853 uint32_t 854 urtwn_read_4(void *cookie, uint16_t addr) 855 { 856 struct urtwn_softc *sc = cookie; 857 uint32_t val; 858 859 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 860 return (0xffffffff); 861 return (letoh32(val)); 862 } 863 864 int 865 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 866 { 867 int ntries; 868 869 urtwn_write_4(sc, R92C_LLT_INIT, 870 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 871 SM(R92C_LLT_INIT_ADDR, addr) | 872 SM(R92C_LLT_INIT_DATA, data)); 873 /* Wait for write operation to complete. */ 874 for (ntries = 0; ntries < 20; ntries++) { 875 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 876 R92C_LLT_INIT_OP_NO_ACTIVE) 877 return (0); 878 DELAY(5); 879 } 880 return (ETIMEDOUT); 881 } 882 883 void 884 urtwn_calib_to(void *arg) 885 { 886 struct urtwn_softc *sc = arg; 887 888 if (usbd_is_dying(sc->sc_udev)) 889 return; 890 891 usbd_ref_incr(sc->sc_udev); 892 893 /* Do it in a process context. */ 894 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0); 895 896 usbd_ref_decr(sc->sc_udev); 897 } 898 899 /* ARGSUSED */ 900 void 901 urtwn_calib_cb(struct urtwn_softc *sc, void *arg) 902 { 903 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 904 int s; 905 906 s = splnet(); 907 if (ic->ic_opmode == IEEE80211_M_STA) { 908 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn); 909 } 910 splx(s); 911 912 rtwn_calib(&sc->sc_sc); 913 } 914 915 void 916 urtwn_next_calib(void *cookie) 917 { 918 struct urtwn_softc *sc = cookie; 919 920 if (!usbd_is_dying(sc->sc_udev)) 921 timeout_add_sec(&sc->calib_to, 2); 922 } 923 924 void 925 urtwn_cancel_calib(void *cookie) 926 { 927 struct urtwn_softc *sc = cookie; 928 929 if (timeout_initialized(&sc->calib_to)) 930 timeout_del(&sc->calib_to); 931 } 932 933 void 934 urtwn_scan_to(void *arg) 935 { 936 struct urtwn_softc *sc = arg; 937 938 if (usbd_is_dying(sc->sc_udev)) 939 return; 940 941 usbd_ref_incr(sc->sc_udev); 942 rtwn_next_scan(&sc->sc_sc); 943 usbd_ref_decr(sc->sc_udev); 944 } 945 946 void 947 urtwn_next_scan(void *arg) 948 { 949 struct urtwn_softc *sc = arg; 950 951 if (!usbd_is_dying(sc->sc_udev)) 952 timeout_add_msec(&sc->scan_to, 200); 953 } 954 955 void 956 urtwn_cancel_scan(void *cookie) 957 { 958 struct urtwn_softc *sc = cookie; 959 960 if (timeout_initialized(&sc->scan_to)) 961 timeout_del(&sc->scan_to); 962 } 963 964 int 965 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 966 { 967 struct rtwn_softc *sc_sc = ic->ic_softc; 968 struct device *self = sc_sc->sc_pdev; 969 struct urtwn_softc *sc = (struct urtwn_softc *)self; 970 struct urtwn_cmd_newstate cmd; 971 972 /* Do it in a process context. */ 973 cmd.state = nstate; 974 cmd.arg = arg; 975 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 976 return (0); 977 } 978 979 void 980 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 981 { 982 struct urtwn_cmd_newstate *cmd = arg; 983 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 984 985 rtwn_newstate(ic, cmd->state, cmd->arg); 986 } 987 988 void 989 urtwn_updateslot(struct ieee80211com *ic) 990 { 991 struct rtwn_softc *sc_sc = ic->ic_softc; 992 struct device *self = sc_sc->sc_pdev; 993 struct urtwn_softc *sc = (struct urtwn_softc *)self; 994 995 /* Do it in a process context. */ 996 urtwn_do_async(sc, urtwn_updateslot_cb, NULL, 0); 997 } 998 999 /* ARGSUSED */ 1000 void 1001 urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg) 1002 { 1003 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1004 1005 rtwn_updateslot(ic); 1006 } 1007 1008 void 1009 urtwn_updateedca(struct ieee80211com *ic) 1010 { 1011 struct rtwn_softc *sc_sc = ic->ic_softc; 1012 struct device *self = sc_sc->sc_pdev; 1013 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1014 1015 /* Do it in a process context. */ 1016 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0); 1017 } 1018 1019 /* ARGSUSED */ 1020 void 1021 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg) 1022 { 1023 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1024 1025 rtwn_updateedca(ic); 1026 } 1027 1028 int 1029 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1030 struct ieee80211_key *k) 1031 { 1032 struct rtwn_softc *sc_sc = ic->ic_softc; 1033 struct device *self = sc_sc->sc_pdev; 1034 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1035 struct urtwn_cmd_key cmd; 1036 1037 /* Defer setting of WEP keys until interface is brought up. */ 1038 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1039 (IFF_UP | IFF_RUNNING)) 1040 return (0); 1041 1042 /* Do it in a process context. */ 1043 cmd.key = *k; 1044 cmd.ni = ni; 1045 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd)); 1046 return (0); 1047 } 1048 1049 void 1050 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg) 1051 { 1052 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1053 struct urtwn_cmd_key *cmd = arg; 1054 1055 rtwn_set_key(ic, cmd->ni, &cmd->key); 1056 } 1057 1058 void 1059 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1060 struct ieee80211_key *k) 1061 { 1062 struct rtwn_softc *sc_sc = ic->ic_softc; 1063 struct device *self = sc_sc->sc_pdev; 1064 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1065 struct urtwn_cmd_key cmd; 1066 1067 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1068 ic->ic_state != IEEE80211_S_RUN) 1069 return; /* Nothing to do. */ 1070 1071 /* Do it in a process context. */ 1072 cmd.key = *k; 1073 cmd.ni = ni; 1074 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd)); 1075 } 1076 1077 void 1078 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg) 1079 { 1080 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1081 struct urtwn_cmd_key *cmd = arg; 1082 1083 rtwn_delete_key(ic, cmd->ni, &cmd->key); 1084 } 1085 1086 void 1087 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, 1088 struct mbuf_list *ml) 1089 { 1090 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1091 struct ifnet *ifp = &ic->ic_if; 1092 struct ieee80211_rxinfo rxi; 1093 struct ieee80211_frame *wh; 1094 struct ieee80211_node *ni; 1095 struct r92c_rx_desc_usb *rxd; 1096 uint32_t rxdw0, rxdw3; 1097 struct mbuf *m; 1098 uint8_t rate; 1099 int8_t rssi = 0; 1100 int s, infosz; 1101 1102 rxd = (struct r92c_rx_desc_usb *)buf; 1103 rxdw0 = letoh32(rxd->rxdw0); 1104 rxdw3 = letoh32(rxd->rxdw3); 1105 1106 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1107 /* 1108 * This should not happen since we setup our Rx filter 1109 * to not receive these frames. 1110 */ 1111 ifp->if_ierrors++; 1112 return; 1113 } 1114 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1115 ifp->if_ierrors++; 1116 return; 1117 } 1118 1119 rate = MS(rxdw3, R92C_RXDW3_RATE); 1120 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1121 1122 /* Get RSSI from PHY status descriptor if present. */ 1123 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1124 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]); 1125 /* Update our average RSSI. */ 1126 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi); 1127 } 1128 1129 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1130 pktlen, rate, infosz, rssi)); 1131 1132 MGETHDR(m, M_DONTWAIT, MT_DATA); 1133 if (__predict_false(m == NULL)) { 1134 ifp->if_ierrors++; 1135 return; 1136 } 1137 if (pktlen > MHLEN) { 1138 MCLGET(m, M_DONTWAIT); 1139 if (__predict_false(!(m->m_flags & M_EXT))) { 1140 ifp->if_ierrors++; 1141 m_freem(m); 1142 return; 1143 } 1144 } 1145 /* Finalize mbuf. */ 1146 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz); 1147 memcpy(mtod(m, uint8_t *), wh, pktlen); 1148 m->m_pkthdr.len = m->m_len = pktlen; 1149 1150 s = splnet(); 1151 #if NBPFILTER > 0 1152 if (__predict_false(sc->sc_drvbpf != NULL)) { 1153 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1154 struct mbuf mb; 1155 1156 tap->wr_flags = 0; 1157 /* Map HW rate index to 802.11 rate. */ 1158 if (!(rxdw3 & R92C_RXDW3_HT)) { 1159 switch (rate) { 1160 /* CCK. */ 1161 case 0: tap->wr_rate = 2; break; 1162 case 1: tap->wr_rate = 4; break; 1163 case 2: tap->wr_rate = 11; break; 1164 case 3: tap->wr_rate = 22; break; 1165 /* OFDM. */ 1166 case 4: tap->wr_rate = 12; break; 1167 case 5: tap->wr_rate = 18; break; 1168 case 6: tap->wr_rate = 24; break; 1169 case 7: tap->wr_rate = 36; break; 1170 case 8: tap->wr_rate = 48; break; 1171 case 9: tap->wr_rate = 72; break; 1172 case 10: tap->wr_rate = 96; break; 1173 case 11: tap->wr_rate = 108; break; 1174 } 1175 if (rate <= 3) 1176 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1177 } else if (rate >= 12) { /* MCS0~15. */ 1178 /* Bit 7 set means HT MCS instead of rate. */ 1179 tap->wr_rate = 0x80 | (rate - 12); 1180 } 1181 tap->wr_dbm_antsignal = rssi; 1182 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1183 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1184 1185 mb.m_data = (caddr_t)tap; 1186 mb.m_len = sc->sc_rxtap_len; 1187 mb.m_next = m; 1188 mb.m_nextpkt = NULL; 1189 mb.m_type = 0; 1190 mb.m_flags = 0; 1191 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1192 } 1193 #endif 1194 1195 ni = ieee80211_find_rxnode(ic, wh); 1196 rxi.rxi_flags = 0; 1197 rxi.rxi_rssi = rssi; 1198 rxi.rxi_tstamp = 0; /* Unused. */ 1199 ieee80211_inputm(ifp, m, ni, &rxi, ml); 1200 /* Node is no longer needed. */ 1201 ieee80211_release_node(ic, ni); 1202 splx(s); 1203 } 1204 1205 void 1206 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, 1207 usbd_status status) 1208 { 1209 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1210 struct urtwn_rx_data *data = priv; 1211 struct urtwn_softc *sc = data->sc; 1212 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1213 struct r92c_rx_desc_usb *rxd; 1214 uint32_t rxdw0; 1215 uint8_t *buf; 1216 int len, totlen, pktlen, infosz, npkts, error, align; 1217 1218 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1219 DPRINTF(("RX status=%d\n", status)); 1220 if (status == USBD_STALLED) 1221 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1222 if (status != USBD_CANCELLED) 1223 goto resubmit; 1224 return; 1225 } 1226 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1227 1228 if (__predict_false(len < sizeof(*rxd))) { 1229 DPRINTF(("xfer too short %d\n", len)); 1230 goto resubmit; 1231 } 1232 buf = data->buf; 1233 1234 /* Get the number of encapsulated frames. */ 1235 rxd = (struct r92c_rx_desc_usb *)buf; 1236 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT); 1237 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts)); 1238 1239 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1240 int ntries, type; 1241 struct r88e_tx_rpt_ccx *rxstat; 1242 1243 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT); 1244 1245 if (type == R88E_RXDW3_RPT_TX1) { 1246 buf += sizeof(struct r92c_rx_desc_usb); 1247 rxstat = (struct r88e_tx_rpt_ccx *)buf; 1248 ntries = MS(letoh32(rxstat->rptb2), 1249 R88E_RPTB2_RETRY_CNT); 1250 1251 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK) 1252 sc->amn.amn_txcnt++; 1253 if (ntries > 0) 1254 sc->amn.amn_retrycnt++; 1255 1256 goto resubmit; 1257 } 1258 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1259 int type; 1260 struct r92e_c2h_tx_rpt *txrpt; 1261 1262 if (letoh32(rxd->rxdw2) & R92E_RXDW2_RPT_C2H) { 1263 if (len < sizeof(struct r92c_rx_desc_usb) + 2) 1264 goto resubmit; 1265 1266 type = buf[sizeof(struct r92c_rx_desc_usb)]; 1267 switch (type) { 1268 case R92C_C2HEVT_TX_REPORT: 1269 buf += sizeof(struct r92c_rx_desc_usb) + 2; 1270 txrpt = (struct r92e_c2h_tx_rpt *)buf; 1271 if (MS(txrpt->rptb2, R92E_RPTB2_RETRY_CNT) > 0) 1272 sc->amn.amn_retrycnt++; 1273 if ((txrpt->rptb0 & (R92E_RPTB0_RETRY_OVER | 1274 R92E_RPTB0_LIFE_EXPIRE)) == 0) 1275 sc->amn.amn_txcnt++; 1276 break; 1277 default: 1278 break; 1279 } 1280 goto resubmit; 1281 } 1282 } 1283 1284 align = (sc->sc_sc.chip & RTWN_CHIP_92E ? 7 : 127); 1285 1286 /* Process all of them. */ 1287 while (npkts-- > 0) { 1288 if (__predict_false(len < sizeof(*rxd))) 1289 break; 1290 rxd = (struct r92c_rx_desc_usb *)buf; 1291 rxdw0 = letoh32(rxd->rxdw0); 1292 1293 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1294 if (__predict_false(pktlen == 0)) 1295 break; 1296 1297 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1298 1299 /* Make sure everything fits in xfer. */ 1300 totlen = sizeof(*rxd) + infosz + pktlen; 1301 if (__predict_false(totlen > len)) 1302 break; 1303 1304 /* Process 802.11 frame. */ 1305 urtwn_rx_frame(sc, buf, pktlen, &ml); 1306 1307 /* Handle chunk alignment. */ 1308 totlen = (totlen + align) & ~align; 1309 buf += totlen; 1310 len -= totlen; 1311 } 1312 if_input(&ic->ic_if, &ml); 1313 1314 resubmit: 1315 /* Setup a new transfer. */ 1316 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1317 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1318 error = usbd_transfer(data->xfer); 1319 if (error != 0 && error != USBD_IN_PROGRESS) 1320 DPRINTF(("could not set up new transfer: %d\n", error)); 1321 } 1322 1323 void 1324 urtwn_txeof(struct usbd_xfer *xfer, void *priv, 1325 usbd_status status) 1326 { 1327 struct urtwn_tx_data *data = priv; 1328 struct urtwn_softc *sc = data->sc; 1329 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if; 1330 int s; 1331 1332 s = splnet(); 1333 /* Put this Tx buffer back to our free list. */ 1334 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1335 1336 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1337 DPRINTF(("TX status=%d\n", status)); 1338 if (status == USBD_STALLED) 1339 usbd_clear_endpoint_stall_async(data->pipe); 1340 ifp->if_oerrors++; 1341 splx(s); 1342 return; 1343 } 1344 sc->sc_sc.sc_tx_timer = 0; 1345 1346 /* We just released a Tx buffer, notify Tx. */ 1347 if (ifq_is_oactive(&ifp->if_snd)) { 1348 ifq_clr_oactive(&ifp->if_snd); 1349 rtwn_start(ifp); 1350 } 1351 splx(s); 1352 } 1353 1354 void 1355 urtwn_tx_fill_desc(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1356 struct ieee80211_frame *wh, struct ieee80211_key *k, 1357 struct ieee80211_node *ni) 1358 { 1359 struct r92c_tx_desc_usb *txd; 1360 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1361 uint8_t raid, type; 1362 1363 txd = (struct r92c_tx_desc_usb *)*txdp; 1364 (*txdp) += sizeof(*txd); 1365 memset(txd, 0, sizeof(*txd)); 1366 1367 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1368 1369 txd->txdw0 |= htole32( 1370 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1371 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1372 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1373 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1374 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1375 1376 #ifdef notyet 1377 if (k != NULL) { 1378 switch (k->k_cipher) { 1379 case IEEE80211_CIPHER_WEP40: 1380 case IEEE80211_CIPHER_WEP104: 1381 case IEEE80211_CIPHER_TKIP: 1382 cipher = R92C_TXDW1_CIPHER_RC4; 1383 break; 1384 case IEEE80211_CIPHER_CCMP: 1385 cipher = R92C_TXDW1_CIPHER_AES; 1386 break; 1387 default: 1388 cipher = R92C_TXDW1_CIPHER_NONE; 1389 } 1390 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 1391 } 1392 #endif 1393 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1394 type == IEEE80211_FC0_TYPE_DATA) { 1395 if (ic->ic_curmode == IEEE80211_MODE_11B || 1396 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1397 raid = R92C_RAID_11B; 1398 else 1399 raid = R92C_RAID_11BG; 1400 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1401 txd->txdw1 |= htole32( 1402 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) | 1403 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1404 SM(R92C_TXDW1_RAID, raid)); 1405 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1406 /* Request TX status report for AMRR */ 1407 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT); 1408 } else { 1409 txd->txdw1 |= htole32( 1410 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) | 1411 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1412 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1413 } 1414 1415 if (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1416 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1417 R92C_TXDW4_HWRTSEN); 1418 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1419 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1420 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1421 R92C_TXDW4_HWRTSEN); 1422 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1423 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1424 R92C_TXDW4_HWRTSEN); 1425 } 1426 } 1427 txd->txdw5 |= htole32(0x0001ff00); 1428 1429 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1430 /* Use AMRR */ 1431 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1432 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1433 ni->ni_txrate)); 1434 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1435 ni->ni_txrate)); 1436 } else { 1437 /* Send RTS at OFDM24 and data at OFDM54. */ 1438 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1439 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1440 } 1441 } else { 1442 txd->txdw1 |= htole32( 1443 SM(R92C_TXDW1_MACID, 0) | 1444 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1445 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1446 1447 /* Force CCK1. */ 1448 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1449 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1450 } 1451 /* Set sequence number (already little endian). */ 1452 txd->txdseq |= (*(uint16_t *)wh->i_seq) >> IEEE80211_SEQ_SEQ_SHIFT; 1453 1454 if (!ieee80211_has_qos(wh)) { 1455 /* Use HW sequence numbering for non-QoS frames. */ 1456 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1457 txd->txdseq |= htole16(R92C_TXDW3_HWSEQEN); 1458 } else 1459 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1460 } 1461 1462 void 1463 urtwn_tx_fill_desc_gen2(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1464 struct ieee80211_frame *wh, struct ieee80211_key *k, 1465 struct ieee80211_node *ni) 1466 { 1467 struct r92e_tx_desc_usb *txd; 1468 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1469 uint8_t raid, type; 1470 1471 txd = (struct r92e_tx_desc_usb *)*txdp; 1472 (*txdp) += sizeof(*txd); 1473 memset(txd, 0, sizeof(*txd)); 1474 1475 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1476 1477 txd->txdw0 |= htole32( 1478 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1479 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1480 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1481 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1482 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1483 1484 #ifdef notyet 1485 /* cipher */ 1486 #endif 1487 1488 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1489 type == IEEE80211_FC0_TYPE_DATA) { 1490 if (ic->ic_curmode == IEEE80211_MODE_11B || 1491 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1492 raid = R92E_RAID_11B; 1493 else 1494 raid = R92E_RAID_11BG; 1495 txd->txdw1 |= htole32( 1496 SM(R92E_TXDW1_MACID, R92C_MACID_BSS) | 1497 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1498 SM(R92C_TXDW1_RAID, raid)); 1499 /* Request TX status report for AMRR */ 1500 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT | R88E_TXDW2_AGGBK); 1501 1502 if (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1503 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1504 R92C_TXDW4_HWRTSEN); 1505 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1506 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1507 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1508 R92C_TXDW4_HWRTSEN); 1509 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1510 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1511 R92C_TXDW4_HWRTSEN); 1512 } 1513 } 1514 txd->txdw5 |= htole32(0x0001ff00); 1515 1516 /* Use AMRR */ 1517 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1518 txd->txdw4 |= htole32(SM(R92E_TXDW4_RTSRATE, ni->ni_txrate)); 1519 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, ni->ni_txrate)); 1520 } else { 1521 txd->txdw1 |= htole32( 1522 SM(R92E_TXDW1_MACID, 0) | 1523 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1524 SM(R92C_TXDW1_RAID, R92E_RAID_11B)); 1525 1526 /* Force CCK1. */ 1527 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1528 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, 0)); 1529 } 1530 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATEFB, 0x1f)); 1531 1532 txd->txdseq2 |= htole16(SM(R92E_TXDSEQ2_HWSEQ, *(uint16_t *)wh->i_seq)); 1533 1534 if (!ieee80211_has_qos(wh)) { 1535 /* Use HW sequence numbering for non-QoS frames. */ 1536 txd->txdw7 |= htole16(R92C_TXDW3_HWSEQEN); 1537 } 1538 } 1539 1540 int 1541 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni) 1542 { 1543 struct urtwn_softc *sc = cookie; 1544 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1545 struct ieee80211_frame *wh; 1546 struct ieee80211_key *k = NULL; 1547 struct urtwn_tx_data *data; 1548 struct usbd_pipe *pipe; 1549 uint16_t qos, sum; 1550 uint8_t tid, qid; 1551 int i, xferlen, error; 1552 uint8_t *txdp; 1553 1554 wh = mtod(m, struct ieee80211_frame *); 1555 1556 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1557 k = ieee80211_get_txkey(ic, wh, ni); 1558 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1559 return (ENOBUFS); 1560 wh = mtod(m, struct ieee80211_frame *); 1561 } 1562 1563 if (ieee80211_has_qos(wh)) { 1564 qos = ieee80211_get_qos(wh); 1565 tid = qos & IEEE80211_QOS_TID; 1566 qid = ieee80211_up_to_ac(ic, tid); 1567 } else if ((wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK) 1568 != IEEE80211_FC0_TYPE_DATA) { 1569 /* Use AC VO for management frames. */ 1570 qid = EDCA_AC_VO; 1571 } else 1572 qid = EDCA_AC_BE; 1573 1574 /* Get the USB pipe to use for this AC. */ 1575 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 1576 1577 /* Grab a Tx buffer from our free list. */ 1578 data = TAILQ_FIRST(&sc->tx_free_list); 1579 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1580 1581 /* Fill Tx descriptor. */ 1582 txdp = data->buf; 1583 if (sc->sc_sc.chip & RTWN_CHIP_92E) 1584 urtwn_tx_fill_desc_gen2(sc, &txdp, m, wh, k, ni); 1585 else 1586 urtwn_tx_fill_desc(sc, &txdp, m, wh, k, ni); 1587 1588 /* Compute Tx descriptor checksum. */ 1589 sum = 0; 1590 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 1591 sum ^= ((uint16_t *)data->buf)[i]; 1592 ((uint16_t *)data->buf)[R92C_TXDESC_SUMOFFSET] = sum; 1593 1594 #if NBPFILTER > 0 1595 if (__predict_false(sc->sc_drvbpf != NULL)) { 1596 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1597 struct mbuf mb; 1598 1599 tap->wt_flags = 0; 1600 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1601 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1602 1603 mb.m_data = (caddr_t)tap; 1604 mb.m_len = sc->sc_txtap_len; 1605 mb.m_next = m; 1606 mb.m_nextpkt = NULL; 1607 mb.m_type = 0; 1608 mb.m_flags = 0; 1609 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1610 } 1611 #endif 1612 1613 xferlen = (txdp - data->buf) + m->m_pkthdr.len; 1614 m_copydata(m, 0, m->m_pkthdr.len, txdp); 1615 m_freem(m); 1616 1617 data->pipe = pipe; 1618 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1619 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 1620 urtwn_txeof); 1621 error = usbd_transfer(data->xfer); 1622 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1623 /* Put this Tx buffer back to our free list. */ 1624 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1625 return (error); 1626 } 1627 ieee80211_release_node(ic, ni); 1628 return (0); 1629 } 1630 1631 int 1632 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1633 { 1634 struct rtwn_softc *sc_sc = ifp->if_softc; 1635 struct device *self = sc_sc->sc_pdev; 1636 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1637 int error; 1638 1639 if (usbd_is_dying(sc->sc_udev)) 1640 return ENXIO; 1641 1642 usbd_ref_incr(sc->sc_udev); 1643 error = rtwn_ioctl(ifp, cmd, data); 1644 usbd_ref_decr(sc->sc_udev); 1645 1646 return (error); 1647 } 1648 1649 int 1650 urtwn_r92c_power_on(struct urtwn_softc *sc) 1651 { 1652 uint32_t reg; 1653 int ntries; 1654 1655 /* Wait for autoload done bit. */ 1656 for (ntries = 0; ntries < 1000; ntries++) { 1657 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1658 break; 1659 DELAY(5); 1660 } 1661 if (ntries == 1000) { 1662 printf("%s: timeout waiting for chip autoload\n", 1663 sc->sc_dev.dv_xname); 1664 return (ETIMEDOUT); 1665 } 1666 1667 /* Unlock ISO/CLK/Power control register. */ 1668 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1669 /* Move SPS into PWM mode. */ 1670 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1671 DELAY(100); 1672 1673 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1674 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1675 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1676 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1677 DELAY(100); 1678 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1679 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1680 ~R92C_SYS_ISO_CTRL_MD2PP); 1681 } 1682 1683 /* Auto enable WLAN. */ 1684 urtwn_write_2(sc, R92C_APS_FSMCO, 1685 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1686 for (ntries = 0; ntries < 1000; ntries++) { 1687 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1688 R92C_APS_FSMCO_APFM_ONMAC)) 1689 break; 1690 DELAY(5); 1691 } 1692 if (ntries == 1000) { 1693 printf("%s: timeout waiting for MAC auto ON\n", 1694 sc->sc_dev.dv_xname); 1695 return (ETIMEDOUT); 1696 } 1697 1698 /* Enable radio, GPIO and LED functions. */ 1699 urtwn_write_2(sc, R92C_APS_FSMCO, 1700 R92C_APS_FSMCO_AFSM_HSUS | 1701 R92C_APS_FSMCO_PDN_EN | 1702 R92C_APS_FSMCO_PFM_ALDN); 1703 /* Release RF digital isolation. */ 1704 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1705 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1706 1707 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1708 reg = urtwn_read_2(sc, R92C_CR); 1709 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1710 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1711 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1712 R92C_CR_ENSEC; 1713 urtwn_write_2(sc, R92C_CR, reg); 1714 1715 urtwn_write_1(sc, 0xfe10, 0x19); 1716 return (0); 1717 } 1718 1719 int 1720 urtwn_r92e_power_on(struct urtwn_softc *sc) 1721 { 1722 uint32_t reg; 1723 int ntries; 1724 1725 if (urtwn_read_4(sc, R92C_SYS_CFG) & R92E_SYS_CFG_SPSLDO_SEL) { 1726 /* LDO. */ 1727 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 1728 } else { 1729 reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL2); 1730 reg &= 0xff0fffff; 1731 reg |= 0x00500000; 1732 urtwn_write_4(sc, R92C_SYS_SWR_CTRL2, reg); 1733 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 1734 } 1735 1736 /* 40MHz crystal source */ 1737 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1738 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xfb); 1739 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1740 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xfffffc7f); 1741 1742 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1743 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xbf); 1744 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1745 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xffdfffff); 1746 1747 /* Disable HWPDN. */ 1748 urtwn_write_2(sc, R92C_APS_FSMCO, 1749 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1750 for (ntries = 0; ntries < 5000; ntries++) { 1751 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1752 break; 1753 DELAY(10); 1754 } 1755 if (ntries == 5000) { 1756 printf("%s: timeout waiting for chip power up\n", 1757 sc->sc_dev.dv_xname); 1758 return (ETIMEDOUT); 1759 } 1760 1761 /* Disable WL suspend. */ 1762 urtwn_write_2(sc, R92C_APS_FSMCO, 1763 urtwn_read_2(sc, R92C_APS_FSMCO) & 1764 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1765 1766 /* Auto enable WLAN. */ 1767 urtwn_write_4(sc, R92C_APS_FSMCO, 1768 urtwn_read_4(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 1769 urtwn_write_2(sc, R92C_APS_FSMCO, 1770 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1771 for (ntries = 0; ntries < 5000; ntries++) { 1772 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1773 R92C_APS_FSMCO_APFM_ONMAC)) 1774 break; 1775 DELAY(10); 1776 } 1777 if (ntries == 5000) { 1778 printf("%s: timeout waiting for MAC auto ON\n", 1779 sc->sc_dev.dv_xname); 1780 return (ETIMEDOUT); 1781 } 1782 1783 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1784 urtwn_write_2(sc, R92C_CR, 0); 1785 reg = urtwn_read_2(sc, R92C_CR); 1786 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1787 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1788 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1789 urtwn_write_2(sc, R92C_CR, reg); 1790 return (0); 1791 } 1792 1793 int 1794 urtwn_r88e_power_on(struct urtwn_softc *sc) 1795 { 1796 uint32_t reg; 1797 int ntries; 1798 1799 /* Wait for power ready bit. */ 1800 for (ntries = 0; ntries < 5000; ntries++) { 1801 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1802 break; 1803 DELAY(10); 1804 } 1805 if (ntries == 5000) { 1806 printf("%s: timeout waiting for chip power up\n", 1807 sc->sc_dev.dv_xname); 1808 return (ETIMEDOUT); 1809 } 1810 1811 /* Reset BB. */ 1812 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1813 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 1814 R92C_SYS_FUNC_EN_BB_GLB_RST)); 1815 1816 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 1817 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 1818 1819 /* Disable HWPDN. */ 1820 urtwn_write_2(sc, R92C_APS_FSMCO, 1821 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1822 /* Disable WL suspend. */ 1823 urtwn_write_2(sc, R92C_APS_FSMCO, 1824 urtwn_read_2(sc, R92C_APS_FSMCO) & 1825 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1826 1827 /* Auto enable WLAN. */ 1828 urtwn_write_2(sc, R92C_APS_FSMCO, 1829 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1830 for (ntries = 0; ntries < 5000; ntries++) { 1831 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1832 R92C_APS_FSMCO_APFM_ONMAC)) 1833 break; 1834 DELAY(10); 1835 } 1836 if (ntries == 5000) { 1837 printf("%s: timeout waiting for MAC auto ON\n", 1838 sc->sc_dev.dv_xname); 1839 return (ETIMEDOUT); 1840 } 1841 1842 /* Enable LDO normal mode. */ 1843 urtwn_write_1(sc, R92C_LPLDO_CTRL, 1844 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 1845 1846 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1847 urtwn_write_2(sc, R92C_CR, 0); 1848 reg = urtwn_read_2(sc, R92C_CR); 1849 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1850 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1851 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1852 urtwn_write_2(sc, R92C_CR, reg); 1853 return (0); 1854 } 1855 1856 int 1857 urtwn_llt_init(struct urtwn_softc *sc, int page_count) 1858 { 1859 int i, error, pktbuf_count; 1860 1861 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1862 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 1863 1864 /* Reserve pages [0; page_count]. */ 1865 for (i = 0; i < page_count; i++) { 1866 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1867 return (error); 1868 } 1869 /* NB: 0xff indicates end-of-list. */ 1870 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1871 return (error); 1872 /* 1873 * Use pages [page_count + 1; pktbuf_count - 1] 1874 * as ring buffer. 1875 */ 1876 for (++i; i < pktbuf_count - 1; i++) { 1877 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1878 return (error); 1879 } 1880 /* Make the last page point to the beginning of the ring buffer. */ 1881 error = urtwn_llt_write(sc, i, page_count + 1); 1882 return (error); 1883 } 1884 1885 int 1886 urtwn_auto_llt_init(struct urtwn_softc *sc) 1887 { 1888 int ntries; 1889 1890 urtwn_write_4(sc, R92E_AUTO_LLT, urtwn_read_4(sc, 1891 R92E_AUTO_LLT) | R92E_AUTO_LLT_EN); 1892 for (ntries = 0; ntries < 1000; ntries++) { 1893 if (!(urtwn_read_4(sc, R92E_AUTO_LLT) & R92E_AUTO_LLT_EN)) 1894 return (0); 1895 DELAY(2); 1896 } 1897 1898 return (ETIMEDOUT); 1899 } 1900 1901 int 1902 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len) 1903 { 1904 struct urtwn_softc *sc = cookie; 1905 uint32_t reg; 1906 int off, mlen, error = 0; 1907 1908 reg = urtwn_read_4(sc, R92C_MCUFWDL); 1909 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 1910 urtwn_write_4(sc, R92C_MCUFWDL, reg); 1911 1912 off = R92C_FW_START_ADDR; 1913 while (len > 0) { 1914 if (len > 196) 1915 mlen = 196; 1916 else if (len > 4) 1917 mlen = 4; 1918 else 1919 mlen = 1; 1920 error = urtwn_write_region_1(sc, off, buf, mlen); 1921 if (error != 0) 1922 break; 1923 off += mlen; 1924 buf += mlen; 1925 len -= mlen; 1926 } 1927 return (error); 1928 } 1929 1930 int 1931 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len) 1932 { 1933 struct urtwn_softc *sc = cookie; 1934 const char *name; 1935 int error; 1936 1937 if (sc->sc_sc.chip & RTWN_CHIP_92E) 1938 name = "urtwn-rtl8192eu_nic"; 1939 else if (sc->sc_sc.chip & RTWN_CHIP_88E) 1940 name = "urtwn-rtl8188eufw"; 1941 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 1942 RTWN_CHIP_UMC_A_CUT) 1943 name = "urtwn-rtl8192cfwU"; 1944 else 1945 name = "urtwn-rtl8192cfwT"; 1946 1947 error = loadfirmware(name, fw, len); 1948 if (error) 1949 printf("%s: could not read firmware %s (error %d)\n", 1950 sc->sc_dev.dv_xname, name, error); 1951 return (error); 1952 } 1953 1954 int 1955 urtwn_dma_init(void *cookie) 1956 { 1957 struct urtwn_softc *sc = cookie; 1958 uint32_t reg; 1959 uint16_t dmasize; 1960 int hqpages, lqpages, nqpages, pagecnt, boundary; 1961 int error, hashq, haslq, hasnq; 1962 1963 /* Default initialization of chipset values. */ 1964 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1965 hqpages = R88E_HQ_NPAGES; 1966 lqpages = R88E_LQ_NPAGES; 1967 nqpages = R88E_NQ_NPAGES; 1968 pagecnt = R88E_TX_PAGE_COUNT; 1969 boundary = R88E_TX_PAGE_BOUNDARY; 1970 dmasize = R88E_MAX_RX_DMA_SIZE; 1971 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1972 hqpages = R92E_HQ_NPAGES; 1973 lqpages = R92E_LQ_NPAGES; 1974 nqpages = R92E_NQ_NPAGES; 1975 pagecnt = R92E_TX_PAGE_COUNT; 1976 boundary = R92E_TX_PAGE_BOUNDARY; 1977 dmasize = R92E_MAX_RX_DMA_SIZE; 1978 } else { 1979 hqpages = R92C_HQ_NPAGES; 1980 lqpages = R92C_LQ_NPAGES; 1981 nqpages = R92C_NQ_NPAGES; 1982 pagecnt = R92C_TX_PAGE_COUNT; 1983 boundary = R92C_TX_PAGE_BOUNDARY; 1984 dmasize = R92C_MAX_RX_DMA_SIZE; 1985 } 1986 1987 /* Initialize LLT table. */ 1988 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1989 error = urtwn_auto_llt_init(sc); 1990 } else { 1991 error = urtwn_llt_init(sc, pagecnt); 1992 } 1993 if (error != 0) 1994 return (error); 1995 1996 /* Get Tx queues to USB endpoints mapping. */ 1997 hashq = hasnq = haslq = 0; 1998 switch (sc->ntx) { 1999 case 3: 2000 haslq = 1; 2001 pagecnt -= lqpages; 2002 /* FALLTHROUGH */ 2003 case 2: 2004 hasnq = 1; 2005 pagecnt -= nqpages; 2006 /* FALLTHROUGH */ 2007 case 1: 2008 hashq = 1; 2009 pagecnt -= hqpages; 2010 break; 2011 } 2012 2013 /* Set number of pages for normal priority queue. */ 2014 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2015 urtwn_write_4(sc, R92C_RQPN, 2016 /* Set number of pages for public queue. */ 2017 SM(R92C_RQPN_PUBQ, pagecnt) | 2018 /* Set number of pages for high priority queue. */ 2019 SM(R92C_RQPN_HPQ, hashq ? hqpages : 0) | 2020 /* Set number of pages for low priority queue. */ 2021 SM(R92C_RQPN_LPQ, haslq ? lqpages : 0) | 2022 /* Load values. */ 2023 R92C_RQPN_LD); 2024 2025 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, boundary); 2026 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, boundary); 2027 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, boundary); 2028 urtwn_write_1(sc, R92C_TRXFF_BNDY, boundary); 2029 urtwn_write_1(sc, R92C_TDECTRL + 1, boundary); 2030 2031 /* Set queue to USB pipe mapping. */ 2032 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2033 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2034 if (haslq) 2035 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2036 else if (hashq) { 2037 if (!hasnq) 2038 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2039 else 2040 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2041 } 2042 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2043 2044 /* Set Tx/Rx transfer page boundary. */ 2045 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, dmasize - 1); 2046 2047 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2048 /* Set Tx/Rx transfer page size. */ 2049 urtwn_write_1(sc, R92C_PBP, 2050 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2051 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2052 } 2053 return (error); 2054 } 2055 2056 void 2057 urtwn_aggr_init(void *cookie) 2058 { 2059 struct urtwn_softc *sc = cookie; 2060 uint32_t reg = 0; 2061 int dmasize, dmatiming, ndesc; 2062 2063 /* Set burst packet length. */ 2064 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2065 urtwn_burstlen_init(sc); 2066 2067 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2068 dmasize = 6; 2069 dmatiming = 32; 2070 ndesc = 3; 2071 } else { 2072 dmasize = 48; 2073 dmatiming = 4; 2074 ndesc = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1 : 6; 2075 } 2076 2077 /* Tx aggregation setting. */ 2078 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2079 urtwn_write_1(sc, R92E_DWBCN1_CTRL, ndesc << 1); 2080 } else { 2081 reg = urtwn_read_4(sc, R92C_TDECTRL); 2082 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, ndesc); 2083 urtwn_write_4(sc, R92C_TDECTRL, reg); 2084 } 2085 2086 /* Rx aggregation setting. */ 2087 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2088 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 2089 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 2090 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 2091 } 2092 2093 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, dmasize); 2094 if (sc->sc_sc.chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) 2095 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, dmatiming); 2096 else 2097 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, dmatiming); 2098 2099 /* Drop incorrect bulk out. */ 2100 urtwn_write_4(sc, R92C_TXDMA_OFFSET_CHK, 2101 urtwn_read_4(sc, R92C_TXDMA_OFFSET_CHK) | 2102 R92C_TXDMA_OFFSET_CHK_DROP_DATA_EN); 2103 } 2104 2105 void 2106 urtwn_mac_init(void *cookie) 2107 { 2108 struct urtwn_softc *sc = cookie; 2109 int i; 2110 2111 /* Write MAC initialization values. */ 2112 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2113 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2114 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2115 rtl8188eu_mac[i].val); 2116 } 2117 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2118 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2119 for (i = 0; i < nitems(rtl8192eu_mac); i++) { 2120 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 2121 rtl8192eu_mac[i].val); 2122 } 2123 } else { 2124 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2125 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2126 rtl8192cu_mac[i].val); 2127 } 2128 } 2129 2130 void 2131 urtwn_bb_init(void *cookie) 2132 { 2133 struct urtwn_softc *sc = cookie; 2134 const struct r92c_bb_prog *prog; 2135 uint32_t reg; 2136 uint8_t xtal; 2137 int i; 2138 2139 /* Enable BB and RF. */ 2140 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2141 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2142 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2143 R92C_SYS_FUNC_EN_DIO_RF); 2144 2145 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) 2146 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2147 2148 urtwn_write_1(sc, R92C_RF_CTRL, 2149 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2150 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2151 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2152 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2153 2154 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2155 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2156 urtwn_write_1(sc, 0x15, 0xe9); 2157 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2158 } 2159 2160 /* Select BB programming based on board type. */ 2161 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2162 prog = &rtl8188eu_bb_prog; 2163 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2164 prog = &rtl8192eu_bb_prog; 2165 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) { 2166 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2167 prog = &rtl8188ce_bb_prog; 2168 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA) 2169 prog = &rtl8188ru_bb_prog; 2170 else 2171 prog = &rtl8188cu_bb_prog; 2172 } else { 2173 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2174 prog = &rtl8192ce_bb_prog; 2175 else 2176 prog = &rtl8192cu_bb_prog; 2177 } 2178 /* Write BB initialization values. */ 2179 for (i = 0; i < prog->count; i++) { 2180 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2181 DELAY(1); 2182 } 2183 2184 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) { 2185 /* 8192C 1T only configuration. */ 2186 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2187 reg = (reg & ~0x00000003) | 0x2; 2188 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2189 2190 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2191 reg = (reg & ~0x00300033) | 0x00200022; 2192 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2193 2194 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2195 reg = (reg & ~0xff000000) | 0x45 << 24; 2196 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2197 2198 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2199 reg = (reg & ~0x000000ff) | 0x23; 2200 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2201 2202 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2203 reg = (reg & ~0x00000030) | 1 << 4; 2204 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2205 2206 reg = urtwn_bb_read(sc, 0xe74); 2207 reg = (reg & ~0x0c000000) | 2 << 26; 2208 urtwn_bb_write(sc, 0xe74, reg); 2209 reg = urtwn_bb_read(sc, 0xe78); 2210 reg = (reg & ~0x0c000000) | 2 << 26; 2211 urtwn_bb_write(sc, 0xe78, reg); 2212 reg = urtwn_bb_read(sc, 0xe7c); 2213 reg = (reg & ~0x0c000000) | 2 << 26; 2214 urtwn_bb_write(sc, 0xe7c, reg); 2215 reg = urtwn_bb_read(sc, 0xe80); 2216 reg = (reg & ~0x0c000000) | 2 << 26; 2217 urtwn_bb_write(sc, 0xe80, reg); 2218 reg = urtwn_bb_read(sc, 0xe88); 2219 reg = (reg & ~0x0c000000) | 2 << 26; 2220 urtwn_bb_write(sc, 0xe88, reg); 2221 } 2222 2223 /* Write AGC values. */ 2224 for (i = 0; i < prog->agccount; i++) { 2225 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2226 prog->agcvals[i]); 2227 DELAY(1); 2228 } 2229 2230 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2231 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2232 DELAY(1); 2233 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2234 DELAY(1); 2235 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2236 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022); 2237 DELAY(1); 2238 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020); 2239 DELAY(1); 2240 } 2241 2242 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2243 xtal = sc->sc_sc.crystal_cap & 0x3f; 2244 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2245 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2246 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6)); 2247 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2248 xtal = sc->sc_sc.crystal_cap & 0x3f; 2249 reg = urtwn_read_4(sc, R92C_AFE_CTRL3); 2250 reg &= 0xff000fff; 2251 reg |= (xtal | (xtal << 6)) << 12; 2252 urtwn_write_4(sc, R92C_AFE_CTRL3, reg); 2253 2254 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb); 2255 } 2256 2257 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 2258 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR; 2259 } 2260 2261 void 2262 urtwn_burstlen_init(struct urtwn_softc *sc) 2263 { 2264 uint8_t reg; 2265 2266 reg = urtwn_read_1(sc, R92E_RXDMA_PRO); 2267 reg &= ~0x30; 2268 switch (sc->sc_udev->speed) { 2269 case USB_SPEED_HIGH: 2270 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x1e); 2271 break; 2272 default: 2273 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x2e); 2274 break; 2275 } 2276 } 2277 2278 int 2279 urtwn_power_on(void *cookie) 2280 { 2281 struct urtwn_softc *sc = cookie; 2282 2283 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2284 return (urtwn_r88e_power_on(sc)); 2285 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2286 return (urtwn_r92e_power_on(sc)); 2287 2288 return (urtwn_r92c_power_on(sc)); 2289 } 2290 2291 int 2292 urtwn_alloc_buffers(void *cookie) 2293 { 2294 struct urtwn_softc *sc = cookie; 2295 int error; 2296 2297 /* Init host async commands ring. */ 2298 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2299 2300 /* Allocate Tx/Rx buffers. */ 2301 error = urtwn_alloc_rx_list(sc); 2302 if (error != 0) { 2303 printf("%s: could not allocate Rx buffers\n", 2304 sc->sc_dev.dv_xname); 2305 return (error); 2306 } 2307 error = urtwn_alloc_tx_list(sc); 2308 if (error != 0) { 2309 printf("%s: could not allocate Tx buffers\n", 2310 sc->sc_dev.dv_xname); 2311 return (error); 2312 } 2313 2314 return (0); 2315 } 2316 2317 int 2318 urtwn_init(void *cookie) 2319 { 2320 struct urtwn_softc *sc = cookie; 2321 int i, error; 2322 2323 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2324 urtwn_write_1(sc, R92C_ACLK_MON, 0); 2325 2326 /* Queue Rx xfers. */ 2327 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 2328 struct urtwn_rx_data *data = &sc->rx_data[i]; 2329 2330 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 2331 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2332 USBD_NO_TIMEOUT, urtwn_rxeof); 2333 error = usbd_transfer(data->xfer); 2334 if (error != 0 && error != USBD_IN_PROGRESS) 2335 return (error); 2336 } 2337 2338 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2339 2340 /* 2341 * Enable TX reports for AMRR. 2342 * In order to get reports we need to explicitly reset the register. 2343 */ 2344 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2345 urtwn_write_1(sc, R88E_TX_RPT_CTRL, (urtwn_read_1(sc, 2346 R88E_TX_RPT_CTRL) & ~0) | R88E_TX_RPT_CTRL_EN); 2347 2348 return (0); 2349 } 2350 2351 void 2352 urtwn_stop(void *cookie) 2353 { 2354 struct urtwn_softc *sc = cookie; 2355 int i; 2356 2357 /* Abort Tx. */ 2358 for (i = 0; i < R92C_MAX_EPOUT; i++) { 2359 if (sc->tx_pipe[i] != NULL) 2360 usbd_abort_pipe(sc->tx_pipe[i]); 2361 } 2362 /* Stop Rx pipe. */ 2363 usbd_abort_pipe(sc->rx_pipe); 2364 /* Free Tx/Rx buffers. */ 2365 urtwn_free_tx_list(sc); 2366 urtwn_free_rx_list(sc); 2367 } 2368 2369 int 2370 urtwn_is_oactive(void *cookie) 2371 { 2372 struct urtwn_softc *sc = cookie; 2373 2374 return (TAILQ_EMPTY(&sc->tx_free_list)); 2375 } 2376