1*33de4f94Sdv /* $OpenBSD: i8253.h,v 1.10 2022/09/01 22:01:40 dv Exp $ */ 2ecc93de1Smlarkin /* 3ecc93de1Smlarkin * Copyright (c) 2016 Mike Larkin <mlarkin@openbsd.org> 4ecc93de1Smlarkin * 5ecc93de1Smlarkin * Permission to use, copy, modify, and distribute this software for any 6ecc93de1Smlarkin * purpose with or without fee is hereby granted, provided that the above 7ecc93de1Smlarkin * copyright notice and this permission notice appear in all copies. 8ecc93de1Smlarkin * 9ecc93de1Smlarkin * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10ecc93de1Smlarkin * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11ecc93de1Smlarkin * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12ecc93de1Smlarkin * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13ecc93de1Smlarkin * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14ecc93de1Smlarkin * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15ecc93de1Smlarkin * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16ecc93de1Smlarkin */ 17ecc93de1Smlarkin 18ecc93de1Smlarkin /* 19ecc93de1Smlarkin * Emulated i8253 PIT (counter) 20ecc93de1Smlarkin */ 21ecc93de1Smlarkin #define TIMER_BASE 0x40 /* 8253 timer 0 */ 22ecc93de1Smlarkin #define TIMER_CTRL 0x43 /* 8253 timer control */ 23ecc93de1Smlarkin #define NS_PER_TICK (1000000000 / TIMER_FREQ) 24764091f3Smlarkin #define TIMER_RB_COUNT 0x20 /* read back count value */ 25764091f3Smlarkin #define TIMER_RB_STATUS 0x10 /* read back status */ 26764091f3Smlarkin #define TIMER_RB_C0 0x2 /* read back channel 0 */ 27764091f3Smlarkin #define TIMER_RB_C1 0x4 /* read back channel 1 */ 28764091f3Smlarkin #define TIMER_RB_C2 0x8 /* read back channel 1 */ 29*33de4f94Sdv #define PCKBC_AUX 0x61 /* PC keyboard aux port for i8253 misc access */ 30ecc93de1Smlarkin 31ecc93de1Smlarkin /* i8253 registers */ 32d23749a0Smlarkin struct i8253_channel { 3394c97f60Scheloha struct timespec ts; /* timer start time */ 34ecc93de1Smlarkin uint16_t start; /* starting value */ 35ecc93de1Smlarkin uint16_t olatch; /* output latch */ 36ecc93de1Smlarkin uint16_t ilatch; /* input latch */ 37ecc93de1Smlarkin uint8_t last_r; /* last read byte (MSB/LSB) */ 38ecc93de1Smlarkin uint8_t last_w; /* last written byte (MSB/LSB) */ 39ecc93de1Smlarkin uint8_t mode; /* counter mode */ 40764091f3Smlarkin uint8_t rbs; /* channel is in readback status mode */ 41ecc93de1Smlarkin struct event timer; /* timer event for this counter */ 426cc75de0Smlarkin uint32_t vm_id; /* owning VM id */ 4352e954a3Spd int in_use; /* denotes if this counter was ever used */ 4403fd2d06Smlarkin uint8_t state; /* 0 if channel is counting, 1 if fired */ 45ecc93de1Smlarkin }; 46ecc93de1Smlarkin 47ecc93de1Smlarkin void i8253_init(uint32_t); 48ecc93de1Smlarkin void i8253_reset(uint8_t); 49ecc93de1Smlarkin void i8253_fire(int, short, void *); 50149417b6Sreyk int i8253_dump(int); 51149417b6Sreyk int i8253_restore(int, uint32_t); 52ecc93de1Smlarkin uint8_t vcpu_exit_i8253(struct vm_run_params *); 5303fd2d06Smlarkin uint8_t vcpu_exit_i8253_misc(struct vm_run_params *); 54764091f3Smlarkin void i8253_do_readback(uint32_t); 55149417b6Sreyk void i8253_stop(void); 5652e954a3Spd void i8253_start(void); 57