1 /* 2 * Copyright (c) 1992 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Ralph Campbell, and Kazumasa Utashiro of Software Research 7 * Associates, Inc. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)machConst.h 7.1 (Berkeley) 06/04/92 12 * 13 * machConst.h -- 14 * 15 * Machine dependent constants. 16 * 17 * Copyright (C) 1989 Digital Equipment Corporation. 18 * Permission to use, copy, modify, and distribute this software and 19 * its documentation for any purpose and without fee is hereby granted, 20 * provided that the above copyright notice appears in all copies. 21 * Digital Equipment Corporation makes no representations about the 22 * suitability of this software for any purpose. It is provided "as is" 23 * without express or implied warranty. 24 * 25 * from: $Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 26 * v 9.2 89/10/21 15:55:22 jhh Exp $ SPRITE (DECWRL) 27 * from: $Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 28 * v 1.2 89/08/15 18:28:21 rab Exp $ SPRITE (DECWRL) 29 * from: $Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 30 * v 9.1 89/09/18 17:33:00 shirriff Exp $ SPRITE (DECWRL) 31 */ 32 33 #ifndef _MACHCONST 34 #define _MACHCONST 35 36 #define MACH_KUSEG_ADDR 0x0 37 #define MACH_CACHED_MEMORY_ADDR 0x80000000 38 #define MACH_UNCACHED_MEMORY_ADDR 0xa0000000 39 #define MACH_KSEG2_ADDR 0xc0000000 40 41 #define MACH_CACHED_TO_PHYS(x) MACH_UNMAPPED_TO_PHYS(x) 42 #define MACH_UNCACHED_TO_PHYS(x) MACH_UNMAPPED_TO_PHYS(x) 43 #define MACH_UNMAPPED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 44 45 #define MACH_PHYS_TO_CACHED(x) ((unsigned)(x) | MACH_CACHED_MEMORY_ADDR) 46 #define MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR) 47 48 #define MACH_CACHED_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR) 49 #define MACH_UNCACHED_TO_CACHED(x) ((unsigned)(x) & 0x9ffffffff) 50 51 #define BETWEEN(x,a,b) ((unsigned)(x) >= (a) && (unsigned)(x) < (b)) 52 53 #define MACH_IS_UNMAPPED(x) \ 54 BETWEEN(x, MACH_CACHED_MEMORY_ADDR, MACH_KSEG2_ADDR) 55 #define MACH_IS_CACHED(x) \ 56 BETWEEN(x, MACH_CACHED_MEMORY_ADDR, MACH_UNCACHED_MEMORY_ADDR) 57 #define MACH_IS_UNCACHED(x) \ 58 BETWEEN(x, MACH_UNCACHED_MEMORY_ADDR, MACH_KSEG2_ADDR) 59 #define MACH_IS_MAPPED(x) \ 60 BETWEEN(x, MACH_CACHED_MEMORY_ADDR, MACH_KSEG2_ADDR) 61 #define MACH_IS_USPACE(x) \ 62 ((unsigned)(x) < MACH_CACHED_MEMORY_ADDR) 63 64 #ifdef sony_news 65 #define MACH_CODE_START 0x80001000 66 #define MACH_RESERVED_ADDR 0xb3000000 /* KU:XXX need this? */ 67 #define MACH_KERNWORK_ADDR 0x800001c0 68 #define MACH_MAXMEMSIZE_ADDR MACH_KERNWORK_ADDR + 0 * 4 69 #define MACH_BOOTSW_ADDR MACH_KERNWORK_ADDR + 1 * 4 70 #define MACH_BOOTDEV_ADDR MACH_KERNWORK_ADDR + 2 * 4 71 #define MACH_HOWTO_ADDR MACH_KERNWORK_ADDR + 3 * 4 72 #endif 73 74 #ifdef DS3100 75 #define MACH_CODE_START 0x80030000 76 #define MACH_MAX_MEM_ADDR 0xa1800000 77 #define MACH_CACHED_FRAME_BUFFER_ADDR 0x8fc00000 78 #define MACH_UNCACHED_FRAME_BUFFER_ADDR 0xafc00000 79 #define MACH_PLANE_MASK_ADDR 0xb0000000 80 #define MACH_CURSOR_REG_ADDR 0xb1000000 81 #define MACH_COLOR_MAP_ADDR 0xb2000000 82 #define MACH_RESERVED_ADDR 0xb3000000 83 #define MACH_WRITE_ERROR_ADDR 0xb7000000 84 #define MACH_NETWORK_INTERFACE_ADDR 0xb8000000 85 #define MACH_NETWORK_BUFFER_ADDR 0xb9000000 86 #define MACH_SCSI_INTERFACE_ADDR 0xba000000 87 #define MACH_SCSI_BUFFER_ADDR 0xbb000000 88 #define MACH_SERIAL_INTERFACE_ADDR 0xbc000000 89 #define MACH_CLOCK_ADDR 0xbd000000 90 #define MACH_SYS_CSR_ADDR 0xbe000000 91 #endif 92 93 #ifdef DS5000 94 #define MACH_CODE_START 0x80030000 95 #define MACH_MAX_MEM_ADDR 0xbe000000 96 #define MACH_RESERVED_ADDR 0xbfc80000 97 #define MACH_CHKSYN_ADDR 0xbfd00000 98 #define MACH_ERROR_ADDR 0xbfd80000 99 #define MACH_SERIAL_INTERFACE_ADDR 0xbfe00000 100 #define MACH_CLOCK_ADDR 0xbfe80000 101 #define MACH_SYS_CSR_ADDR 0xbff00000 102 #endif 103 104 /* 105 * The bits in the cause register. 106 * 107 * MACH_CR_BR_DELAY Exception happened in branch delay slot. 108 * MACH_CR_COP_ERR Coprocessor error. 109 * Interrupt pending bits defined below. 110 * MACH_CR_EXC_CODE The exception type (see exception codes below). 111 */ 112 #define MACH_CR_BR_DELAY 0x80000000 113 #define MACH_CR_COP_ERR 0x30000000 114 #define MACH_CR_EXC_CODE 0x0000003C 115 #define MACH_CR_EXC_CODE_SHIFT 2 116 117 /* 118 * The bits in the status register. All bits are active when set to 1. 119 * 120 * MACH_SR_CO_USABILITY Control the usability of the four coprocessors. 121 * MACH_SR_BOOT_EXC_VEC Use alternate exception vectors. 122 * MACH_SR_TLB_SHUTDOWN TLB disabled. 123 * MACH_SR_PARITY_ERR Parity error. 124 * MACH_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 125 * MACH_SR_PARITY_ZERO Zero replaces outgoing parity bits. 126 * MACH_SR_SWAP_CACHES Swap I-cache and D-cache. 127 * MACH_SR_ISOL_CACHES Isolate D-cache from main memory. 128 * Interrupt enable bits defined below. 129 * MACH_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 130 * MACH_SR_INT_ENA_OLD Old interrupt enable bit. 131 * MACH_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 132 * MACH_SR_INT_ENA_PREV Previous interrupt enable bit. 133 * MACH_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 134 * MACH_SR_INT_ENA_CUR Current interrupt enable bit. 135 */ 136 #define MACH_SR_COP_USABILITY 0xf0000000 137 #define MACH_SR_COP_0_BIT 0x10000000 138 #define MACH_SR_COP_1_BIT 0x20000000 139 #define MACH_SR_BOOT_EXC_VEC 0x00400000 140 #define MACH_SR_TLB_SHUTDOWN 0x00200000 141 #define MACH_SR_PARITY_ERR 0x00100000 142 #define MACH_SR_CACHE_MISS 0x00080000 143 #define MACH_SR_PARITY_ZERO 0x00040000 144 #define MACH_SR_SWAP_CACHES 0x00020000 145 #define MACH_SR_ISOL_CACHES 0x00010000 146 #define MACH_SR_KU_OLD 0x00000020 147 #define MACH_SR_INT_ENA_OLD 0x00000010 148 #define MACH_SR_KU_PREV 0x00000008 149 #define MACH_SR_INT_ENA_PREV 0x00000004 150 #define MACH_SR_KU_CUR 0x00000002 151 #define MACH_SR_INT_ENA_CUR 0x00000001 152 #define MACH_SR_MBZ 0x0f8000c0 153 154 /* 155 * The interrupt masks. 156 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 157 */ 158 #define MACH_INT_MASK 0xff00 159 #define MACH_INT_MASK_5 0x8000 160 #define MACH_INT_MASK_4 0x4000 161 #define MACH_INT_MASK_3 0x2000 162 #define MACH_INT_MASK_2 0x1000 163 #define MACH_INT_MASK_1 0x0800 164 #define MACH_INT_MASK_0 0x0400 165 #define MACH_HARD_INT_MASK 0xfc00 166 #define MACH_SOFT_INT_MASK 0x0300 167 #define MACH_SOFT_INT_MASK_1 0x0200 168 #define MACH_SOFT_INT_MASK_0 0x0100 169 170 #if defined(news3400) && !defined(PMAXSPL) 171 #define MACH_SPL_MASK_8 0x0000 172 #define MACH_SPL_MASK_7 MACH_SPL_MASK_8 | MACH_INT_MASK_5 173 #define MACH_SPL_MASK_6 MACH_SPL_MASK_7 | MACH_INT_MASK_4 174 #define MACH_SPL_MASK_5 MACH_SPL_MASK_6 | MACH_INT_MASK_3 175 #define MACH_SPL_MASK_4 MACH_SPL_MASK_5 | MACH_INT_MASK_2 176 #define MACH_SPL_MASK_3 MACH_SPL_MASK_4 | MACH_INT_MASK_1 177 #define MACH_SPL_MASK_2 MACH_SPL_MASK_3 | MACH_INT_MASK_0 178 #define MACH_SPL_MASK_1 MACH_SPL_MASK_2 | MACH_SOFT_INT_MASK_1 179 #define MACH_SPL_MASK_0 MACH_SPL_MASK_1 | MACH_SOFT_INT_MASK_0 180 #endif 181 182 /* 183 * The system control status register. 184 */ 185 #ifdef DS3100 186 #define MACH_CSR_MONO 0x0800 187 #define MACH_CSR_MEM_ERR 0x0400 188 #define MACH_CSR_VINT 0x0200 189 #define MACH_CSR_MBZ 0x9800 190 #endif 191 192 #ifdef DS5000 193 #define MACH_CSR_IOINT_MASK 0x000000FF 194 #define MACH_CSR_BAUD38 0x00000100 195 #define MACH_CSR_DIAGDN 0x00000200 196 #define MACH_CSR_BNK32M 0x00000400 197 #define MACH_CSR_TXDIS 0x00000800 198 #define MACH_CSR_LEDIAG 0x00001000 199 #define MACH_CSR_CORRECT 0x00002000 200 #define MACH_CSR_ECCMD 0x0000C000 201 #define MACH_CSR_IOINTEN_MASK 0x00FF0000 202 #define MACH_CSR_IOINTEN_SHIFT 16 203 #define MACH_CSR_NRMMOD 0x01000000 204 #define MACH_CSR_REFEVEN 0x02000000 205 #define MACH_CSR_PRSVNVR 0x04000000 206 #define MACH_CSR_PSWARN 0x08000000 207 #define MACH_CSR_MBZ 0xFF000000 208 #endif 209 210 /* 211 * The bits in the context register. 212 */ 213 #define MACH_CNTXT_PTE_BASE 0xFFE00000 214 #define MACH_CNTXT_BAD_VPN 0x001FFFFC 215 216 /* 217 * Location of exception vectors. 218 */ 219 #define MACH_RESET_EXC_VEC 0xBFC00000 220 #define MACH_UTLB_MISS_EXC_VEC 0x80000000 221 #define MACH_GEN_EXC_VEC 0x80000080 222 223 /* 224 * Coprocessor 0 registers: 225 * 226 * MACH_COP_0_TLB_INDEX TLB index. 227 * MACH_COP_0_TLB_RANDOM TLB random. 228 * MACH_COP_0_TLB_LOW TLB entry low. 229 * MACH_COP_0_TLB_CONTEXT TLB context. 230 * MACH_COP_0_BAD_VADDR Bad virtual address. 231 * MACH_COP_0_TLB_HI TLB entry high. 232 * MACH_COP_0_STATUS_REG Status register. 233 * MACH_COP_0_CAUSE_REG Exception cause register. 234 * MACH_COP_0_EXC_PC Exception PC. 235 * MACH_COP_0_PRID Processor revision identifier. 236 */ 237 #define MACH_COP_0_TLB_INDEX $0 238 #define MACH_COP_0_TLB_RANDOM $1 239 #define MACH_COP_0_TLB_LOW $2 240 #define MACH_COP_0_TLB_CONTEXT $4 241 #define MACH_COP_0_BAD_VADDR $8 242 #define MACH_COP_0_TLB_HI $10 243 #define MACH_COP_0_STATUS_REG $12 244 #define MACH_COP_0_CAUSE_REG $13 245 #define MACH_COP_0_EXC_PC $14 246 #define MACH_COP_0_PRID $15 247 248 /* 249 * Values for the code field in a break instruction. 250 */ 251 #define MACH_BREAK_INSTR 0x0000000d 252 #define MACH_BREAK_VAL_MASK 0x03ff0000 253 #define MACH_BREAK_VAL_SHIFT 16 254 #define MACH_BREAK_KDB_VAL 512 255 #define MACH_BREAK_SSTEP_VAL 513 256 #define MACH_BREAK_BRKPT_VAL 514 257 #define MACH_BREAK_KDB (MACH_BREAK_INSTR | \ 258 (MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT)) 259 #define MACH_BREAK_SSTEP (MACH_BREAK_INSTR | \ 260 (MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT)) 261 #define MACH_BREAK_BRKPT (MACH_BREAK_INSTR | \ 262 (MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT)) 263 264 /* 265 * Mininum and maximum cache sizes. 266 */ 267 #define MACH_MIN_CACHE_SIZE (16 * 1024) 268 #define MACH_MAX_CACHE_SIZE (256 * 1024) 269 270 /* 271 * The floating point version and status registers. 272 */ 273 #define MACH_FPC_ID $0 274 #define MACH_FPC_CSR $31 275 276 /* 277 * The floating point coprocessor status register bits. 278 */ 279 #define MACH_FPC_ROUNDING_BITS 0x00000003 280 #define MACH_FPC_ROUND_RN 0x00000000 281 #define MACH_FPC_ROUND_RZ 0x00000001 282 #define MACH_FPC_ROUND_RP 0x00000002 283 #define MACH_FPC_ROUND_RM 0x00000003 284 #define MACH_FPC_STICKY_BITS 0x0000007c 285 #define MACH_FPC_STICKY_INEXACT 0x00000004 286 #define MACH_FPC_STICKY_UNDERFLOW 0x00000008 287 #define MACH_FPC_STICKY_OVERFLOW 0x00000010 288 #define MACH_FPC_STICKY_DIV0 0x00000020 289 #define MACH_FPC_STICKY_INVALID 0x00000040 290 #define MACH_FPC_ENABLE_BITS 0x00000f80 291 #define MACH_FPC_ENABLE_INEXACT 0x00000080 292 #define MACH_FPC_ENABLE_UNDERFLOW 0x00000100 293 #define MACH_FPC_ENABLE_OVERFLOW 0x00000200 294 #define MACH_FPC_ENABLE_DIV0 0x00000400 295 #define MACH_FPC_ENABLE_INVALID 0x00000800 296 #define MACH_FPC_EXCEPTION_BITS 0x0003f000 297 #define MACH_FPC_EXCEPTION_INEXACT 0x00001000 298 #define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000 299 #define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000 300 #define MACH_FPC_EXCEPTION_DIV0 0x00008000 301 #define MACH_FPC_EXCEPTION_INVALID 0x00010000 302 #define MACH_FPC_EXCEPTION_UNIMPL 0x00020000 303 #define MACH_FPC_COND_BIT 0x00800000 304 #define MACH_FPC_MBZ_BITS 0xff7c0000 305 306 /* 307 * Constants to determine if have a floating point instruction. 308 */ 309 #define MACH_OPCODE_SHIFT 26 310 #define MACH_OPCODE_C1 0x11 311 312 /* 313 * The low part of the TLB entry. 314 */ 315 #define VMMACH_TLB_PF_NUM 0xfffff000 316 #define VMMACH_TLB_NON_CACHEABLE_BIT 0x00000800 317 #define VMMACH_TLB_MOD_BIT 0x00000400 318 #define VMMACH_TLB_VALID_BIT 0x00000200 319 #define VMMACH_TLB_GLOBAL_BIT 0x00000100 320 321 #define VMMACH_TLB_PHYS_PAGE_SHIFT 12 322 323 /* 324 * The high part of the TLB entry. 325 */ 326 #define VMMACH_TLB_VIRT_PAGE_NUM 0xfffff000 327 #define VMMACH_TLB_PID 0x00000fc0 328 #define VMMACH_TLB_PID_SHIFT 6 329 #define VMMACH_TLB_VIRT_PAGE_SHIFT 12 330 331 /* 332 * The shift to put the index in the right spot. 333 */ 334 #define VMMACH_TLB_INDEX_SHIFT 8 335 336 /* 337 * The number of TLB entries and the first one that write random hits. 338 */ 339 #define VMMACH_NUM_TLB_ENTRIES 64 340 #define VMMACH_FIRST_RAND_ENTRY 8 341 342 /* 343 * The number of process id entries. 344 */ 345 #define VMMACH_NUM_PIDS 64 346 347 /* 348 * TLB probe return codes. 349 */ 350 #define VMMACH_TLB_NOT_FOUND 0 351 #define VMMACH_TLB_FOUND 1 352 #define VMMACH_TLB_FOUND_WITH_PATCH 2 353 #define VMMACH_TLB_PROBE_ERROR 3 354 355 /* 356 * Kernel virtual address for user page table entries 357 * (i.e., the address for the context register). 358 */ 359 #define VMMACH_PTE_BASE 0xFFC00000 360 361 #endif /* _MACHCONST */ 362