1 /* 2 * Copyright (c) 1988 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Computer Consoles Inc. 7 * 8 * Redistribution and use in source and binary forms are permitted 9 * provided that the above copyright notice and this paragraph are 10 * duplicated in all such forms and that any documentation, 11 * advertising materials, and other materials related to such 12 * distribution and use acknowledge that the software was developed 13 * by the University of California, Berkeley. The name of the 14 * University may not be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 18 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 19 * 20 * @(#)dr.c 7.7 (Berkeley) 06/21/90 21 */ 22 23 #include "dr.h" 24 #if NDR > 0 25 /* 26 * DRV11-W DMA interface driver. 27 * 28 * UNTESTED WITH 4.3 29 */ 30 #include "machine/mtpr.h" 31 #include "machine/pte.h" 32 33 #include "param.h" 34 #include "conf.h" 35 #include "user.h" 36 #include "proc.h" 37 #include "map.h" 38 #include "ioctl.h" 39 #include "buf.h" 40 #include "vm.h" 41 #include "kernel.h" 42 43 #include "../tahoevba/vbavar.h" 44 #include "../tahoevba/drreg.h" 45 46 #define YES 1 47 #define NO 0 48 49 struct vba_device *drinfo[NDR]; 50 struct dr_aux dr_aux[NDR]; 51 52 unsigned drminphys(); 53 int drprobe(), drintr(), drattach(), drtimo(), drrwtimo(); 54 int drstrategy(); 55 extern struct vba_device *drinfo[]; 56 static long drstd[] = { 0 }; 57 struct vba_driver drdriver = 58 { drprobe, 0, drattach, 0, drstd, "rs", drinfo }; 59 60 #define RSUNIT(dev) (minor(dev) & 7) 61 #define SPL_UP spl5 62 63 /* -------- Per-unit data -------- */ 64 65 extern struct dr_aux dr_aux[]; 66 67 #ifdef DR_DEBUG 68 long DR11 = 0; 69 #endif 70 71 drprobe(reg, vi) 72 caddr_t reg; 73 struct vba_device *vi; 74 { 75 register int br, cvec; /* must be r12, r11 */ 76 struct rsdevice *dr; 77 78 #ifdef lint 79 br = 0; cvec = br; br = cvec; 80 drintr(0); 81 #endif 82 if (badaddr(reg, 2)) 83 return (0); 84 dr = (struct rsdevice *)reg; 85 dr->dr_intvect = --vi->ui_hd->vh_lastiv; 86 #ifdef DR_DEBUG 87 printf("dprobe: Set interrupt vector %lx and init\n",dr->dr_intvec); 88 #endif 89 /* generate interrupt here for autoconfig */ 90 dr->dr_cstat = MCLR; /* init board and device */ 91 #ifdef DR_DEBUG 92 printf("drprobe: Initial status %lx\n", dr->dr_cstat); 93 #endif 94 br = 0x18, cvec = dr->dr_intvect; /* XXX */ 95 return (sizeof (struct rsdevice)); /* DR11 exist */ 96 } 97 98 /* ARGSUSED */ 99 drattach(ui) 100 struct vba_device *ui; 101 { 102 register struct dr_aux *rsd; 103 104 rsd = &dr_aux[ui->ui_unit]; 105 rsd->dr_flags = DR_PRES; /* This dr11 is present */ 106 rsd->dr_addr = (struct rsdevice *)ui->ui_addr; /* Save addr of this dr11 */ 107 rsd->dr_istat = 0; 108 rsd->dr_bycnt = 0; 109 rsd->dr_cmd = 0; 110 rsd->currenttimo = 0; 111 } 112 113 /*ARGSUSED*/ 114 dropen(dev, flag) 115 dev_t dev; 116 int flag; 117 { 118 register int unit = RSUNIT(dev); 119 register struct rsdevice *dr; 120 register struct dr_aux *rsd; 121 122 if (drinfo[unit] == 0 || !drinfo[unit]->ui_alive) 123 return (ENXIO); 124 dr = RSADDR(unit); 125 rsd = &dr_aux[unit]; 126 if (rsd->dr_flags & DR_OPEN) { 127 #ifdef DR_DEBUG 128 printf("\ndropen: dr11 unit %ld already open",unit); 129 #endif 130 return (ENXIO); /* DR11 already open */ 131 } 132 rsd->dr_flags |= DR_OPEN; /* Mark it OPEN */ 133 rsd->dr_istat = 0; /* Clear status of previous interrupt */ 134 rsd->rtimoticks = hz; /* Set read no stall timout to 1 sec */ 135 rsd->wtimoticks = hz*60; /* Set write no stall timout to 1 min */ 136 dr->dr_cstat = DR_ZERO; /* Clear function & latches */ 137 dr->dr_pulse = (RDMA | RATN); /* clear leftover attn & e-o-r flags */ 138 drtimo(dev); /* start the self kicker */ 139 return (0); 140 } 141 142 drclose (dev) 143 dev_t dev; 144 { 145 register int unit = RSUNIT(dev); 146 register struct dr_aux *dra; 147 register struct rsdevice *rs; 148 register short s; 149 150 dra = &dr_aux[unit]; 151 if ((dra->dr_flags & DR_OPEN) == 0) { 152 #ifdef DR_DEBUG 153 printf("\ndrclose: DR11 device %ld not open",unit); 154 #endif 155 return; 156 } 157 dra->dr_flags &= ~(DR_OPEN|DR_ACTV); 158 rs = dra->dr_addr; 159 s = SPL_UP(); 160 rs->dr_cstat = DR_ZERO; 161 if (dra->dr_buf.b_flags & B_BUSY) { 162 dra->dr_buf.b_flags &= ~B_BUSY; 163 wakeup((caddr_t)&dra->dr_buf.b_flags); 164 } 165 splx(s); 166 return (0); 167 } 168 169 170 /* drread() works exactly like drwrite() except that the 171 B_READ flag is used when physio() is called 172 */ 173 drread (dev, uio) 174 dev_t dev; 175 struct uio *uio; 176 { register struct dr_aux *dra; 177 register struct buf *bp; 178 register int spl, err; 179 register int unit = RSUNIT(dev); 180 181 if (uio->uio_iov->iov_len <= 0 || /* Negative count */ 182 uio->uio_iov->iov_len & 1 || /* odd count */ 183 (int)uio->uio_iov->iov_base & 1) /* odd destination address */ 184 return (EINVAL); 185 #ifdef DR_DEBUG 186 if (DR11 & 8) 187 printf("\ndrread: (len:%ld)(base:%lx)", 188 uio->uio_iov->iov_len,(int)uio->uio_iov->iov_base); 189 #endif 190 dra = &dr_aux[RSUNIT(dev)]; 191 dra->dr_op = DR_READ; 192 bp = &dra->dr_buf; 193 bp->b_resid = 0; 194 if (dra->dr_flags & DR_NORSTALL) { 195 /* 196 * We are in no stall mode, start the timer, 197 * raise IPL so nothing can stop us once the 198 * timer's running 199 */ 200 spl = SPL_UP(); 201 timeout(drrwtimo, (caddr_t)((dra->currenttimo<<8) | unit), 202 (int)dra->rtimoticks); 203 err = physio(drstrategy, bp, dev,B_READ, drminphys, uio); 204 splx(spl); 205 if (err) 206 return (err); 207 dra->currenttimo++; /* Update current timeout number */ 208 /* Did we timeout */ 209 if (dra->dr_flags & DR_TMDM) 210 dra->dr_flags &= ~DR_TMDM; /* Clear timeout flag */ 211 return (err); 212 } 213 return (physio(drstrategy, bp, dev,B_READ, drminphys, uio)); 214 } 215 216 drwrite(dev, uio) 217 dev_t dev; 218 struct uio *uio; 219 { register struct dr_aux *dra; 220 register struct buf *bp; 221 register int unit = RSUNIT(dev); 222 int spl, err; 223 224 if (uio->uio_iov->iov_len <= 0 || uio->uio_iov->iov_len & 1 || 225 (int)uio->uio_iov->iov_base & 1) 226 return (EINVAL); 227 #ifdef DR_DEBUG 228 if (DR11 & 4) 229 printf("\ndrwrite: (len:%ld)(base:%lx)", 230 uio->uio_iov->iov_len,(int)uio->uio_iov->iov_base); 231 #endif 232 dra = &dr_aux[RSUNIT(dev)]; 233 dra->dr_op = DR_WRITE; 234 bp = &dra->dr_buf; 235 bp->b_resid = 0; 236 if (dra->dr_flags & DR_NOWSTALL) { 237 /* 238 * We are in no stall mode, start the timer, 239 * raise IPL so nothing can stop us once the 240 * timer's running 241 */ 242 spl = SPL_UP(); 243 timeout(drrwtimo,(caddr_t)((dra->currenttimo<<8) | unit), 244 (int)dra->wtimoticks); 245 err = physio (drstrategy, bp, dev,B_WRITE, drminphys, uio); 246 splx(spl); 247 if (err) 248 return (err); 249 dra->currenttimo++; /* Update current timeout number */ 250 /* Did we timeout */ 251 if (dra->dr_flags & DR_TMDM) 252 dra->dr_flags &= ~DR_TMDM; /* Clear timeout flag */ 253 return (err); 254 } 255 return (physio(drstrategy, bp, dev,B_WRITE, drminphys, uio)); 256 } 257 258 /* 259 * Routine used by calling program to issue commands to dr11 driver and 260 * through it to the device. 261 * It is also used to read status from the device and driver and to wait 262 * for attention interrupts. 263 * Status is returned in an 8 elements unsigned short integer array, the 264 * first two elements of the array are also used to pass arguments to 265 * drioctl() if required. 266 * The function bits to be written to the dr11 are included in the cmd 267 * argument. Even if they are not being written to the dr11 in a particular 268 * drioctl() call, they will update the copy of cmd that is stored in the 269 * driver. When drstrategy() is called, this updated copy is used if a 270 * deferred function bit write has been specified. The "side effect" of 271 * calls to the drioctl() requires that the last call prior to a read or 272 * write has an appropriate copy of the function bits in cmd if they are 273 * to be used in drstrategy(). 274 * When used as command value, the contents of data[0] is the command 275 * parameter. 276 */ 277 drioctl(dev, cmd, data) 278 dev_t dev; 279 int cmd; 280 long *data; 281 { 282 register int unit = RSUNIT(dev); 283 register struct dr_aux *dra; 284 register struct rsdevice *rsaddr = RSADDR(unit); 285 int s, error = 0; 286 u_short status; 287 long temp; 288 289 #ifdef DR_DEBUG 290 if (DR11 & 0x10) 291 printf("\ndrioctl: (dev:%lx)(cmd:%lx)(data:%lx)(data[0]:%lx)", 292 dev,cmd,data,data[0]); 293 #endif 294 dra = &dr_aux[unit]; 295 dra->dr_cmd = 0; /* Fresh copy; clear all previous flags */ 296 switch (cmd) { 297 298 case DRWAIT: /* Wait for attention interrupt */ 299 #ifdef DR_DEBUG 300 printf("\ndrioctl: wait for attention interrupt"); 301 #endif 302 s = SPL_UP(); 303 /* 304 * If the attention flag in dr_flags is set, it probably 305 * means that an attention has arrived by the time a 306 * previous DMA end-of-range interrupt was serviced. If 307 * ATRX is set, we will return with out sleeping, since 308 * we have received an attention since the last call to 309 * wait on attention. This may not be appropriate for 310 * some applications. 311 */ 312 if ((dra->dr_flags & DR_ATRX) == 0) { 313 dra->dr_flags |= DR_ATWT; /* Set waiting flag */ 314 /* 315 * Enable interrupt; use pulse reg. 316 * so function bits are not changed 317 */ 318 rsaddr->dr_pulse = IENB; 319 error = tsleep((caddr_t)&dra->dr_cmd, DRPRI | PCATCH, 320 devio, 0); 321 } 322 splx(s); 323 break; 324 325 case DRPIOW: /* Write to p-i/o register */ 326 rsaddr->dr_data = data[0]; 327 break; 328 329 case DRPACL: /* Send pulse to device */ 330 rsaddr->dr_pulse = FCN2; 331 break; 332 333 case DRDACL: /* Defer alco pulse until go */ 334 dra->dr_cmd |= DR_DACL; 335 break; 336 337 case DRPCYL: /* Set cycle with next go */ 338 dra->dr_cmd |= DR_PCYL; 339 break; 340 341 case DRDFCN: /* Update function with next go */ 342 dra->dr_cmd |= DR_DFCN; 343 break; 344 345 case DRRATN: /* Reset attention flag */ 346 rsaddr->dr_pulse = RATN; 347 break; 348 349 case DRRDMA: /* Reset DMA e-o-r flag */ 350 rsaddr->dr_pulse = RDMA; 351 break; 352 353 case DRSFCN: /* Set function bits */ 354 temp = data[0] & DR_FMSK; 355 /* 356 * This has a very important side effect -- It clears 357 * the interrupt enable flag. That is fine for this driver, 358 * but if it is desired to leave interrupt enable at all 359 * times, it will be necessary to read the status register 360 * first to get IENB, or carry a software flag that indicates 361 * whether interrupts are set, and or this into the control 362 * register value being written. 363 */ 364 rsaddr->dr_cstat = temp; 365 break; 366 367 case DRRPER: /* Clear parity flag */ 368 rsaddr->dr_pulse = RPER; 369 break; 370 371 case DRSETRSTALL: /* Set read stall mode. */ 372 dra->dr_flags &= (~DR_NORSTALL); 373 break; 374 375 case DRSETNORSTALL: /* Set no stall read mode. */ 376 dra->dr_flags |= DR_NORSTALL; 377 break; 378 379 case DRGETRSTALL: /* Returns true if in read stall mode */ 380 data[0] = (dra->dr_flags & DR_NORSTALL)? 0 : 1; 381 break; 382 383 case DRSETRTIMEOUT: /* Set read stall timeout (1/10 secs) */ 384 if (data[0] < 1) 385 error = EINVAL; 386 dra->rtimoticks = (data[0] * hz )/10; 387 break; 388 389 case DRGETRTIMEOUT: /* Return read stall timeout */ 390 data[0] = ((dra->rtimoticks)*10)/hz; 391 break; 392 393 case DRSETWSTALL: /* Set write stall mode. */ 394 dra->dr_flags &= (~DR_NOWSTALL); 395 break; 396 397 case DRSETNOWSTALL: /* Set write stall mode. */ 398 dra->dr_flags |= DR_NOWSTALL; 399 break; 400 401 case DRGETWSTALL: /* Return true if in write stall mode */ 402 data[0] = (dra->dr_flags & DR_NOWSTALL)? 0 : 1; 403 break; 404 405 case DRSETWTIMEOUT: /* Set write stall timeout (1/10's) */ 406 if (data[0] < 1) 407 error = EINVAL; 408 dra->wtimoticks = (data[0] * hz )/10; 409 break; 410 411 case DRGETWTIMEOUT: /* Return write stall timeout */ 412 data[0] = ((dra->wtimoticks)*10)/hz; 413 break; 414 415 case DRWRITEREADY: /* Return true if can write data */ 416 data[0] = (rsaddr->dr_cstat & STTA)? 1 : 0; 417 break; 418 419 case DRREADREADY: /* Return true if data to be read */ 420 data[0] = (rsaddr->dr_cstat & STTB)? 1 : 0; 421 break; 422 423 case DRBUSY: /* Return true if device busy */ 424 /* 425 * Internally this is the DR11-W 426 * STAT C bit, but there is a bug in the Omega 500/FIFO 427 * interface board that it cannot drive this signal low 428 * for certain DR11-W ctlr such as the Ikon. We use the 429 * REDY signal of the CSR on the Ikon DR11-W instead. 430 */ 431 #ifdef notdef 432 data[0] = (rsaddr->dr_cstat & STTC)? 1 : 0; 433 #else 434 data[0] = ((rsaddr->dr_cstat & REDY)? 0 : 1); 435 #endif 436 break; 437 438 case DRRESET: /* Reset device */ 439 /* Reset DMA ATN RPER flag */ 440 rsaddr->dr_pulse = (MCLR|RDMA|RATN|RPER); 441 DELAY(0x1f000); 442 while ((rsaddr->dr_cstat & REDY) == 0 && error == 0) 443 /* Wakeup by drtimo() */ 444 error = tsleep((caddr_t)dra, DRPRI | PCATCH, devio, 0); 445 dra->dr_istat = 0; 446 dra->dr_cmd = 0; 447 dra->currenttimo = 0; 448 break; 449 450 case DR11STAT: { /* Copy back dr11 status to user */ 451 register struct dr11io *dr = (struct dr11io *)data; 452 dr->arg[0] = dra->dr_flags; 453 dr->arg[1] = rsaddr->dr_cstat; 454 dr->arg[2] = dra->dr_istat; /* Status at last interrupt */ 455 dr->arg[3] = rsaddr->dr_data; /* P-i/o input data */ 456 status = (u_short)((rsaddr->dr_addmod << 8) & 0xff00); 457 dr->arg[4] = status | (u_short)(rsaddr->dr_intvect & 0xff); 458 dr->arg[5] = rsaddr->dr_range; 459 dr->arg[6] = rsaddr->dr_rahi; 460 dr->arg[7] = rsaddr->dr_ralo; 461 break; 462 } 463 case DR11LOOP: /* Perform loopback test */ 464 /* 465 * NB: MUST HAVE LOOPBACK CABLE ATTACHED -- 466 * Test results are printed on system console 467 */ 468 if (error = suser(u.u_cred, &u.u_acflag)) 469 break; 470 dr11loop(rsaddr, dra, unit); 471 break; 472 473 default: 474 return (EINVAL); 475 } 476 #ifdef DR_DEBUG 477 if (DR11 & 0x10) 478 printf("**** (data[0]:%lx)",data[0]); 479 #endif 480 return (error); 481 } 482 483 #define NPAT 2 484 #define DMATBL 20 485 u_short tstpat[DMATBL] = { 0xAAAA, 0x5555}; 486 long DMAin = 0; 487 488 /* 489 * Perform loopback test -- MUST HAVE LOOPBACK CABLE ATTACHED 490 * Test results are printed on system console 491 */ 492 dr11loop(dr, dra, unit) 493 struct rsdevice *dr; 494 struct dr_aux *dra; 495 int unit; 496 { 497 register long result, ix; 498 long addr, wait; 499 500 dr->dr_cstat = MCLR; /* Clear board & device, disable intr */ 501 printf("\n\t ----- DR11 unit %ld loopback test -----", unit); 502 printf("\n\t Program I/O ..."); 503 for (ix=0;ix<NPAT;ix++) { 504 dr->dr_data = tstpat[ix]; /* Write to Data out register */ 505 result = dr->dr_data & 0xFFFF; /* Read it back */ 506 if (result != tstpat[ix]) { 507 printf("Failed, expected : %lx --- actual : %lx", 508 tstpat[ix], result); 509 return; 510 } 511 } 512 printf("OK\n\t Functions & Status Bits ..."); 513 dr->dr_cstat = (FCN1 | FCN3); 514 result = dr->dr_cstat & 0xffff; /* Read them back */ 515 if ((result & (STTC | STTA)) != (STTC |STTA)) { 516 printf("Failed, expected : %lx --- actual : %lx, ISR:%lx", 517 (STTA|STTC), (result & (STTA|STTC)), result); 518 return; 519 } 520 dr->dr_cstat = FCN2; 521 result = dr->dr_cstat & 0xffff; /* Read them back */ 522 if ((result & STTB) != STTB) { 523 printf("Failed, expected : %lx --- actual : %lx, ISR:%lx", 524 STTB, (result & STTB), result); 525 return; 526 } 527 printf("OK\n\t DMA output ..."); 528 if (DMAin) 529 goto dmain; 530 /* Initialize DMA data buffer */ 531 for (ix=0; ix<DMATBL; ix++) 532 tstpat[ix] = 0xCCCC + ix; 533 tstpat[DMATBL-1] = 0xCCCC; /* Last word output */ 534 /* Setup normal DMA */ 535 addr = (long)vtoph((struct proc *)0, (unsigned)tstpat); 536 dr->dr_walo = (addr >> 1) & 0xffff; 537 dr->dr_wahi = (addr >> 17) & 0x7fff; 538 /* Set DMA range count: (number of words - 1) */ 539 dr->dr_range = DMATBL - 1; 540 /* Set address modifier code to be used for DMA access to memory */ 541 dr->dr_addmod = DRADDMOD; 542 543 /* 544 * Clear dmaf and attf to assure a clean dma start, also disable 545 * attention interrupt 546 */ 547 dr->dr_pulse = RDMA|RATN|RMSK; /* Use pulse register */ 548 dr->dr_cstat = GO|CYCL; /* GO...... */ 549 550 /* Wait for DMA complete; REDY and DMAF are true in ISR */ 551 wait = 0; 552 while ((result=(dr->dr_cstat & (REDY|DMAF))) != (REDY|DMAF)) { 553 printf("\n\tWait for DMA complete...ISR : %lx", result); 554 if (++wait > 5) { 555 printf("\n\t DMA output fails...timeout!!, ISR:%lx", 556 result); 557 return; 558 } 559 } 560 result = dr->dr_data & 0xffff; /* Read last word output */ 561 if (result != 0xCCCC) { 562 printf("\n\t Fails, expected : %lx --- actual : %lx", 563 0xCCCC, result); 564 return; 565 } 566 printf("OK\n\t DMA input ..."); 567 dmain: 568 dr->dr_data = 0x1111; /* DMA input data */ 569 /* Setup normal DMA */ 570 addr = (long)vtoph((struct proc *)0, (unsigned)tstpat); 571 dr->dr_walo = (addr >> 1) & 0xffff; 572 dr->dr_wahi = (addr >> 17) & 0x7fff; 573 dr->dr_range = DMATBL - 1; 574 dr->dr_addmod = (char)DRADDMOD; 575 dr->dr_cstat = FCN1; /* Set FCN1 in ICR to DMA in*/ 576 if ((dra->dr_flags & DR_LOOPTST) == 0) { 577 /* Use pulse reg */ 578 dr->dr_pulse = RDMA|RATN|RMSK|CYCL|GO; 579 /* Wait for DMA complete; REDY and DMAF are true in ISR */ 580 wait = 0; 581 while ((result=(dr->dr_cstat & (REDY|DMAF))) != (REDY|DMAF)) { 582 printf("\n\tWait for DMA to complete...ISR:%lx",result); 583 if (++wait > 5) { 584 printf("\n\t DMA input timeout!!, ISR:%lx", 585 result); 586 return; 587 } 588 } 589 } else { 590 /* Enable DMA e-o-r interrupt */ 591 dr->dr_pulse = IENB|RDMA|RATN|CYCL|GO; 592 /* Wait for DMA complete; DR_LOOPTST is false in dra->dr_flags*/ 593 wait = 0; 594 while (dra->dr_flags & DR_LOOPTST) { 595 result = dr->dr_cstat & 0xffff; 596 printf("\n\tWait for DMA e-o-r intr...ISR:%lx", result); 597 if (++wait > 7) { 598 printf("\n\t DMA e-o-r timeout!!, ISR:%lx", 599 result); 600 dra->dr_flags &= ~DR_LOOPTST; 601 return; 602 } 603 } 604 dra->dr_flags |= DR_LOOPTST; 605 } 606 mtpr(P1DC, tstpat); /* Purge cache */ 607 mtpr(P1DC, 0x3ff+tstpat); 608 for (ix=0; ix<DMATBL; ix++) { 609 if (tstpat[ix] != 0x1111) { 610 printf("\n\t Fails, ix:%d, expected:%x --- actual:%x", 611 ix, 0x1111, tstpat[ix]); 612 return; 613 } 614 } 615 if ((dra->dr_flags & DR_LOOPTST) == 0) { 616 dra->dr_flags |= DR_LOOPTST; 617 printf(" OK..\n\tDMA end of range interrupt..."); 618 goto dmain; 619 } 620 printf(" OK..\n\tAttention interrupt...."); 621 dr->dr_pulse = IENB|RDMA; 622 dr->dr_pulse = FCN2; 623 /* Wait for ATTN interrupt; DR_LOOPTST is false in dra->dr_flags*/ 624 wait = 0; 625 while (dra->dr_flags & DR_LOOPTST) { 626 result = dr->dr_cstat & 0xffff; 627 printf("\n\tWait for Attention intr...ISR:%lx",result); 628 if (++wait > 7) { 629 printf("\n\t Attention interrupt timeout!!, ISR:%lx", 630 result); 631 dra->dr_flags &= ~DR_LOOPTST; 632 return; 633 } 634 } 635 dra->dr_flags &= ~DR_LOOPTST; 636 printf(" OK..\n\tDone..."); 637 } 638 639 /* Reset state on Unibus reset */ 640 /*ARGSUSED*/ 641 drreset(uban) 642 int uban; 643 { 644 645 } 646 647 /* 648 * An interrupt is caused either by an error, 649 * base address overflow, or transfer complete 650 */ 651 drintr(dr11) 652 int dr11; 653 { 654 register struct dr_aux *dra = &dr_aux[dr11]; 655 register struct rsdevice *rsaddr = RSADDR(dr11); 656 register struct buf *bp; 657 register short status; 658 659 status = rsaddr->dr_cstat & 0xffff; /* get board status register */ 660 dra->dr_istat = status; 661 #ifdef DR_DEBUG 662 if (DR11 & 2) 663 printf("\ndrintr: dr11 status : %lx",status & 0xffff); 664 #endif 665 if (dra->dr_flags & DR_LOOPTST) { /* doing loopback test */ 666 dra->dr_flags &= ~DR_LOOPTST; 667 return; 668 } 669 /* 670 * Make sure this is not a stray interrupt; at least one of dmaf or attf 671 * must be set. Note that if the dr11 interrupt enable latch is reset 672 * during a hardware interrupt ack sequence, and by the we get to this 673 * point in the interrupt code it will be 0. This is done to give the 674 * programmer some control over how the two more-or-less independent 675 * interrupt sources on the board are handled. 676 * If the attention flag is set when drstrategy() is called to start a 677 * dma read or write an interrupt will be generated as soon as the 678 * strategy routine enables interrupts for dma end-of-range. This will 679 * cause execution of the interrupt routine (not necessarily bad) and 680 * will cause the interrupt enable mask to be reset (very bad since the 681 * dma end-of-range condition will not be able to generate an interrupt 682 * when it occurs) causing the dma operation to time-out (even though 683 * the dma transfer will be done successfully) or hang the process if a 684 * software time-out capability is not implemented. One way to avoid 685 * this situation is to check for a pending attention interrupt (attf 686 * set) by calling drioctl() before doing a read or a write. For the 687 * time being this driver will solve the problem by clearing the attf 688 * flag in the status register before enabling interrupts in 689 * drstrategy(). 690 * 691 * **** The IKON 10084 for which this driver is written will set both 692 * attf and dmaf if dma is terminated by an attention pulse. This will 693 * cause a wakeup(&dr_aux), which will be ignored since it is not being 694 * waited on, and an iodone(bp) which is the desired action. Some other 695 * dr11 emulators, in particular the IKON 10077 for the Multibus, donot 696 * dmaf in this case. This may require some addtional code in the inter- 697 * rupt routine to ensure that en iodone(bp) is issued when dma is term- 698 * inated by attention. 699 */ 700 bp = dra->dr_actf; 701 if ((status & (ATTF | DMAF)) == 0) { 702 printf("dr%d: stray interrupt, status=%x", dr11, status); 703 return; 704 } 705 if (status & DMAF) { /* End-of-range interrupt */ 706 dra->dr_flags |= DR_DMAX; 707 708 #ifdef DR_DEBUG 709 if (DR11 & 2) 710 printf("\ndrintr: e-o-r interrupt,cstat:%lx,dr_flags:%lx", 711 status&0xffff, dra->dr_flags & DR_ACTV); 712 #endif 713 if ((dra->dr_flags & DR_ACTV) == 0) { 714 /* We are not doing DMA !! */ 715 bp->b_flags |= B_ERROR; 716 } else { 717 if (dra->dr_op == DR_READ) 718 mtpr(P1DC, bp->b_un.b_addr); 719 dra->dr_bycnt -= bp->b_bcount; 720 if (dra->dr_bycnt >0) { 721 bp->b_un.b_addr += bp->b_bcount; 722 bp->b_bcount = (dra->dr_bycnt > NBPG) ? NBPG: 723 dra->dr_bycnt; 724 drstart(rsaddr, dra, bp); 725 return; 726 } 727 } 728 dra->dr_flags &= ~DR_ACTV; 729 wakeup((caddr_t)dra); /* Wakeup waiting in drwait() */ 730 rsaddr->dr_pulse = (RPER|RDMA|RATN); /* reset dma e-o-r flag */ 731 } 732 /* 733 * Now test for attention interrupt -- It may be set in addition to 734 * the dma e-o-r interrupt. If we get one we will issue a wakeup to 735 * the drioctl() routine which is presumable waiting for one. 736 * The program may have to monitor the attention interrupt received 737 * flag in addition to doing waits for the interrupt. Futhermore, 738 * interrupts are not enabled unless dma is in progress or drioctl() 739 * has been called to wait for attention -- this may produce some 740 * strange results if attf is set on the dr11 when a read or a write 741 * is initiated, since that will enables interrupts. 742 * **** The appropriate code for this interrupt routine will probably 743 * be rather application dependent. 744 */ 745 if (status & ATTF) { 746 dra->dr_flags |= DR_ATRX; 747 dra->dr_flags &= ~DR_ATWT; 748 rsaddr->dr_cstat = RATN; /* reset attention flag */ 749 /* 750 * Some applications which use attention to terminate 751 * dma may also want to issue an iodone() here to 752 * wakeup physio(). 753 */ 754 wakeup((caddr_t)&dra->dr_cmd); 755 } 756 } 757 758 unsigned 759 drminphys(bp) 760 struct buf *bp; 761 { 762 763 if (bp->b_bcount > 65536) 764 bp->b_bcount = 65536; 765 } 766 767 /* 768 * This routine performs the device unique operations on the DR11W 769 * it is passed as an argument to and invoked by physio 770 */ 771 drstrategy (bp) 772 register struct buf *bp; 773 { 774 register int s; 775 int unit = RSUNIT(bp->b_dev); 776 register struct rsdevice *rsaddr = RSADDR(unit); 777 register struct dr_aux *dra = &dr_aux[unit]; 778 register int ok; 779 #ifdef DR_DEBUG 780 register char *caddr; 781 long drva(); 782 #endif 783 784 if ((dra->dr_flags & DR_OPEN) == 0) { /* Device not open */ 785 bp->b_error = ENXIO; 786 bp->b_flags |= B_ERROR; 787 iodone (bp); 788 return; 789 } 790 while (dra->dr_flags & DR_ACTV) 791 /* Device is active; should never be in here... */ 792 (void) tsleep((caddr_t)&dra->dr_flags, DRPRI, devio, 0); 793 dra->dr_actf = bp; 794 #ifdef DR_DEBUG 795 drva(dra, bp->b_proc, bp->b_un.b_addr, bp->b_bcount); 796 #endif 797 dra->dr_oba = bp->b_un.b_addr; /* Save original addr, count */ 798 dra->dr_obc = bp->b_bcount; 799 dra->dr_bycnt = bp->b_bcount; /* Save xfer count used by drintr() */ 800 if ((((long)bp->b_un.b_addr & 0x3fffffff) >> PGSHIFT) != 801 ((((long)bp->b_un.b_addr & 0x3fffffff) + bp->b_bcount) >> PGSHIFT)) 802 bp->b_bcount = NBPG - (((long)bp->b_un.b_addr) & PGOFSET); 803 dra->dr_flags |= DR_ACTV; /* Mark active (use in intr handler) */ 804 s = SPL_UP(); 805 drstart(rsaddr,dra,bp); 806 splx(s); 807 ok = drwait(rsaddr,dra); 808 #ifdef DR_DEBUG 809 if (DR11 & 0x40) { 810 caddr = (char *)dra->dr_oba; 811 if (dra->dr_op == DR_READ) 812 printf("\nAfter read: (%lx)(%lx)", 813 caddr[0]&0xff, caddr[1]&0xff); 814 } 815 #endif 816 dra->dr_flags &= ~DR_ACTV; /* Clear active flag */ 817 bp->b_un.b_addr = dra->dr_oba; /* Restore original addr, count */ 818 bp->b_bcount = dra->dr_obc; 819 if (!ok) 820 bp->b_flags |= B_ERROR; 821 /* Mark buffer B_DONE,so physstrat() in ml/machdep.c won't sleep */ 822 iodone(bp); 823 wakeup((caddr_t)&dra->dr_flags); 824 /* 825 * Return to the calling program (physio()). Physio() will sleep 826 * until awaken by a call to iodone() in the interupt handler -- 827 * which will be called by the dispatcher when it receives dma 828 * end-of-range interrupt. 829 */ 830 } 831 832 drwait(rs, dr) 833 register struct rsdevice *rs; 834 register struct dr_aux *dr; 835 { 836 int s; 837 838 s = SPL_UP(); 839 while (dr->dr_flags & DR_ACTV) 840 (void) tsleep((caddr_t)dr, DRPRI, devio, 0); 841 splx(s); 842 if (dr->dr_flags & DR_TMDM) { /* DMA timed out */ 843 dr->dr_flags &= ~DR_TMDM; 844 return (0); 845 } 846 if (rs->dr_cstat & (PERR|BERR|TERR)) { 847 dr->dr_actf->b_flags |= B_ERROR; 848 return (0); 849 } 850 dr->dr_flags &= ~DR_DMAX; 851 return (1); 852 } 853 854 /* 855 * 856 * The lower 8-bit of tinfo is the minor device number, the 857 * remaining higher 8-bit is the current timout number 858 */ 859 drrwtimo(tinfo) 860 register u_long tinfo; 861 { 862 register long unit = tinfo & 0xff; 863 register struct dr_aux *dr = &dr_aux[unit]; 864 register struct rsdevice *rs = dr->dr_addr; 865 866 /* 867 * If this is not the timeout that drwrite/drread is waiting 868 * for then we should just go away 869 */ 870 if ((tinfo &~ 0xff) != (dr->currenttimo << 8)) 871 return; 872 /* Mark the device timed out */ 873 dr->dr_flags |= DR_TMDM; 874 dr->dr_flags &= ~DR_ACTV; 875 rs->dr_pulse = RMSK; /* Inihibit interrupt */ 876 rs->dr_pulse = (RPER|RDMA|RATN|IENB); /* Clear DMA logic */ 877 /* 878 * Some applications will not issue a master after dma timeout, 879 * since doing so sends an INIT H pulse to the external device, 880 * which may produce undesirable side-effects. 881 */ 882 /* Wake up process waiting in drwait() and flag the error */ 883 dr->dr_actf->b_flags |= B_ERROR; 884 wakeup((caddr_t)dr->dr_cmd); 885 } 886 887 /* 888 * Kick the driver every second 889 */ 890 drtimo(dev) 891 dev_t dev; 892 { 893 register int unit = RSUNIT(dev); 894 register struct dr_aux *dr; 895 896 dr = &dr_aux[unit]; 897 if (dr->dr_flags & DR_OPEN) 898 timeout(drtimo, (caddr_t)dev, hz); 899 wakeup((caddr_t)dr); /* Wakeup any process waiting for interrupt */ 900 } 901 902 #ifdef DR_DEBUG 903 drva(dra, p, va, bcnt) 904 struct dr_aux *dra; 905 struct proc *p; 906 char *va; 907 long bcnt; 908 { 909 register long first, last , np; 910 911 if (DR11 & 0x20) { 912 first = ((long)(vtoph(p, (unsigned)va))) >> 10; 913 last = ((long)(vtoph(p, (unsigned)va+bcnt))) >> 10; 914 np = bcnt / 0x3ff; 915 printf("\ndrva: (op:%ld)(first:%ld)(last:%ld)(np:%ld)(cnt:%ld)", 916 dra->dr_op,first,last,np,bcnt); 917 } 918 } 919 #endif 920 921 drstart(rsaddr, dra, bp) 922 register struct rsdevice *rsaddr; 923 register struct dr_aux *dra; 924 register struct buf *bp; 925 { 926 register long addr; 927 u_short go; 928 929 #ifdef DR_DEBUG 930 if (dra->dr_op == DR_READ && (DR11 & 8)) { 931 char *caddr = (char *)bp->b_un.b_addr; 932 printf("\ndrstart: READ, bcnt:%ld",bp->b_bcount); 933 printf(",(%lx)(%lx)",caddr[0]&0xff,caddr[1]&0xff); 934 } 935 #endif 936 /* we are doing raw IO, bp->b_un.b_addr is user's address */ 937 addr = (long)vtoph(bp->b_proc, (unsigned)bp->b_un.b_addr); 938 /* 939 * Set DMA address into DR11 interace registers: DR11 requires that 940 * the address be right shifted 1 bit position before it is written 941 * to the board (The board will left shift it one bit position before 942 * it places the address on the bus 943 */ 944 rsaddr->dr_walo = (addr >> 1) & 0xffff; 945 rsaddr->dr_wahi = (addr >> 17) & 0x7fff; 946 /* Set DMA range count: (number of words - 1) */ 947 rsaddr->dr_range = (bp->b_bcount >> 1) - 1; 948 /* Set address modifier code to be used for DMA access to memory */ 949 rsaddr->dr_addmod = DRADDMOD; 950 /* 951 * Now determine whether this is a read or a write. ***** This is 952 * probably only usefull for link mode operation, since dr11 doesnot 953 * controll the direction of data transfer. The C1 control input 954 * controls whether the hardware is doing a read or a write. In link 955 * mode this is controlled by function 1 latch (looped back by the 956 * cable) and could be set the program. In the general case, the dr11 957 * doesnot know in advance what the direction of transfer is - although 958 * the program and protocol logic probably is 959 */ 960 #ifdef DR_DEBUG 961 if (DR11 & 1) 962 printf( 963 "\ndrstrat: about to GO..,dr_cmd:%lx,drstat:%lx,drcnt:%ld,cdata:%lx,OP:%ld", 964 dra->dr_cmd, rsaddr->dr_cstat, rsaddr->dr_range, 965 rsaddr->dr_data, dra->dr_op); 966 #endif 967 /* 968 * Update function latches may have been done already by drioctl() if 969 * request from drioctl() 970 */ 971 if (dra->dr_cmd & DR_DFCN) { /* deferred function write */ 972 dra->dr_cmd &= ~DR_DFCN; /* Clear request */ 973 go = dra->dr_cmd & DR_FMSK; /* mask out fcn bits */ 974 rsaddr->dr_cstat = go; /* Write it to the board */ 975 } 976 /* Clear dmaf and attf to assure a clean dma start */ 977 rsaddr->dr_pulse = RATN|RDMA|RPER; 978 rsaddr->dr_cstat = IENB|GO|CYCL|dra->dr_op; /* GO...... */ 979 /* 980 * Now check for software cycle request -- usually 981 * by transmitter in link mode. 982 */ 983 if (dra->dr_cmd & DR_PCYL) { 984 dra->dr_cmd &= ~DR_PCYL; /* Clear request */ 985 rsaddr->dr_pulse = CYCL; /* Use pulse register again */ 986 } 987 /* 988 * Now check for deferred ACLO FCNT2 pulse request -- usually to tell 989 * the transmitter (via its attention) that we have enabled dma. 990 */ 991 if (dra->dr_cmd & DR_DACL) { 992 dra->dr_cmd &= ~DR_DACL; /* Clear request */ 993 rsaddr->dr_pulse = FCN2; /* Use pulse register again */ 994 } 995 } 996 #endif NDR 997