xref: /original-bsd/sys/tahoe/vba/vdreg.h (revision 479d5e4b)
158a10c11Skarels /*
258a10c11Skarels  * Copyright (c) 1988 Regents of the University of California.
358a10c11Skarels  * All rights reserved.
458a10c11Skarels  *
5493988bdSkarels  * This code is derived from software contributed to Berkeley by
6493988bdSkarels  * Computer Consoles Inc.
7493988bdSkarels  *
8*479d5e4bSbostic  * %sccs.include.redist.c%
958a10c11Skarels  *
10*479d5e4bSbostic  *	@(#)vdreg.h	7.7 (Berkeley) 06/28/90
1158a10c11Skarels  */
120364ca21Ssam 
130364ca21Ssam /*
1485bf3e8aSsam  * Versabus VDDC/SMDE disk controller definitions.
150364ca21Ssam  */
16054318bdSkarels #define	VDDC_SECSIZE	512	/* sector size for VDDC */
17054318bdSkarels #define	VD_MAXSECSIZE	1024	/* max sector size for SMD/E */
180364ca21Ssam 
190364ca21Ssam /*
2085bf3e8aSsam  * Controller communications block.
210364ca21Ssam  */
2285bf3e8aSsam struct vddevice {
2385bf3e8aSsam 	u_long	vdcdr;		/* controller device register */
2485bf3e8aSsam 	u_long	vdreset;	/* controller reset register */
2585bf3e8aSsam 	u_long	vdcsr;		/* control-status register */
2685bf3e8aSsam 	long	vdrstclr;	/* reset clear register */
2785bf3e8aSsam 	u_short	vdstatus[16];	/* per-drive status register */
2885bf3e8aSsam 	u_short	vdicf_status;	/* status change interupt control format */
2985bf3e8aSsam 	u_short	vdicf_done;	/* interrupt complete control format */
3085bf3e8aSsam 	u_short	vdicf_error;	/* interrupt error control format */
3185bf3e8aSsam 	u_short	vdicf_success;	/* interrupt success control format */
3285bf3e8aSsam 	u_short	vdtcf_mdcb;	/* mdcb transfer control format */
3385bf3e8aSsam 	u_short	vdtcf_dcb;	/* dcb transfer control format */
3485bf3e8aSsam 	u_short	vdtcf_trail;	/* trail transfer control format */
3585bf3e8aSsam 	u_short	vdtcf_data;	/* data transfer control format */
3685bf3e8aSsam 	u_long	vdccf;		/* controller configuration flags */
3785bf3e8aSsam 	u_long	vdsecsize;	/* sector size */
3885bf3e8aSsam 	u_short	vdfill0;
3985bf3e8aSsam 	u_char	vdcylskew;	/* cylinder to cylinder skew factor */
4085bf3e8aSsam 	u_char	vdtrackskew;	/* track to track skew factor */
4185bf3e8aSsam 	u_long	vdfill1;
4285bf3e8aSsam 	u_long	vddfr;		/* diagnostic flag register */
4385bf3e8aSsam 	u_long	vddda;		/* diagnostic dump address */
4485bf3e8aSsam };
450364ca21Ssam 
4685bf3e8aSsam /* controller types */
4785bf3e8aSsam #define	VDTYPE_VDDC	1	/* old vddc controller (smd only) */
4885bf3e8aSsam #define	VDTYPE_SMDE	2	/* new smde controller (smd-e) */
490364ca21Ssam 
500364ca21Ssam /*
5185bf3e8aSsam  * Controller status definitions.
520364ca21Ssam  */
5385bf3e8aSsam #define	CS_SCS	0xf		/* status change source (drive number) */
5485bf3e8aSsam #define	CS_ELC	0x10		/* error on last command */
5585bf3e8aSsam #define	CS_ICC	0x60		/* interupt cause code */
5685bf3e8aSsam #define   ICC_NOI  0x00		/* no interupt */
5785bf3e8aSsam #define   ICC_DUN  0x20		/* no interupt */
5885bf3e8aSsam #define   ICC_ERR  0x40		/* no interupt */
5985bf3e8aSsam #define   ICC_SUC  0x60		/* no interupt */
6085bf3e8aSsam #define	CS_GO	0x80		/* go bit (controller busy) */
6185bf3e8aSsam #define	CS_BE	0x100		/* buss error */
6285bf3e8aSsam #define	CS_BOK	0x4000		/* board ok */
6385bf3e8aSsam #define	CS_SFL	0x8000		/* system fail */
6485bf3e8aSsam #define	CS_LEC	0xff000000	/* last error code */
650364ca21Ssam 
660364ca21Ssam /*
6785bf3e8aSsam  * Drive status definitions.
680364ca21Ssam  */
6985bf3e8aSsam #define	STA_UR	0x1		/* unit ready */
7085bf3e8aSsam #define	STA_OC	0x2		/* on cylinder */
7185bf3e8aSsam #define	STA_SE	0x4		/* seek error */
7285bf3e8aSsam #define	STA_DF	0x8		/* drive fault */
7385bf3e8aSsam #define	STA_WP	0x10		/* write protected */
7485bf3e8aSsam #define	STA_US	0x20		/* unit selected */
7579866b39Skarels #define	STA_TYPE	0x300	/* drive type: */
7679866b39Skarels #define	STA_SMD		0x000		/* SMD */
7779866b39Skarels #define	STA_ESDI	0x100		/* ESDI */
780364ca21Ssam 
790364ca21Ssam /*
8085bf3e8aSsam  * Interupt Control Field definitions.
810364ca21Ssam  */
8285bf3e8aSsam #define	ICF_IPL	0x7		/* interupt priority level */
8385bf3e8aSsam #define	ICF_IEN	0x8		/* interupt enable */
8485bf3e8aSsam #define	ICF_IV	0xff00		/* interupt vector */
850364ca21Ssam 
860364ca21Ssam /*
8785bf3e8aSsam  * Transfer Control Format definitions.
880364ca21Ssam  */
890364ca21Ssam #define	TCF_AM	0xff		/* Address Modifier */
900364ca21Ssam #define	  AM_SNPDA   0x01	/* Standard Non-Privileged Data Access */
910364ca21Ssam #define	  AM_SASA    0x81	/* Standard Ascending Sequential Access */
920364ca21Ssam #define	  AM_ENPDA   0xf1	/* Extended Non-Privileged Data Access */
930364ca21Ssam #define	  AM_EASA    0xe1	/* Extended Ascending Sequential Access */
940364ca21Ssam #define	TCF_BTE	0x800		/* Block Transfer Enable */
950364ca21Ssam 
9685bf3e8aSsam /*
9785bf3e8aSsam  * Controller Configuration Flags.
9885bf3e8aSsam  */
9985bf3e8aSsam #define	CCF_STS	0x1		/* sectors per track selectable */
10085bf3e8aSsam #define	CCF_EAV	0x2		/* enable auto vector */
10185bf3e8aSsam #define	CCF_ERR	0x4		/* enable reset register */
10279866b39Skarels #define CCF_RFE 0x8		/* recovery flag enable */
10385bf3e8aSsam #define	CCF_XMD	0x60		/* xmd transfer mode (bus size) */
10485bf3e8aSsam #define	  XMD_8BIT  0x20	/*   do only 8 bit transfers */
10585bf3e8aSsam #define	  XMD_16BIT 0x40	/*   do only 16 bit transfers */
10685bf3e8aSsam #define	  XMD_32BIT 0x60	/*   do only 32 bit transfers */
10779866b39Skarels #define	CCF_DIU	0x80		/* disable initial update of DCB @cmd start */
10885bf3e8aSsam #define	CCF_BSZ	0x300		/* burst size */
1090364ca21Ssam #define	  BSZ_16WRD 0x000	/*   16 word transfer burst */
1100364ca21Ssam #define	  BSZ_12WRD 0x100	/*   12 word transfer burst */
1110364ca21Ssam #define	  BSZ_8WRD  0x200	/*   8 word transfer burst */
1120364ca21Ssam #define	  BSZ_4WRD  0x300	/*   4 word transfer burst */
11385bf3e8aSsam #define CCF_SEN	0x400		/* cylinder/track skew enable (for format) */
11485bf3e8aSsam #define	CCF_ENP	0x1000		/* enable parity */
11585bf3e8aSsam #define	CCF_EPE	0x2000		/* enable parity errors */
11685bf3e8aSsam #define	CCF_EDE	0x10000		/* error detection enable */
11785bf3e8aSsam #define	CCF_ECE	0x20000		/* error correction enable */
1180364ca21Ssam 
1190364ca21Ssam /*
1200364ca21Ssam  * Diagnostic register definitions.
1210364ca21Ssam  */
12285bf3e8aSsam #define	DIA_DC	0x7f		/* dump count mask */
12385bf3e8aSsam #define	DIA_DWR	0x80		/* dump write/read flag */
12485bf3e8aSsam #define	DIA_ARE	0x100		/* auto rebuild enable */
12585bf3e8aSsam #define	DIA_CEN	0x200		/* call enable flag */
12685bf3e8aSsam #define	DIA_KEY	0xAA550000	/* reset enable key */
1270364ca21Ssam 
1280364ca21Ssam /*
129054318bdSkarels  * Hardware interface flags, in dcb.devselect and d_devflags
130054318bdSkarels  */
131054318bdSkarels #define VD_ESDI	0x10		/* drive is on ESDI interface */
132054318bdSkarels #define	d_devflags	d_drivedata[0]		/* in disk label */
133054318bdSkarels 
134054318bdSkarels /*
135054318bdSkarels  * Error recovery flags.
136054318bdSkarels  */
137054318bdSkarels #define	VDRF_RTZ	0x0001	/* return to zero */
138054318bdSkarels #define	VDRF_OCF	0x0002	/* on cylinder false */
139054318bdSkarels #define	VDRF_OSP	0x0004	/* offset plus */
140054318bdSkarels #define	VDRF_OSM	0x0008	/* offset minus */
141054318bdSkarels #define	VDRF_DSE	0x0080	/* data strobe early */
142054318bdSkarels #define	VDRF_DSL	0x0100	/* data strobe late */
143054318bdSkarels 
144054318bdSkarels #define	VDRF_NONE	0
1456fc7b70aSkarels #define	VDRF_NORMAL	(VDRF_RTZ|VDRF_OCF|VDRF_OSP|VDRF_OSM|VDRF_DSE|VDRF_DSL)
146054318bdSkarels 
147054318bdSkarels /*
1480364ca21Ssam  * Perform a reset on the controller.
1490364ca21Ssam  */
15085bf3e8aSsam #define	VDRESET(a,t) { \
15185bf3e8aSsam 	if ((t) == VDTYPE_SMDE) { \
15285bf3e8aSsam 		((struct vddevice *)(a))->vddfr = DIA_KEY|DIA_CEN; \
15385bf3e8aSsam 		((struct vddevice *)(a))->vdcdr = (u_long)0xffffffff; \
1540364ca21Ssam 		DELAY(5000000); \
1550364ca21Ssam 	} else { \
15685bf3e8aSsam 		((struct vddevice *)(a))->vdreset = 0; \
1570364ca21Ssam 		DELAY(1500000); \
1580364ca21Ssam 	} \
1590364ca21Ssam }
1600364ca21Ssam 
1610364ca21Ssam /*
1620364ca21Ssam  * Abort a controller operation.
1630364ca21Ssam  */
16485bf3e8aSsam #define	VDABORT(a,t) { \
16585bf3e8aSsam 	if ((t) == VDTYPE_VDDC) { \
16685bf3e8aSsam 		movow((a), (VDOP_ABORT&0xffff0000)>>16) ; \
16785bf3e8aSsam 		movow((int)(a)+2, VDOP_ABORT&0xffff); \
1680364ca21Ssam 	} else \
16985bf3e8aSsam 		((struct vddevice *)(a))->vdcdr = (u_long)VDOP_ABORT; \
1700364ca21Ssam 	DELAY(1000000); \
1710364ca21Ssam }
1720364ca21Ssam 
1730364ca21Ssam /*
17485bf3e8aSsam  * Start a command.
1750364ca21Ssam  */
17685bf3e8aSsam #define VDGO(a,mdcb,t) {\
17785bf3e8aSsam 	if ((t) == VDTYPE_VDDC) { \
17885bf3e8aSsam 		movow((a), ((int)(mdcb)&0xffff0000)>>16) ; \
17985bf3e8aSsam 		movow((int)((a))+2, (int)(mdcb)&0xffff); \
1800364ca21Ssam 	} else \
18185bf3e8aSsam 		((struct vddevice *)(a))->vdcdr = (mdcb); \
1820364ca21Ssam }
1830364ca21Ssam 
1840364ca21Ssam /*
18585bf3e8aSsam  * MDCB layout.
18685bf3e8aSsam  */
18785bf3e8aSsam struct mdcb {
18885bf3e8aSsam 	struct	dcb *mdcb_head;		/* first dcb in list */
18985bf3e8aSsam 	struct	dcb *mdcb_busy;		/* dcb being processed */
19085bf3e8aSsam 	struct	dcb *mdcb_intr;		/* dcb causing interrupt */
19185bf3e8aSsam 	long	mdcb_status;		/* status of dcb in mdcb_busy */
19285bf3e8aSsam };
19385bf3e8aSsam 
19485bf3e8aSsam /*
19585bf3e8aSsam  * DCB definitions.
19685bf3e8aSsam  */
19785bf3e8aSsam 
19885bf3e8aSsam /*
1990364ca21Ssam  * A disk address.
2000364ca21Ssam  */
2010364ca21Ssam typedef struct {
20285bf3e8aSsam 	u_char	track;			/* all 8 bits */
20385bf3e8aSsam 	u_char	sector;			/* all 8  bits */
20485bf3e8aSsam 	u_short	cylinder;		/* low order 12 bits */
2050364ca21Ssam } dskadr;
2060364ca21Ssam 
2070364ca21Ssam /*
2080364ca21Ssam  * DCB trailer formats.
2090364ca21Ssam  */
2100364ca21Ssam /* read/write trailer */
21148bbf601Skarels struct trrw {
212f3efb5ffSkarels 	u_long	memadr;		/* memory address */
2130364ca21Ssam 	u_long	wcount;		/* 16 bit word count */
2140364ca21Ssam 	dskadr	disk;		/* disk address */
21548bbf601Skarels };
2160364ca21Ssam 
2170364ca21Ssam /* scatter/gather trailer */
21848bbf601Skarels #define	VDMAXPAGES	(MAXPHYS / NBPG)
21948bbf601Skarels struct trsg {
22048bbf601Skarels 	struct	trrw start_addr;
22148bbf601Skarels 	struct addr_chain {
222f3efb5ffSkarels 		u_long	nxt_addr;
2230364ca21Ssam 		u_long	nxt_len;
224f3efb5ffSkarels 	} addr_chain[VDMAXPAGES + 1];
22548bbf601Skarels };
2260364ca21Ssam 
2270364ca21Ssam /* seek trailer format */
22848bbf601Skarels struct trseek {
2290364ca21Ssam 	dskadr	skaddr;
23048bbf601Skarels };
2310364ca21Ssam 
2320364ca21Ssam /* format trailer */
23348bbf601Skarels struct trfmt {
2340364ca21Ssam 	char	*addr;		/* data buffer to be filled on sector*/
2350364ca21Ssam 	long	nsectors;	/* # of sectors to be formatted */
2360364ca21Ssam 	dskadr	disk;		/* disk physical address info */
2370364ca21Ssam 	dskadr  hdr;		/* header address info */
23848bbf601Skarels };
2390364ca21Ssam 
2400364ca21Ssam /* reset/configure trailer */
24148bbf601Skarels struct treset {
2420364ca21Ssam 	long	ncyl;		/* # cylinders */
2430364ca21Ssam 	long	nsurfaces;	/* # surfaces */
2440364ca21Ssam 	long	nsectors;	/* # sectors */
2450364ca21Ssam 	long	slip_sec;	/* # of slip sectors */
246cb1a65fbSsam 	long	recovery;	/* recovery flags */
24748bbf601Skarels };
24848bbf601Skarels 
24948bbf601Skarels /* ident trailer */
25048bbf601Skarels struct trid {
25148bbf601Skarels 	long	name;
25279866b39Skarels 	long	rev;
25348bbf601Skarels 	long	date;
25448bbf601Skarels };
2550364ca21Ssam 
2560364ca21Ssam /*
2570364ca21Ssam  * DCB layout.
2580364ca21Ssam  */
25985bf3e8aSsam struct dcb {
26085bf3e8aSsam 	struct	dcb *nxtdcb;	/* next dcb */
2610364ca21Ssam 	short	intflg;		/* interrupt settings and flags */
2620364ca21Ssam 	short	opcode;		/* DCB command code etc... */
2630364ca21Ssam 	long	operrsta;	/* error & status info */
2640364ca21Ssam 	short	fill;		/* not used */
2650364ca21Ssam 	char	devselect;	/* drive selection */
2660364ca21Ssam 	char	trailcnt;	/* trailer Word Count */
2670364ca21Ssam 	long	err_memadr;	/* error memory address */
26879866b39Skarels 	u_char	err_code;	/* error codes for SMD/E */
2690364ca21Ssam 	char	fill2;		/* not used */
2700364ca21Ssam 	short	err_wcount;	/* error word count */
2710364ca21Ssam 	char	err_trk;	/* error track/sector */
2720364ca21Ssam 	char	err_sec;	/* error track/sector */
2730364ca21Ssam 	short	err_cyl;	/* error cylinder adr */
2740364ca21Ssam 	union {
27548bbf601Skarels 		struct	trid idtrail;	/* ident command trailer */
27648bbf601Skarels 		struct	trseek sktrail;	/* seek command trailer */
27748bbf601Skarels 		struct	trsg sgtrail;	/* scatter/gather trailer */
27848bbf601Skarels 		struct	trrw rwtrail;	/* read/write trailer */
27948bbf601Skarels 		struct	trfmt fmtrail;	/* format trailer */
28048bbf601Skarels 		struct	treset rstrail;	/* reset/configure trailer */
28148bbf601Skarels 	} trail;
28248bbf601Skarels };
28348bbf601Skarels 
28448bbf601Skarels /*
28548bbf601Skarels  * smaller DCB with seek trailer only (no scatter-gather).
28648bbf601Skarels  */
28748bbf601Skarels struct skdcb {
28848bbf601Skarels 	struct	dcb *nxtdcb;	/* next dcb */
28948bbf601Skarels 	short	intflg;		/* interrupt settings and flags */
29048bbf601Skarels 	short	opcode;		/* DCB command code etc... */
29148bbf601Skarels 	long	operrsta;	/* error & status info */
29248bbf601Skarels 	short	fill;		/* not used */
29348bbf601Skarels 	char	devselect;	/* drive selection */
29448bbf601Skarels 	char	trailcnt;	/* trailer Word Count */
29548bbf601Skarels 	long	err_memadr;	/* error memory address */
29679866b39Skarels 	u_char	err_code;	/* error codes for SMD/E */
29748bbf601Skarels 	char	fill2;		/* not used */
29848bbf601Skarels 	short	err_wcount;	/* error word count */
29948bbf601Skarels 	char	err_trk;	/* error track/sector */
30048bbf601Skarels 	char	err_sec;	/* error track/sector */
30148bbf601Skarels 	short	err_cyl;	/* error cylinder adr */
30248bbf601Skarels 	union {
30348bbf601Skarels 		struct	trseek sktrail;	/* seek command trailer */
3040364ca21Ssam 	} trail;
3050364ca21Ssam };
3060364ca21Ssam 
30785bf3e8aSsam /*
30885bf3e8aSsam  * DCB command codes.
30985bf3e8aSsam  */
31085bf3e8aSsam #define	VDOP_RD		0x80		/* read data */
31185bf3e8aSsam #define	VDOP_FTR	0xc0		/* full track read */
31285bf3e8aSsam #define	VDOP_RAS	0x90		/* read and scatter */
31385bf3e8aSsam #define	VDOP_RDRAW	0x600		/* read unformatted disk sector */
31485bf3e8aSsam #define	VDOP_CMP	0xa0		/* compare */
31585bf3e8aSsam #define	VDOP_FTC	0xe0		/* full track compare */
31685bf3e8aSsam #define	VDOP_RHDE	0x180		/* read header, data & ecc */
31785bf3e8aSsam #define	VDOP_WD		0x00		/* write data */
31885bf3e8aSsam #define	VDOP_FTW	0x40		/* full track write */
31985bf3e8aSsam #define	VDOP_WTC	0x20		/* write then compare */
32085bf3e8aSsam #define	VDOP_FTWTC	0x60		/* full track write then compare */
32185bf3e8aSsam #define	VDOP_GAW	0x10		/* gather and write */
32285bf3e8aSsam #define	VDOP_WDE	0x100		/* write data & ecc */
32385bf3e8aSsam #define	VDOP_FSECT	0x900		/* format sector */
32485bf3e8aSsam #define	VDOP_GWC	0x30		/* gather write & compare */
32585bf3e8aSsam #define	VDOP_START	0x800		/* start drives */
32685bf3e8aSsam #define	VDOP_RELEASE	0xa00		/* stop drives */
32785bf3e8aSsam #define	VDOP_SEEK	0xb00		/* seek */
32885bf3e8aSsam #define	VDOP_INIT	0xc00		/* initialize controller */
32985bf3e8aSsam #define	VDOP_DIAG	0xd00		/* diagnose (self-test) controller */
33085bf3e8aSsam #define	VDOP_CONFIG	0xe00		/* reset & configure drive */
33185bf3e8aSsam #define	VDOP_STATUS	0xf00		/* get drive status */
33248bbf601Skarels #define	VDOP_IDENT	0x700		/* identify controller */
333e77537d8Skarels #define	VDOP_PROBE	0x500		/* probe drives and update status */
3340364ca21Ssam 
33585bf3e8aSsam #define	VDOP_ABORT	0x80000000	/* abort current command */
33685bf3e8aSsam 
33785bf3e8aSsam /*
33885bf3e8aSsam  * DCB status definitions.
33985bf3e8aSsam  */
34085bf3e8aSsam #define	DCBS_HCRC	0x00000001	/* header crc error */
34185bf3e8aSsam #define	DCBS_HCE	0x00000002	/* header compare error */
34285bf3e8aSsam #define	DCBS_WPT	0x00000004	/* drive write protected */
34385bf3e8aSsam #define	DCBS_CHE	0x00000008	/* controller hardware error */
34485bf3e8aSsam #define	DCBS_SKI	0x00000010	/* seek incomplete */
34585bf3e8aSsam #define	DCBS_UDE	0x00000020	/* uncorrectable data error */
34685bf3e8aSsam #define	DCBS_OCYL	0x00000040	/* off cylinder */
34785bf3e8aSsam #define	DCBS_NRDY	0x00000080	/* drive not ready */
34885bf3e8aSsam #define	DCBS_ATA	0x00000100	/* alternate track accessed */
34985bf3e8aSsam #define	DCBS_SKS	0x00000200	/* seek started */
35085bf3e8aSsam #define	DCBS_IVA	0x00000400	/* invalid disk address error */
35185bf3e8aSsam #define	DCBS_NEM	0x00000800	/* non-existant memory error */
35285bf3e8aSsam #define	DCBS_DPE	0x00001000	/* memory data parity error */
35385bf3e8aSsam #define	DCBS_DCE	0x00002000	/* data compare error */
35485bf3e8aSsam #define	DCBS_DDI	0x00004000	/* ddi ready */
35585bf3e8aSsam #define	DCBS_OAB	0x00008000	/* operation aborted */
35685bf3e8aSsam #define	DCBS_DSE	0x00010000	/* data strobe early */
35785bf3e8aSsam #define	DCBS_DSL	0x00020000	/* data strobe late */
35885bf3e8aSsam #define	DCBS_TOP	0x00040000	/* track offset plus */
35985bf3e8aSsam #define	DCBS_TOM	0x00080000	/* track offset minus */
36085bf3e8aSsam #define	DCBS_CCD	0x00100000	/* controller corrected data */
36185bf3e8aSsam #define	DCBS_HARD	0x00200000	/* hard error */
36285bf3e8aSsam #define	DCBS_SOFT	0x00400000	/* soft error (retry succesful) */
36385bf3e8aSsam #define	DCBS_ERR	0x00800000	/* composite error */
36485bf3e8aSsam #define DCBS_IVC	0x01000000	/* invalid command error */
36585bf3e8aSsam /* bits 24-27 unused */
36685bf3e8aSsam #define	DCBS_BSY	0x10000000	/* controller busy */
36785bf3e8aSsam #define	DCBS_ICC	0x60000000	/* interrupt cause code */
36885bf3e8aSsam #define	DCBS_INT	0x80000000	/* interrupt generated for this dcb */
36985bf3e8aSsam 
37085bf3e8aSsam #define	VDERRBITS	"\20\1HCRC\2HCE\3WPT\4CHE\5DSKI\6UDE\7OCYL\10NRDY\
37185bf3e8aSsam \11ATA\12SKS\13IVA\14NEM\15DPE\16DCE\17DDI\20OAB\21DSE\22DSL\23TOP\24TOM\
37285bf3e8aSsam \25CCD\26HARD\27SOFT\30ERR\31IVC\35ABORTED\36FAIL\37COMPLETE\40STARTED"
37385bf3e8aSsam 
37485bf3e8aSsam /* drive related errors */
37585bf3e8aSsam #define	VDERR_DRIVE	(DCBS_SKI|DCBS_OCYL|DCBS_NRDY|DCBS_IVA)
37685bf3e8aSsam /* controller related errors */
37785bf3e8aSsam #define	VDERR_CTLR	(DCBS_CHE|DCBS_OAB|DCBS_IVC|DCBS_NEM)
37885bf3e8aSsam /* potentially recoverable errors */
379f3efb5ffSkarels #define	VDERR_RETRY \
38085bf3e8aSsam     (VDERR_DRIVE|VDERR_CTLR|DCBS_DCE|DCBS_DPE|DCBS_HCRC|DCBS_HCE)
38185bf3e8aSsam /* uncorrected data errors */
382f3efb5ffSkarels #define	VDERR_HARD	(VDERR_RETRY|DCBS_WPT|DCBS_UDE)
38385bf3e8aSsam 
38485bf3e8aSsam /*
38585bf3e8aSsam  * DCB status codes.
38685bf3e8aSsam  */
38785bf3e8aSsam #define	DCBS_ABORT	0x10000000	/* dcb aborted */
38885bf3e8aSsam #define	DCBS_FAIL	0x20000000	/* dcb unsuccesfully completed */
38985bf3e8aSsam #define	DCBS_DONE	0x40000000	/* dcb complete */
39085bf3e8aSsam #define	DCBS_START	0x80000000	/* dcb started */
39185bf3e8aSsam 
39285bf3e8aSsam /*
39385bf3e8aSsam  * DCB interrupt control.
39485bf3e8aSsam  */
39585bf3e8aSsam #define	DCBINT_NONE	0x0		/* don't interrupt */
39685bf3e8aSsam #define	DCBINT_ERR	0x2		/* interrupt on error */
39785bf3e8aSsam #define	DCBINT_SUC	0x1		/* interrupt on success */
39885bf3e8aSsam #define	DCBINT_DONE	(DCBINT_ERR|DCBINT_SUC)
39985bf3e8aSsam #define	DCBINT_PBA	0x4		/* proceed before acknowledge */
40085bf3e8aSsam 
40185bf3e8aSsam /*
40285bf3e8aSsam  * Sector formats.
40385bf3e8aSsam  */
40485bf3e8aSsam typedef union {
40585bf3e8aSsam 	struct {
40685bf3e8aSsam 		dskadr	hdr_addr;
40785bf3e8aSsam 		short	smd_crc;
40885bf3e8aSsam 	} smd;
40985bf3e8aSsam 	struct {
41085bf3e8aSsam 		dskadr	physical;
41185bf3e8aSsam 		dskadr	logical;
41285bf3e8aSsam 		long	smd_e_crc;
41385bf3e8aSsam 	} smd_e;
41485bf3e8aSsam } fmt_hdr;
41585bf3e8aSsam 
41685bf3e8aSsam /* Sector Header bit assignments */
41785bf3e8aSsam #define	VDMF	0x8000		/* Manufacturer Fault 1=good sector */
41885bf3e8aSsam #define	VDUF	0x4000		/* User Fault 1=good sector */
41985bf3e8aSsam #define	VDALT	0x2000		/* Alternate Sector 1=alternate */
42085bf3e8aSsam #define	VDWPT	0x1000		/* Write Protect 1=Read Only Sector */
4215bd9b13fSkarels 
4225bd9b13fSkarels /* input register assignments for DIOCWFORMAT ioctl */
4235bd9b13fSkarels #define	dk_op		df_reg[0]	/* opcode */
4246fc7b70aSkarels #define	dk_althdr	df_reg[1]	/* alt. sect. dskadr, in an int! */
4255bd9b13fSkarels #define	dk_fmtflags	df_reg[2]	/* header format flags */
4265bd9b13fSkarels 
4275bd9b13fSkarels /* output register assignments for DIOCWFORMAT ioctl */
4285bd9b13fSkarels #define	dk_operrsta	df_reg[0]	/* dcb operrsta */
4296fc7b70aSkarels #define	dk_ecodecnt	df_reg[1]	/* smd-e ecode and error word count */
4306fc7b70aSkarels #define	dk_ecode(ecodecnt)	((u_long)(ecodecnt) >> 2)
4316fc7b70aSkarels #define	dk_errcnt(ecodecnt)	(((ecodecnt) & 0xffff) << 1)
4326fc7b70aSkarels #define	dk_erraddr	df_reg[2]	/* error dskadr, in an int! */
433