1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qemu/module.h" 15 #include "hw/arm/bcm2835_peripherals.h" 16 #include "hw/misc/bcm2835_mbox_defs.h" 17 #include "hw/arm/raspi_platform.h" 18 #include "sysemu/sysemu.h" 19 20 /* Peripheral base address on the VC (GPU) system bus */ 21 #define BCM2835_VC_PERI_BASE 0x7e000000 22 23 /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */ 24 #define BCM2835_SDHC_CAPAREG 0x52134b4 25 26 /* 27 * According to Linux driver & DTS, dma channels 0--10 have separate IRQ, 28 * while channels 11--14 share one IRQ: 29 */ 30 #define SEPARATE_DMA_IRQ_MAX 10 31 #define ORGATED_DMA_IRQ_COUNT 4 32 33 /* All three I2C controllers share the same IRQ */ 34 #define ORGATED_I2C_IRQ_COUNT 3 35 36 void create_unimp(BCMSocPeripheralBaseState *ps, 37 UnimplementedDeviceState *uds, 38 const char *name, hwaddr ofs, hwaddr size) 39 { 40 object_initialize_child(OBJECT(ps), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 41 qdev_prop_set_string(DEVICE(uds), "name", name); 42 qdev_prop_set_uint64(DEVICE(uds), "size", size); 43 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 44 memory_region_add_subregion_overlap(&ps->peri_mr, ofs, 45 sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0), -1000); 46 } 47 48 static void bcm2835_peripherals_init(Object *obj) 49 { 50 BCM2835PeripheralState *s = BCM2835_PERIPHERALS(obj); 51 BCMSocPeripheralBaseState *s_base = BCM_SOC_PERIPHERALS_BASE(obj); 52 53 /* Random Number Generator */ 54 object_initialize_child(obj, "rng", &s->rng, TYPE_BCM2835_RNG); 55 56 /* Thermal */ 57 object_initialize_child(obj, "thermal", &s->thermal, TYPE_BCM2835_THERMAL); 58 59 /* GPIO */ 60 object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2835_GPIO); 61 62 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci", 63 OBJECT(&s_base->sdhci.sdbus)); 64 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost", 65 OBJECT(&s_base->sdhost.sdbus)); 66 67 /* Gated DMA interrupts */ 68 object_initialize_child(obj, "orgated-dma-irq", 69 &s_base->orgated_dma_irq, TYPE_OR_IRQ); 70 object_property_set_int(OBJECT(&s_base->orgated_dma_irq), "num-lines", 71 ORGATED_DMA_IRQ_COUNT, &error_abort); 72 } 73 74 static void raspi_peripherals_base_init(Object *obj) 75 { 76 BCMSocPeripheralBaseState *s = BCM_SOC_PERIPHERALS_BASE(obj); 77 BCMSocPeripheralBaseClass *bc = BCM_SOC_PERIPHERALS_BASE_GET_CLASS(obj); 78 79 /* Memory region for peripheral devices, which we export to our parent */ 80 memory_region_init(&s->peri_mr, obj, "bcm2835-peripherals", bc->peri_size); 81 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_mr); 82 83 /* Internal memory region for peripheral bus addresses (not exported) */ 84 memory_region_init(&s->gpu_bus_mr, obj, "bcm2835-gpu", (uint64_t)1 << 32); 85 86 /* Internal memory region for request/response communication with 87 * mailbox-addressable peripherals (not exported) 88 */ 89 memory_region_init(&s->mbox_mr, obj, "bcm2835-mbox", 90 MBOX_CHAN_COUNT << MBOX_AS_CHAN_SHIFT); 91 92 /* Interrupt Controller */ 93 object_initialize_child(obj, "ic", &s->ic, TYPE_BCM2835_IC); 94 95 /* SYS Timer */ 96 object_initialize_child(obj, "systimer", &s->systmr, 97 TYPE_BCM2835_SYSTIMER); 98 99 /* UART0 */ 100 object_initialize_child(obj, "uart0", &s->uart0, TYPE_PL011); 101 102 /* AUX / UART1 */ 103 object_initialize_child(obj, "aux", &s->aux, TYPE_BCM2835_AUX); 104 105 /* Mailboxes */ 106 object_initialize_child(obj, "mbox", &s->mboxes, TYPE_BCM2835_MBOX); 107 108 object_property_add_const_link(OBJECT(&s->mboxes), "mbox-mr", 109 OBJECT(&s->mbox_mr)); 110 111 /* Framebuffer */ 112 object_initialize_child(obj, "fb", &s->fb, TYPE_BCM2835_FB); 113 object_property_add_alias(obj, "vcram-size", OBJECT(&s->fb), "vcram-size"); 114 object_property_add_alias(obj, "vcram-base", OBJECT(&s->fb), "vcram-base"); 115 116 object_property_add_const_link(OBJECT(&s->fb), "dma-mr", 117 OBJECT(&s->gpu_bus_mr)); 118 119 /* Property channel */ 120 object_initialize_child(obj, "property", &s->property, 121 TYPE_BCM2835_PROPERTY); 122 object_property_add_alias(obj, "board-rev", OBJECT(&s->property), 123 "board-rev"); 124 object_property_add_alias(obj, "command-line", OBJECT(&s->property), 125 "command-line"); 126 127 object_property_add_const_link(OBJECT(&s->property), "fb", 128 OBJECT(&s->fb)); 129 object_property_add_const_link(OBJECT(&s->property), "dma-mr", 130 OBJECT(&s->gpu_bus_mr)); 131 132 /* Extended Mass Media Controller */ 133 object_initialize_child(obj, "sdhci", &s->sdhci, TYPE_SYSBUS_SDHCI); 134 135 /* SDHOST */ 136 object_initialize_child(obj, "sdhost", &s->sdhost, TYPE_BCM2835_SDHOST); 137 138 /* DMA Channels */ 139 object_initialize_child(obj, "dma", &s->dma, TYPE_BCM2835_DMA); 140 141 object_property_add_const_link(OBJECT(&s->dma), "dma-mr", 142 OBJECT(&s->gpu_bus_mr)); 143 144 /* Mphi */ 145 object_initialize_child(obj, "mphi", &s->mphi, TYPE_BCM2835_MPHI); 146 147 /* DWC2 */ 148 object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB); 149 150 /* CPRMAN clock manager */ 151 object_initialize_child(obj, "cprman", &s->cprman, TYPE_BCM2835_CPRMAN); 152 153 object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", 154 OBJECT(&s->gpu_bus_mr)); 155 156 /* Power Management */ 157 object_initialize_child(obj, "powermgt", &s->powermgt, 158 TYPE_BCM2835_POWERMGT); 159 160 /* SPI */ 161 object_initialize_child(obj, "bcm2835-spi0", &s->spi[0], 162 TYPE_BCM2835_SPI); 163 164 /* I2C */ 165 object_initialize_child(obj, "bcm2835-i2c0", &s->i2c[0], 166 TYPE_BCM2835_I2C); 167 object_initialize_child(obj, "bcm2835-i2c1", &s->i2c[1], 168 TYPE_BCM2835_I2C); 169 object_initialize_child(obj, "bcm2835-i2c2", &s->i2c[2], 170 TYPE_BCM2835_I2C); 171 172 object_initialize_child(obj, "orgated-i2c-irq", 173 &s->orgated_i2c_irq, TYPE_OR_IRQ); 174 object_property_set_int(OBJECT(&s->orgated_i2c_irq), "num-lines", 175 ORGATED_I2C_IRQ_COUNT, &error_abort); 176 } 177 178 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 179 { 180 MemoryRegion *mphi_mr; 181 BCM2835PeripheralState *s = BCM2835_PERIPHERALS(dev); 182 BCMSocPeripheralBaseState *s_base = BCM_SOC_PERIPHERALS_BASE(dev); 183 int n; 184 185 bcm_soc_peripherals_common_realize(dev, errp); 186 187 /* Extended Mass Media Controller */ 188 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->sdhci), 0, 189 qdev_get_gpio_in_named(DEVICE(&s_base->ic), BCM2835_IC_GPU_IRQ, 190 INTERRUPT_ARASANSDIO)); 191 192 /* Connect DMA 0-12 to the interrupt controller */ 193 for (n = 0; n <= SEPARATE_DMA_IRQ_MAX; n++) { 194 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), n, 195 qdev_get_gpio_in_named(DEVICE(&s_base->ic), 196 BCM2835_IC_GPU_IRQ, 197 INTERRUPT_DMA0 + n)); 198 } 199 200 if (!qdev_realize(DEVICE(&s_base->orgated_dma_irq), NULL, errp)) { 201 return; 202 } 203 for (n = 0; n < ORGATED_DMA_IRQ_COUNT; n++) { 204 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 205 SEPARATE_DMA_IRQ_MAX + 1 + n, 206 qdev_get_gpio_in(DEVICE(&s_base->orgated_dma_irq), n)); 207 } 208 qdev_connect_gpio_out(DEVICE(&s_base->orgated_dma_irq), 0, 209 qdev_get_gpio_in_named(DEVICE(&s_base->ic), 210 BCM2835_IC_GPU_IRQ, 211 INTERRUPT_DMA0 + SEPARATE_DMA_IRQ_MAX + 1)); 212 213 /* Random Number Generator */ 214 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) { 215 return; 216 } 217 memory_region_add_subregion( 218 &s_base->peri_mr, RNG_OFFSET, 219 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0)); 220 221 /* THERMAL */ 222 if (!sysbus_realize(SYS_BUS_DEVICE(&s->thermal), errp)) { 223 return; 224 } 225 memory_region_add_subregion(&s_base->peri_mr, THERMAL_OFFSET, 226 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->thermal), 0)); 227 228 /* Map MPHI to the peripherals memory map */ 229 mphi_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s_base->mphi), 0); 230 memory_region_add_subregion(&s_base->peri_mr, MPHI_OFFSET, mphi_mr); 231 232 /* GPIO */ 233 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 234 return; 235 } 236 memory_region_add_subregion( 237 &s_base->peri_mr, GPIO_OFFSET, 238 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0)); 239 240 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus"); 241 } 242 243 void bcm_soc_peripherals_common_realize(DeviceState *dev, Error **errp) 244 { 245 BCMSocPeripheralBaseState *s = BCM_SOC_PERIPHERALS_BASE(dev); 246 Object *obj; 247 MemoryRegion *ram; 248 Error *err = NULL; 249 uint64_t ram_size, vcram_size, vcram_base; 250 int n; 251 252 obj = object_property_get_link(OBJECT(dev), "ram", &error_abort); 253 254 ram = MEMORY_REGION(obj); 255 ram_size = memory_region_size(ram); 256 257 /* Map peripherals and RAM into the GPU address space. */ 258 memory_region_init_alias(&s->peri_mr_alias, OBJECT(s), 259 "bcm2835-peripherals", &s->peri_mr, 0, 260 memory_region_size(&s->peri_mr)); 261 262 memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE, 263 &s->peri_mr_alias, 1); 264 265 /* RAM is aliased four times (different cache configurations) on the GPU */ 266 for (n = 0; n < 4; n++) { 267 memory_region_init_alias(&s->ram_alias[n], OBJECT(s), 268 "bcm2835-gpu-ram-alias[*]", ram, 0, ram_size); 269 memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30, 270 &s->ram_alias[n], 0); 271 } 272 273 /* Interrupt Controller */ 274 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ic), errp)) { 275 return; 276 } 277 278 /* CPRMAN clock manager */ 279 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cprman), errp)) { 280 return; 281 } 282 memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET, 283 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0)); 284 qdev_connect_clock_in(DEVICE(&s->uart0), "clk", 285 qdev_get_clock_out(DEVICE(&s->cprman), "uart-out")); 286 287 memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET, 288 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0)); 289 sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic)); 290 291 /* Sys Timer */ 292 if (!sysbus_realize(SYS_BUS_DEVICE(&s->systmr), errp)) { 293 return; 294 } 295 memory_region_add_subregion(&s->peri_mr, ST_OFFSET, 296 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systmr), 0)); 297 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 0, 298 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 299 INTERRUPT_TIMER0)); 300 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 1, 301 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 302 INTERRUPT_TIMER1)); 303 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 2, 304 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 305 INTERRUPT_TIMER2)); 306 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 3, 307 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 308 INTERRUPT_TIMER3)); 309 310 /* UART0 */ 311 qdev_prop_set_chr(DEVICE(&s->uart0), "chardev", serial_hd(0)); 312 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart0), errp)) { 313 return; 314 } 315 316 memory_region_add_subregion(&s->peri_mr, UART0_OFFSET, 317 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart0), 0)); 318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart0), 0, 319 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 320 INTERRUPT_UART0)); 321 322 /* AUX / UART1 */ 323 qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1)); 324 325 if (!sysbus_realize(SYS_BUS_DEVICE(&s->aux), errp)) { 326 return; 327 } 328 329 memory_region_add_subregion(&s->peri_mr, AUX_OFFSET, 330 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0)); 331 sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0, 332 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 333 INTERRUPT_AUX)); 334 335 /* Mailboxes */ 336 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mboxes), errp)) { 337 return; 338 } 339 340 memory_region_add_subregion(&s->peri_mr, ARMCTRL_0_SBM_OFFSET, 341 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mboxes), 0)); 342 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mboxes), 0, 343 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ, 344 INTERRUPT_ARM_MAILBOX)); 345 346 /* Framebuffer */ 347 vcram_size = object_property_get_uint(OBJECT(s), "vcram-size", &err); 348 if (err) { 349 error_propagate(errp, err); 350 return; 351 } 352 353 vcram_base = object_property_get_uint(OBJECT(s), "vcram-base", &err); 354 if (err) { 355 error_propagate(errp, err); 356 return; 357 } 358 359 if (vcram_base == 0) { 360 vcram_base = ram_size - vcram_size; 361 } 362 vcram_base = MIN(vcram_base, UPPER_RAM_BASE - vcram_size); 363 364 if (!object_property_set_uint(OBJECT(&s->fb), "vcram-base", vcram_base, 365 errp)) { 366 return; 367 } 368 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fb), errp)) { 369 return; 370 } 371 372 memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_FB << MBOX_AS_CHAN_SHIFT, 373 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->fb), 0)); 374 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fb), 0, 375 qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB)); 376 377 /* Property channel */ 378 if (!sysbus_realize(SYS_BUS_DEVICE(&s->property), errp)) { 379 return; 380 } 381 382 memory_region_add_subregion(&s->mbox_mr, 383 MBOX_CHAN_PROPERTY << MBOX_AS_CHAN_SHIFT, 384 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->property), 0)); 385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0, 386 qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY)); 387 388 /* Extended Mass Media Controller 389 * 390 * Compatible with: 391 * - SD Host Controller Specification Version 3.0 Draft 1.0 392 * - SDIO Specification Version 3.0 393 * - MMC Specification Version 4.4 394 * 395 * For the exact details please refer to the Arasan documentation: 396 * SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf 397 */ 398 object_property_set_uint(OBJECT(&s->sdhci), "sd-spec-version", 3, 399 &error_abort); 400 object_property_set_uint(OBJECT(&s->sdhci), "capareg", 401 BCM2835_SDHC_CAPAREG, &error_abort); 402 object_property_set_bool(OBJECT(&s->sdhci), "pending-insert-quirk", true, 403 &error_abort); 404 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 405 return; 406 } 407 408 memory_region_add_subregion(&s->peri_mr, EMMC1_OFFSET, 409 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0)); 410 411 /* SDHOST */ 412 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhost), errp)) { 413 return; 414 } 415 416 memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET, 417 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0)); 418 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0, 419 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 420 INTERRUPT_SDIO)); 421 422 /* DMA Channels */ 423 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp)) { 424 return; 425 } 426 427 memory_region_add_subregion(&s->peri_mr, DMA_OFFSET, 428 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 0)); 429 memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET, 430 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1)); 431 432 /* Mphi */ 433 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mphi), errp)) { 434 return; 435 } 436 437 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0, 438 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 439 INTERRUPT_HOSTPORT)); 440 441 /* DWC2 */ 442 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dwc2), errp)) { 443 return; 444 } 445 446 memory_region_add_subregion(&s->peri_mr, USB_OTG_OFFSET, 447 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dwc2), 0)); 448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dwc2), 0, 449 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 450 INTERRUPT_USB)); 451 452 /* Power Management */ 453 if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) { 454 return; 455 } 456 457 memory_region_add_subregion(&s->peri_mr, PM_OFFSET, 458 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0)); 459 460 /* SPI */ 461 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[0]), errp)) { 462 return; 463 } 464 465 memory_region_add_subregion(&s->peri_mr, SPI0_OFFSET, 466 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi[0]), 0)); 467 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[0]), 0, 468 qdev_get_gpio_in_named(DEVICE(&s->ic), 469 BCM2835_IC_GPU_IRQ, 470 INTERRUPT_SPI)); 471 472 /* I2C */ 473 for (n = 0; n < 3; n++) { 474 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[n]), errp)) { 475 return; 476 } 477 } 478 479 memory_region_add_subregion(&s->peri_mr, BSC0_OFFSET, 480 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[0]), 0)); 481 memory_region_add_subregion(&s->peri_mr, BSC1_OFFSET, 482 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[1]), 0)); 483 memory_region_add_subregion(&s->peri_mr, BSC2_OFFSET, 484 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[2]), 0)); 485 486 if (!qdev_realize(DEVICE(&s->orgated_i2c_irq), NULL, errp)) { 487 return; 488 } 489 for (n = 0; n < ORGATED_I2C_IRQ_COUNT; n++) { 490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[n]), 0, 491 qdev_get_gpio_in(DEVICE(&s->orgated_i2c_irq), n)); 492 } 493 qdev_connect_gpio_out(DEVICE(&s->orgated_i2c_irq), 0, 494 qdev_get_gpio_in_named(DEVICE(&s->ic), 495 BCM2835_IC_GPU_IRQ, 496 INTERRUPT_I2C)); 497 498 create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000); 499 create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); 500 create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); 501 create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); 502 create_unimp(s, &s->bscsl, "bcm2835-spis", BSC_SL_OFFSET, 0x100); 503 create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80); 504 create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000); 505 create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000); 506 create_unimp(s, &s->v3d, "bcm2835-v3d", V3D_OFFSET, 0x1000); 507 create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100); 508 } 509 510 static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data) 511 { 512 DeviceClass *dc = DEVICE_CLASS(oc); 513 BCMSocPeripheralBaseClass *bc = BCM_SOC_PERIPHERALS_BASE_CLASS(oc); 514 515 bc->peri_size = 0x1000000; 516 dc->realize = bcm2835_peripherals_realize; 517 } 518 519 static const TypeInfo bcm2835_peripherals_types[] = { 520 { 521 .name = TYPE_BCM2835_PERIPHERALS, 522 .parent = TYPE_BCM_SOC_PERIPHERALS_BASE, 523 .instance_size = sizeof(BCM2835PeripheralState), 524 .instance_init = bcm2835_peripherals_init, 525 .class_init = bcm2835_peripherals_class_init, 526 }, { 527 .name = TYPE_BCM_SOC_PERIPHERALS_BASE, 528 .parent = TYPE_SYS_BUS_DEVICE, 529 .instance_size = sizeof(BCMSocPeripheralBaseState), 530 .instance_init = raspi_peripherals_base_init, 531 .class_size = sizeof(BCMSocPeripheralBaseClass), 532 .abstract = true, 533 } 534 }; 535 536 DEFINE_TYPES(bcm2835_peripherals_types) 537