1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/tpm.h" 49 #include "sysemu/tcg.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "sysemu/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/core/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/intc/arm_gicv3_its_common.h" 67 #include "hw/irq.h" 68 #include "kvm_arm.h" 69 #include "hw/firmware/smbios.h" 70 #include "qapi/visitor.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "standard-headers/linux/input.h" 73 #include "hw/arm/smmuv3.h" 74 #include "hw/acpi/acpi.h" 75 #include "target/arm/internals.h" 76 #include "hw/mem/memory-device.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "hw/acpi/generic_event_device.h" 80 #include "hw/virtio/virtio-mem-pci.h" 81 #include "hw/virtio/virtio-iommu.h" 82 #include "hw/char/pl011.h" 83 #include "qemu/guest-random.h" 84 85 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 86 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 87 void *data) \ 88 { \ 89 MachineClass *mc = MACHINE_CLASS(oc); \ 90 virt_machine_##major##_##minor##_options(mc); \ 91 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 92 if (latest) { \ 93 mc->alias = "virt"; \ 94 } \ 95 } \ 96 static const TypeInfo machvirt_##major##_##minor##_info = { \ 97 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 98 .parent = TYPE_VIRT_MACHINE, \ 99 .class_init = virt_##major##_##minor##_class_init, \ 100 }; \ 101 static void machvirt_machine_##major##_##minor##_init(void) \ 102 { \ 103 type_register_static(&machvirt_##major##_##minor##_info); \ 104 } \ 105 type_init(machvirt_machine_##major##_##minor##_init); 106 107 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 108 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 109 #define DEFINE_VIRT_MACHINE(major, minor) \ 110 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 111 112 113 /* Number of external interrupt lines to configure the GIC with */ 114 #define NUM_IRQS 256 115 116 #define PLATFORM_BUS_NUM_IRQS 64 117 118 /* Legacy RAM limit in GB (< version 4.0) */ 119 #define LEGACY_RAMLIMIT_GB 255 120 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 121 122 /* Addresses and sizes of our components. 123 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 124 * 128MB..256MB is used for miscellaneous device I/O. 125 * 256MB..1GB is reserved for possible future PCI support (ie where the 126 * PCI memory window will go if we add a PCI host controller). 127 * 1GB and up is RAM (which may happily spill over into the 128 * high memory region beyond 4GB). 129 * This represents a compromise between how much RAM can be given to 130 * a 32 bit VM and leaving space for expansion and in particular for PCI. 131 * Note that devices should generally be placed at multiples of 0x10000, 132 * to accommodate guests using 64K pages. 133 */ 134 static const MemMapEntry base_memmap[] = { 135 /* Space up to 0x8000000 is reserved for a boot ROM */ 136 [VIRT_FLASH] = { 0, 0x08000000 }, 137 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 138 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 139 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 140 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 141 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 142 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 143 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 144 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 145 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 146 /* This redistributor space allows up to 2*64kB*123 CPUs */ 147 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 148 [VIRT_UART] = { 0x09000000, 0x00001000 }, 149 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 150 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 151 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 152 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 153 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 154 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 155 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 156 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 157 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 158 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 159 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 160 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 161 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 162 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 163 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 164 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 165 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 166 /* Actual RAM size depends on initial RAM and device memory settings */ 167 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 168 }; 169 170 /* 171 * Highmem IO Regions: This memory map is floating, located after the RAM. 172 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 173 * top of the RAM, so that its base get the same alignment as the size, 174 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 175 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 176 * Note the extended_memmap is sized so that it eventually also includes the 177 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 178 * index of base_memmap). 179 * 180 * The memory map for these Highmem IO Regions can be in legacy or compact 181 * layout, depending on 'compact-highmem' property. With legacy layout, the 182 * PA space for one specific region is always reserved, even if the region 183 * has been disabled or doesn't fit into the PA space. However, the PA space 184 * for the region won't be reserved in these circumstances with compact layout. 185 */ 186 static MemMapEntry extended_memmap[] = { 187 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 188 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 189 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 190 /* Second PCIe window */ 191 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 192 }; 193 194 static const int a15irqmap[] = { 195 [VIRT_UART] = 1, 196 [VIRT_RTC] = 2, 197 [VIRT_PCIE] = 3, /* ... to 6 */ 198 [VIRT_GPIO] = 7, 199 [VIRT_SECURE_UART] = 8, 200 [VIRT_ACPI_GED] = 9, 201 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 202 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 203 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 204 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 205 }; 206 207 static const char *valid_cpus[] = { 208 #ifdef CONFIG_TCG 209 ARM_CPU_TYPE_NAME("cortex-a7"), 210 ARM_CPU_TYPE_NAME("cortex-a15"), 211 ARM_CPU_TYPE_NAME("cortex-a35"), 212 ARM_CPU_TYPE_NAME("cortex-a55"), 213 ARM_CPU_TYPE_NAME("cortex-a72"), 214 ARM_CPU_TYPE_NAME("cortex-a76"), 215 ARM_CPU_TYPE_NAME("a64fx"), 216 ARM_CPU_TYPE_NAME("neoverse-n1"), 217 ARM_CPU_TYPE_NAME("neoverse-v1"), 218 #endif 219 ARM_CPU_TYPE_NAME("cortex-a53"), 220 ARM_CPU_TYPE_NAME("cortex-a57"), 221 ARM_CPU_TYPE_NAME("host"), 222 ARM_CPU_TYPE_NAME("max"), 223 }; 224 225 static bool cpu_type_valid(const char *cpu) 226 { 227 int i; 228 229 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 230 if (strcmp(cpu, valid_cpus[i]) == 0) { 231 return true; 232 } 233 } 234 return false; 235 } 236 237 static void create_randomness(MachineState *ms, const char *node) 238 { 239 struct { 240 uint64_t kaslr; 241 uint8_t rng[32]; 242 } seed; 243 244 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 245 return; 246 } 247 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 248 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 249 } 250 251 static void create_fdt(VirtMachineState *vms) 252 { 253 MachineState *ms = MACHINE(vms); 254 int nb_numa_nodes = ms->numa_state->num_nodes; 255 void *fdt = create_device_tree(&vms->fdt_size); 256 257 if (!fdt) { 258 error_report("create_device_tree() failed"); 259 exit(1); 260 } 261 262 ms->fdt = fdt; 263 264 /* Header */ 265 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 266 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 267 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 268 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 269 270 /* /chosen must exist for load_dtb to fill in necessary properties later */ 271 qemu_fdt_add_subnode(fdt, "/chosen"); 272 if (vms->dtb_randomness) { 273 create_randomness(ms, "/chosen"); 274 } 275 276 if (vms->secure) { 277 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 278 if (vms->dtb_randomness) { 279 create_randomness(ms, "/secure-chosen"); 280 } 281 } 282 283 /* Clock node, for the benefit of the UART. The kernel device tree 284 * binding documentation claims the PL011 node clock properties are 285 * optional but in practice if you omit them the kernel refuses to 286 * probe for the device. 287 */ 288 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 289 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 290 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 291 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 292 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 293 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 294 "clk24mhz"); 295 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 296 297 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 298 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 299 uint32_t *matrix = g_malloc0(size); 300 int idx, i, j; 301 302 for (i = 0; i < nb_numa_nodes; i++) { 303 for (j = 0; j < nb_numa_nodes; j++) { 304 idx = (i * nb_numa_nodes + j) * 3; 305 matrix[idx + 0] = cpu_to_be32(i); 306 matrix[idx + 1] = cpu_to_be32(j); 307 matrix[idx + 2] = 308 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 309 } 310 } 311 312 qemu_fdt_add_subnode(fdt, "/distance-map"); 313 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 314 "numa-distance-map-v1"); 315 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 316 matrix, size); 317 g_free(matrix); 318 } 319 } 320 321 static void fdt_add_timer_nodes(const VirtMachineState *vms) 322 { 323 /* On real hardware these interrupts are level-triggered. 324 * On KVM they were edge-triggered before host kernel version 4.4, 325 * and level-triggered afterwards. 326 * On emulated QEMU they are level-triggered. 327 * 328 * Getting the DTB info about them wrong is awkward for some 329 * guest kernels: 330 * pre-4.8 ignore the DT and leave the interrupt configured 331 * with whatever the GIC reset value (or the bootloader) left it at 332 * 4.8 before rc6 honour the incorrect data by programming it back 333 * into the GIC, causing problems 334 * 4.8rc6 and later ignore the DT and always write "level triggered" 335 * into the GIC 336 * 337 * For backwards-compatibility, virt-2.8 and earlier will continue 338 * to say these are edge-triggered, but later machines will report 339 * the correct information. 340 */ 341 ARMCPU *armcpu; 342 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 343 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 344 MachineState *ms = MACHINE(vms); 345 346 if (vmc->claim_edge_triggered_timers) { 347 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 348 } 349 350 if (vms->gic_version == VIRT_GIC_VERSION_2) { 351 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 352 GIC_FDT_IRQ_PPI_CPU_WIDTH, 353 (1 << MACHINE(vms)->smp.cpus) - 1); 354 } 355 356 qemu_fdt_add_subnode(ms->fdt, "/timer"); 357 358 armcpu = ARM_CPU(qemu_get_cpu(0)); 359 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 360 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 361 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 362 compat, sizeof(compat)); 363 } else { 364 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 365 "arm,armv7-timer"); 366 } 367 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 368 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 369 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 370 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 371 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 372 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 373 } 374 375 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 376 { 377 int cpu; 378 int addr_cells = 1; 379 const MachineState *ms = MACHINE(vms); 380 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 381 int smp_cpus = ms->smp.cpus; 382 383 /* 384 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 385 * On ARM v8 64-bit systems value should be set to 2, 386 * that corresponds to the MPIDR_EL1 register size. 387 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 388 * in the system, #address-cells can be set to 1, since 389 * MPIDR_EL1[63:32] bits are not used for CPUs 390 * identification. 391 * 392 * Here we actually don't know whether our system is 32- or 64-bit one. 393 * The simplest way to go is to examine affinity IDs of all our CPUs. If 394 * at least one of them has Aff3 populated, we set #address-cells to 2. 395 */ 396 for (cpu = 0; cpu < smp_cpus; cpu++) { 397 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 398 399 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 400 addr_cells = 2; 401 break; 402 } 403 } 404 405 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 406 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 407 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 408 409 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 410 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 411 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 412 CPUState *cs = CPU(armcpu); 413 414 qemu_fdt_add_subnode(ms->fdt, nodename); 415 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 416 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 417 armcpu->dtb_compatible); 418 419 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 420 qemu_fdt_setprop_string(ms->fdt, nodename, 421 "enable-method", "psci"); 422 } 423 424 if (addr_cells == 2) { 425 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 426 armcpu->mp_affinity); 427 } else { 428 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 429 armcpu->mp_affinity); 430 } 431 432 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 433 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 434 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 435 } 436 437 if (!vmc->no_cpu_topology) { 438 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 439 qemu_fdt_alloc_phandle(ms->fdt)); 440 } 441 442 g_free(nodename); 443 } 444 445 if (!vmc->no_cpu_topology) { 446 /* 447 * Add vCPU topology description through fdt node cpu-map. 448 * 449 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 450 * In a SMP system, the hierarchy of CPUs can be defined through 451 * four entities that are used to describe the layout of CPUs in 452 * the system: socket/cluster/core/thread. 453 * 454 * A socket node represents the boundary of system physical package 455 * and its child nodes must be one or more cluster nodes. A system 456 * can contain several layers of clustering within a single physical 457 * package and cluster nodes can be contained in parent cluster nodes. 458 * 459 * Note: currently we only support one layer of clustering within 460 * each physical package. 461 */ 462 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 463 464 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 465 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 466 char *map_path; 467 468 if (ms->smp.threads > 1) { 469 map_path = g_strdup_printf( 470 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 471 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 472 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 473 (cpu / ms->smp.threads) % ms->smp.cores, 474 cpu % ms->smp.threads); 475 } else { 476 map_path = g_strdup_printf( 477 "/cpus/cpu-map/socket%d/cluster%d/core%d", 478 cpu / (ms->smp.clusters * ms->smp.cores), 479 (cpu / ms->smp.cores) % ms->smp.clusters, 480 cpu % ms->smp.cores); 481 } 482 qemu_fdt_add_path(ms->fdt, map_path); 483 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 484 485 g_free(map_path); 486 g_free(cpu_path); 487 } 488 } 489 } 490 491 static void fdt_add_its_gic_node(VirtMachineState *vms) 492 { 493 char *nodename; 494 MachineState *ms = MACHINE(vms); 495 496 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 497 nodename = g_strdup_printf("/intc/its@%" PRIx64, 498 vms->memmap[VIRT_GIC_ITS].base); 499 qemu_fdt_add_subnode(ms->fdt, nodename); 500 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 501 "arm,gic-v3-its"); 502 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 503 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 504 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 505 2, vms->memmap[VIRT_GIC_ITS].base, 506 2, vms->memmap[VIRT_GIC_ITS].size); 507 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 508 g_free(nodename); 509 } 510 511 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 512 { 513 MachineState *ms = MACHINE(vms); 514 char *nodename; 515 516 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 517 vms->memmap[VIRT_GIC_V2M].base); 518 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 519 qemu_fdt_add_subnode(ms->fdt, nodename); 520 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 521 "arm,gic-v2m-frame"); 522 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 523 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 524 2, vms->memmap[VIRT_GIC_V2M].base, 525 2, vms->memmap[VIRT_GIC_V2M].size); 526 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 527 g_free(nodename); 528 } 529 530 static void fdt_add_gic_node(VirtMachineState *vms) 531 { 532 MachineState *ms = MACHINE(vms); 533 char *nodename; 534 535 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 536 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 537 538 nodename = g_strdup_printf("/intc@%" PRIx64, 539 vms->memmap[VIRT_GIC_DIST].base); 540 qemu_fdt_add_subnode(ms->fdt, nodename); 541 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 542 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 543 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 544 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 545 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 546 if (vms->gic_version != VIRT_GIC_VERSION_2) { 547 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 548 549 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 550 "arm,gic-v3"); 551 552 qemu_fdt_setprop_cell(ms->fdt, nodename, 553 "#redistributor-regions", nb_redist_regions); 554 555 if (nb_redist_regions == 1) { 556 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 557 2, vms->memmap[VIRT_GIC_DIST].base, 558 2, vms->memmap[VIRT_GIC_DIST].size, 559 2, vms->memmap[VIRT_GIC_REDIST].base, 560 2, vms->memmap[VIRT_GIC_REDIST].size); 561 } else { 562 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 563 2, vms->memmap[VIRT_GIC_DIST].base, 564 2, vms->memmap[VIRT_GIC_DIST].size, 565 2, vms->memmap[VIRT_GIC_REDIST].base, 566 2, vms->memmap[VIRT_GIC_REDIST].size, 567 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 568 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 569 } 570 571 if (vms->virt) { 572 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 573 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 574 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 575 } 576 } else { 577 /* 'cortex-a15-gic' means 'GIC v2' */ 578 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 579 "arm,cortex-a15-gic"); 580 if (!vms->virt) { 581 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 582 2, vms->memmap[VIRT_GIC_DIST].base, 583 2, vms->memmap[VIRT_GIC_DIST].size, 584 2, vms->memmap[VIRT_GIC_CPU].base, 585 2, vms->memmap[VIRT_GIC_CPU].size); 586 } else { 587 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 588 2, vms->memmap[VIRT_GIC_DIST].base, 589 2, vms->memmap[VIRT_GIC_DIST].size, 590 2, vms->memmap[VIRT_GIC_CPU].base, 591 2, vms->memmap[VIRT_GIC_CPU].size, 592 2, vms->memmap[VIRT_GIC_HYP].base, 593 2, vms->memmap[VIRT_GIC_HYP].size, 594 2, vms->memmap[VIRT_GIC_VCPU].base, 595 2, vms->memmap[VIRT_GIC_VCPU].size); 596 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 597 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 598 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 599 } 600 } 601 602 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 603 g_free(nodename); 604 } 605 606 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 607 { 608 ARMCPU *armcpu = ARM_CPU(first_cpu); 609 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 610 MachineState *ms = MACHINE(vms); 611 612 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 613 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 614 return; 615 } 616 617 if (vms->gic_version == VIRT_GIC_VERSION_2) { 618 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 619 GIC_FDT_IRQ_PPI_CPU_WIDTH, 620 (1 << MACHINE(vms)->smp.cpus) - 1); 621 } 622 623 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 624 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 625 const char compat[] = "arm,armv8-pmuv3"; 626 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 627 compat, sizeof(compat)); 628 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 629 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 630 } 631 } 632 633 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 634 { 635 DeviceState *dev; 636 MachineState *ms = MACHINE(vms); 637 int irq = vms->irqmap[VIRT_ACPI_GED]; 638 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 639 640 if (ms->ram_slots) { 641 event |= ACPI_GED_MEM_HOTPLUG_EVT; 642 } 643 644 if (ms->nvdimms_state->is_enabled) { 645 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 646 } 647 648 dev = qdev_new(TYPE_ACPI_GED); 649 qdev_prop_set_uint32(dev, "ged-event", event); 650 651 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 652 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 653 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 654 655 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 656 657 return dev; 658 } 659 660 static void create_its(VirtMachineState *vms) 661 { 662 const char *itsclass = its_class_name(); 663 DeviceState *dev; 664 665 if (!strcmp(itsclass, "arm-gicv3-its")) { 666 if (!vms->tcg_its) { 667 itsclass = NULL; 668 } 669 } 670 671 if (!itsclass) { 672 /* Do nothing if not supported */ 673 return; 674 } 675 676 dev = qdev_new(itsclass); 677 678 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 679 &error_abort); 680 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 681 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 682 683 fdt_add_its_gic_node(vms); 684 vms->msi_controller = VIRT_MSI_CTRL_ITS; 685 } 686 687 static void create_v2m(VirtMachineState *vms) 688 { 689 int i; 690 int irq = vms->irqmap[VIRT_GIC_V2M]; 691 DeviceState *dev; 692 693 dev = qdev_new("arm-gicv2m"); 694 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 695 qdev_prop_set_uint32(dev, "base-spi", irq); 696 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 697 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 698 699 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 700 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 701 qdev_get_gpio_in(vms->gic, irq + i)); 702 } 703 704 fdt_add_v2m_gic_node(vms); 705 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 706 } 707 708 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 709 { 710 MachineState *ms = MACHINE(vms); 711 /* We create a standalone GIC */ 712 SysBusDevice *gicbusdev; 713 const char *gictype; 714 int i; 715 unsigned int smp_cpus = ms->smp.cpus; 716 uint32_t nb_redist_regions = 0; 717 int revision; 718 719 if (vms->gic_version == VIRT_GIC_VERSION_2) { 720 gictype = gic_class_name(); 721 } else { 722 gictype = gicv3_class_name(); 723 } 724 725 switch (vms->gic_version) { 726 case VIRT_GIC_VERSION_2: 727 revision = 2; 728 break; 729 case VIRT_GIC_VERSION_3: 730 revision = 3; 731 break; 732 case VIRT_GIC_VERSION_4: 733 revision = 4; 734 break; 735 default: 736 g_assert_not_reached(); 737 } 738 vms->gic = qdev_new(gictype); 739 qdev_prop_set_uint32(vms->gic, "revision", revision); 740 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 741 /* Note that the num-irq property counts both internal and external 742 * interrupts; there are always 32 of the former (mandated by GIC spec). 743 */ 744 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 745 if (!kvm_irqchip_in_kernel()) { 746 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 747 } 748 749 if (vms->gic_version != VIRT_GIC_VERSION_2) { 750 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 751 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 752 753 nb_redist_regions = virt_gicv3_redist_region_count(vms); 754 755 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 756 nb_redist_regions); 757 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 758 759 if (!kvm_irqchip_in_kernel()) { 760 if (vms->tcg_its) { 761 object_property_set_link(OBJECT(vms->gic), "sysmem", 762 OBJECT(mem), &error_fatal); 763 qdev_prop_set_bit(vms->gic, "has-lpi", true); 764 } 765 } 766 767 if (nb_redist_regions == 2) { 768 uint32_t redist1_capacity = 769 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 770 771 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 772 MIN(smp_cpus - redist0_count, redist1_capacity)); 773 } 774 } else { 775 if (!kvm_irqchip_in_kernel()) { 776 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 777 vms->virt); 778 } 779 } 780 gicbusdev = SYS_BUS_DEVICE(vms->gic); 781 sysbus_realize_and_unref(gicbusdev, &error_fatal); 782 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 783 if (vms->gic_version != VIRT_GIC_VERSION_2) { 784 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 785 if (nb_redist_regions == 2) { 786 sysbus_mmio_map(gicbusdev, 2, 787 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 788 } 789 } else { 790 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 791 if (vms->virt) { 792 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 793 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 794 } 795 } 796 797 /* Wire the outputs from each CPU's generic timer and the GICv3 798 * maintenance interrupt signal to the appropriate GIC PPI inputs, 799 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 800 */ 801 for (i = 0; i < smp_cpus; i++) { 802 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 803 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 804 int irq; 805 /* Mapping from the output timer irq lines from the CPU to the 806 * GIC PPI inputs we use for the virt board. 807 */ 808 const int timer_irq[] = { 809 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 810 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 811 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 812 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 813 }; 814 815 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 816 qdev_connect_gpio_out(cpudev, irq, 817 qdev_get_gpio_in(vms->gic, 818 ppibase + timer_irq[irq])); 819 } 820 821 if (vms->gic_version != VIRT_GIC_VERSION_2) { 822 qemu_irq irq = qdev_get_gpio_in(vms->gic, 823 ppibase + ARCH_GIC_MAINT_IRQ); 824 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 825 0, irq); 826 } else if (vms->virt) { 827 qemu_irq irq = qdev_get_gpio_in(vms->gic, 828 ppibase + ARCH_GIC_MAINT_IRQ); 829 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 830 } 831 832 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 833 qdev_get_gpio_in(vms->gic, ppibase 834 + VIRTUAL_PMU_IRQ)); 835 836 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 837 sysbus_connect_irq(gicbusdev, i + smp_cpus, 838 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 839 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 840 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 841 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 842 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 843 } 844 845 fdt_add_gic_node(vms); 846 847 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 848 create_its(vms); 849 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 850 create_v2m(vms); 851 } 852 } 853 854 static void create_uart(const VirtMachineState *vms, int uart, 855 MemoryRegion *mem, Chardev *chr) 856 { 857 char *nodename; 858 hwaddr base = vms->memmap[uart].base; 859 hwaddr size = vms->memmap[uart].size; 860 int irq = vms->irqmap[uart]; 861 const char compat[] = "arm,pl011\0arm,primecell"; 862 const char clocknames[] = "uartclk\0apb_pclk"; 863 DeviceState *dev = qdev_new(TYPE_PL011); 864 SysBusDevice *s = SYS_BUS_DEVICE(dev); 865 MachineState *ms = MACHINE(vms); 866 867 qdev_prop_set_chr(dev, "chardev", chr); 868 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 869 memory_region_add_subregion(mem, base, 870 sysbus_mmio_get_region(s, 0)); 871 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 872 873 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 874 qemu_fdt_add_subnode(ms->fdt, nodename); 875 /* Note that we can't use setprop_string because of the embedded NUL */ 876 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 877 compat, sizeof(compat)); 878 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 879 2, base, 2, size); 880 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 881 GIC_FDT_IRQ_TYPE_SPI, irq, 882 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 883 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 884 vms->clock_phandle, vms->clock_phandle); 885 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 886 clocknames, sizeof(clocknames)); 887 888 if (uart == VIRT_UART) { 889 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 890 } else { 891 /* Mark as not usable by the normal world */ 892 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 893 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 894 895 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 896 nodename); 897 } 898 899 g_free(nodename); 900 } 901 902 static void create_rtc(const VirtMachineState *vms) 903 { 904 char *nodename; 905 hwaddr base = vms->memmap[VIRT_RTC].base; 906 hwaddr size = vms->memmap[VIRT_RTC].size; 907 int irq = vms->irqmap[VIRT_RTC]; 908 const char compat[] = "arm,pl031\0arm,primecell"; 909 MachineState *ms = MACHINE(vms); 910 911 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 912 913 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 914 qemu_fdt_add_subnode(ms->fdt, nodename); 915 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 916 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 917 2, base, 2, size); 918 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 919 GIC_FDT_IRQ_TYPE_SPI, irq, 920 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 921 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 922 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 923 g_free(nodename); 924 } 925 926 static DeviceState *gpio_key_dev; 927 static void virt_powerdown_req(Notifier *n, void *opaque) 928 { 929 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 930 931 if (s->acpi_dev) { 932 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 933 } else { 934 /* use gpio Pin 3 for power button event */ 935 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 936 } 937 } 938 939 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 940 uint32_t phandle) 941 { 942 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 943 qdev_get_gpio_in(pl061_dev, 3)); 944 945 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 946 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 947 948 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 949 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 950 "label", "GPIO Key Poweroff"); 951 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 952 KEY_POWER); 953 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 954 "gpios", phandle, 3, 0); 955 } 956 957 #define SECURE_GPIO_POWEROFF 0 958 #define SECURE_GPIO_RESET 1 959 960 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 961 uint32_t phandle) 962 { 963 DeviceState *gpio_pwr_dev; 964 965 /* gpio-pwr */ 966 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 967 968 /* connect secure pl061 to gpio-pwr */ 969 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 970 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 971 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 972 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 973 974 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 975 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 976 "gpio-poweroff"); 977 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 978 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 979 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 980 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 981 "okay"); 982 983 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 984 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 985 "gpio-restart"); 986 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 987 "gpios", phandle, SECURE_GPIO_RESET, 0); 988 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 989 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 990 "okay"); 991 } 992 993 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 994 MemoryRegion *mem) 995 { 996 char *nodename; 997 DeviceState *pl061_dev; 998 hwaddr base = vms->memmap[gpio].base; 999 hwaddr size = vms->memmap[gpio].size; 1000 int irq = vms->irqmap[gpio]; 1001 const char compat[] = "arm,pl061\0arm,primecell"; 1002 SysBusDevice *s; 1003 MachineState *ms = MACHINE(vms); 1004 1005 pl061_dev = qdev_new("pl061"); 1006 /* Pull lines down to 0 if not driven by the PL061 */ 1007 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1008 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1009 s = SYS_BUS_DEVICE(pl061_dev); 1010 sysbus_realize_and_unref(s, &error_fatal); 1011 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1012 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1013 1014 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1015 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1016 qemu_fdt_add_subnode(ms->fdt, nodename); 1017 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1018 2, base, 2, size); 1019 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1020 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1021 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1022 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1023 GIC_FDT_IRQ_TYPE_SPI, irq, 1024 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1025 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1026 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1027 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1028 1029 if (gpio != VIRT_GPIO) { 1030 /* Mark as not usable by the normal world */ 1031 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1032 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1033 } 1034 g_free(nodename); 1035 1036 /* Child gpio devices */ 1037 if (gpio == VIRT_GPIO) { 1038 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1039 } else { 1040 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1041 } 1042 } 1043 1044 static void create_virtio_devices(const VirtMachineState *vms) 1045 { 1046 int i; 1047 hwaddr size = vms->memmap[VIRT_MMIO].size; 1048 MachineState *ms = MACHINE(vms); 1049 1050 /* We create the transports in forwards order. Since qbus_realize() 1051 * prepends (not appends) new child buses, the incrementing loop below will 1052 * create a list of virtio-mmio buses with decreasing base addresses. 1053 * 1054 * When a -device option is processed from the command line, 1055 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1056 * order. The upshot is that -device options in increasing command line 1057 * order are mapped to virtio-mmio buses with decreasing base addresses. 1058 * 1059 * When this code was originally written, that arrangement ensured that the 1060 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1061 * the first -device on the command line. (The end-to-end order is a 1062 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1063 * guest kernel's name-to-address assignment strategy.) 1064 * 1065 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1066 * the message, if not necessarily the code, of commit 70161ff336. 1067 * Therefore the loop now establishes the inverse of the original intent. 1068 * 1069 * Unfortunately, we can't counteract the kernel change by reversing the 1070 * loop; it would break existing command lines. 1071 * 1072 * In any case, the kernel makes no guarantee about the stability of 1073 * enumeration order of virtio devices (as demonstrated by it changing 1074 * between kernel versions). For reliable and stable identification 1075 * of disks users must use UUIDs or similar mechanisms. 1076 */ 1077 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1078 int irq = vms->irqmap[VIRT_MMIO] + i; 1079 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1080 1081 sysbus_create_simple("virtio-mmio", base, 1082 qdev_get_gpio_in(vms->gic, irq)); 1083 } 1084 1085 /* We add dtb nodes in reverse order so that they appear in the finished 1086 * device tree lowest address first. 1087 * 1088 * Note that this mapping is independent of the loop above. The previous 1089 * loop influences virtio device to virtio transport assignment, whereas 1090 * this loop controls how virtio transports are laid out in the dtb. 1091 */ 1092 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1093 char *nodename; 1094 int irq = vms->irqmap[VIRT_MMIO] + i; 1095 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1096 1097 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1098 qemu_fdt_add_subnode(ms->fdt, nodename); 1099 qemu_fdt_setprop_string(ms->fdt, nodename, 1100 "compatible", "virtio,mmio"); 1101 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1102 2, base, 2, size); 1103 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1104 GIC_FDT_IRQ_TYPE_SPI, irq, 1105 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1106 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1107 g_free(nodename); 1108 } 1109 } 1110 1111 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1112 1113 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1114 const char *name, 1115 const char *alias_prop_name) 1116 { 1117 /* 1118 * Create a single flash device. We use the same parameters as 1119 * the flash devices on the Versatile Express board. 1120 */ 1121 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1122 1123 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1124 qdev_prop_set_uint8(dev, "width", 4); 1125 qdev_prop_set_uint8(dev, "device-width", 2); 1126 qdev_prop_set_bit(dev, "big-endian", false); 1127 qdev_prop_set_uint16(dev, "id0", 0x89); 1128 qdev_prop_set_uint16(dev, "id1", 0x18); 1129 qdev_prop_set_uint16(dev, "id2", 0x00); 1130 qdev_prop_set_uint16(dev, "id3", 0x00); 1131 qdev_prop_set_string(dev, "name", name); 1132 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1133 object_property_add_alias(OBJECT(vms), alias_prop_name, 1134 OBJECT(dev), "drive"); 1135 return PFLASH_CFI01(dev); 1136 } 1137 1138 static void virt_flash_create(VirtMachineState *vms) 1139 { 1140 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1141 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1142 } 1143 1144 static void virt_flash_map1(PFlashCFI01 *flash, 1145 hwaddr base, hwaddr size, 1146 MemoryRegion *sysmem) 1147 { 1148 DeviceState *dev = DEVICE(flash); 1149 1150 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1151 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1152 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1153 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1154 1155 memory_region_add_subregion(sysmem, base, 1156 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1157 0)); 1158 } 1159 1160 static void virt_flash_map(VirtMachineState *vms, 1161 MemoryRegion *sysmem, 1162 MemoryRegion *secure_sysmem) 1163 { 1164 /* 1165 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1166 * sysmem is the system memory space. secure_sysmem is the secure view 1167 * of the system, and the first flash device should be made visible only 1168 * there. The second flash device is visible to both secure and nonsecure. 1169 * If sysmem == secure_sysmem this means there is no separate Secure 1170 * address space and both flash devices are generally visible. 1171 */ 1172 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1173 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1174 1175 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1176 secure_sysmem); 1177 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1178 sysmem); 1179 } 1180 1181 static void virt_flash_fdt(VirtMachineState *vms, 1182 MemoryRegion *sysmem, 1183 MemoryRegion *secure_sysmem) 1184 { 1185 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1186 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1187 MachineState *ms = MACHINE(vms); 1188 char *nodename; 1189 1190 if (sysmem == secure_sysmem) { 1191 /* Report both flash devices as a single node in the DT */ 1192 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1193 qemu_fdt_add_subnode(ms->fdt, nodename); 1194 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1195 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1196 2, flashbase, 2, flashsize, 1197 2, flashbase + flashsize, 2, flashsize); 1198 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1199 g_free(nodename); 1200 } else { 1201 /* 1202 * Report the devices as separate nodes so we can mark one as 1203 * only visible to the secure world. 1204 */ 1205 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1206 qemu_fdt_add_subnode(ms->fdt, nodename); 1207 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1208 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1209 2, flashbase, 2, flashsize); 1210 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1211 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1212 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1213 g_free(nodename); 1214 1215 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1216 qemu_fdt_add_subnode(ms->fdt, nodename); 1217 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1218 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1219 2, flashbase + flashsize, 2, flashsize); 1220 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1221 g_free(nodename); 1222 } 1223 } 1224 1225 static bool virt_firmware_init(VirtMachineState *vms, 1226 MemoryRegion *sysmem, 1227 MemoryRegion *secure_sysmem) 1228 { 1229 int i; 1230 const char *bios_name; 1231 BlockBackend *pflash_blk0; 1232 1233 /* Map legacy -drive if=pflash to machine properties */ 1234 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1235 pflash_cfi01_legacy_drive(vms->flash[i], 1236 drive_get(IF_PFLASH, 0, i)); 1237 } 1238 1239 virt_flash_map(vms, sysmem, secure_sysmem); 1240 1241 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1242 1243 bios_name = MACHINE(vms)->firmware; 1244 if (bios_name) { 1245 char *fname; 1246 MemoryRegion *mr; 1247 int image_size; 1248 1249 if (pflash_blk0) { 1250 error_report("The contents of the first flash device may be " 1251 "specified with -bios or with -drive if=pflash... " 1252 "but you cannot use both options at once"); 1253 exit(1); 1254 } 1255 1256 /* Fall back to -bios */ 1257 1258 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1259 if (!fname) { 1260 error_report("Could not find ROM image '%s'", bios_name); 1261 exit(1); 1262 } 1263 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1264 image_size = load_image_mr(fname, mr); 1265 g_free(fname); 1266 if (image_size < 0) { 1267 error_report("Could not load ROM image '%s'", bios_name); 1268 exit(1); 1269 } 1270 } 1271 1272 return pflash_blk0 || bios_name; 1273 } 1274 1275 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1276 { 1277 MachineState *ms = MACHINE(vms); 1278 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1279 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1280 FWCfgState *fw_cfg; 1281 char *nodename; 1282 1283 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1284 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1285 1286 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1287 qemu_fdt_add_subnode(ms->fdt, nodename); 1288 qemu_fdt_setprop_string(ms->fdt, nodename, 1289 "compatible", "qemu,fw-cfg-mmio"); 1290 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1291 2, base, 2, size); 1292 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1293 g_free(nodename); 1294 return fw_cfg; 1295 } 1296 1297 static void create_pcie_irq_map(const MachineState *ms, 1298 uint32_t gic_phandle, 1299 int first_irq, const char *nodename) 1300 { 1301 int devfn, pin; 1302 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1303 uint32_t *irq_map = full_irq_map; 1304 1305 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1306 for (pin = 0; pin < 4; pin++) { 1307 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1308 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1309 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1310 int i; 1311 1312 uint32_t map[] = { 1313 devfn << 8, 0, 0, /* devfn */ 1314 pin + 1, /* PCI pin */ 1315 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1316 1317 /* Convert map to big endian */ 1318 for (i = 0; i < 10; i++) { 1319 irq_map[i] = cpu_to_be32(map[i]); 1320 } 1321 irq_map += 10; 1322 } 1323 } 1324 1325 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1326 full_irq_map, sizeof(full_irq_map)); 1327 1328 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1329 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1330 0, 0, 1331 0x7 /* PCI irq */); 1332 } 1333 1334 static void create_smmu(const VirtMachineState *vms, 1335 PCIBus *bus) 1336 { 1337 char *node; 1338 const char compat[] = "arm,smmu-v3"; 1339 int irq = vms->irqmap[VIRT_SMMU]; 1340 int i; 1341 hwaddr base = vms->memmap[VIRT_SMMU].base; 1342 hwaddr size = vms->memmap[VIRT_SMMU].size; 1343 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1344 DeviceState *dev; 1345 MachineState *ms = MACHINE(vms); 1346 1347 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1348 return; 1349 } 1350 1351 dev = qdev_new(TYPE_ARM_SMMUV3); 1352 1353 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1354 &error_abort); 1355 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1356 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1357 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1358 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1359 qdev_get_gpio_in(vms->gic, irq + i)); 1360 } 1361 1362 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1363 qemu_fdt_add_subnode(ms->fdt, node); 1364 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1365 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1366 1367 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1368 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1369 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1370 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1371 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1372 1373 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1374 sizeof(irq_names)); 1375 1376 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1377 1378 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1379 1380 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1381 g_free(node); 1382 } 1383 1384 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1385 { 1386 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1387 uint16_t bdf = vms->virtio_iommu_bdf; 1388 MachineState *ms = MACHINE(vms); 1389 char *node; 1390 1391 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1392 1393 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1394 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1395 qemu_fdt_add_subnode(ms->fdt, node); 1396 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1397 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1398 1, bdf << 8, 1, 0, 1, 0, 1399 1, 0, 1, 0); 1400 1401 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1402 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1403 g_free(node); 1404 1405 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1406 0x0, vms->iommu_phandle, 0x0, bdf, 1407 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1408 } 1409 1410 static void create_pcie(VirtMachineState *vms) 1411 { 1412 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1413 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1414 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1415 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1416 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1417 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1418 hwaddr base_ecam, size_ecam; 1419 hwaddr base = base_mmio; 1420 int nr_pcie_buses; 1421 int irq = vms->irqmap[VIRT_PCIE]; 1422 MemoryRegion *mmio_alias; 1423 MemoryRegion *mmio_reg; 1424 MemoryRegion *ecam_alias; 1425 MemoryRegion *ecam_reg; 1426 DeviceState *dev; 1427 char *nodename; 1428 int i, ecam_id; 1429 PCIHostState *pci; 1430 MachineState *ms = MACHINE(vms); 1431 MachineClass *mc = MACHINE_GET_CLASS(ms); 1432 1433 dev = qdev_new(TYPE_GPEX_HOST); 1434 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1435 1436 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1437 base_ecam = vms->memmap[ecam_id].base; 1438 size_ecam = vms->memmap[ecam_id].size; 1439 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1440 /* Map only the first size_ecam bytes of ECAM space */ 1441 ecam_alias = g_new0(MemoryRegion, 1); 1442 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1443 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1444 ecam_reg, 0, size_ecam); 1445 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1446 1447 /* Map the MMIO window into system address space so as to expose 1448 * the section of PCI MMIO space which starts at the same base address 1449 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1450 * the window). 1451 */ 1452 mmio_alias = g_new0(MemoryRegion, 1); 1453 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1454 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1455 mmio_reg, base_mmio, size_mmio); 1456 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1457 1458 if (vms->highmem_mmio) { 1459 /* Map high MMIO space */ 1460 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1461 1462 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1463 mmio_reg, base_mmio_high, size_mmio_high); 1464 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1465 high_mmio_alias); 1466 } 1467 1468 /* Map IO port space */ 1469 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1470 1471 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1472 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1473 qdev_get_gpio_in(vms->gic, irq + i)); 1474 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1475 } 1476 1477 pci = PCI_HOST_BRIDGE(dev); 1478 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1479 vms->bus = pci->bus; 1480 if (vms->bus) { 1481 for (i = 0; i < nb_nics; i++) { 1482 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); 1483 } 1484 } 1485 1486 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1487 qemu_fdt_add_subnode(ms->fdt, nodename); 1488 qemu_fdt_setprop_string(ms->fdt, nodename, 1489 "compatible", "pci-host-ecam-generic"); 1490 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1491 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1492 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1493 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1494 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1495 nr_pcie_buses - 1); 1496 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1497 1498 if (vms->msi_phandle) { 1499 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1500 0, vms->msi_phandle, 0, 0x10000); 1501 } 1502 1503 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1504 2, base_ecam, 2, size_ecam); 1505 1506 if (vms->highmem_mmio) { 1507 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1508 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1509 2, base_pio, 2, size_pio, 1510 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1511 2, base_mmio, 2, size_mmio, 1512 1, FDT_PCI_RANGE_MMIO_64BIT, 1513 2, base_mmio_high, 1514 2, base_mmio_high, 2, size_mmio_high); 1515 } else { 1516 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1517 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1518 2, base_pio, 2, size_pio, 1519 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1520 2, base_mmio, 2, size_mmio); 1521 } 1522 1523 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1524 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1525 1526 if (vms->iommu) { 1527 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1528 1529 switch (vms->iommu) { 1530 case VIRT_IOMMU_SMMUV3: 1531 create_smmu(vms, vms->bus); 1532 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1533 0x0, vms->iommu_phandle, 0x0, 0x10000); 1534 break; 1535 default: 1536 g_assert_not_reached(); 1537 } 1538 } 1539 } 1540 1541 static void create_platform_bus(VirtMachineState *vms) 1542 { 1543 DeviceState *dev; 1544 SysBusDevice *s; 1545 int i; 1546 MemoryRegion *sysmem = get_system_memory(); 1547 1548 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1549 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1550 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1551 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1552 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1553 vms->platform_bus_dev = dev; 1554 1555 s = SYS_BUS_DEVICE(dev); 1556 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1557 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1558 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1559 } 1560 1561 memory_region_add_subregion(sysmem, 1562 vms->memmap[VIRT_PLATFORM_BUS].base, 1563 sysbus_mmio_get_region(s, 0)); 1564 } 1565 1566 static void create_tag_ram(MemoryRegion *tag_sysmem, 1567 hwaddr base, hwaddr size, 1568 const char *name) 1569 { 1570 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1571 1572 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1573 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1574 } 1575 1576 static void create_secure_ram(VirtMachineState *vms, 1577 MemoryRegion *secure_sysmem, 1578 MemoryRegion *secure_tag_sysmem) 1579 { 1580 MemoryRegion *secram = g_new(MemoryRegion, 1); 1581 char *nodename; 1582 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1583 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1584 MachineState *ms = MACHINE(vms); 1585 1586 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1587 &error_fatal); 1588 memory_region_add_subregion(secure_sysmem, base, secram); 1589 1590 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1591 qemu_fdt_add_subnode(ms->fdt, nodename); 1592 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1593 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1594 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1595 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1596 1597 if (secure_tag_sysmem) { 1598 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1599 } 1600 1601 g_free(nodename); 1602 } 1603 1604 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1605 { 1606 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1607 bootinfo); 1608 MachineState *ms = MACHINE(board); 1609 1610 1611 *fdt_size = board->fdt_size; 1612 return ms->fdt; 1613 } 1614 1615 static void virt_build_smbios(VirtMachineState *vms) 1616 { 1617 MachineClass *mc = MACHINE_GET_CLASS(vms); 1618 MachineState *ms = MACHINE(vms); 1619 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1620 uint8_t *smbios_tables, *smbios_anchor; 1621 size_t smbios_tables_len, smbios_anchor_len; 1622 struct smbios_phys_mem_area mem_array; 1623 const char *product = "QEMU Virtual Machine"; 1624 1625 if (kvm_enabled()) { 1626 product = "KVM Virtual Machine"; 1627 } 1628 1629 smbios_set_defaults("QEMU", product, 1630 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1631 true, SMBIOS_ENTRY_POINT_TYPE_64); 1632 1633 /* build the array of physical mem area from base_memmap */ 1634 mem_array.address = vms->memmap[VIRT_MEM].base; 1635 mem_array.length = ms->ram_size; 1636 1637 smbios_get_tables(ms, &mem_array, 1, 1638 &smbios_tables, &smbios_tables_len, 1639 &smbios_anchor, &smbios_anchor_len, 1640 &error_fatal); 1641 1642 if (smbios_anchor) { 1643 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1644 smbios_tables, smbios_tables_len); 1645 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1646 smbios_anchor, smbios_anchor_len); 1647 } 1648 } 1649 1650 static 1651 void virt_machine_done(Notifier *notifier, void *data) 1652 { 1653 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1654 machine_done); 1655 MachineState *ms = MACHINE(vms); 1656 ARMCPU *cpu = ARM_CPU(first_cpu); 1657 struct arm_boot_info *info = &vms->bootinfo; 1658 AddressSpace *as = arm_boot_address_space(cpu, info); 1659 1660 /* 1661 * If the user provided a dtb, we assume the dynamic sysbus nodes 1662 * already are integrated there. This corresponds to a use case where 1663 * the dynamic sysbus nodes are complex and their generation is not yet 1664 * supported. In that case the user can take charge of the guest dt 1665 * while qemu takes charge of the qom stuff. 1666 */ 1667 if (info->dtb_filename == NULL) { 1668 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1669 vms->memmap[VIRT_PLATFORM_BUS].base, 1670 vms->memmap[VIRT_PLATFORM_BUS].size, 1671 vms->irqmap[VIRT_PLATFORM_BUS]); 1672 } 1673 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1674 exit(1); 1675 } 1676 1677 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1678 1679 virt_acpi_setup(vms); 1680 virt_build_smbios(vms); 1681 } 1682 1683 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1684 { 1685 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1686 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1687 1688 if (!vmc->disallow_affinity_adjustment) { 1689 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1690 * GIC's target-list limitations. 32-bit KVM hosts currently 1691 * always create clusters of 4 CPUs, but that is expected to 1692 * change when they gain support for gicv3. When KVM is enabled 1693 * it will override the changes we make here, therefore our 1694 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1695 * and to improve SGI efficiency. 1696 */ 1697 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1698 clustersz = GIC_TARGETLIST_BITS; 1699 } else { 1700 clustersz = GICV3_TARGETLIST_BITS; 1701 } 1702 } 1703 return arm_cpu_mp_affinity(idx, clustersz); 1704 } 1705 1706 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1707 int index) 1708 { 1709 bool *enabled_array[] = { 1710 &vms->highmem_redists, 1711 &vms->highmem_ecam, 1712 &vms->highmem_mmio, 1713 }; 1714 1715 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1716 ARRAY_SIZE(enabled_array)); 1717 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1718 1719 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1720 } 1721 1722 static void virt_set_high_memmap(VirtMachineState *vms, 1723 hwaddr base, int pa_bits) 1724 { 1725 hwaddr region_base, region_size; 1726 bool *region_enabled, fits; 1727 int i; 1728 1729 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1730 region_enabled = virt_get_high_memmap_enabled(vms, i); 1731 region_base = ROUND_UP(base, extended_memmap[i].size); 1732 region_size = extended_memmap[i].size; 1733 1734 vms->memmap[i].base = region_base; 1735 vms->memmap[i].size = region_size; 1736 1737 /* 1738 * Check each device to see if it fits in the PA space, 1739 * moving highest_gpa as we go. For compatibility, move 1740 * highest_gpa for disabled fitting devices as well, if 1741 * the compact layout has been disabled. 1742 * 1743 * For each device that doesn't fit, disable it. 1744 */ 1745 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1746 *region_enabled &= fits; 1747 if (vms->highmem_compact && !*region_enabled) { 1748 continue; 1749 } 1750 1751 base = region_base + region_size; 1752 if (fits) { 1753 vms->highest_gpa = base - 1; 1754 } 1755 } 1756 } 1757 1758 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1759 { 1760 MachineState *ms = MACHINE(vms); 1761 hwaddr base, device_memory_base, device_memory_size, memtop; 1762 int i; 1763 1764 vms->memmap = extended_memmap; 1765 1766 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1767 vms->memmap[i] = base_memmap[i]; 1768 } 1769 1770 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1771 error_report("unsupported number of memory slots: %"PRIu64, 1772 ms->ram_slots); 1773 exit(EXIT_FAILURE); 1774 } 1775 1776 /* 1777 * !highmem is exactly the same as limiting the PA space to 32bit, 1778 * irrespective of the underlying capabilities of the HW. 1779 */ 1780 if (!vms->highmem) { 1781 pa_bits = 32; 1782 } 1783 1784 /* 1785 * We compute the base of the high IO region depending on the 1786 * amount of initial and device memory. The device memory start/size 1787 * is aligned on 1GiB. We never put the high IO region below 256GiB 1788 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1789 * The device region size assumes 1GiB page max alignment per slot. 1790 */ 1791 device_memory_base = 1792 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1793 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1794 1795 /* Base address of the high IO region */ 1796 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1797 if (memtop > BIT_ULL(pa_bits)) { 1798 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1799 pa_bits, memtop - BIT_ULL(pa_bits)); 1800 exit(EXIT_FAILURE); 1801 } 1802 if (base < device_memory_base) { 1803 error_report("maxmem/slots too huge"); 1804 exit(EXIT_FAILURE); 1805 } 1806 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1807 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1808 } 1809 1810 /* We know for sure that at least the memory fits in the PA space */ 1811 vms->highest_gpa = memtop - 1; 1812 1813 virt_set_high_memmap(vms, base, pa_bits); 1814 1815 if (device_memory_size > 0) { 1816 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1817 ms->device_memory->base = device_memory_base; 1818 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1819 "device-memory", device_memory_size); 1820 } 1821 } 1822 1823 static VirtGICType finalize_gic_version_do(const char *accel_name, 1824 VirtGICType gic_version, 1825 int gics_supported, 1826 unsigned int max_cpus) 1827 { 1828 /* Convert host/max/nosel to GIC version number */ 1829 switch (gic_version) { 1830 case VIRT_GIC_VERSION_HOST: 1831 if (!kvm_enabled()) { 1832 error_report("gic-version=host requires KVM"); 1833 exit(1); 1834 } 1835 1836 /* For KVM, gic-version=host means gic-version=max */ 1837 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1838 gics_supported, max_cpus); 1839 case VIRT_GIC_VERSION_MAX: 1840 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1841 gic_version = VIRT_GIC_VERSION_4; 1842 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1843 gic_version = VIRT_GIC_VERSION_3; 1844 } else { 1845 gic_version = VIRT_GIC_VERSION_2; 1846 } 1847 break; 1848 case VIRT_GIC_VERSION_NOSEL: 1849 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1850 max_cpus <= GIC_NCPU) { 1851 gic_version = VIRT_GIC_VERSION_2; 1852 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1853 /* 1854 * in case the host does not support v2 emulation or 1855 * the end-user requested more than 8 VCPUs we now default 1856 * to v3. In any case defaulting to v2 would be broken. 1857 */ 1858 gic_version = VIRT_GIC_VERSION_3; 1859 } else if (max_cpus > GIC_NCPU) { 1860 error_report("%s only supports GICv2 emulation but more than 8 " 1861 "vcpus are requested", accel_name); 1862 exit(1); 1863 } 1864 break; 1865 case VIRT_GIC_VERSION_2: 1866 case VIRT_GIC_VERSION_3: 1867 case VIRT_GIC_VERSION_4: 1868 break; 1869 } 1870 1871 /* Check chosen version is effectively supported */ 1872 switch (gic_version) { 1873 case VIRT_GIC_VERSION_2: 1874 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1875 error_report("%s does not support GICv2 emulation", accel_name); 1876 exit(1); 1877 } 1878 break; 1879 case VIRT_GIC_VERSION_3: 1880 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1881 error_report("%s does not support GICv3 emulation", accel_name); 1882 exit(1); 1883 } 1884 break; 1885 case VIRT_GIC_VERSION_4: 1886 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1887 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1888 accel_name); 1889 exit(1); 1890 } 1891 break; 1892 default: 1893 error_report("logic error in finalize_gic_version"); 1894 exit(1); 1895 break; 1896 } 1897 1898 return gic_version; 1899 } 1900 1901 /* 1902 * finalize_gic_version - Determines the final gic_version 1903 * according to the gic-version property 1904 * 1905 * Default GIC type is v2 1906 */ 1907 static void finalize_gic_version(VirtMachineState *vms) 1908 { 1909 const char *accel_name = current_accel_name(); 1910 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1911 int gics_supported = 0; 1912 1913 /* Determine which GIC versions the current environment supports */ 1914 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 1915 int probe_bitmap = kvm_arm_vgic_probe(); 1916 1917 if (!probe_bitmap) { 1918 error_report("Unable to determine GIC version supported by host"); 1919 exit(1); 1920 } 1921 1922 if (probe_bitmap & KVM_ARM_VGIC_V2) { 1923 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1924 } 1925 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1926 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1927 } 1928 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 1929 /* KVM w/o kernel irqchip can only deal with GICv2 */ 1930 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1931 accel_name = "KVM with kernel-irqchip=off"; 1932 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 1933 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1934 if (module_object_class_by_name("arm-gicv3")) { 1935 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1936 if (vms->virt) { 1937 /* GICv4 only makes sense if CPU has EL2 */ 1938 gics_supported |= VIRT_GIC_VERSION_4_MASK; 1939 } 1940 } 1941 } else { 1942 error_report("Unsupported accelerator, can not determine GIC support"); 1943 exit(1); 1944 } 1945 1946 /* 1947 * Then convert helpers like host/max to concrete GIC versions and ensure 1948 * the desired version is supported 1949 */ 1950 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 1951 gics_supported, max_cpus); 1952 } 1953 1954 /* 1955 * virt_cpu_post_init() must be called after the CPUs have 1956 * been realized and the GIC has been created. 1957 */ 1958 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1959 { 1960 int max_cpus = MACHINE(vms)->smp.max_cpus; 1961 bool aarch64, pmu, steal_time; 1962 CPUState *cpu; 1963 1964 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1965 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1966 steal_time = object_property_get_bool(OBJECT(first_cpu), 1967 "kvm-steal-time", NULL); 1968 1969 if (kvm_enabled()) { 1970 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1971 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1972 1973 if (steal_time) { 1974 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1975 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1976 1977 /* The memory region size must be a multiple of host page size. */ 1978 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1979 1980 if (pvtime_size > pvtime_reg_size) { 1981 error_report("pvtime requires a %" HWADDR_PRId 1982 " byte memory region for %d CPUs," 1983 " but only %" HWADDR_PRId " has been reserved", 1984 pvtime_size, max_cpus, pvtime_reg_size); 1985 exit(1); 1986 } 1987 1988 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1989 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1990 } 1991 1992 CPU_FOREACH(cpu) { 1993 if (pmu) { 1994 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1995 if (kvm_irqchip_in_kernel()) { 1996 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 1997 } 1998 kvm_arm_pmu_init(cpu); 1999 } 2000 if (steal_time) { 2001 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 2002 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 2003 } 2004 } 2005 } else { 2006 if (aarch64 && vms->highmem) { 2007 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2008 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2009 2010 if (pamax < requested_pa_size) { 2011 error_report("VCPU supports less PA bits (%d) than " 2012 "requested by the memory map (%d)", 2013 pamax, requested_pa_size); 2014 exit(1); 2015 } 2016 } 2017 } 2018 } 2019 2020 static void machvirt_init(MachineState *machine) 2021 { 2022 VirtMachineState *vms = VIRT_MACHINE(machine); 2023 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2024 MachineClass *mc = MACHINE_GET_CLASS(machine); 2025 const CPUArchIdList *possible_cpus; 2026 MemoryRegion *sysmem = get_system_memory(); 2027 MemoryRegion *secure_sysmem = NULL; 2028 MemoryRegion *tag_sysmem = NULL; 2029 MemoryRegion *secure_tag_sysmem = NULL; 2030 int n, virt_max_cpus; 2031 bool firmware_loaded; 2032 bool aarch64 = true; 2033 bool has_ged = !vmc->no_ged; 2034 unsigned int smp_cpus = machine->smp.cpus; 2035 unsigned int max_cpus = machine->smp.max_cpus; 2036 2037 if (!cpu_type_valid(machine->cpu_type)) { 2038 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 2039 exit(1); 2040 } 2041 2042 possible_cpus = mc->possible_cpu_arch_ids(machine); 2043 2044 /* 2045 * In accelerated mode, the memory map is computed earlier in kvm_type() 2046 * to create a VM with the right number of IPA bits. 2047 */ 2048 if (!vms->memmap) { 2049 Object *cpuobj; 2050 ARMCPU *armcpu; 2051 int pa_bits; 2052 2053 /* 2054 * Instantiate a temporary CPU object to find out about what 2055 * we are about to deal with. Once this is done, get rid of 2056 * the object. 2057 */ 2058 cpuobj = object_new(possible_cpus->cpus[0].type); 2059 armcpu = ARM_CPU(cpuobj); 2060 2061 pa_bits = arm_pamax(armcpu); 2062 2063 object_unref(cpuobj); 2064 2065 virt_set_memmap(vms, pa_bits); 2066 } 2067 2068 /* We can probe only here because during property set 2069 * KVM is not available yet 2070 */ 2071 finalize_gic_version(vms); 2072 2073 if (vms->secure) { 2074 /* 2075 * The Secure view of the world is the same as the NonSecure, 2076 * but with a few extra devices. Create it as a container region 2077 * containing the system memory at low priority; any secure-only 2078 * devices go in at higher priority and take precedence. 2079 */ 2080 secure_sysmem = g_new(MemoryRegion, 1); 2081 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2082 UINT64_MAX); 2083 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2084 } 2085 2086 firmware_loaded = virt_firmware_init(vms, sysmem, 2087 secure_sysmem ?: sysmem); 2088 2089 /* If we have an EL3 boot ROM then the assumption is that it will 2090 * implement PSCI itself, so disable QEMU's internal implementation 2091 * so it doesn't get in the way. Instead of starting secondary 2092 * CPUs in PSCI powerdown state we will start them all running and 2093 * let the boot ROM sort them out. 2094 * The usual case is that we do use QEMU's PSCI implementation; 2095 * if the guest has EL2 then we will use SMC as the conduit, 2096 * and otherwise we will use HVC (for backwards compatibility and 2097 * because if we're using KVM then we must use HVC). 2098 */ 2099 if (vms->secure && firmware_loaded) { 2100 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2101 } else if (vms->virt) { 2102 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2103 } else { 2104 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2105 } 2106 2107 /* 2108 * The maximum number of CPUs depends on the GIC version, or on how 2109 * many redistributors we can fit into the memory map (which in turn 2110 * depends on whether this is a GICv3 or v4). 2111 */ 2112 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2113 virt_max_cpus = GIC_NCPU; 2114 } else { 2115 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2116 if (vms->highmem_redists) { 2117 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2118 } 2119 } 2120 2121 if (max_cpus > virt_max_cpus) { 2122 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2123 "supported by machine 'mach-virt' (%d)", 2124 max_cpus, virt_max_cpus); 2125 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2126 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2127 } 2128 2129 exit(1); 2130 } 2131 2132 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2133 error_report("mach-virt: %s does not support providing " 2134 "Security extensions (TrustZone) to the guest CPU", 2135 current_accel_name()); 2136 exit(1); 2137 } 2138 2139 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2140 error_report("mach-virt: %s does not support providing " 2141 "Virtualization extensions to the guest CPU", 2142 current_accel_name()); 2143 exit(1); 2144 } 2145 2146 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2147 error_report("mach-virt: %s does not support providing " 2148 "MTE to the guest CPU", 2149 current_accel_name()); 2150 exit(1); 2151 } 2152 2153 create_fdt(vms); 2154 2155 assert(possible_cpus->len == max_cpus); 2156 for (n = 0; n < possible_cpus->len; n++) { 2157 Object *cpuobj; 2158 CPUState *cs; 2159 2160 if (n >= smp_cpus) { 2161 break; 2162 } 2163 2164 cpuobj = object_new(possible_cpus->cpus[n].type); 2165 object_property_set_int(cpuobj, "mp-affinity", 2166 possible_cpus->cpus[n].arch_id, NULL); 2167 2168 cs = CPU(cpuobj); 2169 cs->cpu_index = n; 2170 2171 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2172 &error_fatal); 2173 2174 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2175 2176 if (!vms->secure) { 2177 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2178 } 2179 2180 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2181 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2182 } 2183 2184 if (vmc->kvm_no_adjvtime && 2185 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2186 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2187 } 2188 2189 if (vmc->no_kvm_steal_time && 2190 object_property_find(cpuobj, "kvm-steal-time")) { 2191 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2192 } 2193 2194 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2195 object_property_set_bool(cpuobj, "pmu", false, NULL); 2196 } 2197 2198 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2199 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2200 } 2201 2202 if (object_property_find(cpuobj, "reset-cbar")) { 2203 object_property_set_int(cpuobj, "reset-cbar", 2204 vms->memmap[VIRT_CPUPERIPHS].base, 2205 &error_abort); 2206 } 2207 2208 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2209 &error_abort); 2210 if (vms->secure) { 2211 object_property_set_link(cpuobj, "secure-memory", 2212 OBJECT(secure_sysmem), &error_abort); 2213 } 2214 2215 if (vms->mte) { 2216 /* Create the memory region only once, but link to all cpus. */ 2217 if (!tag_sysmem) { 2218 /* 2219 * The property exists only if MemTag is supported. 2220 * If it is, we must allocate the ram to back that up. 2221 */ 2222 if (!object_property_find(cpuobj, "tag-memory")) { 2223 error_report("MTE requested, but not supported " 2224 "by the guest CPU"); 2225 exit(1); 2226 } 2227 2228 tag_sysmem = g_new(MemoryRegion, 1); 2229 memory_region_init(tag_sysmem, OBJECT(machine), 2230 "tag-memory", UINT64_MAX / 32); 2231 2232 if (vms->secure) { 2233 secure_tag_sysmem = g_new(MemoryRegion, 1); 2234 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2235 "secure-tag-memory", UINT64_MAX / 32); 2236 2237 /* As with ram, secure-tag takes precedence over tag. */ 2238 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2239 tag_sysmem, -1); 2240 } 2241 } 2242 2243 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2244 &error_abort); 2245 if (vms->secure) { 2246 object_property_set_link(cpuobj, "secure-tag-memory", 2247 OBJECT(secure_tag_sysmem), 2248 &error_abort); 2249 } 2250 } 2251 2252 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2253 object_unref(cpuobj); 2254 } 2255 fdt_add_timer_nodes(vms); 2256 fdt_add_cpu_nodes(vms); 2257 2258 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2259 machine->ram); 2260 if (machine->device_memory) { 2261 memory_region_add_subregion(sysmem, machine->device_memory->base, 2262 &machine->device_memory->mr); 2263 } 2264 2265 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2266 2267 create_gic(vms, sysmem); 2268 2269 virt_cpu_post_init(vms, sysmem); 2270 2271 fdt_add_pmu_nodes(vms); 2272 2273 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2274 2275 if (vms->secure) { 2276 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2277 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2278 } 2279 2280 if (tag_sysmem) { 2281 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2282 machine->ram_size, "mach-virt.tag"); 2283 } 2284 2285 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2286 2287 create_rtc(vms); 2288 2289 create_pcie(vms); 2290 2291 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2292 vms->acpi_dev = create_acpi_ged(vms); 2293 } else { 2294 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2295 } 2296 2297 if (vms->secure && !vmc->no_secure_gpio) { 2298 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2299 } 2300 2301 /* connect powerdown request */ 2302 vms->powerdown_notifier.notify = virt_powerdown_req; 2303 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2304 2305 /* Create mmio transports, so the user can create virtio backends 2306 * (which will be automatically plugged in to the transports). If 2307 * no backend is created the transport will just sit harmlessly idle. 2308 */ 2309 create_virtio_devices(vms); 2310 2311 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2312 rom_set_fw(vms->fw_cfg); 2313 2314 create_platform_bus(vms); 2315 2316 if (machine->nvdimms_state->is_enabled) { 2317 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2318 .space_id = AML_AS_SYSTEM_MEMORY, 2319 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2320 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2321 }; 2322 2323 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2324 arm_virt_nvdimm_acpi_dsmio, 2325 vms->fw_cfg, OBJECT(vms)); 2326 } 2327 2328 vms->bootinfo.ram_size = machine->ram_size; 2329 vms->bootinfo.board_id = -1; 2330 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2331 vms->bootinfo.get_dtb = machvirt_dtb; 2332 vms->bootinfo.skip_dtb_autoload = true; 2333 vms->bootinfo.firmware_loaded = firmware_loaded; 2334 vms->bootinfo.psci_conduit = vms->psci_conduit; 2335 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2336 2337 vms->machine_done.notify = virt_machine_done; 2338 qemu_add_machine_init_done_notifier(&vms->machine_done); 2339 } 2340 2341 static bool virt_get_secure(Object *obj, Error **errp) 2342 { 2343 VirtMachineState *vms = VIRT_MACHINE(obj); 2344 2345 return vms->secure; 2346 } 2347 2348 static void virt_set_secure(Object *obj, bool value, Error **errp) 2349 { 2350 VirtMachineState *vms = VIRT_MACHINE(obj); 2351 2352 vms->secure = value; 2353 } 2354 2355 static bool virt_get_virt(Object *obj, Error **errp) 2356 { 2357 VirtMachineState *vms = VIRT_MACHINE(obj); 2358 2359 return vms->virt; 2360 } 2361 2362 static void virt_set_virt(Object *obj, bool value, Error **errp) 2363 { 2364 VirtMachineState *vms = VIRT_MACHINE(obj); 2365 2366 vms->virt = value; 2367 } 2368 2369 static bool virt_get_highmem(Object *obj, Error **errp) 2370 { 2371 VirtMachineState *vms = VIRT_MACHINE(obj); 2372 2373 return vms->highmem; 2374 } 2375 2376 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2377 { 2378 VirtMachineState *vms = VIRT_MACHINE(obj); 2379 2380 vms->highmem = value; 2381 } 2382 2383 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2384 { 2385 VirtMachineState *vms = VIRT_MACHINE(obj); 2386 2387 return vms->highmem_compact; 2388 } 2389 2390 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2391 { 2392 VirtMachineState *vms = VIRT_MACHINE(obj); 2393 2394 vms->highmem_compact = value; 2395 } 2396 2397 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2398 { 2399 VirtMachineState *vms = VIRT_MACHINE(obj); 2400 2401 return vms->highmem_redists; 2402 } 2403 2404 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2405 { 2406 VirtMachineState *vms = VIRT_MACHINE(obj); 2407 2408 vms->highmem_redists = value; 2409 } 2410 2411 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2412 { 2413 VirtMachineState *vms = VIRT_MACHINE(obj); 2414 2415 return vms->highmem_ecam; 2416 } 2417 2418 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2419 { 2420 VirtMachineState *vms = VIRT_MACHINE(obj); 2421 2422 vms->highmem_ecam = value; 2423 } 2424 2425 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2426 { 2427 VirtMachineState *vms = VIRT_MACHINE(obj); 2428 2429 return vms->highmem_mmio; 2430 } 2431 2432 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2433 { 2434 VirtMachineState *vms = VIRT_MACHINE(obj); 2435 2436 vms->highmem_mmio = value; 2437 } 2438 2439 2440 static bool virt_get_its(Object *obj, Error **errp) 2441 { 2442 VirtMachineState *vms = VIRT_MACHINE(obj); 2443 2444 return vms->its; 2445 } 2446 2447 static void virt_set_its(Object *obj, bool value, Error **errp) 2448 { 2449 VirtMachineState *vms = VIRT_MACHINE(obj); 2450 2451 vms->its = value; 2452 } 2453 2454 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2455 { 2456 VirtMachineState *vms = VIRT_MACHINE(obj); 2457 2458 return vms->dtb_randomness; 2459 } 2460 2461 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2462 { 2463 VirtMachineState *vms = VIRT_MACHINE(obj); 2464 2465 vms->dtb_randomness = value; 2466 } 2467 2468 static char *virt_get_oem_id(Object *obj, Error **errp) 2469 { 2470 VirtMachineState *vms = VIRT_MACHINE(obj); 2471 2472 return g_strdup(vms->oem_id); 2473 } 2474 2475 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2476 { 2477 VirtMachineState *vms = VIRT_MACHINE(obj); 2478 size_t len = strlen(value); 2479 2480 if (len > 6) { 2481 error_setg(errp, 2482 "User specified oem-id value is bigger than 6 bytes in size"); 2483 return; 2484 } 2485 2486 strncpy(vms->oem_id, value, 6); 2487 } 2488 2489 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2490 { 2491 VirtMachineState *vms = VIRT_MACHINE(obj); 2492 2493 return g_strdup(vms->oem_table_id); 2494 } 2495 2496 static void virt_set_oem_table_id(Object *obj, const char *value, 2497 Error **errp) 2498 { 2499 VirtMachineState *vms = VIRT_MACHINE(obj); 2500 size_t len = strlen(value); 2501 2502 if (len > 8) { 2503 error_setg(errp, 2504 "User specified oem-table-id value is bigger than 8 bytes in size"); 2505 return; 2506 } 2507 strncpy(vms->oem_table_id, value, 8); 2508 } 2509 2510 2511 bool virt_is_acpi_enabled(VirtMachineState *vms) 2512 { 2513 if (vms->acpi == ON_OFF_AUTO_OFF) { 2514 return false; 2515 } 2516 return true; 2517 } 2518 2519 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2520 void *opaque, Error **errp) 2521 { 2522 VirtMachineState *vms = VIRT_MACHINE(obj); 2523 OnOffAuto acpi = vms->acpi; 2524 2525 visit_type_OnOffAuto(v, name, &acpi, errp); 2526 } 2527 2528 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2529 void *opaque, Error **errp) 2530 { 2531 VirtMachineState *vms = VIRT_MACHINE(obj); 2532 2533 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2534 } 2535 2536 static bool virt_get_ras(Object *obj, Error **errp) 2537 { 2538 VirtMachineState *vms = VIRT_MACHINE(obj); 2539 2540 return vms->ras; 2541 } 2542 2543 static void virt_set_ras(Object *obj, bool value, Error **errp) 2544 { 2545 VirtMachineState *vms = VIRT_MACHINE(obj); 2546 2547 vms->ras = value; 2548 } 2549 2550 static bool virt_get_mte(Object *obj, Error **errp) 2551 { 2552 VirtMachineState *vms = VIRT_MACHINE(obj); 2553 2554 return vms->mte; 2555 } 2556 2557 static void virt_set_mte(Object *obj, bool value, Error **errp) 2558 { 2559 VirtMachineState *vms = VIRT_MACHINE(obj); 2560 2561 vms->mte = value; 2562 } 2563 2564 static char *virt_get_gic_version(Object *obj, Error **errp) 2565 { 2566 VirtMachineState *vms = VIRT_MACHINE(obj); 2567 const char *val; 2568 2569 switch (vms->gic_version) { 2570 case VIRT_GIC_VERSION_4: 2571 val = "4"; 2572 break; 2573 case VIRT_GIC_VERSION_3: 2574 val = "3"; 2575 break; 2576 default: 2577 val = "2"; 2578 break; 2579 } 2580 return g_strdup(val); 2581 } 2582 2583 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2584 { 2585 VirtMachineState *vms = VIRT_MACHINE(obj); 2586 2587 if (!strcmp(value, "4")) { 2588 vms->gic_version = VIRT_GIC_VERSION_4; 2589 } else if (!strcmp(value, "3")) { 2590 vms->gic_version = VIRT_GIC_VERSION_3; 2591 } else if (!strcmp(value, "2")) { 2592 vms->gic_version = VIRT_GIC_VERSION_2; 2593 } else if (!strcmp(value, "host")) { 2594 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2595 } else if (!strcmp(value, "max")) { 2596 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2597 } else { 2598 error_setg(errp, "Invalid gic-version value"); 2599 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2600 } 2601 } 2602 2603 static char *virt_get_iommu(Object *obj, Error **errp) 2604 { 2605 VirtMachineState *vms = VIRT_MACHINE(obj); 2606 2607 switch (vms->iommu) { 2608 case VIRT_IOMMU_NONE: 2609 return g_strdup("none"); 2610 case VIRT_IOMMU_SMMUV3: 2611 return g_strdup("smmuv3"); 2612 default: 2613 g_assert_not_reached(); 2614 } 2615 } 2616 2617 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2618 { 2619 VirtMachineState *vms = VIRT_MACHINE(obj); 2620 2621 if (!strcmp(value, "smmuv3")) { 2622 vms->iommu = VIRT_IOMMU_SMMUV3; 2623 } else if (!strcmp(value, "none")) { 2624 vms->iommu = VIRT_IOMMU_NONE; 2625 } else { 2626 error_setg(errp, "Invalid iommu value"); 2627 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2628 } 2629 } 2630 2631 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2632 { 2633 VirtMachineState *vms = VIRT_MACHINE(obj); 2634 2635 return vms->default_bus_bypass_iommu; 2636 } 2637 2638 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2639 Error **errp) 2640 { 2641 VirtMachineState *vms = VIRT_MACHINE(obj); 2642 2643 vms->default_bus_bypass_iommu = value; 2644 } 2645 2646 static CpuInstanceProperties 2647 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2648 { 2649 MachineClass *mc = MACHINE_GET_CLASS(ms); 2650 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2651 2652 assert(cpu_index < possible_cpus->len); 2653 return possible_cpus->cpus[cpu_index].props; 2654 } 2655 2656 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2657 { 2658 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2659 2660 return socket_id % ms->numa_state->num_nodes; 2661 } 2662 2663 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2664 { 2665 int n; 2666 unsigned int max_cpus = ms->smp.max_cpus; 2667 VirtMachineState *vms = VIRT_MACHINE(ms); 2668 MachineClass *mc = MACHINE_GET_CLASS(vms); 2669 2670 if (ms->possible_cpus) { 2671 assert(ms->possible_cpus->len == max_cpus); 2672 return ms->possible_cpus; 2673 } 2674 2675 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2676 sizeof(CPUArchId) * max_cpus); 2677 ms->possible_cpus->len = max_cpus; 2678 for (n = 0; n < ms->possible_cpus->len; n++) { 2679 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2680 ms->possible_cpus->cpus[n].arch_id = 2681 virt_cpu_mp_affinity(vms, n); 2682 2683 assert(!mc->smp_props.dies_supported); 2684 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2685 ms->possible_cpus->cpus[n].props.socket_id = 2686 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2687 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2688 ms->possible_cpus->cpus[n].props.cluster_id = 2689 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2690 ms->possible_cpus->cpus[n].props.has_core_id = true; 2691 ms->possible_cpus->cpus[n].props.core_id = 2692 (n / ms->smp.threads) % ms->smp.cores; 2693 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2694 ms->possible_cpus->cpus[n].props.thread_id = 2695 n % ms->smp.threads; 2696 } 2697 return ms->possible_cpus; 2698 } 2699 2700 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2701 Error **errp) 2702 { 2703 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2704 const MachineState *ms = MACHINE(hotplug_dev); 2705 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2706 2707 if (!vms->acpi_dev) { 2708 error_setg(errp, 2709 "memory hotplug is not enabled: missing acpi-ged device"); 2710 return; 2711 } 2712 2713 if (vms->mte) { 2714 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2715 return; 2716 } 2717 2718 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2719 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2720 return; 2721 } 2722 2723 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2724 } 2725 2726 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2727 DeviceState *dev, Error **errp) 2728 { 2729 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2730 MachineState *ms = MACHINE(hotplug_dev); 2731 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2732 2733 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2734 2735 if (is_nvdimm) { 2736 nvdimm_plug(ms->nvdimms_state); 2737 } 2738 2739 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2740 dev, &error_abort); 2741 } 2742 2743 static void virt_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 2744 DeviceState *dev, Error **errp) 2745 { 2746 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2747 Error *local_err = NULL; 2748 2749 if (!hotplug_dev2 && dev->hotplugged) { 2750 /* 2751 * Without a bus hotplug handler, we cannot control the plug/unplug 2752 * order. We should never reach this point when hotplugging on ARM. 2753 * However, it's nice to add a safety net, similar to what we have 2754 * on x86. 2755 */ 2756 error_setg(errp, "hotplug of virtio based memory devices not supported" 2757 " on this bus."); 2758 return; 2759 } 2760 /* 2761 * First, see if we can plug this memory device at all. If that 2762 * succeeds, branch of to the actual hotplug handler. 2763 */ 2764 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2765 &local_err); 2766 if (!local_err && hotplug_dev2) { 2767 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2768 } 2769 error_propagate(errp, local_err); 2770 } 2771 2772 static void virt_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 2773 DeviceState *dev, Error **errp) 2774 { 2775 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2776 Error *local_err = NULL; 2777 2778 /* 2779 * Plug the memory device first and then branch off to the actual 2780 * hotplug handler. If that one fails, we can easily undo the memory 2781 * device bits. 2782 */ 2783 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2784 if (hotplug_dev2) { 2785 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2786 if (local_err) { 2787 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2788 } 2789 } 2790 error_propagate(errp, local_err); 2791 } 2792 2793 static void virt_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 2794 DeviceState *dev, Error **errp) 2795 { 2796 /* We don't support hot unplug of virtio based memory devices */ 2797 error_setg(errp, "virtio based memory devices cannot be unplugged."); 2798 } 2799 2800 2801 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2802 DeviceState *dev, Error **errp) 2803 { 2804 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2805 2806 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2807 virt_memory_pre_plug(hotplug_dev, dev, errp); 2808 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2809 virt_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 2810 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2811 hwaddr db_start = 0, db_end = 0; 2812 char *resv_prop_str; 2813 2814 if (vms->iommu != VIRT_IOMMU_NONE) { 2815 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2816 return; 2817 } 2818 2819 switch (vms->msi_controller) { 2820 case VIRT_MSI_CTRL_NONE: 2821 return; 2822 case VIRT_MSI_CTRL_ITS: 2823 /* GITS_TRANSLATER page */ 2824 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2825 db_end = base_memmap[VIRT_GIC_ITS].base + 2826 base_memmap[VIRT_GIC_ITS].size - 1; 2827 break; 2828 case VIRT_MSI_CTRL_GICV2M: 2829 /* MSI_SETSPI_NS page */ 2830 db_start = base_memmap[VIRT_GIC_V2M].base; 2831 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2832 break; 2833 } 2834 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2835 db_start, db_end, 2836 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2837 2838 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 2839 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 2840 resv_prop_str, errp); 2841 g_free(resv_prop_str); 2842 } 2843 } 2844 2845 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2846 DeviceState *dev, Error **errp) 2847 { 2848 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2849 2850 if (vms->platform_bus_dev) { 2851 MachineClass *mc = MACHINE_GET_CLASS(vms); 2852 2853 if (device_is_dynamic_sysbus(mc, dev)) { 2854 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2855 SYS_BUS_DEVICE(dev)); 2856 } 2857 } 2858 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2859 virt_memory_plug(hotplug_dev, dev, errp); 2860 } 2861 2862 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2863 virt_virtio_md_pci_plug(hotplug_dev, dev, errp); 2864 } 2865 2866 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2867 PCIDevice *pdev = PCI_DEVICE(dev); 2868 2869 vms->iommu = VIRT_IOMMU_VIRTIO; 2870 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2871 create_virtio_iommu_dt_bindings(vms); 2872 } 2873 } 2874 2875 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2876 DeviceState *dev, Error **errp) 2877 { 2878 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2879 2880 if (!vms->acpi_dev) { 2881 error_setg(errp, 2882 "memory hotplug is not enabled: missing acpi-ged device"); 2883 return; 2884 } 2885 2886 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2887 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 2888 return; 2889 } 2890 2891 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2892 errp); 2893 } 2894 2895 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2896 DeviceState *dev, Error **errp) 2897 { 2898 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2899 Error *local_err = NULL; 2900 2901 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2902 if (local_err) { 2903 goto out; 2904 } 2905 2906 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2907 qdev_unrealize(dev); 2908 2909 out: 2910 error_propagate(errp, local_err); 2911 } 2912 2913 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2914 DeviceState *dev, Error **errp) 2915 { 2916 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2917 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2918 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2919 virt_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 2920 } else { 2921 error_setg(errp, "device unplug request for unsupported device" 2922 " type: %s", object_get_typename(OBJECT(dev))); 2923 } 2924 } 2925 2926 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2927 DeviceState *dev, Error **errp) 2928 { 2929 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2930 virt_dimm_unplug(hotplug_dev, dev, errp); 2931 } else { 2932 error_setg(errp, "virt: device unplug for unsupported device" 2933 " type: %s", object_get_typename(OBJECT(dev))); 2934 } 2935 } 2936 2937 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2938 DeviceState *dev) 2939 { 2940 MachineClass *mc = MACHINE_GET_CLASS(machine); 2941 2942 if (device_is_dynamic_sysbus(mc, dev) || 2943 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2944 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 2945 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2946 return HOTPLUG_HANDLER(machine); 2947 } 2948 return NULL; 2949 } 2950 2951 /* 2952 * for arm64 kvm_type [7-0] encodes the requested number of bits 2953 * in the IPA address space 2954 */ 2955 static int virt_kvm_type(MachineState *ms, const char *type_str) 2956 { 2957 VirtMachineState *vms = VIRT_MACHINE(ms); 2958 int max_vm_pa_size, requested_pa_size; 2959 bool fixed_ipa; 2960 2961 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2962 2963 /* we freeze the memory map to compute the highest gpa */ 2964 virt_set_memmap(vms, max_vm_pa_size); 2965 2966 requested_pa_size = 64 - clz64(vms->highest_gpa); 2967 2968 /* 2969 * KVM requires the IPA size to be at least 32 bits. 2970 */ 2971 if (requested_pa_size < 32) { 2972 requested_pa_size = 32; 2973 } 2974 2975 if (requested_pa_size > max_vm_pa_size) { 2976 error_report("-m and ,maxmem option values " 2977 "require an IPA range (%d bits) larger than " 2978 "the one supported by the host (%d bits)", 2979 requested_pa_size, max_vm_pa_size); 2980 exit(1); 2981 } 2982 /* 2983 * We return the requested PA log size, unless KVM only supports 2984 * the implicit legacy 40b IPA setting, in which case the kvm_type 2985 * must be 0. 2986 */ 2987 return fixed_ipa ? 0 : requested_pa_size; 2988 } 2989 2990 static void virt_machine_class_init(ObjectClass *oc, void *data) 2991 { 2992 MachineClass *mc = MACHINE_CLASS(oc); 2993 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2994 2995 mc->init = machvirt_init; 2996 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2997 * The value may be reduced later when we have more information about the 2998 * configuration of the particular instance. 2999 */ 3000 mc->max_cpus = 512; 3001 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 3002 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 3003 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 3004 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 3005 #ifdef CONFIG_TPM 3006 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 3007 #endif 3008 mc->block_default_type = IF_VIRTIO; 3009 mc->no_cdrom = 1; 3010 mc->pci_allow_0_address = true; 3011 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 3012 mc->minimum_page_bits = 12; 3013 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 3014 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 3015 #ifdef CONFIG_TCG 3016 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 3017 #else 3018 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 3019 #endif 3020 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 3021 mc->kvm_type = virt_kvm_type; 3022 assert(!mc->get_hotplug_handler); 3023 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 3024 hc->pre_plug = virt_machine_device_pre_plug_cb; 3025 hc->plug = virt_machine_device_plug_cb; 3026 hc->unplug_request = virt_machine_device_unplug_request_cb; 3027 hc->unplug = virt_machine_device_unplug_cb; 3028 mc->nvdimm_supported = true; 3029 mc->smp_props.clusters_supported = true; 3030 mc->auto_enable_numa_with_memhp = true; 3031 mc->auto_enable_numa_with_memdev = true; 3032 /* platform instead of architectural choice */ 3033 mc->cpu_cluster_has_numa_boundary = true; 3034 mc->default_ram_id = "mach-virt.ram"; 3035 mc->default_nic = "virtio-net-pci"; 3036 3037 object_class_property_add(oc, "acpi", "OnOffAuto", 3038 virt_get_acpi, virt_set_acpi, 3039 NULL, NULL); 3040 object_class_property_set_description(oc, "acpi", 3041 "Enable ACPI"); 3042 object_class_property_add_bool(oc, "secure", virt_get_secure, 3043 virt_set_secure); 3044 object_class_property_set_description(oc, "secure", 3045 "Set on/off to enable/disable the ARM " 3046 "Security Extensions (TrustZone)"); 3047 3048 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 3049 virt_set_virt); 3050 object_class_property_set_description(oc, "virtualization", 3051 "Set on/off to enable/disable emulating a " 3052 "guest CPU which implements the ARM " 3053 "Virtualization Extensions"); 3054 3055 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 3056 virt_set_highmem); 3057 object_class_property_set_description(oc, "highmem", 3058 "Set on/off to enable/disable using " 3059 "physical address space above 32 bits"); 3060 3061 object_class_property_add_bool(oc, "compact-highmem", 3062 virt_get_compact_highmem, 3063 virt_set_compact_highmem); 3064 object_class_property_set_description(oc, "compact-highmem", 3065 "Set on/off to enable/disable compact " 3066 "layout for high memory regions"); 3067 3068 object_class_property_add_bool(oc, "highmem-redists", 3069 virt_get_highmem_redists, 3070 virt_set_highmem_redists); 3071 object_class_property_set_description(oc, "highmem-redists", 3072 "Set on/off to enable/disable high " 3073 "memory region for GICv3 or GICv4 " 3074 "redistributor"); 3075 3076 object_class_property_add_bool(oc, "highmem-ecam", 3077 virt_get_highmem_ecam, 3078 virt_set_highmem_ecam); 3079 object_class_property_set_description(oc, "highmem-ecam", 3080 "Set on/off to enable/disable high " 3081 "memory region for PCI ECAM"); 3082 3083 object_class_property_add_bool(oc, "highmem-mmio", 3084 virt_get_highmem_mmio, 3085 virt_set_highmem_mmio); 3086 object_class_property_set_description(oc, "highmem-mmio", 3087 "Set on/off to enable/disable high " 3088 "memory region for PCI MMIO"); 3089 3090 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3091 virt_set_gic_version); 3092 object_class_property_set_description(oc, "gic-version", 3093 "Set GIC version. " 3094 "Valid values are 2, 3, 4, host and max"); 3095 3096 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3097 object_class_property_set_description(oc, "iommu", 3098 "Set the IOMMU type. " 3099 "Valid values are none and smmuv3"); 3100 3101 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3102 virt_get_default_bus_bypass_iommu, 3103 virt_set_default_bus_bypass_iommu); 3104 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3105 "Set on/off to enable/disable " 3106 "bypass_iommu for default root bus"); 3107 3108 object_class_property_add_bool(oc, "ras", virt_get_ras, 3109 virt_set_ras); 3110 object_class_property_set_description(oc, "ras", 3111 "Set on/off to enable/disable reporting host memory errors " 3112 "to a KVM guest using ACPI and guest external abort exceptions"); 3113 3114 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3115 object_class_property_set_description(oc, "mte", 3116 "Set on/off to enable/disable emulating a " 3117 "guest CPU which implements the ARM " 3118 "Memory Tagging Extension"); 3119 3120 object_class_property_add_bool(oc, "its", virt_get_its, 3121 virt_set_its); 3122 object_class_property_set_description(oc, "its", 3123 "Set on/off to enable/disable " 3124 "ITS instantiation"); 3125 3126 object_class_property_add_bool(oc, "dtb-randomness", 3127 virt_get_dtb_randomness, 3128 virt_set_dtb_randomness); 3129 object_class_property_set_description(oc, "dtb-randomness", 3130 "Set off to disable passing random or " 3131 "non-deterministic dtb nodes to guest"); 3132 3133 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3134 virt_get_dtb_randomness, 3135 virt_set_dtb_randomness); 3136 object_class_property_set_description(oc, "dtb-kaslr-seed", 3137 "Deprecated synonym of dtb-randomness"); 3138 3139 object_class_property_add_str(oc, "x-oem-id", 3140 virt_get_oem_id, 3141 virt_set_oem_id); 3142 object_class_property_set_description(oc, "x-oem-id", 3143 "Override the default value of field OEMID " 3144 "in ACPI table header." 3145 "The string may be up to 6 bytes in size"); 3146 3147 3148 object_class_property_add_str(oc, "x-oem-table-id", 3149 virt_get_oem_table_id, 3150 virt_set_oem_table_id); 3151 object_class_property_set_description(oc, "x-oem-table-id", 3152 "Override the default value of field OEM Table ID " 3153 "in ACPI table header." 3154 "The string may be up to 8 bytes in size"); 3155 3156 } 3157 3158 static void virt_instance_init(Object *obj) 3159 { 3160 VirtMachineState *vms = VIRT_MACHINE(obj); 3161 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3162 3163 /* EL3 is disabled by default on virt: this makes us consistent 3164 * between KVM and TCG for this board, and it also allows us to 3165 * boot UEFI blobs which assume no TrustZone support. 3166 */ 3167 vms->secure = false; 3168 3169 /* EL2 is also disabled by default, for similar reasons */ 3170 vms->virt = false; 3171 3172 /* High memory is enabled by default */ 3173 vms->highmem = true; 3174 vms->highmem_compact = !vmc->no_highmem_compact; 3175 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3176 3177 vms->highmem_ecam = !vmc->no_highmem_ecam; 3178 vms->highmem_mmio = true; 3179 vms->highmem_redists = true; 3180 3181 if (vmc->no_its) { 3182 vms->its = false; 3183 } else { 3184 /* Default allows ITS instantiation */ 3185 vms->its = true; 3186 3187 if (vmc->no_tcg_its) { 3188 vms->tcg_its = false; 3189 } else { 3190 vms->tcg_its = true; 3191 } 3192 } 3193 3194 /* Default disallows iommu instantiation */ 3195 vms->iommu = VIRT_IOMMU_NONE; 3196 3197 /* The default root bus is attached to iommu by default */ 3198 vms->default_bus_bypass_iommu = false; 3199 3200 /* Default disallows RAS instantiation */ 3201 vms->ras = false; 3202 3203 /* MTE is disabled by default. */ 3204 vms->mte = false; 3205 3206 /* Supply kaslr-seed and rng-seed by default */ 3207 vms->dtb_randomness = true; 3208 3209 vms->irqmap = a15irqmap; 3210 3211 virt_flash_create(vms); 3212 3213 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3214 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3215 } 3216 3217 static const TypeInfo virt_machine_info = { 3218 .name = TYPE_VIRT_MACHINE, 3219 .parent = TYPE_MACHINE, 3220 .abstract = true, 3221 .instance_size = sizeof(VirtMachineState), 3222 .class_size = sizeof(VirtMachineClass), 3223 .class_init = virt_machine_class_init, 3224 .instance_init = virt_instance_init, 3225 .interfaces = (InterfaceInfo[]) { 3226 { TYPE_HOTPLUG_HANDLER }, 3227 { } 3228 }, 3229 }; 3230 3231 static void machvirt_machine_init(void) 3232 { 3233 type_register_static(&virt_machine_info); 3234 } 3235 type_init(machvirt_machine_init); 3236 3237 static void virt_machine_8_1_options(MachineClass *mc) 3238 { 3239 } 3240 DEFINE_VIRT_MACHINE_AS_LATEST(8, 1) 3241 3242 static void virt_machine_8_0_options(MachineClass *mc) 3243 { 3244 virt_machine_8_1_options(mc); 3245 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3246 } 3247 DEFINE_VIRT_MACHINE(8, 0) 3248 3249 static void virt_machine_7_2_options(MachineClass *mc) 3250 { 3251 virt_machine_8_0_options(mc); 3252 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3253 } 3254 DEFINE_VIRT_MACHINE(7, 2) 3255 3256 static void virt_machine_7_1_options(MachineClass *mc) 3257 { 3258 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3259 3260 virt_machine_7_2_options(mc); 3261 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3262 /* Compact layout for high memory regions was introduced with 7.2 */ 3263 vmc->no_highmem_compact = true; 3264 } 3265 DEFINE_VIRT_MACHINE(7, 1) 3266 3267 static void virt_machine_7_0_options(MachineClass *mc) 3268 { 3269 virt_machine_7_1_options(mc); 3270 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3271 } 3272 DEFINE_VIRT_MACHINE(7, 0) 3273 3274 static void virt_machine_6_2_options(MachineClass *mc) 3275 { 3276 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3277 3278 virt_machine_7_0_options(mc); 3279 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3280 vmc->no_tcg_lpa2 = true; 3281 } 3282 DEFINE_VIRT_MACHINE(6, 2) 3283 3284 static void virt_machine_6_1_options(MachineClass *mc) 3285 { 3286 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3287 3288 virt_machine_6_2_options(mc); 3289 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3290 mc->smp_props.prefer_sockets = true; 3291 vmc->no_cpu_topology = true; 3292 3293 /* qemu ITS was introduced with 6.2 */ 3294 vmc->no_tcg_its = true; 3295 } 3296 DEFINE_VIRT_MACHINE(6, 1) 3297 3298 static void virt_machine_6_0_options(MachineClass *mc) 3299 { 3300 virt_machine_6_1_options(mc); 3301 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3302 } 3303 DEFINE_VIRT_MACHINE(6, 0) 3304 3305 static void virt_machine_5_2_options(MachineClass *mc) 3306 { 3307 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3308 3309 virt_machine_6_0_options(mc); 3310 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3311 vmc->no_secure_gpio = true; 3312 } 3313 DEFINE_VIRT_MACHINE(5, 2) 3314 3315 static void virt_machine_5_1_options(MachineClass *mc) 3316 { 3317 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3318 3319 virt_machine_5_2_options(mc); 3320 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3321 vmc->no_kvm_steal_time = true; 3322 } 3323 DEFINE_VIRT_MACHINE(5, 1) 3324 3325 static void virt_machine_5_0_options(MachineClass *mc) 3326 { 3327 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3328 3329 virt_machine_5_1_options(mc); 3330 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3331 mc->numa_mem_supported = true; 3332 vmc->acpi_expose_flash = true; 3333 mc->auto_enable_numa_with_memdev = false; 3334 } 3335 DEFINE_VIRT_MACHINE(5, 0) 3336 3337 static void virt_machine_4_2_options(MachineClass *mc) 3338 { 3339 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3340 3341 virt_machine_5_0_options(mc); 3342 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3343 vmc->kvm_no_adjvtime = true; 3344 } 3345 DEFINE_VIRT_MACHINE(4, 2) 3346 3347 static void virt_machine_4_1_options(MachineClass *mc) 3348 { 3349 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3350 3351 virt_machine_4_2_options(mc); 3352 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3353 vmc->no_ged = true; 3354 mc->auto_enable_numa_with_memhp = false; 3355 } 3356 DEFINE_VIRT_MACHINE(4, 1) 3357 3358 static void virt_machine_4_0_options(MachineClass *mc) 3359 { 3360 virt_machine_4_1_options(mc); 3361 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3362 } 3363 DEFINE_VIRT_MACHINE(4, 0) 3364 3365 static void virt_machine_3_1_options(MachineClass *mc) 3366 { 3367 virt_machine_4_0_options(mc); 3368 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3369 } 3370 DEFINE_VIRT_MACHINE(3, 1) 3371 3372 static void virt_machine_3_0_options(MachineClass *mc) 3373 { 3374 virt_machine_3_1_options(mc); 3375 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3376 } 3377 DEFINE_VIRT_MACHINE(3, 0) 3378 3379 static void virt_machine_2_12_options(MachineClass *mc) 3380 { 3381 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3382 3383 virt_machine_3_0_options(mc); 3384 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3385 vmc->no_highmem_ecam = true; 3386 mc->max_cpus = 255; 3387 } 3388 DEFINE_VIRT_MACHINE(2, 12) 3389 3390 static void virt_machine_2_11_options(MachineClass *mc) 3391 { 3392 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3393 3394 virt_machine_2_12_options(mc); 3395 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3396 vmc->smbios_old_sys_ver = true; 3397 } 3398 DEFINE_VIRT_MACHINE(2, 11) 3399 3400 static void virt_machine_2_10_options(MachineClass *mc) 3401 { 3402 virt_machine_2_11_options(mc); 3403 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3404 /* before 2.11 we never faulted accesses to bad addresses */ 3405 mc->ignore_memory_transaction_failures = true; 3406 } 3407 DEFINE_VIRT_MACHINE(2, 10) 3408 3409 static void virt_machine_2_9_options(MachineClass *mc) 3410 { 3411 virt_machine_2_10_options(mc); 3412 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3413 } 3414 DEFINE_VIRT_MACHINE(2, 9) 3415 3416 static void virt_machine_2_8_options(MachineClass *mc) 3417 { 3418 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3419 3420 virt_machine_2_9_options(mc); 3421 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3422 /* For 2.8 and earlier we falsely claimed in the DT that 3423 * our timers were edge-triggered, not level-triggered. 3424 */ 3425 vmc->claim_edge_triggered_timers = true; 3426 } 3427 DEFINE_VIRT_MACHINE(2, 8) 3428 3429 static void virt_machine_2_7_options(MachineClass *mc) 3430 { 3431 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3432 3433 virt_machine_2_8_options(mc); 3434 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3435 /* ITS was introduced with 2.8 */ 3436 vmc->no_its = true; 3437 /* Stick with 1K pages for migration compatibility */ 3438 mc->minimum_page_bits = 0; 3439 } 3440 DEFINE_VIRT_MACHINE(2, 7) 3441 3442 static void virt_machine_2_6_options(MachineClass *mc) 3443 { 3444 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3445 3446 virt_machine_2_7_options(mc); 3447 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3448 vmc->disallow_affinity_adjustment = true; 3449 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3450 vmc->no_pmu = true; 3451 } 3452 DEFINE_VIRT_MACHINE(2, 6) 3453