1 /* 2 * QEMU TCX Frame buffer 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu-common.h" 28 #include "ui/console.h" 29 #include "ui/pixel_ops.h" 30 #include "hw/loader.h" 31 #include "hw/sysbus.h" 32 #include "qemu/error-report.h" 33 34 #define TCX_ROM_FILE "QEMU,tcx.bin" 35 #define FCODE_MAX_ROM_SIZE 0x10000 36 37 #define MAXX 1024 38 #define MAXY 768 39 #define TCX_DAC_NREGS 16 40 #define TCX_THC_NREGS 0x1000 41 #define TCX_DHC_NREGS 0x4000 42 #define TCX_TEC_NREGS 0x1000 43 #define TCX_ALT_NREGS 0x8000 44 #define TCX_STIP_NREGS 0x800000 45 #define TCX_BLIT_NREGS 0x800000 46 #define TCX_RSTIP_NREGS 0x800000 47 #define TCX_RBLIT_NREGS 0x800000 48 49 #define TCX_THC_MISC 0x818 50 #define TCX_THC_CURSXY 0x8fc 51 #define TCX_THC_CURSMASK 0x900 52 #define TCX_THC_CURSBITS 0x980 53 54 #define TYPE_TCX "SUNW,tcx" 55 #define TCX(obj) OBJECT_CHECK(TCXState, (obj), TYPE_TCX) 56 57 typedef struct TCXState { 58 SysBusDevice parent_obj; 59 60 QemuConsole *con; 61 qemu_irq irq; 62 uint8_t *vram; 63 uint32_t *vram24, *cplane; 64 hwaddr prom_addr; 65 MemoryRegion rom; 66 MemoryRegion vram_mem; 67 MemoryRegion vram_8bit; 68 MemoryRegion vram_24bit; 69 MemoryRegion stip; 70 MemoryRegion blit; 71 MemoryRegion vram_cplane; 72 MemoryRegion rstip; 73 MemoryRegion rblit; 74 MemoryRegion tec; 75 MemoryRegion dac; 76 MemoryRegion thc; 77 MemoryRegion dhc; 78 MemoryRegion alt; 79 MemoryRegion thc24; 80 81 ram_addr_t vram24_offset, cplane_offset; 82 uint32_t tmpblit; 83 uint32_t vram_size; 84 uint32_t palette[260]; 85 uint8_t r[260], g[260], b[260]; 86 uint16_t width, height, depth; 87 uint8_t dac_index, dac_state; 88 uint32_t thcmisc; 89 uint32_t cursmask[32]; 90 uint32_t cursbits[32]; 91 uint16_t cursx; 92 uint16_t cursy; 93 } TCXState; 94 95 static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len) 96 { 97 memory_region_set_dirty(&s->vram_mem, addr, len); 98 99 if (s->depth == 24) { 100 memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4, 101 len * 4); 102 memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4, 103 len * 4); 104 } 105 } 106 107 static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap, 108 ram_addr_t addr, int len) 109 { 110 int ret; 111 112 ret = memory_region_snapshot_get_dirty(&s->vram_mem, snap, addr, len); 113 114 if (s->depth == 24) { 115 ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap, 116 s->vram24_offset + addr * 4, len * 4); 117 ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap, 118 s->cplane_offset + addr * 4, len * 4); 119 } 120 121 return ret; 122 } 123 124 static void update_palette_entries(TCXState *s, int start, int end) 125 { 126 DisplaySurface *surface = qemu_console_surface(s->con); 127 int i; 128 129 for (i = start; i < end; i++) { 130 if (is_surface_bgr(surface)) { 131 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); 132 } else { 133 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); 134 } 135 } 136 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 137 } 138 139 static void tcx_draw_line32(TCXState *s1, uint8_t *d, 140 const uint8_t *s, int width) 141 { 142 int x; 143 uint8_t val; 144 uint32_t *p = (uint32_t *)d; 145 146 for (x = 0; x < width; x++) { 147 val = *s++; 148 *p++ = s1->palette[val]; 149 } 150 } 151 152 static void tcx_draw_cursor32(TCXState *s1, uint8_t *d, 153 int y, int width) 154 { 155 int x, len; 156 uint32_t mask, bits; 157 uint32_t *p = (uint32_t *)d; 158 159 y = y - s1->cursy; 160 mask = s1->cursmask[y]; 161 bits = s1->cursbits[y]; 162 len = MIN(width - s1->cursx, 32); 163 p = &p[s1->cursx]; 164 for (x = 0; x < len; x++) { 165 if (mask & 0x80000000) { 166 if (bits & 0x80000000) { 167 *p = s1->palette[259]; 168 } else { 169 *p = s1->palette[258]; 170 } 171 } 172 p++; 173 mask <<= 1; 174 bits <<= 1; 175 } 176 } 177 178 /* 179 XXX Could be much more optimal: 180 * detect if line/page/whole screen is in 24 bit mode 181 * if destination is also BGR, use memcpy 182 */ 183 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, 184 const uint8_t *s, int width, 185 const uint32_t *cplane, 186 const uint32_t *s24) 187 { 188 DisplaySurface *surface = qemu_console_surface(s1->con); 189 int x, bgr, r, g, b; 190 uint8_t val, *p8; 191 uint32_t *p = (uint32_t *)d; 192 uint32_t dval; 193 bgr = is_surface_bgr(surface); 194 for(x = 0; x < width; x++, s++, s24++) { 195 if (be32_to_cpu(*cplane) & 0x03000000) { 196 /* 24-bit direct, BGR order */ 197 p8 = (uint8_t *)s24; 198 p8++; 199 b = *p8++; 200 g = *p8++; 201 r = *p8; 202 if (bgr) 203 dval = rgb_to_pixel32bgr(r, g, b); 204 else 205 dval = rgb_to_pixel32(r, g, b); 206 } else { 207 /* 8-bit pseudocolor */ 208 val = *s; 209 dval = s1->palette[val]; 210 } 211 *p++ = dval; 212 cplane++; 213 } 214 } 215 216 /* Fixed line length 1024 allows us to do nice tricks not possible on 217 VGA... */ 218 219 static void tcx_update_display(void *opaque) 220 { 221 TCXState *ts = opaque; 222 DisplaySurface *surface = qemu_console_surface(ts->con); 223 ram_addr_t page; 224 DirtyBitmapSnapshot *snap = NULL; 225 int y, y_start, dd, ds; 226 uint8_t *d, *s; 227 228 if (surface_bits_per_pixel(surface) != 32) { 229 return; 230 } 231 232 page = 0; 233 y_start = -1; 234 d = surface_data(surface); 235 s = ts->vram; 236 dd = surface_stride(surface); 237 ds = 1024; 238 239 snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0, 240 memory_region_size(&ts->vram_mem), 241 DIRTY_MEMORY_VGA); 242 243 for (y = 0; y < ts->height; y++, page += ds) { 244 if (tcx_check_dirty(ts, snap, page, ds)) { 245 if (y_start < 0) 246 y_start = y; 247 248 tcx_draw_line32(ts, d, s, ts->width); 249 if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) { 250 tcx_draw_cursor32(ts, d, y, ts->width); 251 } 252 } else { 253 if (y_start >= 0) { 254 /* flush to display */ 255 dpy_gfx_update(ts->con, 0, y_start, 256 ts->width, y - y_start); 257 y_start = -1; 258 } 259 } 260 s += ds; 261 d += dd; 262 } 263 if (y_start >= 0) { 264 /* flush to display */ 265 dpy_gfx_update(ts->con, 0, y_start, 266 ts->width, y - y_start); 267 } 268 g_free(snap); 269 } 270 271 static void tcx24_update_display(void *opaque) 272 { 273 TCXState *ts = opaque; 274 DisplaySurface *surface = qemu_console_surface(ts->con); 275 ram_addr_t page; 276 DirtyBitmapSnapshot *snap = NULL; 277 int y, y_start, dd, ds; 278 uint8_t *d, *s; 279 uint32_t *cptr, *s24; 280 281 if (surface_bits_per_pixel(surface) != 32) { 282 return; 283 } 284 285 page = 0; 286 y_start = -1; 287 d = surface_data(surface); 288 s = ts->vram; 289 s24 = ts->vram24; 290 cptr = ts->cplane; 291 dd = surface_stride(surface); 292 ds = 1024; 293 294 snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0, 295 memory_region_size(&ts->vram_mem), 296 DIRTY_MEMORY_VGA); 297 298 for (y = 0; y < ts->height; y++, page += ds) { 299 if (tcx_check_dirty(ts, snap, page, ds)) { 300 if (y_start < 0) 301 y_start = y; 302 303 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 304 if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) { 305 tcx_draw_cursor32(ts, d, y, ts->width); 306 } 307 } else { 308 if (y_start >= 0) { 309 /* flush to display */ 310 dpy_gfx_update(ts->con, 0, y_start, 311 ts->width, y - y_start); 312 y_start = -1; 313 } 314 } 315 d += dd; 316 s += ds; 317 cptr += ds; 318 s24 += ds; 319 } 320 if (y_start >= 0) { 321 /* flush to display */ 322 dpy_gfx_update(ts->con, 0, y_start, 323 ts->width, y - y_start); 324 } 325 g_free(snap); 326 } 327 328 static void tcx_invalidate_display(void *opaque) 329 { 330 TCXState *s = opaque; 331 332 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 333 qemu_console_resize(s->con, s->width, s->height); 334 } 335 336 static void tcx24_invalidate_display(void *opaque) 337 { 338 TCXState *s = opaque; 339 340 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 341 qemu_console_resize(s->con, s->width, s->height); 342 } 343 344 static int vmstate_tcx_post_load(void *opaque, int version_id) 345 { 346 TCXState *s = opaque; 347 348 update_palette_entries(s, 0, 256); 349 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 350 return 0; 351 } 352 353 static const VMStateDescription vmstate_tcx = { 354 .name ="tcx", 355 .version_id = 4, 356 .minimum_version_id = 4, 357 .post_load = vmstate_tcx_post_load, 358 .fields = (VMStateField[]) { 359 VMSTATE_UINT16(height, TCXState), 360 VMSTATE_UINT16(width, TCXState), 361 VMSTATE_UINT16(depth, TCXState), 362 VMSTATE_BUFFER(r, TCXState), 363 VMSTATE_BUFFER(g, TCXState), 364 VMSTATE_BUFFER(b, TCXState), 365 VMSTATE_UINT8(dac_index, TCXState), 366 VMSTATE_UINT8(dac_state, TCXState), 367 VMSTATE_END_OF_LIST() 368 } 369 }; 370 371 static void tcx_reset(DeviceState *d) 372 { 373 TCXState *s = TCX(d); 374 375 /* Initialize palette */ 376 memset(s->r, 0, 260); 377 memset(s->g, 0, 260); 378 memset(s->b, 0, 260); 379 s->r[255] = s->g[255] = s->b[255] = 255; 380 s->r[256] = s->g[256] = s->b[256] = 255; 381 s->r[258] = s->g[258] = s->b[258] = 255; 382 update_palette_entries(s, 0, 260); 383 memset(s->vram, 0, MAXX*MAXY); 384 memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), 385 DIRTY_MEMORY_VGA); 386 s->dac_index = 0; 387 s->dac_state = 0; 388 s->cursx = 0xf000; /* Put cursor off screen */ 389 s->cursy = 0xf000; 390 } 391 392 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr, 393 unsigned size) 394 { 395 TCXState *s = opaque; 396 uint32_t val = 0; 397 398 switch (s->dac_state) { 399 case 0: 400 val = s->r[s->dac_index] << 24; 401 s->dac_state++; 402 break; 403 case 1: 404 val = s->g[s->dac_index] << 24; 405 s->dac_state++; 406 break; 407 case 2: 408 val = s->b[s->dac_index] << 24; 409 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ 410 default: 411 s->dac_state = 0; 412 break; 413 } 414 415 return val; 416 } 417 418 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val, 419 unsigned size) 420 { 421 TCXState *s = opaque; 422 unsigned index; 423 424 switch (addr) { 425 case 0: /* Address */ 426 s->dac_index = val >> 24; 427 s->dac_state = 0; 428 break; 429 case 4: /* Pixel colours */ 430 case 12: /* Overlay (cursor) colours */ 431 if (addr & 8) { 432 index = (s->dac_index & 3) + 256; 433 } else { 434 index = s->dac_index; 435 } 436 switch (s->dac_state) { 437 case 0: 438 s->r[index] = val >> 24; 439 update_palette_entries(s, index, index + 1); 440 s->dac_state++; 441 break; 442 case 1: 443 s->g[index] = val >> 24; 444 update_palette_entries(s, index, index + 1); 445 s->dac_state++; 446 break; 447 case 2: 448 s->b[index] = val >> 24; 449 update_palette_entries(s, index, index + 1); 450 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ 451 default: 452 s->dac_state = 0; 453 break; 454 } 455 break; 456 default: /* Control registers */ 457 break; 458 } 459 } 460 461 static const MemoryRegionOps tcx_dac_ops = { 462 .read = tcx_dac_readl, 463 .write = tcx_dac_writel, 464 .endianness = DEVICE_NATIVE_ENDIAN, 465 .valid = { 466 .min_access_size = 4, 467 .max_access_size = 4, 468 }, 469 }; 470 471 static uint64_t tcx_stip_readl(void *opaque, hwaddr addr, 472 unsigned size) 473 { 474 return 0; 475 } 476 477 static void tcx_stip_writel(void *opaque, hwaddr addr, 478 uint64_t val, unsigned size) 479 { 480 TCXState *s = opaque; 481 int i; 482 uint32_t col; 483 484 if (!(addr & 4)) { 485 s->tmpblit = val; 486 } else { 487 addr = (addr >> 3) & 0xfffff; 488 col = cpu_to_be32(s->tmpblit); 489 if (s->depth == 24) { 490 for (i = 0; i < 32; i++) { 491 if (val & 0x80000000) { 492 s->vram[addr + i] = s->tmpblit; 493 s->vram24[addr + i] = col; 494 } 495 val <<= 1; 496 } 497 } else { 498 for (i = 0; i < 32; i++) { 499 if (val & 0x80000000) { 500 s->vram[addr + i] = s->tmpblit; 501 } 502 val <<= 1; 503 } 504 } 505 tcx_set_dirty(s, addr, 32); 506 } 507 } 508 509 static void tcx_rstip_writel(void *opaque, hwaddr addr, 510 uint64_t val, unsigned size) 511 { 512 TCXState *s = opaque; 513 int i; 514 uint32_t col; 515 516 if (!(addr & 4)) { 517 s->tmpblit = val; 518 } else { 519 addr = (addr >> 3) & 0xfffff; 520 col = cpu_to_be32(s->tmpblit); 521 if (s->depth == 24) { 522 for (i = 0; i < 32; i++) { 523 if (val & 0x80000000) { 524 s->vram[addr + i] = s->tmpblit; 525 s->vram24[addr + i] = col; 526 s->cplane[addr + i] = col; 527 } 528 val <<= 1; 529 } 530 } else { 531 for (i = 0; i < 32; i++) { 532 if (val & 0x80000000) { 533 s->vram[addr + i] = s->tmpblit; 534 } 535 val <<= 1; 536 } 537 } 538 tcx_set_dirty(s, addr, 32); 539 } 540 } 541 542 static const MemoryRegionOps tcx_stip_ops = { 543 .read = tcx_stip_readl, 544 .write = tcx_stip_writel, 545 .endianness = DEVICE_NATIVE_ENDIAN, 546 .valid = { 547 .min_access_size = 4, 548 .max_access_size = 4, 549 }, 550 }; 551 552 static const MemoryRegionOps tcx_rstip_ops = { 553 .read = tcx_stip_readl, 554 .write = tcx_rstip_writel, 555 .endianness = DEVICE_NATIVE_ENDIAN, 556 .valid = { 557 .min_access_size = 4, 558 .max_access_size = 4, 559 }, 560 }; 561 562 static uint64_t tcx_blit_readl(void *opaque, hwaddr addr, 563 unsigned size) 564 { 565 return 0; 566 } 567 568 static void tcx_blit_writel(void *opaque, hwaddr addr, 569 uint64_t val, unsigned size) 570 { 571 TCXState *s = opaque; 572 uint32_t adsr, len; 573 int i; 574 575 if (!(addr & 4)) { 576 s->tmpblit = val; 577 } else { 578 addr = (addr >> 3) & 0xfffff; 579 adsr = val & 0xffffff; 580 len = ((val >> 24) & 0x1f) + 1; 581 if (adsr == 0xffffff) { 582 memset(&s->vram[addr], s->tmpblit, len); 583 if (s->depth == 24) { 584 val = s->tmpblit & 0xffffff; 585 val = cpu_to_be32(val); 586 for (i = 0; i < len; i++) { 587 s->vram24[addr + i] = val; 588 } 589 } 590 } else { 591 memcpy(&s->vram[addr], &s->vram[adsr], len); 592 if (s->depth == 24) { 593 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); 594 } 595 } 596 tcx_set_dirty(s, addr, len); 597 } 598 } 599 600 static void tcx_rblit_writel(void *opaque, hwaddr addr, 601 uint64_t val, unsigned size) 602 { 603 TCXState *s = opaque; 604 uint32_t adsr, len; 605 int i; 606 607 if (!(addr & 4)) { 608 s->tmpblit = val; 609 } else { 610 addr = (addr >> 3) & 0xfffff; 611 adsr = val & 0xffffff; 612 len = ((val >> 24) & 0x1f) + 1; 613 if (adsr == 0xffffff) { 614 memset(&s->vram[addr], s->tmpblit, len); 615 if (s->depth == 24) { 616 val = s->tmpblit & 0xffffff; 617 val = cpu_to_be32(val); 618 for (i = 0; i < len; i++) { 619 s->vram24[addr + i] = val; 620 s->cplane[addr + i] = val; 621 } 622 } 623 } else { 624 memcpy(&s->vram[addr], &s->vram[adsr], len); 625 if (s->depth == 24) { 626 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); 627 memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4); 628 } 629 } 630 tcx_set_dirty(s, addr, len); 631 } 632 } 633 634 static const MemoryRegionOps tcx_blit_ops = { 635 .read = tcx_blit_readl, 636 .write = tcx_blit_writel, 637 .endianness = DEVICE_NATIVE_ENDIAN, 638 .valid = { 639 .min_access_size = 4, 640 .max_access_size = 4, 641 }, 642 }; 643 644 static const MemoryRegionOps tcx_rblit_ops = { 645 .read = tcx_blit_readl, 646 .write = tcx_rblit_writel, 647 .endianness = DEVICE_NATIVE_ENDIAN, 648 .valid = { 649 .min_access_size = 4, 650 .max_access_size = 4, 651 }, 652 }; 653 654 static void tcx_invalidate_cursor_position(TCXState *s) 655 { 656 int ymin, ymax, start, end; 657 658 /* invalidate only near the cursor */ 659 ymin = s->cursy; 660 if (ymin >= s->height) { 661 return; 662 } 663 ymax = MIN(s->height, ymin + 32); 664 start = ymin * 1024; 665 end = ymax * 1024; 666 667 tcx_set_dirty(s, start, end - start); 668 } 669 670 static uint64_t tcx_thc_readl(void *opaque, hwaddr addr, 671 unsigned size) 672 { 673 TCXState *s = opaque; 674 uint64_t val; 675 676 if (addr == TCX_THC_MISC) { 677 val = s->thcmisc | 0x02000000; 678 } else { 679 val = 0; 680 } 681 return val; 682 } 683 684 static void tcx_thc_writel(void *opaque, hwaddr addr, 685 uint64_t val, unsigned size) 686 { 687 TCXState *s = opaque; 688 689 if (addr == TCX_THC_CURSXY) { 690 tcx_invalidate_cursor_position(s); 691 s->cursx = val >> 16; 692 s->cursy = val; 693 tcx_invalidate_cursor_position(s); 694 } else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) { 695 s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val; 696 tcx_invalidate_cursor_position(s); 697 } else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) { 698 s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val; 699 tcx_invalidate_cursor_position(s); 700 } else if (addr == TCX_THC_MISC) { 701 s->thcmisc = val; 702 } 703 704 } 705 706 static const MemoryRegionOps tcx_thc_ops = { 707 .read = tcx_thc_readl, 708 .write = tcx_thc_writel, 709 .endianness = DEVICE_NATIVE_ENDIAN, 710 .valid = { 711 .min_access_size = 4, 712 .max_access_size = 4, 713 }, 714 }; 715 716 static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr, 717 unsigned size) 718 { 719 return 0; 720 } 721 722 static void tcx_dummy_writel(void *opaque, hwaddr addr, 723 uint64_t val, unsigned size) 724 { 725 return; 726 } 727 728 static const MemoryRegionOps tcx_dummy_ops = { 729 .read = tcx_dummy_readl, 730 .write = tcx_dummy_writel, 731 .endianness = DEVICE_NATIVE_ENDIAN, 732 .valid = { 733 .min_access_size = 4, 734 .max_access_size = 4, 735 }, 736 }; 737 738 static const GraphicHwOps tcx_ops = { 739 .invalidate = tcx_invalidate_display, 740 .gfx_update = tcx_update_display, 741 }; 742 743 static const GraphicHwOps tcx24_ops = { 744 .invalidate = tcx24_invalidate_display, 745 .gfx_update = tcx24_update_display, 746 }; 747 748 static void tcx_initfn(Object *obj) 749 { 750 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 751 TCXState *s = TCX(obj); 752 753 memory_region_init_ram_nomigrate(&s->rom, obj, "tcx.prom", FCODE_MAX_ROM_SIZE, 754 &error_fatal); 755 memory_region_set_readonly(&s->rom, true); 756 sysbus_init_mmio(sbd, &s->rom); 757 758 /* 2/STIP : Stippler */ 759 memory_region_init_io(&s->stip, obj, &tcx_stip_ops, s, "tcx.stip", 760 TCX_STIP_NREGS); 761 sysbus_init_mmio(sbd, &s->stip); 762 763 /* 3/BLIT : Blitter */ 764 memory_region_init_io(&s->blit, obj, &tcx_blit_ops, s, "tcx.blit", 765 TCX_BLIT_NREGS); 766 sysbus_init_mmio(sbd, &s->blit); 767 768 /* 5/RSTIP : Raw Stippler */ 769 memory_region_init_io(&s->rstip, obj, &tcx_rstip_ops, s, "tcx.rstip", 770 TCX_RSTIP_NREGS); 771 sysbus_init_mmio(sbd, &s->rstip); 772 773 /* 6/RBLIT : Raw Blitter */ 774 memory_region_init_io(&s->rblit, obj, &tcx_rblit_ops, s, "tcx.rblit", 775 TCX_RBLIT_NREGS); 776 sysbus_init_mmio(sbd, &s->rblit); 777 778 /* 7/TEC : ??? */ 779 memory_region_init_io(&s->tec, obj, &tcx_dummy_ops, s, "tcx.tec", 780 TCX_TEC_NREGS); 781 sysbus_init_mmio(sbd, &s->tec); 782 783 /* 8/CMAP : DAC */ 784 memory_region_init_io(&s->dac, obj, &tcx_dac_ops, s, "tcx.dac", 785 TCX_DAC_NREGS); 786 sysbus_init_mmio(sbd, &s->dac); 787 788 /* 9/THC : Cursor */ 789 memory_region_init_io(&s->thc, obj, &tcx_thc_ops, s, "tcx.thc", 790 TCX_THC_NREGS); 791 sysbus_init_mmio(sbd, &s->thc); 792 793 /* 11/DHC : ??? */ 794 memory_region_init_io(&s->dhc, obj, &tcx_dummy_ops, s, "tcx.dhc", 795 TCX_DHC_NREGS); 796 sysbus_init_mmio(sbd, &s->dhc); 797 798 /* 12/ALT : ??? */ 799 memory_region_init_io(&s->alt, obj, &tcx_dummy_ops, s, "tcx.alt", 800 TCX_ALT_NREGS); 801 sysbus_init_mmio(sbd, &s->alt); 802 } 803 804 static void tcx_realizefn(DeviceState *dev, Error **errp) 805 { 806 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 807 TCXState *s = TCX(dev); 808 ram_addr_t vram_offset = 0; 809 int size, ret; 810 uint8_t *vram_base; 811 char *fcode_filename; 812 813 memory_region_init_ram_nomigrate(&s->vram_mem, OBJECT(s), "tcx.vram", 814 s->vram_size * (1 + 4 + 4), &error_fatal); 815 vmstate_register_ram_global(&s->vram_mem); 816 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); 817 vram_base = memory_region_get_ram_ptr(&s->vram_mem); 818 819 /* 10/ROM : FCode ROM */ 820 vmstate_register_ram_global(&s->rom); 821 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE); 822 if (fcode_filename) { 823 ret = load_image_mr(fcode_filename, &s->rom); 824 g_free(fcode_filename); 825 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { 826 warn_report("tcx: could not load prom '%s'", TCX_ROM_FILE); 827 } 828 } 829 830 /* 0/DFB8 : 8-bit plane */ 831 s->vram = vram_base; 832 size = s->vram_size; 833 memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit", 834 &s->vram_mem, vram_offset, size); 835 sysbus_init_mmio(sbd, &s->vram_8bit); 836 vram_offset += size; 837 vram_base += size; 838 839 /* 1/DFB24 : 24bit plane */ 840 size = s->vram_size * 4; 841 s->vram24 = (uint32_t *)vram_base; 842 s->vram24_offset = vram_offset; 843 memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit", 844 &s->vram_mem, vram_offset, size); 845 sysbus_init_mmio(sbd, &s->vram_24bit); 846 vram_offset += size; 847 vram_base += size; 848 849 /* 4/RDFB32 : Raw Framebuffer */ 850 size = s->vram_size * 4; 851 s->cplane = (uint32_t *)vram_base; 852 s->cplane_offset = vram_offset; 853 memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane", 854 &s->vram_mem, vram_offset, size); 855 sysbus_init_mmio(sbd, &s->vram_cplane); 856 857 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 858 if (s->depth == 8) { 859 memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s, 860 "tcx.thc24", TCX_THC_NREGS); 861 sysbus_init_mmio(sbd, &s->thc24); 862 } 863 864 sysbus_init_irq(sbd, &s->irq); 865 866 if (s->depth == 8) { 867 s->con = graphic_console_init(DEVICE(dev), 0, &tcx_ops, s); 868 } else { 869 s->con = graphic_console_init(DEVICE(dev), 0, &tcx24_ops, s); 870 } 871 s->thcmisc = 0; 872 873 qemu_console_resize(s->con, s->width, s->height); 874 } 875 876 static Property tcx_properties[] = { 877 DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1), 878 DEFINE_PROP_UINT16("width", TCXState, width, -1), 879 DEFINE_PROP_UINT16("height", TCXState, height, -1), 880 DEFINE_PROP_UINT16("depth", TCXState, depth, -1), 881 DEFINE_PROP_END_OF_LIST(), 882 }; 883 884 static void tcx_class_init(ObjectClass *klass, void *data) 885 { 886 DeviceClass *dc = DEVICE_CLASS(klass); 887 888 dc->realize = tcx_realizefn; 889 dc->reset = tcx_reset; 890 dc->vmsd = &vmstate_tcx; 891 dc->props = tcx_properties; 892 } 893 894 static const TypeInfo tcx_info = { 895 .name = TYPE_TCX, 896 .parent = TYPE_SYS_BUS_DEVICE, 897 .instance_size = sizeof(TCXState), 898 .instance_init = tcx_initfn, 899 .class_init = tcx_class_init, 900 }; 901 902 static void tcx_register_types(void) 903 { 904 type_register_static(&tcx_info); 905 } 906 907 type_init(tcx_register_types) 908