15193899aSPaolo Bonzini /*
25193899aSPaolo Bonzini * TI OMAP processors GPIO emulation.
35193899aSPaolo Bonzini *
45193899aSPaolo Bonzini * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
55193899aSPaolo Bonzini * Copyright (C) 2007-2009 Nokia Corporation
65193899aSPaolo Bonzini *
75193899aSPaolo Bonzini * This program is free software; you can redistribute it and/or
85193899aSPaolo Bonzini * modify it under the terms of the GNU General Public License as
95193899aSPaolo Bonzini * published by the Free Software Foundation; either version 2 or
105193899aSPaolo Bonzini * (at your option) version 3 of the License.
115193899aSPaolo Bonzini *
125193899aSPaolo Bonzini * This program is distributed in the hope that it will be useful,
135193899aSPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of
145193899aSPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
155193899aSPaolo Bonzini * GNU General Public License for more details.
165193899aSPaolo Bonzini *
175193899aSPaolo Bonzini * You should have received a copy of the GNU General Public License along
185193899aSPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>.
195193899aSPaolo Bonzini */
205193899aSPaolo Bonzini
2117b7f2dbSPeter Maydell #include "qemu/osdep.h"
22cd617484SPhilippe Mathieu-Daudé #include "qemu/log.h"
2364552b6bSMarkus Armbruster #include "hw/irq.h"
24a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h"
255193899aSPaolo Bonzini #include "hw/arm/omap.h"
265193899aSPaolo Bonzini #include "hw/sysbus.h"
2784a3a53cSMarkus Armbruster #include "qemu/error-report.h"
280b8fa32fSMarkus Armbruster #include "qemu/module.h"
29ebc116f8Sxiaoqiang zhao #include "qapi/error.h"
305193899aSPaolo Bonzini
315193899aSPaolo Bonzini struct omap_gpio_s {
325193899aSPaolo Bonzini qemu_irq irq;
335193899aSPaolo Bonzini qemu_irq handler[16];
345193899aSPaolo Bonzini
355193899aSPaolo Bonzini uint16_t inputs;
365193899aSPaolo Bonzini uint16_t outputs;
375193899aSPaolo Bonzini uint16_t dir;
385193899aSPaolo Bonzini uint16_t edge;
395193899aSPaolo Bonzini uint16_t mask;
405193899aSPaolo Bonzini uint16_t ints;
415193899aSPaolo Bonzini uint16_t pins;
425193899aSPaolo Bonzini };
435193899aSPaolo Bonzini
44bbcdf7d0SPhilippe Mathieu-Daudé struct Omap1GpioState {
451d300b5fSAndreas Färber SysBusDevice parent_obj;
461d300b5fSAndreas Färber
475193899aSPaolo Bonzini MemoryRegion iomem;
485193899aSPaolo Bonzini int mpu_model;
495193899aSPaolo Bonzini void *clk;
505193899aSPaolo Bonzini struct omap_gpio_s omap1;
515193899aSPaolo Bonzini };
525193899aSPaolo Bonzini
535193899aSPaolo Bonzini /* General-Purpose I/O of OMAP1 */
omap_gpio_set(void * opaque,int line,int level)545193899aSPaolo Bonzini static void omap_gpio_set(void *opaque, int line, int level)
555193899aSPaolo Bonzini {
56bbcdf7d0SPhilippe Mathieu-Daudé Omap1GpioState *p = opaque;
5728180159SPhilippe Mathieu-Daudé struct omap_gpio_s *s = &p->omap1;
585193899aSPaolo Bonzini uint16_t prev = s->inputs;
595193899aSPaolo Bonzini
605193899aSPaolo Bonzini if (level)
615193899aSPaolo Bonzini s->inputs |= 1 << line;
625193899aSPaolo Bonzini else
635193899aSPaolo Bonzini s->inputs &= ~(1 << line);
645193899aSPaolo Bonzini
655193899aSPaolo Bonzini if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
665193899aSPaolo Bonzini (1 << line) & s->dir & ~s->mask) {
675193899aSPaolo Bonzini s->ints |= 1 << line;
685193899aSPaolo Bonzini qemu_irq_raise(s->irq);
695193899aSPaolo Bonzini }
705193899aSPaolo Bonzini }
715193899aSPaolo Bonzini
omap_gpio_read(void * opaque,hwaddr addr,unsigned size)725193899aSPaolo Bonzini static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
735193899aSPaolo Bonzini unsigned size)
745193899aSPaolo Bonzini {
75a75ed3c4SPhilippe Mathieu-Daudé struct omap_gpio_s *s = opaque;
765193899aSPaolo Bonzini int offset = addr & OMAP_MPUI_REG_MASK;
775193899aSPaolo Bonzini
785193899aSPaolo Bonzini if (size != 2) {
795193899aSPaolo Bonzini return omap_badwidth_read16(opaque, addr);
805193899aSPaolo Bonzini }
815193899aSPaolo Bonzini
825193899aSPaolo Bonzini switch (offset) {
835193899aSPaolo Bonzini case 0x00: /* DATA_INPUT */
845193899aSPaolo Bonzini return s->inputs & s->pins;
855193899aSPaolo Bonzini
865193899aSPaolo Bonzini case 0x04: /* DATA_OUTPUT */
875193899aSPaolo Bonzini return s->outputs;
885193899aSPaolo Bonzini
895193899aSPaolo Bonzini case 0x08: /* DIRECTION_CONTROL */
905193899aSPaolo Bonzini return s->dir;
915193899aSPaolo Bonzini
925193899aSPaolo Bonzini case 0x0c: /* INTERRUPT_CONTROL */
935193899aSPaolo Bonzini return s->edge;
945193899aSPaolo Bonzini
955193899aSPaolo Bonzini case 0x10: /* INTERRUPT_MASK */
965193899aSPaolo Bonzini return s->mask;
975193899aSPaolo Bonzini
985193899aSPaolo Bonzini case 0x14: /* INTERRUPT_STATUS */
995193899aSPaolo Bonzini return s->ints;
1005193899aSPaolo Bonzini
1015193899aSPaolo Bonzini case 0x18: /* PIN_CONTROL (not in OMAP310) */
1025193899aSPaolo Bonzini OMAP_BAD_REG(addr);
1035193899aSPaolo Bonzini return s->pins;
1045193899aSPaolo Bonzini }
1055193899aSPaolo Bonzini
1065193899aSPaolo Bonzini OMAP_BAD_REG(addr);
1075193899aSPaolo Bonzini return 0;
1085193899aSPaolo Bonzini }
1095193899aSPaolo Bonzini
omap_gpio_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)1105193899aSPaolo Bonzini static void omap_gpio_write(void *opaque, hwaddr addr,
1115193899aSPaolo Bonzini uint64_t value, unsigned size)
1125193899aSPaolo Bonzini {
113a75ed3c4SPhilippe Mathieu-Daudé struct omap_gpio_s *s = opaque;
1145193899aSPaolo Bonzini int offset = addr & OMAP_MPUI_REG_MASK;
1155193899aSPaolo Bonzini uint16_t diff;
1165193899aSPaolo Bonzini int ln;
1175193899aSPaolo Bonzini
1185193899aSPaolo Bonzini if (size != 2) {
11977a8257eSStefan Weil omap_badwidth_write16(opaque, addr, value);
12077a8257eSStefan Weil return;
1215193899aSPaolo Bonzini }
1225193899aSPaolo Bonzini
1235193899aSPaolo Bonzini switch (offset) {
1245193899aSPaolo Bonzini case 0x00: /* DATA_INPUT */
1255193899aSPaolo Bonzini OMAP_RO_REG(addr);
1265193899aSPaolo Bonzini return;
1275193899aSPaolo Bonzini
1285193899aSPaolo Bonzini case 0x04: /* DATA_OUTPUT */
1295193899aSPaolo Bonzini diff = (s->outputs ^ value) & ~s->dir;
1305193899aSPaolo Bonzini s->outputs = value;
131bd2a8884SStefan Hajnoczi while ((ln = ctz32(diff)) != 32) {
1325193899aSPaolo Bonzini if (s->handler[ln])
1335193899aSPaolo Bonzini qemu_set_irq(s->handler[ln], (value >> ln) & 1);
1345193899aSPaolo Bonzini diff &= ~(1 << ln);
1355193899aSPaolo Bonzini }
1365193899aSPaolo Bonzini break;
1375193899aSPaolo Bonzini
1385193899aSPaolo Bonzini case 0x08: /* DIRECTION_CONTROL */
1395193899aSPaolo Bonzini diff = s->outputs & (s->dir ^ value);
1405193899aSPaolo Bonzini s->dir = value;
1415193899aSPaolo Bonzini
1425193899aSPaolo Bonzini value = s->outputs & ~s->dir;
143bd2a8884SStefan Hajnoczi while ((ln = ctz32(diff)) != 32) {
1445193899aSPaolo Bonzini if (s->handler[ln])
1455193899aSPaolo Bonzini qemu_set_irq(s->handler[ln], (value >> ln) & 1);
1465193899aSPaolo Bonzini diff &= ~(1 << ln);
1475193899aSPaolo Bonzini }
1485193899aSPaolo Bonzini break;
1495193899aSPaolo Bonzini
1505193899aSPaolo Bonzini case 0x0c: /* INTERRUPT_CONTROL */
1515193899aSPaolo Bonzini s->edge = value;
1525193899aSPaolo Bonzini break;
1535193899aSPaolo Bonzini
1545193899aSPaolo Bonzini case 0x10: /* INTERRUPT_MASK */
1555193899aSPaolo Bonzini s->mask = value;
1565193899aSPaolo Bonzini break;
1575193899aSPaolo Bonzini
1585193899aSPaolo Bonzini case 0x14: /* INTERRUPT_STATUS */
1595193899aSPaolo Bonzini s->ints &= ~value;
1605193899aSPaolo Bonzini if (!s->ints)
1615193899aSPaolo Bonzini qemu_irq_lower(s->irq);
1625193899aSPaolo Bonzini break;
1635193899aSPaolo Bonzini
1645193899aSPaolo Bonzini case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
1655193899aSPaolo Bonzini OMAP_BAD_REG(addr);
1665193899aSPaolo Bonzini s->pins = value;
1675193899aSPaolo Bonzini break;
1685193899aSPaolo Bonzini
1695193899aSPaolo Bonzini default:
1705193899aSPaolo Bonzini OMAP_BAD_REG(addr);
1715193899aSPaolo Bonzini return;
1725193899aSPaolo Bonzini }
1735193899aSPaolo Bonzini }
1745193899aSPaolo Bonzini
1755193899aSPaolo Bonzini /* *Some* sources say the memory region is 32-bit. */
1765193899aSPaolo Bonzini static const MemoryRegionOps omap_gpio_ops = {
1775193899aSPaolo Bonzini .read = omap_gpio_read,
1785193899aSPaolo Bonzini .write = omap_gpio_write,
1795193899aSPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN,
1805193899aSPaolo Bonzini };
1815193899aSPaolo Bonzini
omap_gpio_reset(struct omap_gpio_s * s)1825193899aSPaolo Bonzini static void omap_gpio_reset(struct omap_gpio_s *s)
1835193899aSPaolo Bonzini {
1845193899aSPaolo Bonzini s->inputs = 0;
1855193899aSPaolo Bonzini s->outputs = ~0;
1865193899aSPaolo Bonzini s->dir = ~0;
1875193899aSPaolo Bonzini s->edge = ~0;
1885193899aSPaolo Bonzini s->mask = ~0;
1895193899aSPaolo Bonzini s->ints = 0;
1905193899aSPaolo Bonzini s->pins = ~0;
1915193899aSPaolo Bonzini }
1925193899aSPaolo Bonzini
1935193899aSPaolo Bonzini struct omap2_gpio_s {
1945193899aSPaolo Bonzini qemu_irq irq[2];
1955193899aSPaolo Bonzini qemu_irq wkup;
1965193899aSPaolo Bonzini qemu_irq *handler;
1975193899aSPaolo Bonzini MemoryRegion iomem;
1985193899aSPaolo Bonzini
1995193899aSPaolo Bonzini uint8_t revision;
2005193899aSPaolo Bonzini uint8_t config[2];
2015193899aSPaolo Bonzini uint32_t inputs;
2025193899aSPaolo Bonzini uint32_t outputs;
2035193899aSPaolo Bonzini uint32_t dir;
2045193899aSPaolo Bonzini uint32_t level[2];
2055193899aSPaolo Bonzini uint32_t edge[2];
2065193899aSPaolo Bonzini uint32_t mask[2];
2075193899aSPaolo Bonzini uint32_t wumask;
2085193899aSPaolo Bonzini uint32_t ints[2];
2095193899aSPaolo Bonzini uint32_t debounce;
2105193899aSPaolo Bonzini uint8_t delay;
2115193899aSPaolo Bonzini };
2125193899aSPaolo Bonzini
213bb3d1c61SPhilippe Mathieu-Daudé struct Omap2GpioState {
21474d1e352SAndreas Färber SysBusDevice parent_obj;
21574d1e352SAndreas Färber
2165193899aSPaolo Bonzini MemoryRegion iomem;
2175193899aSPaolo Bonzini int mpu_model;
2185193899aSPaolo Bonzini void *iclk;
2195193899aSPaolo Bonzini void *fclk[6];
2205193899aSPaolo Bonzini int modulecount;
2215193899aSPaolo Bonzini struct omap2_gpio_s *modules;
2225193899aSPaolo Bonzini qemu_irq *handler;
2235193899aSPaolo Bonzini int autoidle;
2245193899aSPaolo Bonzini int gpo;
2255193899aSPaolo Bonzini };
2265193899aSPaolo Bonzini
2275193899aSPaolo Bonzini /* General-Purpose Interface of OMAP2/3 */
omap2_gpio_module_int_update(struct omap2_gpio_s * s,int line)2285193899aSPaolo Bonzini static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s,
2295193899aSPaolo Bonzini int line)
2305193899aSPaolo Bonzini {
2315193899aSPaolo Bonzini qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
2325193899aSPaolo Bonzini }
2335193899aSPaolo Bonzini
omap2_gpio_module_wake(struct omap2_gpio_s * s,int line)2345193899aSPaolo Bonzini static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line)
2355193899aSPaolo Bonzini {
2365193899aSPaolo Bonzini if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */
2375193899aSPaolo Bonzini return;
2385193899aSPaolo Bonzini if (!(s->config[0] & (3 << 3))) /* Force Idle */
2395193899aSPaolo Bonzini return;
2405193899aSPaolo Bonzini if (!(s->wumask & (1 << line)))
2415193899aSPaolo Bonzini return;
2425193899aSPaolo Bonzini
2435193899aSPaolo Bonzini qemu_irq_raise(s->wkup);
2445193899aSPaolo Bonzini }
2455193899aSPaolo Bonzini
omap2_gpio_module_out_update(struct omap2_gpio_s * s,uint32_t diff)2465193899aSPaolo Bonzini static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s,
2475193899aSPaolo Bonzini uint32_t diff)
2485193899aSPaolo Bonzini {
2495193899aSPaolo Bonzini int ln;
2505193899aSPaolo Bonzini
2515193899aSPaolo Bonzini s->outputs ^= diff;
2525193899aSPaolo Bonzini diff &= ~s->dir;
253bd2a8884SStefan Hajnoczi while ((ln = ctz32(diff)) != 32) {
2545193899aSPaolo Bonzini qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
2555193899aSPaolo Bonzini diff &= ~(1 << ln);
2565193899aSPaolo Bonzini }
2575193899aSPaolo Bonzini }
2585193899aSPaolo Bonzini
omap2_gpio_module_level_update(struct omap2_gpio_s * s,int line)2595193899aSPaolo Bonzini static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line)
2605193899aSPaolo Bonzini {
2615193899aSPaolo Bonzini s->ints[line] |= s->dir &
2625193899aSPaolo Bonzini ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
2635193899aSPaolo Bonzini omap2_gpio_module_int_update(s, line);
2645193899aSPaolo Bonzini }
2655193899aSPaolo Bonzini
omap2_gpio_module_int(struct omap2_gpio_s * s,int line)2665193899aSPaolo Bonzini static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
2675193899aSPaolo Bonzini {
2685193899aSPaolo Bonzini s->ints[0] |= 1 << line;
2695193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 0);
2705193899aSPaolo Bonzini s->ints[1] |= 1 << line;
2715193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 1);
2725193899aSPaolo Bonzini omap2_gpio_module_wake(s, line);
2735193899aSPaolo Bonzini }
2745193899aSPaolo Bonzini
omap2_gpio_set(void * opaque,int line,int level)2755193899aSPaolo Bonzini static void omap2_gpio_set(void *opaque, int line, int level)
2765193899aSPaolo Bonzini {
277bb3d1c61SPhilippe Mathieu-Daudé Omap2GpioState *p = opaque;
2785193899aSPaolo Bonzini struct omap2_gpio_s *s = &p->modules[line >> 5];
2795193899aSPaolo Bonzini
2805193899aSPaolo Bonzini line &= 31;
2815193899aSPaolo Bonzini if (level) {
2825193899aSPaolo Bonzini if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
2835193899aSPaolo Bonzini omap2_gpio_module_int(s, line);
2845193899aSPaolo Bonzini s->inputs |= 1 << line;
2855193899aSPaolo Bonzini } else {
2865193899aSPaolo Bonzini if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
2875193899aSPaolo Bonzini omap2_gpio_module_int(s, line);
2885193899aSPaolo Bonzini s->inputs &= ~(1 << line);
2895193899aSPaolo Bonzini }
2905193899aSPaolo Bonzini }
2915193899aSPaolo Bonzini
omap2_gpio_module_reset(struct omap2_gpio_s * s)2925193899aSPaolo Bonzini static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
2935193899aSPaolo Bonzini {
2945193899aSPaolo Bonzini s->config[0] = 0;
2955193899aSPaolo Bonzini s->config[1] = 2;
2965193899aSPaolo Bonzini s->ints[0] = 0;
2975193899aSPaolo Bonzini s->ints[1] = 0;
2985193899aSPaolo Bonzini s->mask[0] = 0;
2995193899aSPaolo Bonzini s->mask[1] = 0;
3005193899aSPaolo Bonzini s->wumask = 0;
3015193899aSPaolo Bonzini s->dir = ~0;
3025193899aSPaolo Bonzini s->level[0] = 0;
3035193899aSPaolo Bonzini s->level[1] = 0;
3045193899aSPaolo Bonzini s->edge[0] = 0;
3055193899aSPaolo Bonzini s->edge[1] = 0;
3065193899aSPaolo Bonzini s->debounce = 0;
3075193899aSPaolo Bonzini s->delay = 0;
3085193899aSPaolo Bonzini }
3095193899aSPaolo Bonzini
omap2_gpio_module_read(void * opaque,hwaddr addr)3105193899aSPaolo Bonzini static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
3115193899aSPaolo Bonzini {
312a75ed3c4SPhilippe Mathieu-Daudé struct omap2_gpio_s *s = opaque;
3135193899aSPaolo Bonzini
3145193899aSPaolo Bonzini switch (addr) {
3155193899aSPaolo Bonzini case 0x00: /* GPIO_REVISION */
3165193899aSPaolo Bonzini return s->revision;
3175193899aSPaolo Bonzini
3185193899aSPaolo Bonzini case 0x10: /* GPIO_SYSCONFIG */
3195193899aSPaolo Bonzini return s->config[0];
3205193899aSPaolo Bonzini
3215193899aSPaolo Bonzini case 0x14: /* GPIO_SYSSTATUS */
3225193899aSPaolo Bonzini return 0x01;
3235193899aSPaolo Bonzini
3245193899aSPaolo Bonzini case 0x18: /* GPIO_IRQSTATUS1 */
3255193899aSPaolo Bonzini return s->ints[0];
3265193899aSPaolo Bonzini
3275193899aSPaolo Bonzini case 0x1c: /* GPIO_IRQENABLE1 */
3285193899aSPaolo Bonzini case 0x60: /* GPIO_CLEARIRQENABLE1 */
3295193899aSPaolo Bonzini case 0x64: /* GPIO_SETIRQENABLE1 */
3305193899aSPaolo Bonzini return s->mask[0];
3315193899aSPaolo Bonzini
3325193899aSPaolo Bonzini case 0x20: /* GPIO_WAKEUPENABLE */
3335193899aSPaolo Bonzini case 0x80: /* GPIO_CLEARWKUENA */
3345193899aSPaolo Bonzini case 0x84: /* GPIO_SETWKUENA */
3355193899aSPaolo Bonzini return s->wumask;
3365193899aSPaolo Bonzini
3375193899aSPaolo Bonzini case 0x28: /* GPIO_IRQSTATUS2 */
3385193899aSPaolo Bonzini return s->ints[1];
3395193899aSPaolo Bonzini
3405193899aSPaolo Bonzini case 0x2c: /* GPIO_IRQENABLE2 */
3415193899aSPaolo Bonzini case 0x70: /* GPIO_CLEARIRQENABLE2 */
3425193899aSPaolo Bonzini case 0x74: /* GPIO_SETIREQNEABLE2 */
3435193899aSPaolo Bonzini return s->mask[1];
3445193899aSPaolo Bonzini
3455193899aSPaolo Bonzini case 0x30: /* GPIO_CTRL */
3465193899aSPaolo Bonzini return s->config[1];
3475193899aSPaolo Bonzini
3485193899aSPaolo Bonzini case 0x34: /* GPIO_OE */
3495193899aSPaolo Bonzini return s->dir;
3505193899aSPaolo Bonzini
3515193899aSPaolo Bonzini case 0x38: /* GPIO_DATAIN */
3525193899aSPaolo Bonzini return s->inputs;
3535193899aSPaolo Bonzini
3545193899aSPaolo Bonzini case 0x3c: /* GPIO_DATAOUT */
3555193899aSPaolo Bonzini case 0x90: /* GPIO_CLEARDATAOUT */
3565193899aSPaolo Bonzini case 0x94: /* GPIO_SETDATAOUT */
3575193899aSPaolo Bonzini return s->outputs;
3585193899aSPaolo Bonzini
3595193899aSPaolo Bonzini case 0x40: /* GPIO_LEVELDETECT0 */
3605193899aSPaolo Bonzini return s->level[0];
3615193899aSPaolo Bonzini
3625193899aSPaolo Bonzini case 0x44: /* GPIO_LEVELDETECT1 */
3635193899aSPaolo Bonzini return s->level[1];
3645193899aSPaolo Bonzini
3655193899aSPaolo Bonzini case 0x48: /* GPIO_RISINGDETECT */
3665193899aSPaolo Bonzini return s->edge[0];
3675193899aSPaolo Bonzini
3685193899aSPaolo Bonzini case 0x4c: /* GPIO_FALLINGDETECT */
3695193899aSPaolo Bonzini return s->edge[1];
3705193899aSPaolo Bonzini
3715193899aSPaolo Bonzini case 0x50: /* GPIO_DEBOUNCENABLE */
3725193899aSPaolo Bonzini return s->debounce;
3735193899aSPaolo Bonzini
3745193899aSPaolo Bonzini case 0x54: /* GPIO_DEBOUNCINGTIME */
3755193899aSPaolo Bonzini return s->delay;
3765193899aSPaolo Bonzini }
3775193899aSPaolo Bonzini
3785193899aSPaolo Bonzini OMAP_BAD_REG(addr);
3795193899aSPaolo Bonzini return 0;
3805193899aSPaolo Bonzini }
3815193899aSPaolo Bonzini
omap2_gpio_module_write(void * opaque,hwaddr addr,uint32_t value)3825193899aSPaolo Bonzini static void omap2_gpio_module_write(void *opaque, hwaddr addr,
3835193899aSPaolo Bonzini uint32_t value)
3845193899aSPaolo Bonzini {
385a75ed3c4SPhilippe Mathieu-Daudé struct omap2_gpio_s *s = opaque;
3865193899aSPaolo Bonzini uint32_t diff;
3875193899aSPaolo Bonzini int ln;
3885193899aSPaolo Bonzini
3895193899aSPaolo Bonzini switch (addr) {
3905193899aSPaolo Bonzini case 0x00: /* GPIO_REVISION */
3915193899aSPaolo Bonzini case 0x14: /* GPIO_SYSSTATUS */
3925193899aSPaolo Bonzini case 0x38: /* GPIO_DATAIN */
3935193899aSPaolo Bonzini OMAP_RO_REG(addr);
3945193899aSPaolo Bonzini break;
3955193899aSPaolo Bonzini
3965193899aSPaolo Bonzini case 0x10: /* GPIO_SYSCONFIG */
397dfd4981aSPhilippe Mathieu-Daudé if (((value >> 3) & 3) == 3) {
398dfd4981aSPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR,
399dfd4981aSPhilippe Mathieu-Daudé "%s: Illegal IDLEMODE value: 3\n", __func__);
400dfd4981aSPhilippe Mathieu-Daudé }
4015193899aSPaolo Bonzini if (value & 2)
4025193899aSPaolo Bonzini omap2_gpio_module_reset(s);
4035193899aSPaolo Bonzini s->config[0] = value & 0x1d;
4045193899aSPaolo Bonzini break;
4055193899aSPaolo Bonzini
4065193899aSPaolo Bonzini case 0x18: /* GPIO_IRQSTATUS1 */
4075193899aSPaolo Bonzini if (s->ints[0] & value) {
4085193899aSPaolo Bonzini s->ints[0] &= ~value;
4095193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 0);
4105193899aSPaolo Bonzini }
4115193899aSPaolo Bonzini break;
4125193899aSPaolo Bonzini
4135193899aSPaolo Bonzini case 0x1c: /* GPIO_IRQENABLE1 */
4145193899aSPaolo Bonzini s->mask[0] = value;
4155193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 0);
4165193899aSPaolo Bonzini break;
4175193899aSPaolo Bonzini
4185193899aSPaolo Bonzini case 0x20: /* GPIO_WAKEUPENABLE */
4195193899aSPaolo Bonzini s->wumask = value;
4205193899aSPaolo Bonzini break;
4215193899aSPaolo Bonzini
4225193899aSPaolo Bonzini case 0x28: /* GPIO_IRQSTATUS2 */
4235193899aSPaolo Bonzini if (s->ints[1] & value) {
4245193899aSPaolo Bonzini s->ints[1] &= ~value;
4255193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 1);
4265193899aSPaolo Bonzini }
4275193899aSPaolo Bonzini break;
4285193899aSPaolo Bonzini
4295193899aSPaolo Bonzini case 0x2c: /* GPIO_IRQENABLE2 */
4305193899aSPaolo Bonzini s->mask[1] = value;
4315193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 1);
4325193899aSPaolo Bonzini break;
4335193899aSPaolo Bonzini
4345193899aSPaolo Bonzini case 0x30: /* GPIO_CTRL */
4355193899aSPaolo Bonzini s->config[1] = value & 7;
4365193899aSPaolo Bonzini break;
4375193899aSPaolo Bonzini
4385193899aSPaolo Bonzini case 0x34: /* GPIO_OE */
4395193899aSPaolo Bonzini diff = s->outputs & (s->dir ^ value);
4405193899aSPaolo Bonzini s->dir = value;
4415193899aSPaolo Bonzini
4425193899aSPaolo Bonzini value = s->outputs & ~s->dir;
443bd2a8884SStefan Hajnoczi while ((ln = ctz32(diff)) != 32) {
444bd2a8884SStefan Hajnoczi diff &= ~(1 << ln);
4455193899aSPaolo Bonzini qemu_set_irq(s->handler[ln], (value >> ln) & 1);
4465193899aSPaolo Bonzini }
4475193899aSPaolo Bonzini
4485193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 0);
4495193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 1);
4505193899aSPaolo Bonzini break;
4515193899aSPaolo Bonzini
4525193899aSPaolo Bonzini case 0x3c: /* GPIO_DATAOUT */
4535193899aSPaolo Bonzini omap2_gpio_module_out_update(s, s->outputs ^ value);
4545193899aSPaolo Bonzini break;
4555193899aSPaolo Bonzini
4565193899aSPaolo Bonzini case 0x40: /* GPIO_LEVELDETECT0 */
4575193899aSPaolo Bonzini s->level[0] = value;
4585193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 0);
4595193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 1);
4605193899aSPaolo Bonzini break;
4615193899aSPaolo Bonzini
4625193899aSPaolo Bonzini case 0x44: /* GPIO_LEVELDETECT1 */
4635193899aSPaolo Bonzini s->level[1] = value;
4645193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 0);
4655193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 1);
4665193899aSPaolo Bonzini break;
4675193899aSPaolo Bonzini
4685193899aSPaolo Bonzini case 0x48: /* GPIO_RISINGDETECT */
4695193899aSPaolo Bonzini s->edge[0] = value;
4705193899aSPaolo Bonzini break;
4715193899aSPaolo Bonzini
4725193899aSPaolo Bonzini case 0x4c: /* GPIO_FALLINGDETECT */
4735193899aSPaolo Bonzini s->edge[1] = value;
4745193899aSPaolo Bonzini break;
4755193899aSPaolo Bonzini
4765193899aSPaolo Bonzini case 0x50: /* GPIO_DEBOUNCENABLE */
4775193899aSPaolo Bonzini s->debounce = value;
4785193899aSPaolo Bonzini break;
4795193899aSPaolo Bonzini
4805193899aSPaolo Bonzini case 0x54: /* GPIO_DEBOUNCINGTIME */
4815193899aSPaolo Bonzini s->delay = value;
4825193899aSPaolo Bonzini break;
4835193899aSPaolo Bonzini
4845193899aSPaolo Bonzini case 0x60: /* GPIO_CLEARIRQENABLE1 */
4855193899aSPaolo Bonzini s->mask[0] &= ~value;
4865193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 0);
4875193899aSPaolo Bonzini break;
4885193899aSPaolo Bonzini
4895193899aSPaolo Bonzini case 0x64: /* GPIO_SETIRQENABLE1 */
4905193899aSPaolo Bonzini s->mask[0] |= value;
4915193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 0);
4925193899aSPaolo Bonzini break;
4935193899aSPaolo Bonzini
4945193899aSPaolo Bonzini case 0x70: /* GPIO_CLEARIRQENABLE2 */
4955193899aSPaolo Bonzini s->mask[1] &= ~value;
4965193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 1);
4975193899aSPaolo Bonzini break;
4985193899aSPaolo Bonzini
4995193899aSPaolo Bonzini case 0x74: /* GPIO_SETIREQNEABLE2 */
5005193899aSPaolo Bonzini s->mask[1] |= value;
5015193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 1);
5025193899aSPaolo Bonzini break;
5035193899aSPaolo Bonzini
5045193899aSPaolo Bonzini case 0x80: /* GPIO_CLEARWKUENA */
5055193899aSPaolo Bonzini s->wumask &= ~value;
5065193899aSPaolo Bonzini break;
5075193899aSPaolo Bonzini
5085193899aSPaolo Bonzini case 0x84: /* GPIO_SETWKUENA */
5095193899aSPaolo Bonzini s->wumask |= value;
5105193899aSPaolo Bonzini break;
5115193899aSPaolo Bonzini
5125193899aSPaolo Bonzini case 0x90: /* GPIO_CLEARDATAOUT */
5135193899aSPaolo Bonzini omap2_gpio_module_out_update(s, s->outputs & value);
5145193899aSPaolo Bonzini break;
5155193899aSPaolo Bonzini
5165193899aSPaolo Bonzini case 0x94: /* GPIO_SETDATAOUT */
5175193899aSPaolo Bonzini omap2_gpio_module_out_update(s, ~s->outputs & value);
5185193899aSPaolo Bonzini break;
5195193899aSPaolo Bonzini
5205193899aSPaolo Bonzini default:
5215193899aSPaolo Bonzini OMAP_BAD_REG(addr);
5225193899aSPaolo Bonzini return;
5235193899aSPaolo Bonzini }
5245193899aSPaolo Bonzini }
5255193899aSPaolo Bonzini
omap2_gpio_module_readp(void * opaque,hwaddr addr,unsigned size)526940caf1fSPeter Maydell static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr,
527940caf1fSPeter Maydell unsigned size)
5285193899aSPaolo Bonzini {
5295193899aSPaolo Bonzini return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
5305193899aSPaolo Bonzini }
5315193899aSPaolo Bonzini
omap2_gpio_module_writep(void * opaque,hwaddr addr,uint64_t value,unsigned size)5325193899aSPaolo Bonzini static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
533940caf1fSPeter Maydell uint64_t value, unsigned size)
5345193899aSPaolo Bonzini {
5355193899aSPaolo Bonzini uint32_t cur = 0;
5365193899aSPaolo Bonzini uint32_t mask = 0xffff;
5375193899aSPaolo Bonzini
538940caf1fSPeter Maydell if (size == 4) {
539940caf1fSPeter Maydell omap2_gpio_module_write(opaque, addr, value);
540940caf1fSPeter Maydell return;
541940caf1fSPeter Maydell }
542940caf1fSPeter Maydell
5435193899aSPaolo Bonzini switch (addr & ~3) {
5445193899aSPaolo Bonzini case 0x00: /* GPIO_REVISION */
5455193899aSPaolo Bonzini case 0x14: /* GPIO_SYSSTATUS */
5465193899aSPaolo Bonzini case 0x38: /* GPIO_DATAIN */
5475193899aSPaolo Bonzini OMAP_RO_REG(addr);
5485193899aSPaolo Bonzini break;
5495193899aSPaolo Bonzini
5505193899aSPaolo Bonzini case 0x10: /* GPIO_SYSCONFIG */
5515193899aSPaolo Bonzini case 0x1c: /* GPIO_IRQENABLE1 */
5525193899aSPaolo Bonzini case 0x20: /* GPIO_WAKEUPENABLE */
5535193899aSPaolo Bonzini case 0x2c: /* GPIO_IRQENABLE2 */
5545193899aSPaolo Bonzini case 0x30: /* GPIO_CTRL */
5555193899aSPaolo Bonzini case 0x34: /* GPIO_OE */
5565193899aSPaolo Bonzini case 0x3c: /* GPIO_DATAOUT */
5575193899aSPaolo Bonzini case 0x40: /* GPIO_LEVELDETECT0 */
5585193899aSPaolo Bonzini case 0x44: /* GPIO_LEVELDETECT1 */
5595193899aSPaolo Bonzini case 0x48: /* GPIO_RISINGDETECT */
5605193899aSPaolo Bonzini case 0x4c: /* GPIO_FALLINGDETECT */
5615193899aSPaolo Bonzini case 0x50: /* GPIO_DEBOUNCENABLE */
5625193899aSPaolo Bonzini case 0x54: /* GPIO_DEBOUNCINGTIME */
5635193899aSPaolo Bonzini cur = omap2_gpio_module_read(opaque, addr & ~3) &
5645193899aSPaolo Bonzini ~(mask << ((addr & 3) << 3));
5655193899aSPaolo Bonzini
5665193899aSPaolo Bonzini /* Fall through. */
5675193899aSPaolo Bonzini case 0x18: /* GPIO_IRQSTATUS1 */
5685193899aSPaolo Bonzini case 0x28: /* GPIO_IRQSTATUS2 */
5695193899aSPaolo Bonzini case 0x60: /* GPIO_CLEARIRQENABLE1 */
5705193899aSPaolo Bonzini case 0x64: /* GPIO_SETIRQENABLE1 */
5715193899aSPaolo Bonzini case 0x70: /* GPIO_CLEARIRQENABLE2 */
5725193899aSPaolo Bonzini case 0x74: /* GPIO_SETIREQNEABLE2 */
5735193899aSPaolo Bonzini case 0x80: /* GPIO_CLEARWKUENA */
5745193899aSPaolo Bonzini case 0x84: /* GPIO_SETWKUENA */
5755193899aSPaolo Bonzini case 0x90: /* GPIO_CLEARDATAOUT */
5765193899aSPaolo Bonzini case 0x94: /* GPIO_SETDATAOUT */
5775193899aSPaolo Bonzini value <<= (addr & 3) << 3;
5785193899aSPaolo Bonzini omap2_gpio_module_write(opaque, addr, cur | value);
5795193899aSPaolo Bonzini break;
5805193899aSPaolo Bonzini
5815193899aSPaolo Bonzini default:
5825193899aSPaolo Bonzini OMAP_BAD_REG(addr);
5835193899aSPaolo Bonzini return;
5845193899aSPaolo Bonzini }
5855193899aSPaolo Bonzini }
5865193899aSPaolo Bonzini
5875193899aSPaolo Bonzini static const MemoryRegionOps omap2_gpio_module_ops = {
588940caf1fSPeter Maydell .read = omap2_gpio_module_readp,
589940caf1fSPeter Maydell .write = omap2_gpio_module_writep,
590940caf1fSPeter Maydell .valid.min_access_size = 1,
591940caf1fSPeter Maydell .valid.max_access_size = 4,
5925193899aSPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN,
5935193899aSPaolo Bonzini };
5945193899aSPaolo Bonzini
omap_gpif_reset(DeviceState * dev)5955193899aSPaolo Bonzini static void omap_gpif_reset(DeviceState *dev)
5965193899aSPaolo Bonzini {
597bbcdf7d0SPhilippe Mathieu-Daudé Omap1GpioState *s = OMAP1_GPIO(dev);
5981d300b5fSAndreas Färber
5995193899aSPaolo Bonzini omap_gpio_reset(&s->omap1);
6005193899aSPaolo Bonzini }
6015193899aSPaolo Bonzini
omap2_gpif_reset(DeviceState * dev)6025193899aSPaolo Bonzini static void omap2_gpif_reset(DeviceState *dev)
6035193899aSPaolo Bonzini {
604bb3d1c61SPhilippe Mathieu-Daudé Omap2GpioState *s = OMAP2_GPIO(dev);
6055193899aSPaolo Bonzini int i;
60674d1e352SAndreas Färber
6075193899aSPaolo Bonzini for (i = 0; i < s->modulecount; i++) {
6085193899aSPaolo Bonzini omap2_gpio_module_reset(&s->modules[i]);
6095193899aSPaolo Bonzini }
6105193899aSPaolo Bonzini s->autoidle = 0;
6115193899aSPaolo Bonzini s->gpo = 0;
6125193899aSPaolo Bonzini }
6135193899aSPaolo Bonzini
omap2_gpif_top_read(void * opaque,hwaddr addr,unsigned size)614a75ed3c4SPhilippe Mathieu-Daudé static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
6155193899aSPaolo Bonzini {
616bb3d1c61SPhilippe Mathieu-Daudé Omap2GpioState *s = opaque;
6175193899aSPaolo Bonzini
6185193899aSPaolo Bonzini switch (addr) {
6195193899aSPaolo Bonzini case 0x00: /* IPGENERICOCPSPL_REVISION */
6205193899aSPaolo Bonzini return 0x18;
6215193899aSPaolo Bonzini
6225193899aSPaolo Bonzini case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
6235193899aSPaolo Bonzini return s->autoidle;
6245193899aSPaolo Bonzini
6255193899aSPaolo Bonzini case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
6265193899aSPaolo Bonzini return 0x01;
6275193899aSPaolo Bonzini
6285193899aSPaolo Bonzini case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
6295193899aSPaolo Bonzini return 0x00;
6305193899aSPaolo Bonzini
6315193899aSPaolo Bonzini case 0x40: /* IPGENERICOCPSPL_GPO */
6325193899aSPaolo Bonzini return s->gpo;
6335193899aSPaolo Bonzini
6345193899aSPaolo Bonzini case 0x50: /* IPGENERICOCPSPL_GPI */
6355193899aSPaolo Bonzini return 0x00;
6365193899aSPaolo Bonzini }
6375193899aSPaolo Bonzini
6385193899aSPaolo Bonzini OMAP_BAD_REG(addr);
6395193899aSPaolo Bonzini return 0;
6405193899aSPaolo Bonzini }
6415193899aSPaolo Bonzini
omap2_gpif_top_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)6425193899aSPaolo Bonzini static void omap2_gpif_top_write(void *opaque, hwaddr addr,
6435193899aSPaolo Bonzini uint64_t value, unsigned size)
6445193899aSPaolo Bonzini {
645bb3d1c61SPhilippe Mathieu-Daudé Omap2GpioState *s = opaque;
6465193899aSPaolo Bonzini
6475193899aSPaolo Bonzini switch (addr) {
6485193899aSPaolo Bonzini case 0x00: /* IPGENERICOCPSPL_REVISION */
6495193899aSPaolo Bonzini case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
6505193899aSPaolo Bonzini case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
6515193899aSPaolo Bonzini case 0x50: /* IPGENERICOCPSPL_GPI */
6525193899aSPaolo Bonzini OMAP_RO_REG(addr);
6535193899aSPaolo Bonzini break;
6545193899aSPaolo Bonzini
6555193899aSPaolo Bonzini case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
6565193899aSPaolo Bonzini if (value & (1 << 1)) /* SOFTRESET */
65774d1e352SAndreas Färber omap2_gpif_reset(DEVICE(s));
6585193899aSPaolo Bonzini s->autoidle = value & 1;
6595193899aSPaolo Bonzini break;
6605193899aSPaolo Bonzini
6615193899aSPaolo Bonzini case 0x40: /* IPGENERICOCPSPL_GPO */
6625193899aSPaolo Bonzini s->gpo = value & 1;
6635193899aSPaolo Bonzini break;
6645193899aSPaolo Bonzini
6655193899aSPaolo Bonzini default:
6665193899aSPaolo Bonzini OMAP_BAD_REG(addr);
6675193899aSPaolo Bonzini return;
6685193899aSPaolo Bonzini }
6695193899aSPaolo Bonzini }
6705193899aSPaolo Bonzini
6715193899aSPaolo Bonzini static const MemoryRegionOps omap2_gpif_top_ops = {
6725193899aSPaolo Bonzini .read = omap2_gpif_top_read,
6735193899aSPaolo Bonzini .write = omap2_gpif_top_write,
6745193899aSPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN,
6755193899aSPaolo Bonzini };
6765193899aSPaolo Bonzini
omap_gpio_init(Object * obj)677ebc116f8Sxiaoqiang zhao static void omap_gpio_init(Object *obj)
6785193899aSPaolo Bonzini {
679ebc116f8Sxiaoqiang zhao DeviceState *dev = DEVICE(obj);
680bbcdf7d0SPhilippe Mathieu-Daudé Omap1GpioState *s = OMAP1_GPIO(obj);
681ebc116f8Sxiaoqiang zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
6821d300b5fSAndreas Färber
6831d300b5fSAndreas Färber qdev_init_gpio_in(dev, omap_gpio_set, 16);
6841d300b5fSAndreas Färber qdev_init_gpio_out(dev, s->omap1.handler, 16);
6851d300b5fSAndreas Färber sysbus_init_irq(sbd, &s->omap1.irq);
686ebc116f8Sxiaoqiang zhao memory_region_init_io(&s->iomem, obj, &omap_gpio_ops, &s->omap1,
6875193899aSPaolo Bonzini "omap.gpio", 0x1000);
6881d300b5fSAndreas Färber sysbus_init_mmio(sbd, &s->iomem);
6895193899aSPaolo Bonzini }
6905193899aSPaolo Bonzini
omap_gpio_realize(DeviceState * dev,Error ** errp)691ebc116f8Sxiaoqiang zhao static void omap_gpio_realize(DeviceState *dev, Error **errp)
6925193899aSPaolo Bonzini {
693bbcdf7d0SPhilippe Mathieu-Daudé Omap1GpioState *s = OMAP1_GPIO(dev);
694ebc116f8Sxiaoqiang zhao
695ebc116f8Sxiaoqiang zhao if (!s->clk) {
696ebc116f8Sxiaoqiang zhao error_setg(errp, "omap-gpio: clk not connected");
697ebc116f8Sxiaoqiang zhao }
698ebc116f8Sxiaoqiang zhao }
699ebc116f8Sxiaoqiang zhao
omap2_gpio_realize(DeviceState * dev,Error ** errp)700ebc116f8Sxiaoqiang zhao static void omap2_gpio_realize(DeviceState *dev, Error **errp)
701ebc116f8Sxiaoqiang zhao {
702bb3d1c61SPhilippe Mathieu-Daudé Omap2GpioState *s = OMAP2_GPIO(dev);
703ebc116f8Sxiaoqiang zhao SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
7045193899aSPaolo Bonzini int i;
70574d1e352SAndreas Färber
7065193899aSPaolo Bonzini if (!s->iclk) {
707ebc116f8Sxiaoqiang zhao error_setg(errp, "omap2-gpio: iclk not connected");
708ebc116f8Sxiaoqiang zhao return;
7095193899aSPaolo Bonzini }
71084a3a53cSMarkus Armbruster
71184a3a53cSMarkus Armbruster s->modulecount = s->mpu_model < omap2430 ? 4
71284a3a53cSMarkus Armbruster : s->mpu_model < omap3430 ? 5
71384a3a53cSMarkus Armbruster : 6;
71484a3a53cSMarkus Armbruster
7155193899aSPaolo Bonzini if (s->mpu_model < omap3430) {
716ebc116f8Sxiaoqiang zhao memory_region_init_io(&s->iomem, OBJECT(dev), &omap2_gpif_top_ops, s,
7175193899aSPaolo Bonzini "omap2.gpio", 0x1000);
71874d1e352SAndreas Färber sysbus_init_mmio(sbd, &s->iomem);
7195193899aSPaolo Bonzini }
72084a3a53cSMarkus Armbruster
721b45c03f5SMarkus Armbruster s->modules = g_new0(struct omap2_gpio_s, s->modulecount);
722b45c03f5SMarkus Armbruster s->handler = g_new0(qemu_irq, s->modulecount * 32);
72374d1e352SAndreas Färber qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32);
72474d1e352SAndreas Färber qdev_init_gpio_out(dev, s->handler, s->modulecount * 32);
72584a3a53cSMarkus Armbruster
7265193899aSPaolo Bonzini for (i = 0; i < s->modulecount; i++) {
7275193899aSPaolo Bonzini struct omap2_gpio_s *m = &s->modules[i];
72884a3a53cSMarkus Armbruster
729ebc116f8Sxiaoqiang zhao if (!s->fclk[i]) {
730ebc116f8Sxiaoqiang zhao error_setg(errp, "omap2-gpio: fclk%d not connected", i);
731ebc116f8Sxiaoqiang zhao return;
732ebc116f8Sxiaoqiang zhao }
733ebc116f8Sxiaoqiang zhao
7345193899aSPaolo Bonzini m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25;
7355193899aSPaolo Bonzini m->handler = &s->handler[i * 32];
73674d1e352SAndreas Färber sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */
73774d1e352SAndreas Färber sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */
73874d1e352SAndreas Färber sysbus_init_irq(sbd, &m->wkup);
739ebc116f8Sxiaoqiang zhao memory_region_init_io(&m->iomem, OBJECT(dev), &omap2_gpio_module_ops, m,
7405193899aSPaolo Bonzini "omap.gpio-module", 0x1000);
74174d1e352SAndreas Färber sysbus_init_mmio(sbd, &m->iomem);
7425193899aSPaolo Bonzini }
7435193899aSPaolo Bonzini }
7445193899aSPaolo Bonzini
omap_gpio_set_clk(Omap1GpioState * gpio,omap_clk clk)745bbcdf7d0SPhilippe Mathieu-Daudé void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk)
746ba2aba83SMarc-André Lureau {
747ba2aba83SMarc-André Lureau gpio->clk = clk;
748ba2aba83SMarc-André Lureau }
7495193899aSPaolo Bonzini
7505193899aSPaolo Bonzini static Property omap_gpio_properties[] = {
751bbcdf7d0SPhilippe Mathieu-Daudé DEFINE_PROP_INT32("mpu_model", Omap1GpioState, mpu_model, 0),
7525193899aSPaolo Bonzini DEFINE_PROP_END_OF_LIST(),
7535193899aSPaolo Bonzini };
7545193899aSPaolo Bonzini
omap_gpio_class_init(ObjectClass * klass,void * data)7555193899aSPaolo Bonzini static void omap_gpio_class_init(ObjectClass *klass, void *data)
7565193899aSPaolo Bonzini {
7575193899aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass);
7585193899aSPaolo Bonzini
759ebc116f8Sxiaoqiang zhao dc->realize = omap_gpio_realize;
760*e3d08143SPeter Maydell device_class_set_legacy_reset(dc, omap_gpif_reset);
7614f67d30bSMarc-André Lureau device_class_set_props(dc, omap_gpio_properties);
7621b111dc1SMarkus Armbruster /* Reason: pointer property "clk" */
763e90f2a8cSEduardo Habkost dc->user_creatable = false;
7645193899aSPaolo Bonzini }
7655193899aSPaolo Bonzini
7665193899aSPaolo Bonzini static const TypeInfo omap_gpio_info = {
7671d300b5fSAndreas Färber .name = TYPE_OMAP1_GPIO,
7685193899aSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE,
769bbcdf7d0SPhilippe Mathieu-Daudé .instance_size = sizeof(Omap1GpioState),
770ebc116f8Sxiaoqiang zhao .instance_init = omap_gpio_init,
7715193899aSPaolo Bonzini .class_init = omap_gpio_class_init,
7725193899aSPaolo Bonzini };
7735193899aSPaolo Bonzini
omap2_gpio_set_iclk(Omap2GpioState * gpio,omap_clk clk)774bb3d1c61SPhilippe Mathieu-Daudé void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk)
775ba2aba83SMarc-André Lureau {
776ba2aba83SMarc-André Lureau gpio->iclk = clk;
777ba2aba83SMarc-André Lureau }
778ba2aba83SMarc-André Lureau
omap2_gpio_set_fclk(Omap2GpioState * gpio,uint8_t i,omap_clk clk)779bb3d1c61SPhilippe Mathieu-Daudé void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk)
780ba2aba83SMarc-André Lureau {
781ba2aba83SMarc-André Lureau assert(i <= 5);
782ba2aba83SMarc-André Lureau gpio->fclk[i] = clk;
783ba2aba83SMarc-André Lureau }
784ba2aba83SMarc-André Lureau
7855193899aSPaolo Bonzini static Property omap2_gpio_properties[] = {
786bb3d1c61SPhilippe Mathieu-Daudé DEFINE_PROP_INT32("mpu_model", Omap2GpioState, mpu_model, 0),
7875193899aSPaolo Bonzini DEFINE_PROP_END_OF_LIST(),
7885193899aSPaolo Bonzini };
7895193899aSPaolo Bonzini
omap2_gpio_class_init(ObjectClass * klass,void * data)7905193899aSPaolo Bonzini static void omap2_gpio_class_init(ObjectClass *klass, void *data)
7915193899aSPaolo Bonzini {
7925193899aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass);
7935193899aSPaolo Bonzini
794ebc116f8Sxiaoqiang zhao dc->realize = omap2_gpio_realize;
795*e3d08143SPeter Maydell device_class_set_legacy_reset(dc, omap2_gpif_reset);
7964f67d30bSMarc-André Lureau device_class_set_props(dc, omap2_gpio_properties);
7971b111dc1SMarkus Armbruster /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */
798e90f2a8cSEduardo Habkost dc->user_creatable = false;
7995193899aSPaolo Bonzini }
8005193899aSPaolo Bonzini
8015193899aSPaolo Bonzini static const TypeInfo omap2_gpio_info = {
80274d1e352SAndreas Färber .name = TYPE_OMAP2_GPIO,
8035193899aSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE,
804bb3d1c61SPhilippe Mathieu-Daudé .instance_size = sizeof(Omap2GpioState),
8055193899aSPaolo Bonzini .class_init = omap2_gpio_class_init,
8065193899aSPaolo Bonzini };
8075193899aSPaolo Bonzini
omap_gpio_register_types(void)8085193899aSPaolo Bonzini static void omap_gpio_register_types(void)
8095193899aSPaolo Bonzini {
8105193899aSPaolo Bonzini type_register_static(&omap_gpio_info);
8115193899aSPaolo Bonzini type_register_static(&omap2_gpio_info);
8125193899aSPaolo Bonzini }
8135193899aSPaolo Bonzini
8145193899aSPaolo Bonzini type_init(omap_gpio_register_types)
815