15193899aSPaolo Bonzini /* 25193899aSPaolo Bonzini * TI OMAP processors GPIO emulation. 35193899aSPaolo Bonzini * 45193899aSPaolo Bonzini * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 55193899aSPaolo Bonzini * Copyright (C) 2007-2009 Nokia Corporation 65193899aSPaolo Bonzini * 75193899aSPaolo Bonzini * This program is free software; you can redistribute it and/or 85193899aSPaolo Bonzini * modify it under the terms of the GNU General Public License as 95193899aSPaolo Bonzini * published by the Free Software Foundation; either version 2 or 105193899aSPaolo Bonzini * (at your option) version 3 of the License. 115193899aSPaolo Bonzini * 125193899aSPaolo Bonzini * This program is distributed in the hope that it will be useful, 135193899aSPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 145193899aSPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 155193899aSPaolo Bonzini * GNU General Public License for more details. 165193899aSPaolo Bonzini * 175193899aSPaolo Bonzini * You should have received a copy of the GNU General Public License along 185193899aSPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>. 195193899aSPaolo Bonzini */ 205193899aSPaolo Bonzini 2117b7f2dbSPeter Maydell #include "qemu/osdep.h" 2264552b6bSMarkus Armbruster #include "hw/irq.h" 23a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 245193899aSPaolo Bonzini #include "hw/arm/omap.h" 255193899aSPaolo Bonzini #include "hw/sysbus.h" 2684a3a53cSMarkus Armbruster #include "qemu/error-report.h" 270b8fa32fSMarkus Armbruster #include "qemu/module.h" 28ebc116f8Sxiaoqiang zhao #include "qapi/error.h" 295193899aSPaolo Bonzini 305193899aSPaolo Bonzini struct omap_gpio_s { 315193899aSPaolo Bonzini qemu_irq irq; 325193899aSPaolo Bonzini qemu_irq handler[16]; 335193899aSPaolo Bonzini 345193899aSPaolo Bonzini uint16_t inputs; 355193899aSPaolo Bonzini uint16_t outputs; 365193899aSPaolo Bonzini uint16_t dir; 375193899aSPaolo Bonzini uint16_t edge; 385193899aSPaolo Bonzini uint16_t mask; 395193899aSPaolo Bonzini uint16_t ints; 405193899aSPaolo Bonzini uint16_t pins; 415193899aSPaolo Bonzini }; 425193899aSPaolo Bonzini 435193899aSPaolo Bonzini struct omap_gpif_s { 441d300b5fSAndreas Färber SysBusDevice parent_obj; 451d300b5fSAndreas Färber 465193899aSPaolo Bonzini MemoryRegion iomem; 475193899aSPaolo Bonzini int mpu_model; 485193899aSPaolo Bonzini void *clk; 495193899aSPaolo Bonzini struct omap_gpio_s omap1; 505193899aSPaolo Bonzini }; 515193899aSPaolo Bonzini 525193899aSPaolo Bonzini /* General-Purpose I/O of OMAP1 */ 535193899aSPaolo Bonzini static void omap_gpio_set(void *opaque, int line, int level) 545193899aSPaolo Bonzini { 555193899aSPaolo Bonzini struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1; 565193899aSPaolo Bonzini uint16_t prev = s->inputs; 575193899aSPaolo Bonzini 585193899aSPaolo Bonzini if (level) 595193899aSPaolo Bonzini s->inputs |= 1 << line; 605193899aSPaolo Bonzini else 615193899aSPaolo Bonzini s->inputs &= ~(1 << line); 625193899aSPaolo Bonzini 635193899aSPaolo Bonzini if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) & 645193899aSPaolo Bonzini (1 << line) & s->dir & ~s->mask) { 655193899aSPaolo Bonzini s->ints |= 1 << line; 665193899aSPaolo Bonzini qemu_irq_raise(s->irq); 675193899aSPaolo Bonzini } 685193899aSPaolo Bonzini } 695193899aSPaolo Bonzini 705193899aSPaolo Bonzini static uint64_t omap_gpio_read(void *opaque, hwaddr addr, 715193899aSPaolo Bonzini unsigned size) 725193899aSPaolo Bonzini { 735193899aSPaolo Bonzini struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; 745193899aSPaolo Bonzini int offset = addr & OMAP_MPUI_REG_MASK; 755193899aSPaolo Bonzini 765193899aSPaolo Bonzini if (size != 2) { 775193899aSPaolo Bonzini return omap_badwidth_read16(opaque, addr); 785193899aSPaolo Bonzini } 795193899aSPaolo Bonzini 805193899aSPaolo Bonzini switch (offset) { 815193899aSPaolo Bonzini case 0x00: /* DATA_INPUT */ 825193899aSPaolo Bonzini return s->inputs & s->pins; 835193899aSPaolo Bonzini 845193899aSPaolo Bonzini case 0x04: /* DATA_OUTPUT */ 855193899aSPaolo Bonzini return s->outputs; 865193899aSPaolo Bonzini 875193899aSPaolo Bonzini case 0x08: /* DIRECTION_CONTROL */ 885193899aSPaolo Bonzini return s->dir; 895193899aSPaolo Bonzini 905193899aSPaolo Bonzini case 0x0c: /* INTERRUPT_CONTROL */ 915193899aSPaolo Bonzini return s->edge; 925193899aSPaolo Bonzini 935193899aSPaolo Bonzini case 0x10: /* INTERRUPT_MASK */ 945193899aSPaolo Bonzini return s->mask; 955193899aSPaolo Bonzini 965193899aSPaolo Bonzini case 0x14: /* INTERRUPT_STATUS */ 975193899aSPaolo Bonzini return s->ints; 985193899aSPaolo Bonzini 995193899aSPaolo Bonzini case 0x18: /* PIN_CONTROL (not in OMAP310) */ 1005193899aSPaolo Bonzini OMAP_BAD_REG(addr); 1015193899aSPaolo Bonzini return s->pins; 1025193899aSPaolo Bonzini } 1035193899aSPaolo Bonzini 1045193899aSPaolo Bonzini OMAP_BAD_REG(addr); 1055193899aSPaolo Bonzini return 0; 1065193899aSPaolo Bonzini } 1075193899aSPaolo Bonzini 1085193899aSPaolo Bonzini static void omap_gpio_write(void *opaque, hwaddr addr, 1095193899aSPaolo Bonzini uint64_t value, unsigned size) 1105193899aSPaolo Bonzini { 1115193899aSPaolo Bonzini struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; 1125193899aSPaolo Bonzini int offset = addr & OMAP_MPUI_REG_MASK; 1135193899aSPaolo Bonzini uint16_t diff; 1145193899aSPaolo Bonzini int ln; 1155193899aSPaolo Bonzini 1165193899aSPaolo Bonzini if (size != 2) { 11777a8257eSStefan Weil omap_badwidth_write16(opaque, addr, value); 11877a8257eSStefan Weil return; 1195193899aSPaolo Bonzini } 1205193899aSPaolo Bonzini 1215193899aSPaolo Bonzini switch (offset) { 1225193899aSPaolo Bonzini case 0x00: /* DATA_INPUT */ 1235193899aSPaolo Bonzini OMAP_RO_REG(addr); 1245193899aSPaolo Bonzini return; 1255193899aSPaolo Bonzini 1265193899aSPaolo Bonzini case 0x04: /* DATA_OUTPUT */ 1275193899aSPaolo Bonzini diff = (s->outputs ^ value) & ~s->dir; 1285193899aSPaolo Bonzini s->outputs = value; 129bd2a8884SStefan Hajnoczi while ((ln = ctz32(diff)) != 32) { 1305193899aSPaolo Bonzini if (s->handler[ln]) 1315193899aSPaolo Bonzini qemu_set_irq(s->handler[ln], (value >> ln) & 1); 1325193899aSPaolo Bonzini diff &= ~(1 << ln); 1335193899aSPaolo Bonzini } 1345193899aSPaolo Bonzini break; 1355193899aSPaolo Bonzini 1365193899aSPaolo Bonzini case 0x08: /* DIRECTION_CONTROL */ 1375193899aSPaolo Bonzini diff = s->outputs & (s->dir ^ value); 1385193899aSPaolo Bonzini s->dir = value; 1395193899aSPaolo Bonzini 1405193899aSPaolo Bonzini value = s->outputs & ~s->dir; 141bd2a8884SStefan Hajnoczi while ((ln = ctz32(diff)) != 32) { 1425193899aSPaolo Bonzini if (s->handler[ln]) 1435193899aSPaolo Bonzini qemu_set_irq(s->handler[ln], (value >> ln) & 1); 1445193899aSPaolo Bonzini diff &= ~(1 << ln); 1455193899aSPaolo Bonzini } 1465193899aSPaolo Bonzini break; 1475193899aSPaolo Bonzini 1485193899aSPaolo Bonzini case 0x0c: /* INTERRUPT_CONTROL */ 1495193899aSPaolo Bonzini s->edge = value; 1505193899aSPaolo Bonzini break; 1515193899aSPaolo Bonzini 1525193899aSPaolo Bonzini case 0x10: /* INTERRUPT_MASK */ 1535193899aSPaolo Bonzini s->mask = value; 1545193899aSPaolo Bonzini break; 1555193899aSPaolo Bonzini 1565193899aSPaolo Bonzini case 0x14: /* INTERRUPT_STATUS */ 1575193899aSPaolo Bonzini s->ints &= ~value; 1585193899aSPaolo Bonzini if (!s->ints) 1595193899aSPaolo Bonzini qemu_irq_lower(s->irq); 1605193899aSPaolo Bonzini break; 1615193899aSPaolo Bonzini 1625193899aSPaolo Bonzini case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ 1635193899aSPaolo Bonzini OMAP_BAD_REG(addr); 1645193899aSPaolo Bonzini s->pins = value; 1655193899aSPaolo Bonzini break; 1665193899aSPaolo Bonzini 1675193899aSPaolo Bonzini default: 1685193899aSPaolo Bonzini OMAP_BAD_REG(addr); 1695193899aSPaolo Bonzini return; 1705193899aSPaolo Bonzini } 1715193899aSPaolo Bonzini } 1725193899aSPaolo Bonzini 1735193899aSPaolo Bonzini /* *Some* sources say the memory region is 32-bit. */ 1745193899aSPaolo Bonzini static const MemoryRegionOps omap_gpio_ops = { 1755193899aSPaolo Bonzini .read = omap_gpio_read, 1765193899aSPaolo Bonzini .write = omap_gpio_write, 1775193899aSPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 1785193899aSPaolo Bonzini }; 1795193899aSPaolo Bonzini 1805193899aSPaolo Bonzini static void omap_gpio_reset(struct omap_gpio_s *s) 1815193899aSPaolo Bonzini { 1825193899aSPaolo Bonzini s->inputs = 0; 1835193899aSPaolo Bonzini s->outputs = ~0; 1845193899aSPaolo Bonzini s->dir = ~0; 1855193899aSPaolo Bonzini s->edge = ~0; 1865193899aSPaolo Bonzini s->mask = ~0; 1875193899aSPaolo Bonzini s->ints = 0; 1885193899aSPaolo Bonzini s->pins = ~0; 1895193899aSPaolo Bonzini } 1905193899aSPaolo Bonzini 1915193899aSPaolo Bonzini struct omap2_gpio_s { 1925193899aSPaolo Bonzini qemu_irq irq[2]; 1935193899aSPaolo Bonzini qemu_irq wkup; 1945193899aSPaolo Bonzini qemu_irq *handler; 1955193899aSPaolo Bonzini MemoryRegion iomem; 1965193899aSPaolo Bonzini 1975193899aSPaolo Bonzini uint8_t revision; 1985193899aSPaolo Bonzini uint8_t config[2]; 1995193899aSPaolo Bonzini uint32_t inputs; 2005193899aSPaolo Bonzini uint32_t outputs; 2015193899aSPaolo Bonzini uint32_t dir; 2025193899aSPaolo Bonzini uint32_t level[2]; 2035193899aSPaolo Bonzini uint32_t edge[2]; 2045193899aSPaolo Bonzini uint32_t mask[2]; 2055193899aSPaolo Bonzini uint32_t wumask; 2065193899aSPaolo Bonzini uint32_t ints[2]; 2075193899aSPaolo Bonzini uint32_t debounce; 2085193899aSPaolo Bonzini uint8_t delay; 2095193899aSPaolo Bonzini }; 2105193899aSPaolo Bonzini 2115193899aSPaolo Bonzini struct omap2_gpif_s { 21274d1e352SAndreas Färber SysBusDevice parent_obj; 21374d1e352SAndreas Färber 2145193899aSPaolo Bonzini MemoryRegion iomem; 2155193899aSPaolo Bonzini int mpu_model; 2165193899aSPaolo Bonzini void *iclk; 2175193899aSPaolo Bonzini void *fclk[6]; 2185193899aSPaolo Bonzini int modulecount; 2195193899aSPaolo Bonzini struct omap2_gpio_s *modules; 2205193899aSPaolo Bonzini qemu_irq *handler; 2215193899aSPaolo Bonzini int autoidle; 2225193899aSPaolo Bonzini int gpo; 2235193899aSPaolo Bonzini }; 2245193899aSPaolo Bonzini 2255193899aSPaolo Bonzini /* General-Purpose Interface of OMAP2/3 */ 2265193899aSPaolo Bonzini static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s, 2275193899aSPaolo Bonzini int line) 2285193899aSPaolo Bonzini { 2295193899aSPaolo Bonzini qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]); 2305193899aSPaolo Bonzini } 2315193899aSPaolo Bonzini 2325193899aSPaolo Bonzini static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line) 2335193899aSPaolo Bonzini { 2345193899aSPaolo Bonzini if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */ 2355193899aSPaolo Bonzini return; 2365193899aSPaolo Bonzini if (!(s->config[0] & (3 << 3))) /* Force Idle */ 2375193899aSPaolo Bonzini return; 2385193899aSPaolo Bonzini if (!(s->wumask & (1 << line))) 2395193899aSPaolo Bonzini return; 2405193899aSPaolo Bonzini 2415193899aSPaolo Bonzini qemu_irq_raise(s->wkup); 2425193899aSPaolo Bonzini } 2435193899aSPaolo Bonzini 2445193899aSPaolo Bonzini static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s, 2455193899aSPaolo Bonzini uint32_t diff) 2465193899aSPaolo Bonzini { 2475193899aSPaolo Bonzini int ln; 2485193899aSPaolo Bonzini 2495193899aSPaolo Bonzini s->outputs ^= diff; 2505193899aSPaolo Bonzini diff &= ~s->dir; 251bd2a8884SStefan Hajnoczi while ((ln = ctz32(diff)) != 32) { 2525193899aSPaolo Bonzini qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1); 2535193899aSPaolo Bonzini diff &= ~(1 << ln); 2545193899aSPaolo Bonzini } 2555193899aSPaolo Bonzini } 2565193899aSPaolo Bonzini 2575193899aSPaolo Bonzini static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line) 2585193899aSPaolo Bonzini { 2595193899aSPaolo Bonzini s->ints[line] |= s->dir & 2605193899aSPaolo Bonzini ((s->inputs & s->level[1]) | (~s->inputs & s->level[0])); 2615193899aSPaolo Bonzini omap2_gpio_module_int_update(s, line); 2625193899aSPaolo Bonzini } 2635193899aSPaolo Bonzini 2645193899aSPaolo Bonzini static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line) 2655193899aSPaolo Bonzini { 2665193899aSPaolo Bonzini s->ints[0] |= 1 << line; 2675193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 0); 2685193899aSPaolo Bonzini s->ints[1] |= 1 << line; 2695193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 1); 2705193899aSPaolo Bonzini omap2_gpio_module_wake(s, line); 2715193899aSPaolo Bonzini } 2725193899aSPaolo Bonzini 2735193899aSPaolo Bonzini static void omap2_gpio_set(void *opaque, int line, int level) 2745193899aSPaolo Bonzini { 2755193899aSPaolo Bonzini struct omap2_gpif_s *p = opaque; 2765193899aSPaolo Bonzini struct omap2_gpio_s *s = &p->modules[line >> 5]; 2775193899aSPaolo Bonzini 2785193899aSPaolo Bonzini line &= 31; 2795193899aSPaolo Bonzini if (level) { 2805193899aSPaolo Bonzini if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) 2815193899aSPaolo Bonzini omap2_gpio_module_int(s, line); 2825193899aSPaolo Bonzini s->inputs |= 1 << line; 2835193899aSPaolo Bonzini } else { 2845193899aSPaolo Bonzini if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) 2855193899aSPaolo Bonzini omap2_gpio_module_int(s, line); 2865193899aSPaolo Bonzini s->inputs &= ~(1 << line); 2875193899aSPaolo Bonzini } 2885193899aSPaolo Bonzini } 2895193899aSPaolo Bonzini 2905193899aSPaolo Bonzini static void omap2_gpio_module_reset(struct omap2_gpio_s *s) 2915193899aSPaolo Bonzini { 2925193899aSPaolo Bonzini s->config[0] = 0; 2935193899aSPaolo Bonzini s->config[1] = 2; 2945193899aSPaolo Bonzini s->ints[0] = 0; 2955193899aSPaolo Bonzini s->ints[1] = 0; 2965193899aSPaolo Bonzini s->mask[0] = 0; 2975193899aSPaolo Bonzini s->mask[1] = 0; 2985193899aSPaolo Bonzini s->wumask = 0; 2995193899aSPaolo Bonzini s->dir = ~0; 3005193899aSPaolo Bonzini s->level[0] = 0; 3015193899aSPaolo Bonzini s->level[1] = 0; 3025193899aSPaolo Bonzini s->edge[0] = 0; 3035193899aSPaolo Bonzini s->edge[1] = 0; 3045193899aSPaolo Bonzini s->debounce = 0; 3055193899aSPaolo Bonzini s->delay = 0; 3065193899aSPaolo Bonzini } 3075193899aSPaolo Bonzini 3085193899aSPaolo Bonzini static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr) 3095193899aSPaolo Bonzini { 3105193899aSPaolo Bonzini struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; 3115193899aSPaolo Bonzini 3125193899aSPaolo Bonzini switch (addr) { 3135193899aSPaolo Bonzini case 0x00: /* GPIO_REVISION */ 3145193899aSPaolo Bonzini return s->revision; 3155193899aSPaolo Bonzini 3165193899aSPaolo Bonzini case 0x10: /* GPIO_SYSCONFIG */ 3175193899aSPaolo Bonzini return s->config[0]; 3185193899aSPaolo Bonzini 3195193899aSPaolo Bonzini case 0x14: /* GPIO_SYSSTATUS */ 3205193899aSPaolo Bonzini return 0x01; 3215193899aSPaolo Bonzini 3225193899aSPaolo Bonzini case 0x18: /* GPIO_IRQSTATUS1 */ 3235193899aSPaolo Bonzini return s->ints[0]; 3245193899aSPaolo Bonzini 3255193899aSPaolo Bonzini case 0x1c: /* GPIO_IRQENABLE1 */ 3265193899aSPaolo Bonzini case 0x60: /* GPIO_CLEARIRQENABLE1 */ 3275193899aSPaolo Bonzini case 0x64: /* GPIO_SETIRQENABLE1 */ 3285193899aSPaolo Bonzini return s->mask[0]; 3295193899aSPaolo Bonzini 3305193899aSPaolo Bonzini case 0x20: /* GPIO_WAKEUPENABLE */ 3315193899aSPaolo Bonzini case 0x80: /* GPIO_CLEARWKUENA */ 3325193899aSPaolo Bonzini case 0x84: /* GPIO_SETWKUENA */ 3335193899aSPaolo Bonzini return s->wumask; 3345193899aSPaolo Bonzini 3355193899aSPaolo Bonzini case 0x28: /* GPIO_IRQSTATUS2 */ 3365193899aSPaolo Bonzini return s->ints[1]; 3375193899aSPaolo Bonzini 3385193899aSPaolo Bonzini case 0x2c: /* GPIO_IRQENABLE2 */ 3395193899aSPaolo Bonzini case 0x70: /* GPIO_CLEARIRQENABLE2 */ 3405193899aSPaolo Bonzini case 0x74: /* GPIO_SETIREQNEABLE2 */ 3415193899aSPaolo Bonzini return s->mask[1]; 3425193899aSPaolo Bonzini 3435193899aSPaolo Bonzini case 0x30: /* GPIO_CTRL */ 3445193899aSPaolo Bonzini return s->config[1]; 3455193899aSPaolo Bonzini 3465193899aSPaolo Bonzini case 0x34: /* GPIO_OE */ 3475193899aSPaolo Bonzini return s->dir; 3485193899aSPaolo Bonzini 3495193899aSPaolo Bonzini case 0x38: /* GPIO_DATAIN */ 3505193899aSPaolo Bonzini return s->inputs; 3515193899aSPaolo Bonzini 3525193899aSPaolo Bonzini case 0x3c: /* GPIO_DATAOUT */ 3535193899aSPaolo Bonzini case 0x90: /* GPIO_CLEARDATAOUT */ 3545193899aSPaolo Bonzini case 0x94: /* GPIO_SETDATAOUT */ 3555193899aSPaolo Bonzini return s->outputs; 3565193899aSPaolo Bonzini 3575193899aSPaolo Bonzini case 0x40: /* GPIO_LEVELDETECT0 */ 3585193899aSPaolo Bonzini return s->level[0]; 3595193899aSPaolo Bonzini 3605193899aSPaolo Bonzini case 0x44: /* GPIO_LEVELDETECT1 */ 3615193899aSPaolo Bonzini return s->level[1]; 3625193899aSPaolo Bonzini 3635193899aSPaolo Bonzini case 0x48: /* GPIO_RISINGDETECT */ 3645193899aSPaolo Bonzini return s->edge[0]; 3655193899aSPaolo Bonzini 3665193899aSPaolo Bonzini case 0x4c: /* GPIO_FALLINGDETECT */ 3675193899aSPaolo Bonzini return s->edge[1]; 3685193899aSPaolo Bonzini 3695193899aSPaolo Bonzini case 0x50: /* GPIO_DEBOUNCENABLE */ 3705193899aSPaolo Bonzini return s->debounce; 3715193899aSPaolo Bonzini 3725193899aSPaolo Bonzini case 0x54: /* GPIO_DEBOUNCINGTIME */ 3735193899aSPaolo Bonzini return s->delay; 3745193899aSPaolo Bonzini } 3755193899aSPaolo Bonzini 3765193899aSPaolo Bonzini OMAP_BAD_REG(addr); 3775193899aSPaolo Bonzini return 0; 3785193899aSPaolo Bonzini } 3795193899aSPaolo Bonzini 3805193899aSPaolo Bonzini static void omap2_gpio_module_write(void *opaque, hwaddr addr, 3815193899aSPaolo Bonzini uint32_t value) 3825193899aSPaolo Bonzini { 3835193899aSPaolo Bonzini struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; 3845193899aSPaolo Bonzini uint32_t diff; 3855193899aSPaolo Bonzini int ln; 3865193899aSPaolo Bonzini 3875193899aSPaolo Bonzini switch (addr) { 3885193899aSPaolo Bonzini case 0x00: /* GPIO_REVISION */ 3895193899aSPaolo Bonzini case 0x14: /* GPIO_SYSSTATUS */ 3905193899aSPaolo Bonzini case 0x38: /* GPIO_DATAIN */ 3915193899aSPaolo Bonzini OMAP_RO_REG(addr); 3925193899aSPaolo Bonzini break; 3935193899aSPaolo Bonzini 3945193899aSPaolo Bonzini case 0x10: /* GPIO_SYSCONFIG */ 3955193899aSPaolo Bonzini if (((value >> 3) & 3) == 3) 396a89f364aSAlistair Francis fprintf(stderr, "%s: bad IDLEMODE value\n", __func__); 3975193899aSPaolo Bonzini if (value & 2) 3985193899aSPaolo Bonzini omap2_gpio_module_reset(s); 3995193899aSPaolo Bonzini s->config[0] = value & 0x1d; 4005193899aSPaolo Bonzini break; 4015193899aSPaolo Bonzini 4025193899aSPaolo Bonzini case 0x18: /* GPIO_IRQSTATUS1 */ 4035193899aSPaolo Bonzini if (s->ints[0] & value) { 4045193899aSPaolo Bonzini s->ints[0] &= ~value; 4055193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 0); 4065193899aSPaolo Bonzini } 4075193899aSPaolo Bonzini break; 4085193899aSPaolo Bonzini 4095193899aSPaolo Bonzini case 0x1c: /* GPIO_IRQENABLE1 */ 4105193899aSPaolo Bonzini s->mask[0] = value; 4115193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 0); 4125193899aSPaolo Bonzini break; 4135193899aSPaolo Bonzini 4145193899aSPaolo Bonzini case 0x20: /* GPIO_WAKEUPENABLE */ 4155193899aSPaolo Bonzini s->wumask = value; 4165193899aSPaolo Bonzini break; 4175193899aSPaolo Bonzini 4185193899aSPaolo Bonzini case 0x28: /* GPIO_IRQSTATUS2 */ 4195193899aSPaolo Bonzini if (s->ints[1] & value) { 4205193899aSPaolo Bonzini s->ints[1] &= ~value; 4215193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 1); 4225193899aSPaolo Bonzini } 4235193899aSPaolo Bonzini break; 4245193899aSPaolo Bonzini 4255193899aSPaolo Bonzini case 0x2c: /* GPIO_IRQENABLE2 */ 4265193899aSPaolo Bonzini s->mask[1] = value; 4275193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 1); 4285193899aSPaolo Bonzini break; 4295193899aSPaolo Bonzini 4305193899aSPaolo Bonzini case 0x30: /* GPIO_CTRL */ 4315193899aSPaolo Bonzini s->config[1] = value & 7; 4325193899aSPaolo Bonzini break; 4335193899aSPaolo Bonzini 4345193899aSPaolo Bonzini case 0x34: /* GPIO_OE */ 4355193899aSPaolo Bonzini diff = s->outputs & (s->dir ^ value); 4365193899aSPaolo Bonzini s->dir = value; 4375193899aSPaolo Bonzini 4385193899aSPaolo Bonzini value = s->outputs & ~s->dir; 439bd2a8884SStefan Hajnoczi while ((ln = ctz32(diff)) != 32) { 440bd2a8884SStefan Hajnoczi diff &= ~(1 << ln); 4415193899aSPaolo Bonzini qemu_set_irq(s->handler[ln], (value >> ln) & 1); 4425193899aSPaolo Bonzini } 4435193899aSPaolo Bonzini 4445193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 0); 4455193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 1); 4465193899aSPaolo Bonzini break; 4475193899aSPaolo Bonzini 4485193899aSPaolo Bonzini case 0x3c: /* GPIO_DATAOUT */ 4495193899aSPaolo Bonzini omap2_gpio_module_out_update(s, s->outputs ^ value); 4505193899aSPaolo Bonzini break; 4515193899aSPaolo Bonzini 4525193899aSPaolo Bonzini case 0x40: /* GPIO_LEVELDETECT0 */ 4535193899aSPaolo Bonzini s->level[0] = value; 4545193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 0); 4555193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 1); 4565193899aSPaolo Bonzini break; 4575193899aSPaolo Bonzini 4585193899aSPaolo Bonzini case 0x44: /* GPIO_LEVELDETECT1 */ 4595193899aSPaolo Bonzini s->level[1] = value; 4605193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 0); 4615193899aSPaolo Bonzini omap2_gpio_module_level_update(s, 1); 4625193899aSPaolo Bonzini break; 4635193899aSPaolo Bonzini 4645193899aSPaolo Bonzini case 0x48: /* GPIO_RISINGDETECT */ 4655193899aSPaolo Bonzini s->edge[0] = value; 4665193899aSPaolo Bonzini break; 4675193899aSPaolo Bonzini 4685193899aSPaolo Bonzini case 0x4c: /* GPIO_FALLINGDETECT */ 4695193899aSPaolo Bonzini s->edge[1] = value; 4705193899aSPaolo Bonzini break; 4715193899aSPaolo Bonzini 4725193899aSPaolo Bonzini case 0x50: /* GPIO_DEBOUNCENABLE */ 4735193899aSPaolo Bonzini s->debounce = value; 4745193899aSPaolo Bonzini break; 4755193899aSPaolo Bonzini 4765193899aSPaolo Bonzini case 0x54: /* GPIO_DEBOUNCINGTIME */ 4775193899aSPaolo Bonzini s->delay = value; 4785193899aSPaolo Bonzini break; 4795193899aSPaolo Bonzini 4805193899aSPaolo Bonzini case 0x60: /* GPIO_CLEARIRQENABLE1 */ 4815193899aSPaolo Bonzini s->mask[0] &= ~value; 4825193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 0); 4835193899aSPaolo Bonzini break; 4845193899aSPaolo Bonzini 4855193899aSPaolo Bonzini case 0x64: /* GPIO_SETIRQENABLE1 */ 4865193899aSPaolo Bonzini s->mask[0] |= value; 4875193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 0); 4885193899aSPaolo Bonzini break; 4895193899aSPaolo Bonzini 4905193899aSPaolo Bonzini case 0x70: /* GPIO_CLEARIRQENABLE2 */ 4915193899aSPaolo Bonzini s->mask[1] &= ~value; 4925193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 1); 4935193899aSPaolo Bonzini break; 4945193899aSPaolo Bonzini 4955193899aSPaolo Bonzini case 0x74: /* GPIO_SETIREQNEABLE2 */ 4965193899aSPaolo Bonzini s->mask[1] |= value; 4975193899aSPaolo Bonzini omap2_gpio_module_int_update(s, 1); 4985193899aSPaolo Bonzini break; 4995193899aSPaolo Bonzini 5005193899aSPaolo Bonzini case 0x80: /* GPIO_CLEARWKUENA */ 5015193899aSPaolo Bonzini s->wumask &= ~value; 5025193899aSPaolo Bonzini break; 5035193899aSPaolo Bonzini 5045193899aSPaolo Bonzini case 0x84: /* GPIO_SETWKUENA */ 5055193899aSPaolo Bonzini s->wumask |= value; 5065193899aSPaolo Bonzini break; 5075193899aSPaolo Bonzini 5085193899aSPaolo Bonzini case 0x90: /* GPIO_CLEARDATAOUT */ 5095193899aSPaolo Bonzini omap2_gpio_module_out_update(s, s->outputs & value); 5105193899aSPaolo Bonzini break; 5115193899aSPaolo Bonzini 5125193899aSPaolo Bonzini case 0x94: /* GPIO_SETDATAOUT */ 5135193899aSPaolo Bonzini omap2_gpio_module_out_update(s, ~s->outputs & value); 5145193899aSPaolo Bonzini break; 5155193899aSPaolo Bonzini 5165193899aSPaolo Bonzini default: 5175193899aSPaolo Bonzini OMAP_BAD_REG(addr); 5185193899aSPaolo Bonzini return; 5195193899aSPaolo Bonzini } 5205193899aSPaolo Bonzini } 5215193899aSPaolo Bonzini 522940caf1fSPeter Maydell static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr, 523940caf1fSPeter Maydell unsigned size) 5245193899aSPaolo Bonzini { 5255193899aSPaolo Bonzini return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3); 5265193899aSPaolo Bonzini } 5275193899aSPaolo Bonzini 5285193899aSPaolo Bonzini static void omap2_gpio_module_writep(void *opaque, hwaddr addr, 529940caf1fSPeter Maydell uint64_t value, unsigned size) 5305193899aSPaolo Bonzini { 5315193899aSPaolo Bonzini uint32_t cur = 0; 5325193899aSPaolo Bonzini uint32_t mask = 0xffff; 5335193899aSPaolo Bonzini 534940caf1fSPeter Maydell if (size == 4) { 535940caf1fSPeter Maydell omap2_gpio_module_write(opaque, addr, value); 536940caf1fSPeter Maydell return; 537940caf1fSPeter Maydell } 538940caf1fSPeter Maydell 5395193899aSPaolo Bonzini switch (addr & ~3) { 5405193899aSPaolo Bonzini case 0x00: /* GPIO_REVISION */ 5415193899aSPaolo Bonzini case 0x14: /* GPIO_SYSSTATUS */ 5425193899aSPaolo Bonzini case 0x38: /* GPIO_DATAIN */ 5435193899aSPaolo Bonzini OMAP_RO_REG(addr); 5445193899aSPaolo Bonzini break; 5455193899aSPaolo Bonzini 5465193899aSPaolo Bonzini case 0x10: /* GPIO_SYSCONFIG */ 5475193899aSPaolo Bonzini case 0x1c: /* GPIO_IRQENABLE1 */ 5485193899aSPaolo Bonzini case 0x20: /* GPIO_WAKEUPENABLE */ 5495193899aSPaolo Bonzini case 0x2c: /* GPIO_IRQENABLE2 */ 5505193899aSPaolo Bonzini case 0x30: /* GPIO_CTRL */ 5515193899aSPaolo Bonzini case 0x34: /* GPIO_OE */ 5525193899aSPaolo Bonzini case 0x3c: /* GPIO_DATAOUT */ 5535193899aSPaolo Bonzini case 0x40: /* GPIO_LEVELDETECT0 */ 5545193899aSPaolo Bonzini case 0x44: /* GPIO_LEVELDETECT1 */ 5555193899aSPaolo Bonzini case 0x48: /* GPIO_RISINGDETECT */ 5565193899aSPaolo Bonzini case 0x4c: /* GPIO_FALLINGDETECT */ 5575193899aSPaolo Bonzini case 0x50: /* GPIO_DEBOUNCENABLE */ 5585193899aSPaolo Bonzini case 0x54: /* GPIO_DEBOUNCINGTIME */ 5595193899aSPaolo Bonzini cur = omap2_gpio_module_read(opaque, addr & ~3) & 5605193899aSPaolo Bonzini ~(mask << ((addr & 3) << 3)); 5615193899aSPaolo Bonzini 5625193899aSPaolo Bonzini /* Fall through. */ 5635193899aSPaolo Bonzini case 0x18: /* GPIO_IRQSTATUS1 */ 5645193899aSPaolo Bonzini case 0x28: /* GPIO_IRQSTATUS2 */ 5655193899aSPaolo Bonzini case 0x60: /* GPIO_CLEARIRQENABLE1 */ 5665193899aSPaolo Bonzini case 0x64: /* GPIO_SETIRQENABLE1 */ 5675193899aSPaolo Bonzini case 0x70: /* GPIO_CLEARIRQENABLE2 */ 5685193899aSPaolo Bonzini case 0x74: /* GPIO_SETIREQNEABLE2 */ 5695193899aSPaolo Bonzini case 0x80: /* GPIO_CLEARWKUENA */ 5705193899aSPaolo Bonzini case 0x84: /* GPIO_SETWKUENA */ 5715193899aSPaolo Bonzini case 0x90: /* GPIO_CLEARDATAOUT */ 5725193899aSPaolo Bonzini case 0x94: /* GPIO_SETDATAOUT */ 5735193899aSPaolo Bonzini value <<= (addr & 3) << 3; 5745193899aSPaolo Bonzini omap2_gpio_module_write(opaque, addr, cur | value); 5755193899aSPaolo Bonzini break; 5765193899aSPaolo Bonzini 5775193899aSPaolo Bonzini default: 5785193899aSPaolo Bonzini OMAP_BAD_REG(addr); 5795193899aSPaolo Bonzini return; 5805193899aSPaolo Bonzini } 5815193899aSPaolo Bonzini } 5825193899aSPaolo Bonzini 5835193899aSPaolo Bonzini static const MemoryRegionOps omap2_gpio_module_ops = { 584940caf1fSPeter Maydell .read = omap2_gpio_module_readp, 585940caf1fSPeter Maydell .write = omap2_gpio_module_writep, 586940caf1fSPeter Maydell .valid.min_access_size = 1, 587940caf1fSPeter Maydell .valid.max_access_size = 4, 5885193899aSPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 5895193899aSPaolo Bonzini }; 5905193899aSPaolo Bonzini 5915193899aSPaolo Bonzini static void omap_gpif_reset(DeviceState *dev) 5925193899aSPaolo Bonzini { 5931d300b5fSAndreas Färber struct omap_gpif_s *s = OMAP1_GPIO(dev); 5941d300b5fSAndreas Färber 5955193899aSPaolo Bonzini omap_gpio_reset(&s->omap1); 5965193899aSPaolo Bonzini } 5975193899aSPaolo Bonzini 5985193899aSPaolo Bonzini static void omap2_gpif_reset(DeviceState *dev) 5995193899aSPaolo Bonzini { 60074d1e352SAndreas Färber struct omap2_gpif_s *s = OMAP2_GPIO(dev); 6015193899aSPaolo Bonzini int i; 60274d1e352SAndreas Färber 6035193899aSPaolo Bonzini for (i = 0; i < s->modulecount; i++) { 6045193899aSPaolo Bonzini omap2_gpio_module_reset(&s->modules[i]); 6055193899aSPaolo Bonzini } 6065193899aSPaolo Bonzini s->autoidle = 0; 6075193899aSPaolo Bonzini s->gpo = 0; 6085193899aSPaolo Bonzini } 6095193899aSPaolo Bonzini 6105193899aSPaolo Bonzini static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, 6115193899aSPaolo Bonzini unsigned size) 6125193899aSPaolo Bonzini { 6135193899aSPaolo Bonzini struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque; 6145193899aSPaolo Bonzini 6155193899aSPaolo Bonzini switch (addr) { 6165193899aSPaolo Bonzini case 0x00: /* IPGENERICOCPSPL_REVISION */ 6175193899aSPaolo Bonzini return 0x18; 6185193899aSPaolo Bonzini 6195193899aSPaolo Bonzini case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ 6205193899aSPaolo Bonzini return s->autoidle; 6215193899aSPaolo Bonzini 6225193899aSPaolo Bonzini case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ 6235193899aSPaolo Bonzini return 0x01; 6245193899aSPaolo Bonzini 6255193899aSPaolo Bonzini case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ 6265193899aSPaolo Bonzini return 0x00; 6275193899aSPaolo Bonzini 6285193899aSPaolo Bonzini case 0x40: /* IPGENERICOCPSPL_GPO */ 6295193899aSPaolo Bonzini return s->gpo; 6305193899aSPaolo Bonzini 6315193899aSPaolo Bonzini case 0x50: /* IPGENERICOCPSPL_GPI */ 6325193899aSPaolo Bonzini return 0x00; 6335193899aSPaolo Bonzini } 6345193899aSPaolo Bonzini 6355193899aSPaolo Bonzini OMAP_BAD_REG(addr); 6365193899aSPaolo Bonzini return 0; 6375193899aSPaolo Bonzini } 6385193899aSPaolo Bonzini 6395193899aSPaolo Bonzini static void omap2_gpif_top_write(void *opaque, hwaddr addr, 6405193899aSPaolo Bonzini uint64_t value, unsigned size) 6415193899aSPaolo Bonzini { 6425193899aSPaolo Bonzini struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque; 6435193899aSPaolo Bonzini 6445193899aSPaolo Bonzini switch (addr) { 6455193899aSPaolo Bonzini case 0x00: /* IPGENERICOCPSPL_REVISION */ 6465193899aSPaolo Bonzini case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ 6475193899aSPaolo Bonzini case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ 6485193899aSPaolo Bonzini case 0x50: /* IPGENERICOCPSPL_GPI */ 6495193899aSPaolo Bonzini OMAP_RO_REG(addr); 6505193899aSPaolo Bonzini break; 6515193899aSPaolo Bonzini 6525193899aSPaolo Bonzini case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ 6535193899aSPaolo Bonzini if (value & (1 << 1)) /* SOFTRESET */ 65474d1e352SAndreas Färber omap2_gpif_reset(DEVICE(s)); 6555193899aSPaolo Bonzini s->autoidle = value & 1; 6565193899aSPaolo Bonzini break; 6575193899aSPaolo Bonzini 6585193899aSPaolo Bonzini case 0x40: /* IPGENERICOCPSPL_GPO */ 6595193899aSPaolo Bonzini s->gpo = value & 1; 6605193899aSPaolo Bonzini break; 6615193899aSPaolo Bonzini 6625193899aSPaolo Bonzini default: 6635193899aSPaolo Bonzini OMAP_BAD_REG(addr); 6645193899aSPaolo Bonzini return; 6655193899aSPaolo Bonzini } 6665193899aSPaolo Bonzini } 6675193899aSPaolo Bonzini 6685193899aSPaolo Bonzini static const MemoryRegionOps omap2_gpif_top_ops = { 6695193899aSPaolo Bonzini .read = omap2_gpif_top_read, 6705193899aSPaolo Bonzini .write = omap2_gpif_top_write, 6715193899aSPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 6725193899aSPaolo Bonzini }; 6735193899aSPaolo Bonzini 674ebc116f8Sxiaoqiang zhao static void omap_gpio_init(Object *obj) 6755193899aSPaolo Bonzini { 676ebc116f8Sxiaoqiang zhao DeviceState *dev = DEVICE(obj); 677ebc116f8Sxiaoqiang zhao struct omap_gpif_s *s = OMAP1_GPIO(obj); 678ebc116f8Sxiaoqiang zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 6791d300b5fSAndreas Färber 6801d300b5fSAndreas Färber qdev_init_gpio_in(dev, omap_gpio_set, 16); 6811d300b5fSAndreas Färber qdev_init_gpio_out(dev, s->omap1.handler, 16); 6821d300b5fSAndreas Färber sysbus_init_irq(sbd, &s->omap1.irq); 683ebc116f8Sxiaoqiang zhao memory_region_init_io(&s->iomem, obj, &omap_gpio_ops, &s->omap1, 6845193899aSPaolo Bonzini "omap.gpio", 0x1000); 6851d300b5fSAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 6865193899aSPaolo Bonzini } 6875193899aSPaolo Bonzini 688ebc116f8Sxiaoqiang zhao static void omap_gpio_realize(DeviceState *dev, Error **errp) 6895193899aSPaolo Bonzini { 690ebc116f8Sxiaoqiang zhao struct omap_gpif_s *s = OMAP1_GPIO(dev); 691ebc116f8Sxiaoqiang zhao 692ebc116f8Sxiaoqiang zhao if (!s->clk) { 693ebc116f8Sxiaoqiang zhao error_setg(errp, "omap-gpio: clk not connected"); 694ebc116f8Sxiaoqiang zhao } 695ebc116f8Sxiaoqiang zhao } 696ebc116f8Sxiaoqiang zhao 697ebc116f8Sxiaoqiang zhao static void omap2_gpio_realize(DeviceState *dev, Error **errp) 698ebc116f8Sxiaoqiang zhao { 69974d1e352SAndreas Färber struct omap2_gpif_s *s = OMAP2_GPIO(dev); 700ebc116f8Sxiaoqiang zhao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 7015193899aSPaolo Bonzini int i; 70274d1e352SAndreas Färber 7035193899aSPaolo Bonzini if (!s->iclk) { 704ebc116f8Sxiaoqiang zhao error_setg(errp, "omap2-gpio: iclk not connected"); 705ebc116f8Sxiaoqiang zhao return; 7065193899aSPaolo Bonzini } 70784a3a53cSMarkus Armbruster 70884a3a53cSMarkus Armbruster s->modulecount = s->mpu_model < omap2430 ? 4 70984a3a53cSMarkus Armbruster : s->mpu_model < omap3430 ? 5 71084a3a53cSMarkus Armbruster : 6; 71184a3a53cSMarkus Armbruster 7125193899aSPaolo Bonzini if (s->mpu_model < omap3430) { 713ebc116f8Sxiaoqiang zhao memory_region_init_io(&s->iomem, OBJECT(dev), &omap2_gpif_top_ops, s, 7145193899aSPaolo Bonzini "omap2.gpio", 0x1000); 71574d1e352SAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 7165193899aSPaolo Bonzini } 71784a3a53cSMarkus Armbruster 718b45c03f5SMarkus Armbruster s->modules = g_new0(struct omap2_gpio_s, s->modulecount); 719b45c03f5SMarkus Armbruster s->handler = g_new0(qemu_irq, s->modulecount * 32); 72074d1e352SAndreas Färber qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32); 72174d1e352SAndreas Färber qdev_init_gpio_out(dev, s->handler, s->modulecount * 32); 72284a3a53cSMarkus Armbruster 7235193899aSPaolo Bonzini for (i = 0; i < s->modulecount; i++) { 7245193899aSPaolo Bonzini struct omap2_gpio_s *m = &s->modules[i]; 72584a3a53cSMarkus Armbruster 726ebc116f8Sxiaoqiang zhao if (!s->fclk[i]) { 727ebc116f8Sxiaoqiang zhao error_setg(errp, "omap2-gpio: fclk%d not connected", i); 728ebc116f8Sxiaoqiang zhao return; 729ebc116f8Sxiaoqiang zhao } 730ebc116f8Sxiaoqiang zhao 7315193899aSPaolo Bonzini m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25; 7325193899aSPaolo Bonzini m->handler = &s->handler[i * 32]; 73374d1e352SAndreas Färber sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */ 73474d1e352SAndreas Färber sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */ 73574d1e352SAndreas Färber sysbus_init_irq(sbd, &m->wkup); 736ebc116f8Sxiaoqiang zhao memory_region_init_io(&m->iomem, OBJECT(dev), &omap2_gpio_module_ops, m, 7375193899aSPaolo Bonzini "omap.gpio-module", 0x1000); 73874d1e352SAndreas Färber sysbus_init_mmio(sbd, &m->iomem); 7395193899aSPaolo Bonzini } 7405193899aSPaolo Bonzini } 7415193899aSPaolo Bonzini 742ba2aba83SMarc-André Lureau void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk) 743ba2aba83SMarc-André Lureau { 744ba2aba83SMarc-André Lureau gpio->clk = clk; 745ba2aba83SMarc-André Lureau } 7465193899aSPaolo Bonzini 7475193899aSPaolo Bonzini static Property omap_gpio_properties[] = { 7485193899aSPaolo Bonzini DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0), 7495193899aSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 7505193899aSPaolo Bonzini }; 7515193899aSPaolo Bonzini 7525193899aSPaolo Bonzini static void omap_gpio_class_init(ObjectClass *klass, void *data) 7535193899aSPaolo Bonzini { 7545193899aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 7555193899aSPaolo Bonzini 756ebc116f8Sxiaoqiang zhao dc->realize = omap_gpio_realize; 7575193899aSPaolo Bonzini dc->reset = omap_gpif_reset; 758*4f67d30bSMarc-André Lureau device_class_set_props(dc, omap_gpio_properties); 7591b111dc1SMarkus Armbruster /* Reason: pointer property "clk" */ 760e90f2a8cSEduardo Habkost dc->user_creatable = false; 7615193899aSPaolo Bonzini } 7625193899aSPaolo Bonzini 7635193899aSPaolo Bonzini static const TypeInfo omap_gpio_info = { 7641d300b5fSAndreas Färber .name = TYPE_OMAP1_GPIO, 7655193899aSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 7665193899aSPaolo Bonzini .instance_size = sizeof(struct omap_gpif_s), 767ebc116f8Sxiaoqiang zhao .instance_init = omap_gpio_init, 7685193899aSPaolo Bonzini .class_init = omap_gpio_class_init, 7695193899aSPaolo Bonzini }; 7705193899aSPaolo Bonzini 771ba2aba83SMarc-André Lureau void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk) 772ba2aba83SMarc-André Lureau { 773ba2aba83SMarc-André Lureau gpio->iclk = clk; 774ba2aba83SMarc-André Lureau } 775ba2aba83SMarc-André Lureau 776ba2aba83SMarc-André Lureau void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk) 777ba2aba83SMarc-André Lureau { 778ba2aba83SMarc-André Lureau assert(i <= 5); 779ba2aba83SMarc-André Lureau gpio->fclk[i] = clk; 780ba2aba83SMarc-André Lureau } 781ba2aba83SMarc-André Lureau 7825193899aSPaolo Bonzini static Property omap2_gpio_properties[] = { 7835193899aSPaolo Bonzini DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0), 7845193899aSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 7855193899aSPaolo Bonzini }; 7865193899aSPaolo Bonzini 7875193899aSPaolo Bonzini static void omap2_gpio_class_init(ObjectClass *klass, void *data) 7885193899aSPaolo Bonzini { 7895193899aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 7905193899aSPaolo Bonzini 791ebc116f8Sxiaoqiang zhao dc->realize = omap2_gpio_realize; 7925193899aSPaolo Bonzini dc->reset = omap2_gpif_reset; 793*4f67d30bSMarc-André Lureau device_class_set_props(dc, omap2_gpio_properties); 7941b111dc1SMarkus Armbruster /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */ 795e90f2a8cSEduardo Habkost dc->user_creatable = false; 7965193899aSPaolo Bonzini } 7975193899aSPaolo Bonzini 7985193899aSPaolo Bonzini static const TypeInfo omap2_gpio_info = { 79974d1e352SAndreas Färber .name = TYPE_OMAP2_GPIO, 8005193899aSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 8015193899aSPaolo Bonzini .instance_size = sizeof(struct omap2_gpif_s), 8025193899aSPaolo Bonzini .class_init = omap2_gpio_class_init, 8035193899aSPaolo Bonzini }; 8045193899aSPaolo Bonzini 8055193899aSPaolo Bonzini static void omap_gpio_register_types(void) 8065193899aSPaolo Bonzini { 8075193899aSPaolo Bonzini type_register_static(&omap_gpio_info); 8085193899aSPaolo Bonzini type_register_static(&omap2_gpio_info); 8095193899aSPaolo Bonzini } 8105193899aSPaolo Bonzini 8115193899aSPaolo Bonzini type_init(omap_gpio_register_types) 812